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77241056 MM |
1 | #ifndef _HFI1_SDMA_H |
2 | #define _HFI1_SDMA_H | |
3 | /* | |
4 | * | |
5 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
6 | * redistributing this file, you may do so under either license. | |
7 | * | |
8 | * GPL LICENSE SUMMARY | |
9 | * | |
10 | * Copyright(c) 2015 Intel Corporation. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of version 2 of the GNU General Public License as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * BSD LICENSE | |
22 | * | |
23 | * Copyright(c) 2015 Intel Corporation. | |
24 | * | |
25 | * Redistribution and use in source and binary forms, with or without | |
26 | * modification, are permitted provided that the following conditions | |
27 | * are met: | |
28 | * | |
29 | * - Redistributions of source code must retain the above copyright | |
30 | * notice, this list of conditions and the following disclaimer. | |
31 | * - Redistributions in binary form must reproduce the above copyright | |
32 | * notice, this list of conditions and the following disclaimer in | |
33 | * the documentation and/or other materials provided with the | |
34 | * distribution. | |
35 | * - Neither the name of Intel Corporation nor the names of its | |
36 | * contributors may be used to endorse or promote products derived | |
37 | * from this software without specific prior written permission. | |
38 | * | |
39 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
40 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
41 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
42 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
43 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
44 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
45 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
46 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
47 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
48 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
49 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
50 | * | |
51 | */ | |
52 | ||
53 | #include <linux/types.h> | |
54 | #include <linux/list.h> | |
55 | #include <asm/byteorder.h> | |
56 | #include <linux/workqueue.h> | |
57 | #include <linux/rculist.h> | |
58 | ||
59 | #include "hfi.h" | |
60 | #include "verbs.h" | |
61 | ||
62 | /* increased for AHG */ | |
63 | #define NUM_DESC 6 | |
64 | /* Hardware limit */ | |
65 | #define MAX_DESC 64 | |
66 | /* Hardware limit for SDMA packet size */ | |
67 | #define MAX_SDMA_PKT_SIZE ((16 * 1024) - 1) | |
68 | ||
69 | ||
70 | #define SDMA_TXREQ_S_OK 0 | |
71 | #define SDMA_TXREQ_S_SENDERROR 1 | |
72 | #define SDMA_TXREQ_S_ABORTED 2 | |
73 | #define SDMA_TXREQ_S_SHUTDOWN 3 | |
74 | ||
75 | /* flags bits */ | |
76 | #define SDMA_TXREQ_F_URGENT 0x0001 | |
77 | #define SDMA_TXREQ_F_AHG_COPY 0x0002 | |
78 | #define SDMA_TXREQ_F_USE_AHG 0x0004 | |
79 | ||
80 | #define SDMA_MAP_NONE 0 | |
81 | #define SDMA_MAP_SINGLE 1 | |
82 | #define SDMA_MAP_PAGE 2 | |
83 | ||
84 | #define SDMA_AHG_VALUE_MASK 0xffff | |
85 | #define SDMA_AHG_VALUE_SHIFT 0 | |
86 | #define SDMA_AHG_INDEX_MASK 0xf | |
87 | #define SDMA_AHG_INDEX_SHIFT 16 | |
88 | #define SDMA_AHG_FIELD_LEN_MASK 0xf | |
89 | #define SDMA_AHG_FIELD_LEN_SHIFT 20 | |
90 | #define SDMA_AHG_FIELD_START_MASK 0x1f | |
91 | #define SDMA_AHG_FIELD_START_SHIFT 24 | |
92 | #define SDMA_AHG_UPDATE_ENABLE_MASK 0x1 | |
93 | #define SDMA_AHG_UPDATE_ENABLE_SHIFT 31 | |
94 | ||
95 | /* AHG modes */ | |
96 | ||
97 | /* | |
98 | * Be aware the ordering and values | |
99 | * for SDMA_AHG_APPLY_UPDATE[123] | |
100 | * are assumed in generating a skip | |
101 | * count in submit_tx() in sdma.c | |
102 | */ | |
103 | #define SDMA_AHG_NO_AHG 0 | |
104 | #define SDMA_AHG_COPY 1 | |
105 | #define SDMA_AHG_APPLY_UPDATE1 2 | |
106 | #define SDMA_AHG_APPLY_UPDATE2 3 | |
107 | #define SDMA_AHG_APPLY_UPDATE3 4 | |
108 | ||
109 | /* | |
110 | * Bits defined in the send DMA descriptor. | |
111 | */ | |
3f2686a2 DC |
112 | #define SDMA_DESC0_FIRST_DESC_FLAG (1ULL << 63) |
113 | #define SDMA_DESC0_LAST_DESC_FLAG (1ULL << 62) | |
77241056 MM |
114 | #define SDMA_DESC0_BYTE_COUNT_SHIFT 48 |
115 | #define SDMA_DESC0_BYTE_COUNT_WIDTH 14 | |
116 | #define SDMA_DESC0_BYTE_COUNT_MASK \ | |
3f2686a2 | 117 | ((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1) |
77241056 | 118 | #define SDMA_DESC0_BYTE_COUNT_SMASK \ |
3f2686a2 | 119 | (SDMA_DESC0_BYTE_COUNT_MASK << SDMA_DESC0_BYTE_COUNT_SHIFT) |
77241056 MM |
120 | #define SDMA_DESC0_PHY_ADDR_SHIFT 0 |
121 | #define SDMA_DESC0_PHY_ADDR_WIDTH 48 | |
122 | #define SDMA_DESC0_PHY_ADDR_MASK \ | |
3f2686a2 | 123 | ((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1) |
77241056 | 124 | #define SDMA_DESC0_PHY_ADDR_SMASK \ |
3f2686a2 | 125 | (SDMA_DESC0_PHY_ADDR_MASK << SDMA_DESC0_PHY_ADDR_SHIFT) |
77241056 MM |
126 | |
127 | #define SDMA_DESC1_HEADER_UPDATE1_SHIFT 32 | |
128 | #define SDMA_DESC1_HEADER_UPDATE1_WIDTH 32 | |
129 | #define SDMA_DESC1_HEADER_UPDATE1_MASK \ | |
3f2686a2 | 130 | ((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1) |
77241056 | 131 | #define SDMA_DESC1_HEADER_UPDATE1_SMASK \ |
3f2686a2 | 132 | (SDMA_DESC1_HEADER_UPDATE1_MASK << SDMA_DESC1_HEADER_UPDATE1_SHIFT) |
77241056 MM |
133 | #define SDMA_DESC1_HEADER_MODE_SHIFT 13 |
134 | #define SDMA_DESC1_HEADER_MODE_WIDTH 3 | |
135 | #define SDMA_DESC1_HEADER_MODE_MASK \ | |
3f2686a2 | 136 | ((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1) |
77241056 | 137 | #define SDMA_DESC1_HEADER_MODE_SMASK \ |
3f2686a2 | 138 | (SDMA_DESC1_HEADER_MODE_MASK << SDMA_DESC1_HEADER_MODE_SHIFT) |
77241056 MM |
139 | #define SDMA_DESC1_HEADER_INDEX_SHIFT 8 |
140 | #define SDMA_DESC1_HEADER_INDEX_WIDTH 5 | |
141 | #define SDMA_DESC1_HEADER_INDEX_MASK \ | |
3f2686a2 | 142 | ((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1) |
77241056 | 143 | #define SDMA_DESC1_HEADER_INDEX_SMASK \ |
3f2686a2 | 144 | (SDMA_DESC1_HEADER_INDEX_MASK << SDMA_DESC1_HEADER_INDEX_SHIFT) |
77241056 MM |
145 | #define SDMA_DESC1_HEADER_DWS_SHIFT 4 |
146 | #define SDMA_DESC1_HEADER_DWS_WIDTH 4 | |
147 | #define SDMA_DESC1_HEADER_DWS_MASK \ | |
3f2686a2 | 148 | ((1ULL << SDMA_DESC1_HEADER_DWS_WIDTH) - 1) |
77241056 | 149 | #define SDMA_DESC1_HEADER_DWS_SMASK \ |
3f2686a2 | 150 | (SDMA_DESC1_HEADER_DWS_MASK << SDMA_DESC1_HEADER_DWS_SHIFT) |
77241056 MM |
151 | #define SDMA_DESC1_GENERATION_SHIFT 2 |
152 | #define SDMA_DESC1_GENERATION_WIDTH 2 | |
153 | #define SDMA_DESC1_GENERATION_MASK \ | |
3f2686a2 | 154 | ((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1) |
77241056 | 155 | #define SDMA_DESC1_GENERATION_SMASK \ |
3f2686a2 DC |
156 | (SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT) |
157 | #define SDMA_DESC1_INT_REQ_FLAG (1ULL << 1) | |
158 | #define SDMA_DESC1_HEAD_TO_HOST_FLAG (1ULL << 0) | |
77241056 MM |
159 | |
160 | enum sdma_states { | |
161 | sdma_state_s00_hw_down, | |
162 | sdma_state_s10_hw_start_up_halt_wait, | |
163 | sdma_state_s15_hw_start_up_clean_wait, | |
164 | sdma_state_s20_idle, | |
165 | sdma_state_s30_sw_clean_up_wait, | |
166 | sdma_state_s40_hw_clean_up_wait, | |
167 | sdma_state_s50_hw_halt_wait, | |
168 | sdma_state_s60_idle_halt_wait, | |
169 | sdma_state_s80_hw_freeze, | |
170 | sdma_state_s82_freeze_sw_clean, | |
171 | sdma_state_s99_running, | |
172 | }; | |
173 | ||
174 | enum sdma_events { | |
175 | sdma_event_e00_go_hw_down, | |
176 | sdma_event_e10_go_hw_start, | |
177 | sdma_event_e15_hw_halt_done, | |
178 | sdma_event_e25_hw_clean_up_done, | |
179 | sdma_event_e30_go_running, | |
180 | sdma_event_e40_sw_cleaned, | |
181 | sdma_event_e50_hw_cleaned, | |
182 | sdma_event_e60_hw_halted, | |
183 | sdma_event_e70_go_idle, | |
184 | sdma_event_e80_hw_freeze, | |
185 | sdma_event_e81_hw_frozen, | |
186 | sdma_event_e82_hw_unfreeze, | |
187 | sdma_event_e85_link_down, | |
188 | sdma_event_e90_sw_halted, | |
189 | }; | |
190 | ||
191 | struct sdma_set_state_action { | |
192 | unsigned op_enable:1; | |
193 | unsigned op_intenable:1; | |
194 | unsigned op_halt:1; | |
195 | unsigned op_cleanup:1; | |
196 | unsigned go_s99_running_tofalse:1; | |
197 | unsigned go_s99_running_totrue:1; | |
198 | }; | |
199 | ||
200 | struct sdma_state { | |
201 | struct kref kref; | |
202 | struct completion comp; | |
203 | enum sdma_states current_state; | |
204 | unsigned current_op; | |
205 | unsigned go_s99_running; | |
206 | /* debugging/development */ | |
207 | enum sdma_states previous_state; | |
208 | unsigned previous_op; | |
209 | enum sdma_events last_event; | |
210 | }; | |
211 | ||
212 | /** | |
213 | * DOC: sdma exported routines | |
214 | * | |
215 | * These sdma routines fit into three categories: | |
216 | * - The SDMA API for building and submitting packets | |
217 | * to the ring | |
218 | * | |
219 | * - Initialization and tear down routines to buildup | |
220 | * and tear down SDMA | |
221 | * | |
222 | * - ISR entrances to handle interrupts, state changes | |
223 | * and errors | |
224 | */ | |
225 | ||
226 | /** | |
227 | * DOC: sdma PSM/verbs API | |
228 | * | |
229 | * The sdma API is designed to be used by both PSM | |
230 | * and verbs to supply packets to the SDMA ring. | |
231 | * | |
232 | * The usage of the API is as follows: | |
233 | * | |
234 | * Embed a struct iowait in the QP or | |
235 | * PQ. The iowait should be initialized with a | |
236 | * call to iowait_init(). | |
237 | * | |
238 | * The user of the API should create an allocation method | |
239 | * for their version of the txreq. slabs, pre-allocated lists, | |
240 | * and dma pools can be used. Once the user's overload of | |
241 | * the sdma_txreq has been allocated, the sdma_txreq member | |
242 | * must be initialized with sdma_txinit() or sdma_txinit_ahg(). | |
243 | * | |
244 | * The txreq must be declared with the sdma_txreq first. | |
245 | * | |
246 | * The tx request, once initialized, is manipulated with calls to | |
247 | * sdma_txadd_daddr(), sdma_txadd_page(), or sdma_txadd_kvaddr() | |
248 | * for each disjoint memory location. It is the user's responsibility | |
249 | * to understand the packet boundaries and page boundaries to do the | |
250 | * appropriate number of sdma_txadd_* calls.. The user | |
251 | * must be prepared to deal with failures from these routines due to | |
252 | * either memory allocation or dma_mapping failures. | |
253 | * | |
254 | * The mapping specifics for each memory location are recorded | |
255 | * in the tx. Memory locations added with sdma_txadd_page() | |
256 | * and sdma_txadd_kvaddr() are automatically mapped when added | |
257 | * to the tx and nmapped as part of the progress processing in the | |
258 | * SDMA interrupt handling. | |
259 | * | |
260 | * sdma_txadd_daddr() is used to add an dma_addr_t memory to the | |
261 | * tx. An example of a use case would be a pre-allocated | |
262 | * set of headers allocated via dma_pool_alloc() or | |
263 | * dma_alloc_coherent(). For these memory locations, it | |
264 | * is the responsibility of the user to handle that unmapping. | |
265 | * (This would usually be at an unload or job termination.) | |
266 | * | |
267 | * The routine sdma_send_txreq() is used to submit | |
268 | * a tx to the ring after the appropriate number of | |
269 | * sdma_txadd_* have been done. | |
270 | * | |
271 | * If it is desired to send a burst of sdma_txreqs, sdma_send_txlist() | |
272 | * can be used to submit a list of packets. | |
273 | * | |
274 | * The user is free to use the link overhead in the struct sdma_txreq as | |
275 | * long as the tx isn't in flight. | |
276 | * | |
277 | * The extreme degenerate case of the number of descriptors | |
278 | * exceeding the ring size is automatically handled as | |
279 | * memory locations are added. An overflow of the descriptor | |
280 | * array that is part of the sdma_txreq is also automatically | |
281 | * handled. | |
282 | * | |
283 | */ | |
284 | ||
285 | /** | |
286 | * DOC: Infrastructure calls | |
287 | * | |
288 | * sdma_init() is used to initialize data structures and | |
289 | * CSRs for the desired number of SDMA engines. | |
290 | * | |
291 | * sdma_start() is used to kick the SDMA engines initialized | |
292 | * with sdma_init(). Interrupts must be enabled at this | |
293 | * point since aspects of the state machine are interrupt | |
294 | * driven. | |
295 | * | |
296 | * sdma_engine_error() and sdma_engine_interrupt() are | |
297 | * entrances for interrupts. | |
298 | * | |
299 | * sdma_map_init() is for the management of the mapping | |
300 | * table when the number of vls is changed. | |
301 | * | |
302 | */ | |
303 | ||
304 | /* | |
305 | * struct hw_sdma_desc - raw 128 bit SDMA descriptor | |
306 | * | |
307 | * This is the raw descriptor in the SDMA ring | |
308 | */ | |
309 | struct hw_sdma_desc { | |
310 | /* private: don't use directly */ | |
311 | __le64 qw[2]; | |
312 | }; | |
313 | ||
314 | /* | |
315 | * struct sdma_desc - canonical fragment descriptor | |
316 | * | |
317 | * This is the descriptor carried in the tx request | |
318 | * corresponding to each fragment. | |
319 | * | |
320 | */ | |
321 | struct sdma_desc { | |
322 | /* private: don't use directly */ | |
323 | u64 qw[2]; | |
324 | }; | |
325 | ||
326 | struct sdma_txreq; | |
327 | typedef void (*callback_t)(struct sdma_txreq *, int, int); | |
328 | ||
329 | /** | |
330 | * struct sdma_txreq - the sdma_txreq structure (one per packet) | |
331 | * @list: for use by user and by queuing for wait | |
332 | * | |
333 | * This is the representation of a packet which consists of some | |
334 | * number of fragments. Storage is provided to within the structure. | |
335 | * for all fragments. | |
336 | * | |
337 | * The storage for the descriptors are automatically extended as needed | |
338 | * when the currently allocation is exceeded. | |
339 | * | |
340 | * The user (Verbs or PSM) may overload this structure with fields | |
341 | * specific to their use by putting this struct first in their struct. | |
342 | * The method of allocation of the overloaded structure is user dependent | |
343 | * | |
344 | * The list is the only public field in the structure. | |
345 | * | |
346 | */ | |
347 | ||
348 | struct sdma_txreq { | |
349 | struct list_head list; | |
350 | /* private: */ | |
351 | struct sdma_desc *descp; | |
352 | /* private: */ | |
353 | void *coalesce_buf; | |
354 | /* private: */ | |
f4d26d81 NV |
355 | u16 coalesce_idx; |
356 | /* private: */ | |
77241056 MM |
357 | struct iowait *wait; |
358 | /* private: */ | |
359 | callback_t complete; | |
360 | #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER | |
361 | u64 sn; | |
362 | #endif | |
363 | /* private: - used in coalesce/pad processing */ | |
364 | u16 packet_len; | |
365 | /* private: - down-counted to trigger last */ | |
366 | u16 tlen; | |
367 | /* private: flags */ | |
368 | u16 flags; | |
369 | /* private: */ | |
370 | u16 num_desc; | |
371 | /* private: */ | |
372 | u16 desc_limit; | |
373 | /* private: */ | |
374 | u16 next_descq_idx; | |
375 | /* private: */ | |
376 | struct sdma_desc descs[NUM_DESC]; | |
377 | }; | |
378 | ||
379 | struct verbs_txreq { | |
380 | struct hfi1_pio_header phdr; | |
381 | struct sdma_txreq txreq; | |
895420dd DD |
382 | struct rvt_qp *qp; |
383 | struct rvt_swqe *wqe; | |
cd4ceee3 | 384 | struct rvt_mregion *mr; |
895420dd | 385 | struct rvt_sge_state *ss; |
77241056 MM |
386 | struct sdma_engine *sde; |
387 | u16 hdr_dwords; | |
388 | u16 hdr_inx; | |
389 | }; | |
390 | ||
391 | /** | |
392 | * struct sdma_engine - Data pertaining to each SDMA engine. | |
393 | * @dd: a back-pointer to the device data | |
394 | * @ppd: per port back-pointer | |
395 | * @imask: mask for irq manipulation | |
396 | * @idle_mask: mask for determining if an interrupt is due to sdma_idle | |
397 | * | |
398 | * This structure has the state for each sdma_engine. | |
399 | * | |
400 | * Accessing to non public fields are not supported | |
401 | * since the private members are subject to change. | |
402 | */ | |
403 | struct sdma_engine { | |
404 | /* read mostly */ | |
405 | struct hfi1_devdata *dd; | |
406 | struct hfi1_pportdata *ppd; | |
407 | /* private: */ | |
408 | void __iomem *tail_csr; | |
409 | u64 imask; /* clear interrupt mask */ | |
410 | u64 idle_mask; | |
411 | u64 progress_mask; | |
a699c6c2 | 412 | u64 int_mask; |
77241056 | 413 | /* private: */ |
77241056 MM |
414 | volatile __le64 *head_dma; /* DMA'ed by chip */ |
415 | /* private: */ | |
416 | dma_addr_t head_phys; | |
417 | /* private: */ | |
418 | struct hw_sdma_desc *descq; | |
419 | /* private: */ | |
420 | unsigned descq_full_count; | |
421 | struct sdma_txreq **tx_ring; | |
422 | /* private: */ | |
423 | dma_addr_t descq_phys; | |
424 | /* private */ | |
425 | u32 sdma_mask; | |
426 | /* private */ | |
427 | struct sdma_state state; | |
0a226edd MM |
428 | /* private */ |
429 | int cpu; | |
77241056 MM |
430 | /* private: */ |
431 | u8 sdma_shift; | |
432 | /* private: */ | |
433 | u8 this_idx; /* zero relative engine */ | |
434 | /* protect changes to senddmactrl shadow */ | |
435 | spinlock_t senddmactrl_lock; | |
436 | /* private: */ | |
437 | u64 p_senddmactrl; /* shadow per-engine SendDmaCtrl */ | |
438 | ||
439 | /* read/write using tail_lock */ | |
440 | spinlock_t tail_lock ____cacheline_aligned_in_smp; | |
441 | #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER | |
442 | /* private: */ | |
443 | u64 tail_sn; | |
444 | #endif | |
445 | /* private: */ | |
446 | u32 descq_tail; | |
447 | /* private: */ | |
448 | unsigned long ahg_bits; | |
449 | /* private: */ | |
450 | u16 desc_avail; | |
451 | /* private: */ | |
452 | u16 tx_tail; | |
453 | /* private: */ | |
454 | u16 descq_cnt; | |
455 | ||
456 | /* read/write using head_lock */ | |
457 | /* private: */ | |
458 | seqlock_t head_lock ____cacheline_aligned_in_smp; | |
459 | #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER | |
460 | /* private: */ | |
461 | u64 head_sn; | |
462 | #endif | |
463 | /* private: */ | |
464 | u32 descq_head; | |
465 | /* private: */ | |
466 | u16 tx_head; | |
467 | /* private: */ | |
468 | u64 last_status; | |
a699c6c2 VM |
469 | /* private */ |
470 | u64 err_cnt; | |
471 | /* private */ | |
472 | u64 sdma_int_cnt; | |
473 | u64 idle_int_cnt; | |
474 | u64 progress_int_cnt; | |
77241056 MM |
475 | |
476 | /* private: */ | |
477 | struct list_head dmawait; | |
478 | ||
479 | /* CONFIG SDMA for now, just blindly duplicate */ | |
480 | /* private: */ | |
481 | struct tasklet_struct sdma_hw_clean_up_task | |
482 | ____cacheline_aligned_in_smp; | |
483 | ||
484 | /* private: */ | |
485 | struct tasklet_struct sdma_sw_clean_up_task | |
486 | ____cacheline_aligned_in_smp; | |
487 | /* private: */ | |
488 | struct work_struct err_halt_worker; | |
489 | /* private */ | |
490 | struct timer_list err_progress_check_timer; | |
491 | u32 progress_check_head; | |
492 | /* private: */ | |
493 | struct work_struct flush_worker; | |
494 | spinlock_t flushlist_lock; | |
495 | /* private: */ | |
496 | struct list_head flushlist; | |
497 | }; | |
498 | ||
499 | ||
500 | int sdma_init(struct hfi1_devdata *dd, u8 port); | |
501 | void sdma_start(struct hfi1_devdata *dd); | |
502 | void sdma_exit(struct hfi1_devdata *dd); | |
503 | void sdma_all_running(struct hfi1_devdata *dd); | |
504 | void sdma_all_idle(struct hfi1_devdata *dd); | |
505 | void sdma_freeze_notify(struct hfi1_devdata *dd, int go_idle); | |
506 | void sdma_freeze(struct hfi1_devdata *dd); | |
507 | void sdma_unfreeze(struct hfi1_devdata *dd); | |
508 | void sdma_wait(struct hfi1_devdata *dd); | |
509 | ||
510 | /** | |
511 | * sdma_empty() - idle engine test | |
512 | * @engine: sdma engine | |
513 | * | |
514 | * Currently used by verbs as a latency optimization. | |
515 | * | |
516 | * Return: | |
517 | * 1 - empty, 0 - non-empty | |
518 | */ | |
519 | static inline int sdma_empty(struct sdma_engine *sde) | |
520 | { | |
521 | return sde->descq_tail == sde->descq_head; | |
522 | } | |
523 | ||
524 | static inline u16 sdma_descq_freecnt(struct sdma_engine *sde) | |
525 | { | |
526 | return sde->descq_cnt - | |
527 | (sde->descq_tail - | |
528 | ACCESS_ONCE(sde->descq_head)) - 1; | |
529 | } | |
530 | ||
531 | static inline u16 sdma_descq_inprocess(struct sdma_engine *sde) | |
532 | { | |
533 | return sde->descq_cnt - sdma_descq_freecnt(sde); | |
534 | } | |
535 | ||
536 | /* | |
537 | * Either head_lock or tail lock required to see | |
538 | * a steady state. | |
539 | */ | |
540 | static inline int __sdma_running(struct sdma_engine *engine) | |
541 | { | |
542 | return engine->state.current_state == sdma_state_s99_running; | |
543 | } | |
544 | ||
545 | ||
546 | /** | |
547 | * sdma_running() - state suitability test | |
548 | * @engine: sdma engine | |
549 | * | |
550 | * sdma_running probes the internal state to determine if it is suitable | |
551 | * for submitting packets. | |
552 | * | |
553 | * Return: | |
554 | * 1 - ok to submit, 0 - not ok to submit | |
555 | * | |
556 | */ | |
557 | static inline int sdma_running(struct sdma_engine *engine) | |
558 | { | |
559 | unsigned long flags; | |
560 | int ret; | |
561 | ||
562 | spin_lock_irqsave(&engine->tail_lock, flags); | |
563 | ret = __sdma_running(engine); | |
564 | spin_unlock_irqrestore(&engine->tail_lock, flags); | |
565 | return ret; | |
566 | } | |
567 | ||
568 | void _sdma_txreq_ahgadd( | |
569 | struct sdma_txreq *tx, | |
570 | u8 num_ahg, | |
571 | u8 ahg_entry, | |
572 | u32 *ahg, | |
573 | u8 ahg_hlen); | |
574 | ||
575 | ||
576 | /** | |
577 | * sdma_txinit_ahg() - initialize an sdma_txreq struct with AHG | |
578 | * @tx: tx request to initialize | |
579 | * @flags: flags to key last descriptor additions | |
580 | * @tlen: total packet length (pbc + headers + data) | |
581 | * @ahg_entry: ahg entry to use (0 - 31) | |
582 | * @num_ahg: ahg descriptor for first descriptor (0 - 9) | |
583 | * @ahg: array of AHG descriptors (up to 9 entries) | |
584 | * @ahg_hlen: number of bytes from ASIC entry to use | |
585 | * @cb: callback | |
586 | * | |
587 | * The allocation of the sdma_txreq and it enclosing structure is user | |
588 | * dependent. This routine must be called to initialize the user independent | |
589 | * fields. | |
590 | * | |
591 | * The currently supported flags are SDMA_TXREQ_F_URGENT, | |
592 | * SDMA_TXREQ_F_AHG_COPY, and SDMA_TXREQ_F_USE_AHG. | |
593 | * | |
594 | * SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the | |
595 | * completion is desired as soon as possible. | |
596 | * | |
597 | * SDMA_TXREQ_F_AHG_COPY causes the header in the first descriptor to be | |
598 | * copied to chip entry. SDMA_TXREQ_F_USE_AHG causes the code to add in | |
599 | * the AHG descriptors into the first 1 to 3 descriptors. | |
600 | * | |
601 | * Completions of submitted requests can be gotten on selected | |
602 | * txreqs by giving a completion routine callback to sdma_txinit() or | |
603 | * sdma_txinit_ahg(). The environment in which the callback runs | |
604 | * can be from an ISR, a tasklet, or a thread, so no sleeping | |
605 | * kernel routines can be used. Aspects of the sdma ring may | |
606 | * be locked so care should be taken with locking. | |
607 | * | |
608 | * The callback pointer can be NULL to avoid any callback for the packet | |
609 | * being submitted. The callback will be provided this tx, a status, and a flag. | |
610 | * | |
611 | * The status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR, | |
612 | * SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN. | |
613 | * | |
614 | * The flag, if the is the iowait had been used, indicates the iowait | |
615 | * sdma_busy count has reached zero. | |
616 | * | |
617 | * user data portion of tlen should be precise. The sdma_txadd_* entrances | |
618 | * will pad with a descriptor references 1 - 3 bytes when the number of bytes | |
619 | * specified in tlen have been supplied to the sdma_txreq. | |
620 | * | |
621 | * ahg_hlen is used to determine the number of on-chip entry bytes to | |
622 | * use as the header. This is for cases where the stored header is | |
623 | * larger than the header to be used in a packet. This is typical | |
624 | * for verbs where an RDMA_WRITE_FIRST is larger than the packet in | |
625 | * and RDMA_WRITE_MIDDLE. | |
626 | * | |
627 | */ | |
628 | static inline int sdma_txinit_ahg( | |
629 | struct sdma_txreq *tx, | |
630 | u16 flags, | |
631 | u16 tlen, | |
632 | u8 ahg_entry, | |
633 | u8 num_ahg, | |
634 | u32 *ahg, | |
635 | u8 ahg_hlen, | |
636 | void (*cb)(struct sdma_txreq *, int, int)) | |
637 | { | |
638 | if (tlen == 0) | |
639 | return -ENODATA; | |
640 | if (tlen > MAX_SDMA_PKT_SIZE) | |
641 | return -EMSGSIZE; | |
642 | tx->desc_limit = ARRAY_SIZE(tx->descs); | |
643 | tx->descp = &tx->descs[0]; | |
644 | INIT_LIST_HEAD(&tx->list); | |
645 | tx->num_desc = 0; | |
646 | tx->flags = flags; | |
647 | tx->complete = cb; | |
648 | tx->coalesce_buf = NULL; | |
649 | tx->wait = NULL; | |
650 | tx->tlen = tx->packet_len = tlen; | |
651 | tx->descs[0].qw[0] = SDMA_DESC0_FIRST_DESC_FLAG; | |
652 | tx->descs[0].qw[1] = 0; | |
653 | if (flags & SDMA_TXREQ_F_AHG_COPY) | |
654 | tx->descs[0].qw[1] |= | |
655 | (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK) | |
656 | << SDMA_DESC1_HEADER_INDEX_SHIFT) | | |
657 | (((u64)SDMA_AHG_COPY & SDMA_DESC1_HEADER_MODE_MASK) | |
658 | << SDMA_DESC1_HEADER_MODE_SHIFT); | |
659 | else if (flags & SDMA_TXREQ_F_USE_AHG && num_ahg) | |
660 | _sdma_txreq_ahgadd(tx, num_ahg, ahg_entry, ahg, ahg_hlen); | |
661 | return 0; | |
662 | } | |
663 | ||
664 | /** | |
665 | * sdma_txinit() - initialize an sdma_txreq struct (no AHG) | |
666 | * @tx: tx request to initialize | |
667 | * @flags: flags to key last descriptor additions | |
668 | * @tlen: total packet length (pbc + headers + data) | |
669 | * @cb: callback pointer | |
670 | * | |
671 | * The allocation of the sdma_txreq and it enclosing structure is user | |
672 | * dependent. This routine must be called to initialize the user | |
673 | * independent fields. | |
674 | * | |
675 | * The currently supported flags is SDMA_TXREQ_F_URGENT. | |
676 | * | |
677 | * SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the | |
678 | * completion is desired as soon as possible. | |
679 | * | |
680 | * Completions of submitted requests can be gotten on selected | |
681 | * txreqs by giving a completion routine callback to sdma_txinit() or | |
682 | * sdma_txinit_ahg(). The environment in which the callback runs | |
683 | * can be from an ISR, a tasklet, or a thread, so no sleeping | |
684 | * kernel routines can be used. The head size of the sdma ring may | |
685 | * be locked so care should be taken with locking. | |
686 | * | |
687 | * The callback pointer can be NULL to avoid any callback for the packet | |
688 | * being submitted. | |
689 | * | |
690 | * The callback, if non-NULL, will be provided this tx and a status. The | |
691 | * status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR, | |
692 | * SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN. | |
693 | * | |
694 | */ | |
695 | static inline int sdma_txinit( | |
696 | struct sdma_txreq *tx, | |
697 | u16 flags, | |
698 | u16 tlen, | |
699 | void (*cb)(struct sdma_txreq *, int, int)) | |
700 | { | |
701 | return sdma_txinit_ahg(tx, flags, tlen, 0, 0, NULL, 0, cb); | |
702 | } | |
703 | ||
704 | /* helpers - don't use */ | |
705 | static inline int sdma_mapping_type(struct sdma_desc *d) | |
706 | { | |
707 | return (d->qw[1] & SDMA_DESC1_GENERATION_SMASK) | |
708 | >> SDMA_DESC1_GENERATION_SHIFT; | |
709 | } | |
710 | ||
711 | static inline size_t sdma_mapping_len(struct sdma_desc *d) | |
712 | { | |
713 | return (d->qw[0] & SDMA_DESC0_BYTE_COUNT_SMASK) | |
714 | >> SDMA_DESC0_BYTE_COUNT_SHIFT; | |
715 | } | |
716 | ||
717 | static inline dma_addr_t sdma_mapping_addr(struct sdma_desc *d) | |
718 | { | |
719 | return (d->qw[0] & SDMA_DESC0_PHY_ADDR_SMASK) | |
720 | >> SDMA_DESC0_PHY_ADDR_SHIFT; | |
721 | } | |
722 | ||
723 | static inline void make_tx_sdma_desc( | |
724 | struct sdma_txreq *tx, | |
725 | int type, | |
726 | dma_addr_t addr, | |
727 | size_t len) | |
728 | { | |
729 | struct sdma_desc *desc = &tx->descp[tx->num_desc]; | |
730 | ||
731 | if (!tx->num_desc) { | |
732 | /* qw[0] zero; qw[1] first, ahg mode already in from init */ | |
733 | desc->qw[1] |= ((u64)type & SDMA_DESC1_GENERATION_MASK) | |
734 | << SDMA_DESC1_GENERATION_SHIFT; | |
735 | } else { | |
736 | desc->qw[0] = 0; | |
737 | desc->qw[1] = ((u64)type & SDMA_DESC1_GENERATION_MASK) | |
738 | << SDMA_DESC1_GENERATION_SHIFT; | |
739 | } | |
740 | desc->qw[0] |= (((u64)addr & SDMA_DESC0_PHY_ADDR_MASK) | |
741 | << SDMA_DESC0_PHY_ADDR_SHIFT) | | |
742 | (((u64)len & SDMA_DESC0_BYTE_COUNT_MASK) | |
743 | << SDMA_DESC0_BYTE_COUNT_SHIFT); | |
744 | } | |
745 | ||
746 | /* helper to extend txreq */ | |
f4d26d81 NV |
747 | int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx, |
748 | int type, void *kvaddr, struct page *page, | |
749 | unsigned long offset, u16 len); | |
77241056 MM |
750 | int _pad_sdma_tx_descs(struct hfi1_devdata *, struct sdma_txreq *); |
751 | void sdma_txclean(struct hfi1_devdata *, struct sdma_txreq *); | |
752 | ||
753 | /* helpers used by public routines */ | |
754 | static inline void _sdma_close_tx(struct hfi1_devdata *dd, | |
755 | struct sdma_txreq *tx) | |
756 | { | |
757 | tx->descp[tx->num_desc].qw[0] |= | |
758 | SDMA_DESC0_LAST_DESC_FLAG; | |
759 | tx->descp[tx->num_desc].qw[1] |= | |
760 | dd->default_desc1; | |
761 | if (tx->flags & SDMA_TXREQ_F_URGENT) | |
762 | tx->descp[tx->num_desc].qw[1] |= | |
763 | (SDMA_DESC1_HEAD_TO_HOST_FLAG| | |
764 | SDMA_DESC1_INT_REQ_FLAG); | |
765 | } | |
766 | ||
767 | static inline int _sdma_txadd_daddr( | |
768 | struct hfi1_devdata *dd, | |
769 | int type, | |
770 | struct sdma_txreq *tx, | |
771 | dma_addr_t addr, | |
772 | u16 len) | |
773 | { | |
774 | int rval = 0; | |
775 | ||
77241056 MM |
776 | make_tx_sdma_desc( |
777 | tx, | |
778 | type, | |
779 | addr, len); | |
780 | WARN_ON(len > tx->tlen); | |
781 | tx->tlen -= len; | |
782 | /* special cases for last */ | |
783 | if (!tx->tlen) { | |
a5a9e8cc | 784 | if (tx->packet_len & (sizeof(u32) - 1)) { |
77241056 | 785 | rval = _pad_sdma_tx_descs(dd, tx); |
a5a9e8cc MM |
786 | if (rval) |
787 | return rval; | |
788 | } else { | |
77241056 | 789 | _sdma_close_tx(dd, tx); |
a5a9e8cc | 790 | } |
77241056 MM |
791 | } |
792 | tx->num_desc++; | |
793 | return rval; | |
794 | } | |
795 | ||
796 | /** | |
797 | * sdma_txadd_page() - add a page to the sdma_txreq | |
798 | * @dd: the device to use for mapping | |
799 | * @tx: tx request to which the page is added | |
800 | * @page: page to map | |
801 | * @offset: offset within the page | |
802 | * @len: length in bytes | |
803 | * | |
804 | * This is used to add a page/offset/length descriptor. | |
805 | * | |
806 | * The mapping/unmapping of the page/offset/len is automatically handled. | |
807 | * | |
808 | * Return: | |
809 | * 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't | |
f4d26d81 | 810 | * extend/coalesce descriptor array |
77241056 MM |
811 | */ |
812 | static inline int sdma_txadd_page( | |
813 | struct hfi1_devdata *dd, | |
814 | struct sdma_txreq *tx, | |
815 | struct page *page, | |
816 | unsigned long offset, | |
817 | u16 len) | |
818 | { | |
f4d26d81 NV |
819 | dma_addr_t addr; |
820 | int rval; | |
821 | ||
822 | if ((unlikely(tx->num_desc == tx->desc_limit))) { | |
823 | rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_PAGE, | |
824 | NULL, page, offset, len); | |
825 | if (rval <= 0) | |
826 | return rval; | |
827 | } | |
828 | ||
829 | addr = dma_map_page( | |
830 | &dd->pcidev->dev, | |
831 | page, | |
832 | offset, | |
833 | len, | |
834 | DMA_TO_DEVICE); | |
835 | ||
77241056 MM |
836 | if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { |
837 | sdma_txclean(dd, tx); | |
838 | return -ENOSPC; | |
839 | } | |
f4d26d81 | 840 | |
77241056 MM |
841 | return _sdma_txadd_daddr( |
842 | dd, SDMA_MAP_PAGE, tx, addr, len); | |
843 | } | |
844 | ||
845 | /** | |
846 | * sdma_txadd_daddr() - add a dma address to the sdma_txreq | |
847 | * @dd: the device to use for mapping | |
848 | * @tx: sdma_txreq to which the page is added | |
849 | * @addr: dma address mapped by caller | |
850 | * @len: length in bytes | |
851 | * | |
852 | * This is used to add a descriptor for memory that is already dma mapped. | |
853 | * | |
854 | * In this case, there is no unmapping as part of the progress processing for | |
855 | * this memory location. | |
856 | * | |
857 | * Return: | |
858 | * 0 - success, -ENOMEM - couldn't extend descriptor array | |
859 | */ | |
860 | ||
861 | static inline int sdma_txadd_daddr( | |
862 | struct hfi1_devdata *dd, | |
863 | struct sdma_txreq *tx, | |
864 | dma_addr_t addr, | |
865 | u16 len) | |
866 | { | |
f4d26d81 NV |
867 | int rval; |
868 | ||
869 | if ((unlikely(tx->num_desc == tx->desc_limit))) { | |
870 | rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_NONE, | |
871 | NULL, NULL, 0, 0); | |
872 | if (rval <= 0) | |
873 | return rval; | |
874 | } | |
875 | ||
77241056 MM |
876 | return _sdma_txadd_daddr(dd, SDMA_MAP_NONE, tx, addr, len); |
877 | } | |
878 | ||
879 | /** | |
880 | * sdma_txadd_kvaddr() - add a kernel virtual address to sdma_txreq | |
881 | * @dd: the device to use for mapping | |
882 | * @tx: sdma_txreq to which the page is added | |
883 | * @kvaddr: the kernel virtual address | |
884 | * @len: length in bytes | |
885 | * | |
886 | * This is used to add a descriptor referenced by the indicated kvaddr and | |
887 | * len. | |
888 | * | |
889 | * The mapping/unmapping of the kvaddr and len is automatically handled. | |
890 | * | |
891 | * Return: | |
f4d26d81 | 892 | * 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't extend/coalesce |
77241056 MM |
893 | * descriptor array |
894 | */ | |
895 | static inline int sdma_txadd_kvaddr( | |
896 | struct hfi1_devdata *dd, | |
897 | struct sdma_txreq *tx, | |
898 | void *kvaddr, | |
899 | u16 len) | |
900 | { | |
f4d26d81 NV |
901 | dma_addr_t addr; |
902 | int rval; | |
903 | ||
904 | if ((unlikely(tx->num_desc == tx->desc_limit))) { | |
905 | rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_SINGLE, | |
906 | kvaddr, NULL, 0, len); | |
907 | if (rval <= 0) | |
908 | return rval; | |
909 | } | |
910 | ||
911 | addr = dma_map_single( | |
912 | &dd->pcidev->dev, | |
913 | kvaddr, | |
914 | len, | |
915 | DMA_TO_DEVICE); | |
916 | ||
77241056 MM |
917 | if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { |
918 | sdma_txclean(dd, tx); | |
919 | return -ENOSPC; | |
920 | } | |
f4d26d81 | 921 | |
77241056 MM |
922 | return _sdma_txadd_daddr( |
923 | dd, SDMA_MAP_SINGLE, tx, addr, len); | |
924 | } | |
925 | ||
926 | struct iowait; | |
927 | ||
928 | int sdma_send_txreq(struct sdma_engine *sde, | |
929 | struct iowait *wait, | |
930 | struct sdma_txreq *tx); | |
931 | int sdma_send_txlist(struct sdma_engine *sde, | |
932 | struct iowait *wait, | |
933 | struct list_head *tx_list); | |
934 | ||
935 | int sdma_ahg_alloc(struct sdma_engine *sde); | |
936 | void sdma_ahg_free(struct sdma_engine *sde, int ahg_index); | |
937 | ||
938 | /** | |
939 | * sdma_build_ahg - build ahg descriptor | |
940 | * @data | |
941 | * @dwindex | |
942 | * @startbit | |
943 | * @bits | |
944 | * | |
945 | * Build and return a 32 bit descriptor. | |
946 | */ | |
947 | static inline u32 sdma_build_ahg_descriptor( | |
948 | u16 data, | |
949 | u8 dwindex, | |
950 | u8 startbit, | |
951 | u8 bits) | |
952 | { | |
953 | return (u32)(1UL << SDMA_AHG_UPDATE_ENABLE_SHIFT | | |
954 | ((startbit & SDMA_AHG_FIELD_START_MASK) << | |
955 | SDMA_AHG_FIELD_START_SHIFT) | | |
956 | ((bits & SDMA_AHG_FIELD_LEN_MASK) << | |
957 | SDMA_AHG_FIELD_LEN_SHIFT) | | |
958 | ((dwindex & SDMA_AHG_INDEX_MASK) << | |
959 | SDMA_AHG_INDEX_SHIFT) | | |
960 | ((data & SDMA_AHG_VALUE_MASK) << | |
961 | SDMA_AHG_VALUE_SHIFT)); | |
962 | } | |
963 | ||
964 | /** | |
965 | * sdma_progress - use seq number of detect head progress | |
966 | * @sde: sdma_engine to check | |
967 | * @seq: base seq count | |
968 | * @tx: txreq for which we need to check descriptor availability | |
969 | * | |
970 | * This is used in the appropriate spot in the sleep routine | |
971 | * to check for potential ring progress. This routine gets the | |
972 | * seqcount before queuing the iowait structure for progress. | |
973 | * | |
974 | * If the seqcount indicates that progress needs to be checked, | |
975 | * re-submission is detected by checking whether the descriptor | |
976 | * queue has enough descriptor for the txreq. | |
977 | */ | |
978 | static inline unsigned sdma_progress(struct sdma_engine *sde, unsigned seq, | |
979 | struct sdma_txreq *tx) | |
980 | { | |
981 | if (read_seqretry(&sde->head_lock, seq)) { | |
982 | sde->desc_avail = sdma_descq_freecnt(sde); | |
983 | if (tx->num_desc > sde->desc_avail) | |
984 | return 0; | |
985 | return 1; | |
986 | } | |
987 | return 0; | |
988 | } | |
989 | ||
990 | /** | |
991 | * sdma_iowait_schedule() - initialize wait structure | |
992 | * @sde: sdma_engine to schedule | |
993 | * @wait: wait struct to schedule | |
994 | * | |
995 | * This function initializes the iowait | |
996 | * structure embedded in the QP or PQ. | |
997 | * | |
998 | */ | |
999 | static inline void sdma_iowait_schedule( | |
1000 | struct sdma_engine *sde, | |
1001 | struct iowait *wait) | |
1002 | { | |
0a226edd MM |
1003 | struct hfi1_pportdata *ppd = sde->dd->pport; |
1004 | ||
1005 | iowait_schedule(wait, ppd->hfi1_wq, sde->cpu); | |
77241056 MM |
1006 | } |
1007 | ||
1008 | /* for use by interrupt handling */ | |
1009 | void sdma_engine_error(struct sdma_engine *sde, u64 status); | |
1010 | void sdma_engine_interrupt(struct sdma_engine *sde, u64 status); | |
1011 | ||
1012 | /* | |
1013 | * | |
1014 | * The diagram below details the relationship of the mapping structures | |
1015 | * | |
1016 | * Since the mapping now allows for non-uniform engines per vl, the | |
1017 | * number of engines for a vl is either the vl_engines[vl] or | |
1018 | * a computation based on num_sdma/num_vls: | |
1019 | * | |
1020 | * For example: | |
1021 | * nactual = vl_engines ? vl_engines[vl] : num_sdma/num_vls | |
1022 | * | |
1023 | * n = roundup to next highest power of 2 using nactual | |
1024 | * | |
1025 | * In the case where there are num_sdma/num_vls doesn't divide | |
1026 | * evenly, the extras are added from the last vl downward. | |
1027 | * | |
1028 | * For the case where n > nactual, the engines are assigned | |
1029 | * in a round robin fashion wrapping back to the first engine | |
1030 | * for a particular vl. | |
1031 | * | |
1032 | * dd->sdma_map | |
1033 | * | sdma_map_elem[0] | |
1034 | * | +--------------------+ | |
1035 | * v | mask | | |
1036 | * sdma_vl_map |--------------------| | |
1037 | * +--------------------------+ | sde[0] -> eng 1 | | |
1038 | * | list (RCU) | |--------------------| | |
1039 | * |--------------------------| ->| sde[1] -> eng 2 | | |
1040 | * | mask | --/ |--------------------| | |
1041 | * |--------------------------| -/ | * | | |
1042 | * | actual_vls (max 8) | -/ |--------------------| | |
1043 | * |--------------------------| --/ | sde[n] -> eng n | | |
1044 | * | vls (max 8) | -/ +--------------------+ | |
1045 | * |--------------------------| --/ | |
1046 | * | map[0] |-/ | |
1047 | * |--------------------------| +--------------------+ | |
1048 | * | map[1] |--- | mask | | |
1049 | * |--------------------------| \---- |--------------------| | |
1050 | * | * | \-- | sde[0] -> eng 1+n | | |
1051 | * | * | \---- |--------------------| | |
1052 | * | * | \->| sde[1] -> eng 2+n | | |
1053 | * |--------------------------| |--------------------| | |
1054 | * | map[vls - 1] |- | * | | |
1055 | * +--------------------------+ \- |--------------------| | |
1056 | * \- | sde[m] -> eng m+n | | |
1057 | * \ +--------------------+ | |
1058 | * \- | |
1059 | * \ | |
1060 | * \- +--------------------+ | |
1061 | * \- | mask | | |
1062 | * \ |--------------------| | |
1063 | * \- | sde[0] -> eng 1+m+n| | |
1064 | * \- |--------------------| | |
1065 | * >| sde[1] -> eng 2+m+n| | |
1066 | * |--------------------| | |
1067 | * | * | | |
1068 | * |--------------------| | |
1069 | * | sde[o] -> eng o+m+n| | |
1070 | * +--------------------+ | |
1071 | * | |
1072 | */ | |
1073 | ||
1074 | /** | |
1075 | * struct sdma_map_elem - mapping for a vl | |
1076 | * @mask - selector mask | |
1077 | * @sde - array of engines for this vl | |
1078 | * | |
1079 | * The mask is used to "mod" the selector | |
1080 | * to produce index into the trailing | |
1081 | * array of sdes. | |
1082 | */ | |
1083 | struct sdma_map_elem { | |
1084 | u32 mask; | |
1085 | struct sdma_engine *sde[0]; | |
1086 | }; | |
1087 | ||
1088 | /** | |
1089 | * struct sdma_map_el - mapping for a vl | |
1090 | * @list - rcu head for free callback | |
1091 | * @mask - vl mask to "mod" the vl to produce an index to map array | |
1092 | * @actual_vls - number of vls | |
1093 | * @vls - number of vls rounded to next power of 2 | |
1094 | * @map - array of sdma_map_elem entries | |
1095 | * | |
1096 | * This is the parent mapping structure. The trailing | |
1097 | * members of the struct point to sdma_map_elem entries, which | |
1098 | * in turn point to an array of sde's for that vl. | |
1099 | */ | |
1100 | struct sdma_vl_map { | |
1101 | struct rcu_head list; | |
1102 | u32 mask; | |
1103 | u8 actual_vls; | |
1104 | u8 vls; | |
1105 | struct sdma_map_elem *map[0]; | |
1106 | }; | |
1107 | ||
1108 | int sdma_map_init( | |
1109 | struct hfi1_devdata *dd, | |
1110 | u8 port, | |
1111 | u8 num_vls, | |
1112 | u8 *vl_engines); | |
1113 | ||
1114 | /* slow path */ | |
1115 | void _sdma_engine_progress_schedule(struct sdma_engine *sde); | |
1116 | ||
1117 | /** | |
1118 | * sdma_engine_progress_schedule() - schedule progress on engine | |
1119 | * @sde: sdma_engine to schedule progress | |
1120 | * | |
1121 | * This is the fast path. | |
1122 | * | |
1123 | */ | |
1124 | static inline void sdma_engine_progress_schedule( | |
1125 | struct sdma_engine *sde) | |
1126 | { | |
1127 | if (!sde || sdma_descq_inprocess(sde) < (sde->descq_cnt / 8)) | |
1128 | return; | |
1129 | _sdma_engine_progress_schedule(sde); | |
1130 | } | |
1131 | ||
1132 | struct sdma_engine *sdma_select_engine_sc( | |
1133 | struct hfi1_devdata *dd, | |
1134 | u32 selector, | |
1135 | u8 sc5); | |
1136 | ||
1137 | struct sdma_engine *sdma_select_engine_vl( | |
1138 | struct hfi1_devdata *dd, | |
1139 | u32 selector, | |
1140 | u8 vl); | |
1141 | ||
1142 | void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *); | |
1143 | ||
1144 | #ifdef CONFIG_SDMA_VERBOSITY | |
1145 | void sdma_dumpstate(struct sdma_engine *); | |
1146 | #endif | |
1147 | static inline char *slashstrip(char *s) | |
1148 | { | |
1149 | char *r = s; | |
1150 | ||
1151 | while (*s) | |
1152 | if (*s++ == '/') | |
1153 | r = s; | |
1154 | return r; | |
1155 | } | |
1156 | ||
1157 | u16 sdma_get_descq_cnt(void); | |
1158 | ||
1159 | extern uint mod_num_sdma; | |
1160 | ||
1161 | void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid); | |
1162 | ||
1163 | #endif |