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Merge remote-tracking branch 'staging/staging-next'
[deliverable/linux.git] / drivers / staging / rtl8188eu / hal / usb_halinit.c
CommitLineData
d3f4b828
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
d3f4b828
LF		 14 ******************************************************************************/
15#define _HCI_HAL_INIT_C_
16
17#include <osdep_service.h>
18#include <drv_types.h>
19#include <rtw_efuse.h>
d6c28c23 20#include <fw.h>
d3f4b828
LF		 21#include <rtl8188e_hal.h>
22#include <rtl8188e_led.h>
23#include <rtw_iol.h>
d3f4b828 24#include <usb_hal.h>
ff8f35d8 25#include <phy.h>
d3f4b828 26
d3f4b828 27#define HAL_BB_ENABLE 1
d3f4b828
LF		 28
29static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe)
30{
31 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
32
33 switch (NumOutPipe) {
34 case 3:
35 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
36 haldata->OutEpNumber = 3;
37 break;
38 case 2:
39 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
40 haldata->OutEpNumber = 2;
41 break;
42 case 1:
43 haldata->OutEpQueueSel = TX_SELE_HQ;
44 haldata->OutEpNumber = 1;
45 break;
46 default:
47 break;
48 }
49 DBG_88E("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, haldata->OutEpQueueSel, haldata->OutEpNumber);
50}
51
52static bool HalUsbSetQueuePipeMapping8188EUsb(struct adapter *adapt, u8 NumInPipe, u8 NumOutPipe)
53{
54 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
55 bool result = false;
56
57 _ConfigNormalChipOutEP_8188E(adapt, NumOutPipe);
58
59 /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
ffc9b275
JB		 60 if (haldata->OutEpNumber == 1) {
61 if (NumInPipe != 1)
d3f4b828
LF		 62 return result;
63 }
64
65 /* All config other than above support one Bulk IN and one Interrupt IN. */
66
67 result = Hal_MappingOutPipe(adapt, NumOutPipe);
68
69 return result;
70}
71
7d962ca0 72void rtw_hal_chip_configure(struct adapter *adapt)
d3f4b828
LF		 73{
74 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
75 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt);
76
77 if (pdvobjpriv->ishighspeed)
78 haldata->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/* 512 bytes */
79 else
80 haldata->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/* 64 bytes */
81
82 haldata->interfaceIndex = pdvobjpriv->InterfaceNumber;
83
84 haldata->UsbTxAggMode = 1;
85 haldata->UsbTxAggDescNum = 0x6; /* only 4 bits */
86
87 haldata->UsbRxAggMode = USB_RX_AGG_DMA;/* USB_RX_AGG_DMA; */
88 haldata->UsbRxAggBlockCount = 8; /* unit : 512b */
89 haldata->UsbRxAggBlockTimeout = 0x6;
90 haldata->UsbRxAggPageCount = 48; /* uint :128 b 0x0A; 10 = MAX_RX_DMA_BUFFER_SIZE/2/haldata->UsbBulkOutSize */
91 haldata->UsbRxAggPageTimeout = 0x4; /* 6, absolute time = 34ms/(2^6) */
92
93 HalUsbSetQueuePipeMapping8188EUsb(adapt,
94 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
95}
96
ecee4947 97u32 rtw_hal_power_on(struct adapter *adapt)
d3f4b828
LF		 98{
99 u16 value16;
100 /* HW Power on sequence */
101 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
102 if (haldata->bMacPwrCtrlOn)
103 return _SUCCESS;
104
0e54dbd4 105 if (!rtl88eu_pwrseqcmdparsing(adapt, PWR_CUT_ALL_MSK,
876cbe23 106 Rtl8188E_NIC_PWR_ON_FLOW)) {
d3f4b828
LF		 107 DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__);
108 return _FAIL;
109 }
110
111 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
112 /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
9764ed04 113 usb_write16(adapt, REG_CR, 0x00); /* suggseted by zhouzhou, by page, 20111230 */
d3f4b828
LF		 114
115 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
551a3972 116 value16 = usb_read16(adapt, REG_CR);
d3f4b828
LF		 117 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
118 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
119 /* for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
120
9764ed04 121 usb_write16(adapt, REG_CR, value16);
d3f4b828
LF		 122 haldata->bMacPwrCtrlOn = true;
123
124 return _SUCCESS;
125}
126
127/* Shall USB interface init this? */
128static void _InitInterrupt(struct adapter *Adapter)
129{
130 u32 imr, imr_ex;
131 u8 usb_opt;
132 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
133
134 /* HISR write one to clear */
fc158079 135 usb_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
d3f4b828
LF		 136 /* HIMR - */
137 imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
fc158079 138 usb_write32(Adapter, REG_HIMR_88E, imr);
d3f4b828
LF		 139 haldata->IntrMask[0] = imr;
140
141 imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
fc158079 142 usb_write32(Adapter, REG_HIMRE_88E, imr_ex);
d3f4b828
LF		 143 haldata->IntrMask[1] = imr_ex;
144
145 /* REG_USB_SPECIAL_OPTION - BIT(4) */
146 /* 0; Use interrupt endpoint to upload interrupt pkt */
147 /* 1; Use bulk endpoint to upload interrupt pkt, */
c7b2e995 148 usb_opt = usb_read8(Adapter, REG_USB_SPECIAL_OPTION);
d3f4b828
LF		 149
150 if (!adapter_to_dvobj(Adapter)->ishighspeed)
151 usb_opt = usb_opt & (~INT_BULK_SEL);
152 else
153 usb_opt = usb_opt | (INT_BULK_SEL);
154
e76484d0 155 usb_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
d3f4b828
LF		 156}
157
158static void _InitQueueReservedPage(struct adapter *Adapter)
159{
160 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
161 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
162 u32 numHQ = 0;
163 u32 numLQ = 0;
164 u32 numNQ = 0;
165 u32 numPubQ;
166 u32 value32;
167 u8 value8;
168 bool bWiFiConfig = pregistrypriv->wifi_spec;
169
170 if (bWiFiConfig) {
171 if (haldata->OutEpQueueSel & TX_SELE_HQ)
172 numHQ = 0x29;
173
174 if (haldata->OutEpQueueSel & TX_SELE_LQ)
175 numLQ = 0x1C;
176
f43534b9 177 /* NOTE: This step shall be proceed before writing REG_RQPN. */
d3f4b828
LF		 178 if (haldata->OutEpQueueSel & TX_SELE_NQ)
179 numNQ = 0x1C;
180 value8 = (u8)_NPQ(numNQ);
e76484d0 181 usb_write8(Adapter, REG_RQPN_NPQ, value8);
d3f4b828
LF		 182
183 numPubQ = 0xA8 - numHQ - numLQ - numNQ;
184
185 /* TX DMA */
186 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
fc158079 187 usb_write32(Adapter, REG_RQPN, value32);
d3f4b828 188 } else {
9764ed04 189 usb_write16(Adapter, REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */
190 usb_write16(Adapter, REG_RQPN_NPQ, 0x0d);
fc158079 191 usb_write32(Adapter, REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */
d3f4b828
LF		 192 }
193}
194
195static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
196{
e76484d0 197 usb_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
198 usb_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
199 usb_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
200 usb_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
201 usb_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
d3f4b828
LF		 202}
203
204static void _InitPageBoundary(struct adapter *Adapter)
205{
206 /* RX Page Boundary */
207 /* */
208 u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
209
9764ed04 210 usb_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
d3f4b828
LF		 211}
212
213static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
214 u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
215 u16 hiQ)
216{
551a3972 217 u16 value16 = (usb_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
d3f4b828
LF		 218
219 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
220 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
221 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
222
9764ed04 223 usb_write16(Adapter, REG_TRXDMA_CTRL, value16);
d3f4b828
LF		 224}
225
226static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
227{
228 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
229
230 u16 value = 0;
231 switch (haldata->OutEpQueueSel) {
232 case TX_SELE_HQ:
233 value = QUEUE_HIGH;
234 break;
235 case TX_SELE_LQ:
236 value = QUEUE_LOW;
237 break;
238 case TX_SELE_NQ:
239 value = QUEUE_NORMAL;
240 break;
241 default:
242 break;
243 }
244 _InitNormalChipRegPriority(Adapter, value, value, value, value,
245 value, value);
246}
247
248static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
249{
250 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
251 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
252 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
253 u16 valueHi = 0;
254 u16 valueLow = 0;
255
256 switch (haldata->OutEpQueueSel) {
257 case (TX_SELE_HQ | TX_SELE_LQ):
258 valueHi = QUEUE_HIGH;
259 valueLow = QUEUE_LOW;
260 break;
261 case (TX_SELE_NQ | TX_SELE_LQ):
262 valueHi = QUEUE_NORMAL;
263 valueLow = QUEUE_LOW;
264 break;
265 case (TX_SELE_HQ | TX_SELE_NQ):
266 valueHi = QUEUE_HIGH;
267 valueLow = QUEUE_NORMAL;
268 break;
269 default:
270 break;
271 }
272
273 if (!pregistrypriv->wifi_spec) {
274 beQ = valueLow;
275 bkQ = valueLow;
276 viQ = valueHi;
277 voQ = valueHi;
278 mgtQ = valueHi;
279 hiQ = valueHi;
280 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
281 beQ = valueLow;
282 bkQ = valueHi;
283 viQ = valueHi;
284 voQ = valueLow;
285 mgtQ = valueHi;
286 hiQ = valueHi;
287 }
288 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
289}
290
291static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
292{
293 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
294 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
295
296 if (!pregistrypriv->wifi_spec) {/* typical setting */
297 beQ = QUEUE_LOW;
298 bkQ = QUEUE_LOW;
299 viQ = QUEUE_NORMAL;
300 voQ = QUEUE_HIGH;
301 mgtQ = QUEUE_HIGH;
302 hiQ = QUEUE_HIGH;
303 } else {/* for WMM */
304 beQ = QUEUE_LOW;
305 bkQ = QUEUE_NORMAL;
306 viQ = QUEUE_NORMAL;
307 voQ = QUEUE_HIGH;
308 mgtQ = QUEUE_HIGH;
309 hiQ = QUEUE_HIGH;
310 }
311 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
312}
313
314static void _InitQueuePriority(struct adapter *Adapter)
315{
316 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
317
318 switch (haldata->OutEpNumber) {
319 case 1:
320 _InitNormalChipOneOutEpPriority(Adapter);
321 break;
322 case 2:
323 _InitNormalChipTwoOutEpPriority(Adapter);
324 break;
325 case 3:
326 _InitNormalChipThreeOutEpPriority(Adapter);
327 break;
328 default:
329 break;
330 }
331}
332
333static void _InitNetworkType(struct adapter *Adapter)
334{
335 u32 value32;
336
99ecfb06 337 value32 = usb_read32(Adapter, REG_CR);
d3f4b828
LF		 338 /* TODO: use the other function to set network type */
339 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
340
fc158079 341 usb_write32(Adapter, REG_CR, value32);
d3f4b828
LF		 342}
343
344static void _InitTransferPageSize(struct adapter *Adapter)
345{
346 /* Tx page size is always 128. */
347
348 u8 value8;
349 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
e76484d0 350 usb_write8(Adapter, REG_PBP, value8);
d3f4b828
LF		 351}
352
353static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
354{
e76484d0 355 usb_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
d3f4b828
LF		 356}
357
358static void _InitWMACSetting(struct adapter *Adapter)
359{
360 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
361
362 haldata->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
363 RCR_CBSSID_DATA | RCR_CBSSID_BCN |
364 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
365 RCR_APP_MIC | RCR_APP_PHYSTS;
366
367 /* some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */
fc158079 368 usb_write32(Adapter, REG_RCR, haldata->ReceiveConfig);
d3f4b828
LF		 369
370 /* Accept all multicast address */
fc158079 371 usb_write32(Adapter, REG_MAR, 0xFFFFFFFF);
372 usb_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
d3f4b828
LF		 373}
374
375static void _InitAdaptiveCtrl(struct adapter *Adapter)
376{
377 u16 value16;
378 u32 value32;
379
380 /* Response Rate Set */
99ecfb06 381 value32 = usb_read32(Adapter, REG_RRSR);
d3f4b828
LF		 382 value32 &= ~RATE_BITMAP_ALL;
383 value32 |= RATE_RRSR_CCK_ONLY_1M;
fc158079 384 usb_write32(Adapter, REG_RRSR, value32);
d3f4b828
LF		 385
386 /* CF-END Threshold */
387
388 /* SIFS (used in NAV) */
389 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
9764ed04 390 usb_write16(Adapter, REG_SPEC_SIFS, value16);
d3f4b828
LF		 391
392 /* Retry Limit */
393 value16 = _LRL(0x30) | _SRL(0x30);
9764ed04 394 usb_write16(Adapter, REG_RL, value16);
d3f4b828
LF		 395}
396
397static void _InitEDCA(struct adapter *Adapter)
398{
399 /* Set Spec SIFS (used in NAV) */
9764ed04 400 usb_write16(Adapter, REG_SPEC_SIFS, 0x100a);
401 usb_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
d3f4b828
LF		 402
403 /* Set SIFS for CCK */
9764ed04 404 usb_write16(Adapter, REG_SIFS_CTX, 0x100a);
d3f4b828
LF		 405
406 /* Set SIFS for OFDM */
9764ed04 407 usb_write16(Adapter, REG_SIFS_TRX, 0x100a);
d3f4b828
LF		 408
409 /* TXOP */
fc158079 410 usb_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
411 usb_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
412 usb_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
413 usb_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
d3f4b828
LF		 414}
415
d3f4b828
LF		 416static void _InitRDGSetting(struct adapter *Adapter)
417{
e76484d0 418 usb_write8(Adapter, REG_RD_CTRL, 0xFF);
9764ed04 419 usb_write16(Adapter, REG_RD_NAV_NXT, 0x200);
e76484d0 420 usb_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
d3f4b828
LF		 421}
422
423static void _InitRxSetting(struct adapter *Adapter)
424{
fc158079 425 usb_write32(Adapter, REG_MACID, 0x87654321);
426 usb_write32(Adapter, 0x0700, 0x87654321);
d3f4b828
LF		 427}
428
429static void _InitRetryFunction(struct adapter *Adapter)
430{
431 u8 value8;
432
c7b2e995 433 value8 = usb_read8(Adapter, REG_FWHW_TXQ_CTRL);
d3f4b828 434 value8 |= EN_AMPDU_RTY_NEW;
e76484d0 435 usb_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
d3f4b828
LF		 436
437 /* Set ACK timeout */
e76484d0 438 usb_write8(Adapter, REG_ACKTO, 0x40);
d3f4b828
LF		 439}
440
441/*-----------------------------------------------------------------------------
442 * Function: usb_AggSettingTxUpdate()
443 *
5e809e50 444 * Overview: Separate TX/RX parameters update independent for TP detection and
d3f4b828
LF		 445 * dynamic TX/RX aggreagtion parameters update.
446 *
447 * Input: struct adapter *
448 *
449 * Output/Return: NONE
450 *
451 * Revised History:
452 * When Who Remark
5e809e50 453 * 12/10/2010 MHC Separate to smaller function.
d3f4b828 454 *
637642e2
JB		 455 *---------------------------------------------------------------------------
456 */
d3f4b828
LF		 457static void usb_AggSettingTxUpdate(struct adapter *Adapter)
458{
459 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
460 u32 value32;
461
462 if (Adapter->registrypriv.wifi_spec)
463 haldata->UsbTxAggMode = false;
464
465 if (haldata->UsbTxAggMode) {
99ecfb06 466 value32 = usb_read32(Adapter, REG_TDECTRL);
d3f4b828
LF		 467 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
468 value32 |= ((haldata->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
469
fc158079 470 usb_write32(Adapter, REG_TDECTRL, value32);
d3f4b828
LF		 471 }
472} /* usb_AggSettingTxUpdate */
473
474/*-----------------------------------------------------------------------------
475 * Function: usb_AggSettingRxUpdate()
476 *
5e809e50 477 * Overview: Separate TX/RX parameters update independent for TP detection and
d3f4b828
LF		 478 * dynamic TX/RX aggreagtion parameters update.
479 *
480 * Input: struct adapter *
481 *
482 * Output/Return: NONE
483 *
484 * Revised History:
485 * When Who Remark
5e809e50 486 * 12/10/2010 MHC Separate to smaller function.
d3f4b828 487 *
637642e2
JB		 488 *---------------------------------------------------------------------------
489 */
d3f4b828
LF		 490static void
491usb_AggSettingRxUpdate(
492 struct adapter *Adapter
493 )
494{
495 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
496 u8 valueDMA;
497 u8 valueUSB;
498
c7b2e995 499 valueDMA = usb_read8(Adapter, REG_TRXDMA_CTRL);
500 valueUSB = usb_read8(Adapter, REG_USB_SPECIAL_OPTION);
d3f4b828
LF		 501
502 switch (haldata->UsbRxAggMode) {
503 case USB_RX_AGG_DMA:
504 valueDMA |= RXDMA_AGG_EN;
505 valueUSB &= ~USB_AGG_EN;
506 break;
507 case USB_RX_AGG_USB:
508 valueDMA &= ~RXDMA_AGG_EN;
509 valueUSB |= USB_AGG_EN;
510 break;
511 case USB_RX_AGG_MIX:
512 valueDMA |= RXDMA_AGG_EN;
513 valueUSB |= USB_AGG_EN;
514 break;
515 case USB_RX_AGG_DISABLE:
516 default:
517 valueDMA &= ~RXDMA_AGG_EN;
518 valueUSB &= ~USB_AGG_EN;
519 break;
520 }
521
e76484d0 522 usb_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
523 usb_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
d3f4b828
LF		 524
525 switch (haldata->UsbRxAggMode) {
526 case USB_RX_AGG_DMA:
e76484d0 527 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
528 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, haldata->UsbRxAggPageTimeout);
d3f4b828
LF		 529 break;
530 case USB_RX_AGG_USB:
e76484d0 531 usb_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
532 usb_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
d3f4b828
LF		 533 break;
534 case USB_RX_AGG_MIX:
e76484d0 535 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
536 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (haldata->UsbRxAggPageTimeout & 0x1F));/* 0x280[12:8] */
537 usb_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
538 usb_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
d3f4b828
LF		 539 break;
540 case USB_RX_AGG_DISABLE:
541 default:
542 /* TODO: */
543 break;
544 }
545
546 switch (PBP_128) {
547 case PBP_128:
548 haldata->HwRxPageSize = 128;
549 break;
550 case PBP_64:
551 haldata->HwRxPageSize = 64;
552 break;
553 case PBP_256:
554 haldata->HwRxPageSize = 256;
555 break;
556 case PBP_512:
557 haldata->HwRxPageSize = 512;
558 break;
559 case PBP_1024:
560 haldata->HwRxPageSize = 1024;
561 break;
562 default:
563 break;
564 }
565} /* usb_AggSettingRxUpdate */
566
567static void InitUsbAggregationSetting(struct adapter *Adapter)
568{
569 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
570
571 /* Tx aggregation setting */
572 usb_AggSettingTxUpdate(Adapter);
573
574 /* Rx aggregation setting */
575 usb_AggSettingRxUpdate(Adapter);
576
577 /* 201/12/10 MH Add for USB agg mode dynamic switch. */
578 haldata->UsbRxHighSpeedMode = false;
579}
580
d3f4b828
LF		 581static void _InitBeaconParameters(struct adapter *Adapter)
582{
583 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
584
9764ed04 585 usb_write16(Adapter, REG_BCN_CTRL, 0x1010);
d3f4b828
LF		 586
587 /* TODO: Remove these magic number */
9764ed04 588 usb_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */
e76484d0 589 usb_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/* 5ms */
590 usb_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /* 2ms */
d3f4b828
LF		 591
592 /* Suggested by designer timchen. Change beacon AIFS to the largest number */
593 /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
9764ed04 594 usb_write16(Adapter, REG_BCNTCFG, 0x660F);
d3f4b828 595
c7b2e995 596 haldata->RegBcnCtrlVal = usb_read8(Adapter, REG_BCN_CTRL);
597 haldata->RegTxPause = usb_read8(Adapter, REG_TXPAUSE);
598 haldata->RegFwHwTxQCtrl = usb_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
599 haldata->RegReg542 = usb_read8(Adapter, REG_TBTT_PROHIBIT+2);
600 haldata->RegCR_1 = usb_read8(Adapter, REG_CR+1);
d3f4b828
LF		 601}
602
603static void _BeaconFunctionEnable(struct adapter *Adapter,
604 bool Enable, bool Linked)
605{
9c68ed09 606 usb_write8(Adapter, REG_BCN_CTRL, (BIT(4) | BIT(3) | BIT(1)));
d3f4b828 607
e76484d0 608 usb_write8(Adapter, REG_RD_CTRL+1, 0x6F);
d3f4b828
LF		 609}
610
611/* Set CCK and OFDM Block "ON" */
612static void _BBTurnOnBlock(struct adapter *Adapter)
613{
9c6db651 614 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
615 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
d3f4b828
LF		 616}
617
618enum {
619 Antenna_Lfet = 1,
620 Antenna_Right = 2,
621};
622
623static void _InitAntenna_Selection(struct adapter *Adapter)
624{
625 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
626
627 if (haldata->AntDivCfg == 0)
628 return;
629 DBG_88E("==> %s ....\n", __func__);
630
9c68ed09
AB		 631 usb_write32(Adapter, REG_LEDCFG0, usb_read32(Adapter, REG_LEDCFG0) | BIT(23));
632 phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01);
d3f4b828 633
ecd1f9b3 634 if (phy_query_bb_reg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
d3f4b828
LF		 635 haldata->CurAntenna = Antenna_A;
636 else
637 haldata->CurAntenna = Antenna_B;
638 DBG_88E("%s,Cur_ant:(%x)%s\n", __func__, haldata->CurAntenna, (haldata->CurAntenna == Antenna_A) ? "Antenna_A" : "Antenna_B");
639}
640
641/*-----------------------------------------------------------------------------
642 * Function: HwSuspendModeEnable92Cu()
643 *
644 * Overview: HW suspend mode switch.
645 *
646 * Input: NONE
647 *
648 * Output: NONE
649 *
650 * Return: NONE
651 *
652 * Revised History:
653 * When Who Remark
654 * 08/23/2010 MHC HW suspend mode switch test..
637642e2
JB		 655 *---------------------------------------------------------------------------
656 */
d3f4b828
LF		 657enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
658{
659 u8 val8;
660 enum rt_rf_power_state rfpowerstate = rf_off;
661
662 if (adapt->pwrctrlpriv.bHWPowerdown) {
c7b2e995 663 val8 = usb_read8(adapt, REG_HSISR);
9c68ed09
AB		 664 DBG_88E("pwrdown, 0x5c(BIT(7))=%02x\n", val8);
665 rfpowerstate = (val8 & BIT(7)) ? rf_off : rf_on;
d3f4b828 666 } else { /* rf on/off */
9c68ed09 667 usb_write8(adapt, REG_MAC_PINMUX_CFG, usb_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT(3)));
c7b2e995 668 val8 = usb_read8(adapt, REG_GPIO_IO_SEL);
d3f4b828 669 DBG_88E("GPIO_IN=%02x\n", val8);
9c68ed09 670 rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off;
d3f4b828
LF		 671 }
672 return rfpowerstate;
673} /* HalDetectPwrDownMode */
674
dbc1917a 675u32 rtl8188eu_hal_init(struct adapter *Adapter)
d3f4b828
LF		 676{
677 u8 value8 = 0;
678 u16 value16;
679 u8 txpktbuf_bndy;
680 u32 status = _SUCCESS;
681 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
682 struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
683 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
ed737494 684 unsigned long init_start_time = jiffies;
d3f4b828
LF		 685
686 #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
687
d3f4b828
LF		 688 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
689
690 if (Adapter->pwrctrlpriv.bkeepfwalive) {
d3f4b828 691 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
0ffb6503 692 rtl88eu_phy_iq_calibrate(Adapter, true);
d3f4b828 693 } else {
0ffb6503 694 rtl88eu_phy_iq_calibrate(Adapter, false);
d3f4b828
LF		 695 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
696 }
697
698 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
0cf81f67 699 rtl88eu_phy_lc_calibrate(Adapter);
d3f4b828
LF		 700
701 goto exit;
702 }
703
704 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
ecee4947 705 status = rtw_hal_power_on(Adapter);
d3f4b828
LF		 706 if (status == _FAIL) {
707 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
708 goto exit;
709 }
710
711 /* Save target channel */
712 haldata->CurrentChannel = 6;/* default set to 6 */
713
a48d498b 714 if (pwrctrlpriv->reg_rfoff)
d3f4b828 715 pwrctrlpriv->rf_pwrstate = rf_off;
d3f4b828
LF		 716
717 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
718 /* HW GPIO pin. Before PHY_RFConfig8192C. */
719 /* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
720
721 if (!pregistrypriv->wifi_spec) {
722 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
723 } else {
724 /* for WMM */
725 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
726 }
727
728 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
729 _InitQueueReservedPage(Adapter);
730 _InitQueuePriority(Adapter);
731 _InitPageBoundary(Adapter);
732 _InitTransferPageSize(Adapter);
733
734 _InitTxBufferBoundary(Adapter, 0);
735
736 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
737 if (Adapter->registrypriv.mp_mode == 1) {
738 _InitRxSetting(Adapter);
739 Adapter->bFWReady = false;
d3f4b828 740 } else {
90d88de8 741 status = rtl88eu_download_fw(Adapter);
d3f4b828 742
d6c28c23 743 if (status) {
d3f4b828
LF		 744 DBG_88E("%s: Download Firmware failed!!\n", __func__);
745 Adapter->bFWReady = false;
d3f4b828 746 return status;
d3f4b828 747 }
a634696e
JB		 748 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializeadapt8192CSdio(): Download Firmware Success!!\n"));
749 Adapter->bFWReady = true;
d3f4b828
LF		 750 }
751 rtl8188e_InitializeFirmwareVars(Adapter);
752
90d88de8 753 rtl88eu_phy_mac_config(Adapter);
d3f4b828 754
90d88de8 755 rtl88eu_phy_bb_config(Adapter);
d3f4b828 756
90d88de8 757 rtl88eu_phy_rf_config(Adapter);
d3f4b828
LF		 758
759 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
760 status = rtl8188e_iol_efuse_patch(Adapter);
761 if (status == _FAIL) {
762 DBG_88E("%s rtl8188e_iol_efuse_patch failed\n", __func__);
763 goto exit;
764 }
765
766 _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
767
768 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
769 status = InitLLTTable(Adapter, txpktbuf_bndy);
770 if (status == _FAIL) {
771 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
772 goto exit;
773 }
774
775 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
776 /* Get Rx PHY status in order to report RSSI and others. */
777 _InitDriverInfoSize(Adapter, DRVINFO_SZ);
778
779 _InitInterrupt(Adapter);
780 hal_init_macaddr(Adapter);/* set mac_address */
781 _InitNetworkType(Adapter);/* set msr */
782 _InitWMACSetting(Adapter);
783 _InitAdaptiveCtrl(Adapter);
784 _InitEDCA(Adapter);
785 _InitRetryFunction(Adapter);
786 InitUsbAggregationSetting(Adapter);
d3f4b828 787 _InitBeaconParameters(Adapter);
d3f4b828 788 /* Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */
5e809e50 789 /* Hw bug which Hw initials RxFF boundary size to a value which is larger than the real Rx buffer size in 88E. */
d3f4b828 790 /* Enable MACTXEN/MACRXEN block */
551a3972 791 value16 = usb_read16(Adapter, REG_CR);
d3f4b828 792 value16 |= (MACTXEN | MACRXEN);
e76484d0 793 usb_write8(Adapter, REG_CR, value16);
d3f4b828
LF		 794
795 if (haldata->bRDGEnable)
796 _InitRDGSetting(Adapter);
797
798 /* Enable TX Report */
799 /* Enable Tx Report Timer */
c7b2e995 800 value8 = usb_read8(Adapter, REG_TX_RPT_CTRL);
9c68ed09 801 usb_write8(Adapter, REG_TX_RPT_CTRL, (value8 | BIT(1) | BIT(0)));
d3f4b828 802 /* Set MAX RPT MACID */
e76484d0 803 usb_write8(Adapter, REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
d3f4b828 804 /* Tx RPT Timer. Unit: 32us */
9764ed04 805 usb_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
d3f4b828 806
e76484d0 807 usb_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
d3f4b828 808
9764ed04 809 usb_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
810 usb_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
d3f4b828 811
d3f4b828 812 /* Keep RfRegChnlVal for later use. */
76098bcb
IS		 813 haldata->RfRegChnlVal[0] = rtw_hal_read_rfreg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
814 haldata->RfRegChnlVal[1] = rtw_hal_read_rfreg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
d3f4b828
LF		 815
816HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
817 _BBTurnOnBlock(Adapter);
818
819HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
820 invalidate_cam_all(Adapter);
821
822HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
823 /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */
01c5f833 824 phy_set_tx_power_level(Adapter, haldata->CurrentChannel);
d3f4b828
LF		 825
826/* Move by Neo for USB SS to below setp */
827/* _RfPowerSave(Adapter); */
828
829 _InitAntenna_Selection(Adapter);
830
831 /* */
832 /* Disable BAR, suggested by Scott */
833 /* 2010.04.09 add by hpfan */
834 /* */
fc158079 835 usb_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
d3f4b828
LF		 836
837 /* HW SEQ CTRL */
838 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
e76484d0 839 usb_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
d3f4b828
LF		 840
841 if (pregistrypriv->wifi_spec)
9764ed04 842 usb_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
d3f4b828
LF		 843
844 /* Nav limit , suggest by scott */
e76484d0 845 usb_write8(Adapter, 0x652, 0x0);
d3f4b828
LF		 846
847HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
848 rtl8188e_InitHalDm(Adapter);
849
0cccd45f 850 /* 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */
851 /* and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */
852 /* call initstruct adapter. May cause some problem?? */
853 /* Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */
854 /* in MgntActSet_RF_State() after wake up, because the value of haldata->eRFPowerState */
855 /* is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */
856 /* Added by tynli. 2010.03.30. */
857 pwrctrlpriv->rf_pwrstate = rf_on;
d3f4b828 858
0cccd45f 859 /* enable Tx report. */
860 usb_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F);
d3f4b828 861
0cccd45f 862 /* Suggested by SD1 pisa. Added by tynli. 2011.10.21. */
863 usb_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);/* Pretx_en, for WEP/TKIP SEC */
d3f4b828 864
0cccd45f 865 /* tynli_test_tx_report. */
866 usb_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
d3f4b828 867
0cccd45f 868 /* enable tx DMA to drop the redundate data of packet */
869 usb_write16(Adapter, REG_TXDMA_OFFSET_CHK, (usb_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
d3f4b828
LF		 870
871HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
872 /* 2010/08/26 MH Merge from 8192CE. */
0cccd45f 873 if (pwrctrlpriv->rf_pwrstate == rf_on) {
874 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
a305990d 875 rtl88eu_phy_iq_calibrate(Adapter, true);
0cccd45f 876 } else {
0ffb6503 877 rtl88eu_phy_iq_calibrate(Adapter, false);
0cccd45f 878 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
879 }
d3f4b828
LF		 880
881HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
882
0cccd45f 883 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
d3f4b828
LF		 884
885HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
0cf81f67 886 rtl88eu_phy_lc_calibrate(Adapter);
d3f4b828
LF		 887 }
888
889/* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */
890/* _InitPABias(Adapter); */
e76484d0 891 usb_write8(Adapter, REG_USB_HRPWM, 0);
d3f4b828
LF		 892
893 /* ack for xmit mgmt frames. */
9c68ed09 894 usb_write32(Adapter, REG_FWHW_TXQ_CTRL, usb_read32(Adapter, REG_FWHW_TXQ_CTRL) | BIT(12));
d3f4b828
LF		 895
896exit:
897HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
898
ed737494
RO		 899 DBG_88E("%s in %dms\n", __func__,
900 jiffies_to_msecs(jiffies - init_start_time));
d3f4b828 901
d3f4b828
LF		 902 return status;
903}
904
d3f4b828
LF		 905static void CardDisableRTL8188EU(struct adapter *Adapter)
906{
907 u8 val8;
908 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
909
910 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CardDisableRTL8188EU\n"));
911
912 /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
c7b2e995 913 val8 = usb_read8(Adapter, REG_TX_RPT_CTRL);
9c68ed09 914 usb_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT(1)));
d3f4b828
LF		 915
916 /* stop rx */
e76484d0 917 usb_write8(Adapter, REG_CR, 0x0);
d3f4b828
LF		 918
919 /* Run LPS WL RFOFF flow */
0e54dbd4 920 rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK,
876cbe23 921 Rtl8188E_NIC_LPS_ENTER_FLOW);
d3f4b828
LF		 922
923 /* 2. 0x1F[7:0] = 0 turn off RF */
924
c7b2e995 925 val8 = usb_read8(Adapter, REG_MCUFWDL);
d3f4b828
LF		 926 if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) { /* 8051 RAM code */
927 /* Reset MCU 0x2[10]=0. */
c7b2e995 928 val8 = usb_read8(Adapter, REG_SYS_FUNC_EN+1);
d3f4b828 929 val8 &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
e76484d0 930 usb_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
d3f4b828
LF		 931 }
932
933 /* reset MCU ready status */
e76484d0 934 usb_write8(Adapter, REG_MCUFWDL, 0);
d3f4b828
LF		 935
936 /* YJ,add,111212 */
937 /* Disable 32k */
c7b2e995 938 val8 = usb_read8(Adapter, REG_32K_CTRL);
9c68ed09 939 usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT(0)));
d3f4b828
LF		 940
941 /* Card disable power action flow */
0e54dbd4 942 rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK,
876cbe23 943 Rtl8188E_NIC_DISABLE_FLOW);
d3f4b828
LF		 944
945 /* Reset MCU IO Wrapper */
c7b2e995 946 val8 = usb_read8(Adapter, REG_RSV_CTRL+1);
9c68ed09 947 usb_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT(3))));
c7b2e995 948 val8 = usb_read8(Adapter, REG_RSV_CTRL+1);
9c68ed09 949 usb_write8(Adapter, REG_RSV_CTRL+1, val8 | BIT(3));
d3f4b828
LF		 950
951 /* YJ,test add, 111207. For Power Consumption. */
c7b2e995 952 val8 = usb_read8(Adapter, GPIO_IN);
e76484d0 953 usb_write8(Adapter, GPIO_OUT, val8);
954 usb_write8(Adapter, GPIO_IO_SEL, 0xFF);/* Reg0x46 */
d3f4b828 955
c7b2e995 956 val8 = usb_read8(Adapter, REG_GPIO_IO_SEL);
e76484d0 957 usb_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
c7b2e995 958 val8 = usb_read8(Adapter, REG_GPIO_IO_SEL+1);
e76484d0 959 usb_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);/* Reg0x43 */
fc158079 960 usb_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */
d3f4b828
LF		 961 haldata->bMacPwrCtrlOn = false;
962 Adapter->bFWReady = false;
963}
99f8adc4 964
d3f4b828
LF		 965static void rtl8192cu_hw_power_down(struct adapter *adapt)
966{
967 /* 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. */
968 /* Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. */
969
970 /* Enable register area 0x0-0xc. */
e76484d0 971 usb_write8(adapt, REG_RSV_CTRL, 0x0);
9764ed04 972 usb_write16(adapt, REG_APS_FSMCO, 0x8812);
d3f4b828
LF		 973}
974
b1e120a5 975u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
d3f4b828 976{
d3f4b828
LF		 977 DBG_88E("==> %s\n", __func__);
978
fc158079 979 usb_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
980 usb_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
d3f4b828
LF		 981
982 DBG_88E("bkeepfwalive(%x)\n", Adapter->pwrctrlpriv.bkeepfwalive);
983 if (Adapter->pwrctrlpriv.bkeepfwalive) {
d3f4b828
LF		 984 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
985 rtl8192cu_hw_power_down(Adapter);
986 } else {
987 if (Adapter->hw_init_completed) {
988 CardDisableRTL8188EU(Adapter);
989
990 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
991 rtl8192cu_hw_power_down(Adapter);
992 }
993 }
994 return _SUCCESS;
9cb2dbf3 995}
d3f4b828 996
09ebc91e 997u32 rtw_hal_inirp_init(struct adapter *Adapter)
d3f4b828
LF		 998{
999 u8 i;
1000 struct recv_buf *precvbuf;
1001 uint status;
d5fdbca6 1002 struct recv_priv *precvpriv = &Adapter->recvpriv;
d3f4b828
LF		 1003
1004 status = _SUCCESS;
1005
1006 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1007 ("===> usb_inirp_init\n"));
1008
1009 precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1010
1011 /* issue Rx irp to receive data */
1012 precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1013 for (i = 0; i < NR_RECVBUFF; i++) {
2478a1ce 1014 if (usb_read_port(Adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == false) {
d3f4b828
LF		 1015 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_port error\n"));
1016 status = _FAIL;
1017 goto exit;
1018 }
1019
1020 precvbuf++;
1021 precvpriv->free_recv_buf_queue_cnt--;
1022 }
1023
1024exit:
1025
1026 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<=== usb_inirp_init\n"));
1027
d3f4b828
LF		 1028
1029 return status;
1030}
1031
d3f4b828
LF		 1032/* */
1033/* */
1034/* EEPROM/EFUSE Content Parsing */
1035/* */
1036/* */
d3f4b828
LF		 1037static void Hal_EfuseParsePIDVID_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1038{
1039 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1040
1041 if (!AutoLoadFail) {
1042 /* VID, PID */
1043 haldata->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]);
1044 haldata->EEPROMPID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_PID_88EU]);
1045
1046 /* Customer ID, 0x00 and 0xff are reserved for Realtek. */
1047 haldata->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E];
1048 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1049 } else {
1050 haldata->EEPROMVID = EEPROM_Default_VID;
1051 haldata->EEPROMPID = EEPROM_Default_PID;
1052
1053 /* Customer ID, 0x00 and 0xff are reserved for Realtek. */
1054 haldata->EEPROMCustomerID = EEPROM_Default_CustomerID;
1055 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1056 }
1057
1058 DBG_88E("VID = 0x%04X, PID = 0x%04X\n", haldata->EEPROMVID, haldata->EEPROMPID);
1059 DBG_88E("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", haldata->EEPROMCustomerID, haldata->EEPROMSubCustomerID);
1060}
1061
1062static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1063{
1064 u16 i;
1065 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
1066 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1067
1068 if (AutoLoadFail) {
1069 for (i = 0; i < 6; i++)
1070 eeprom->mac_addr[i] = sMacAddr[i];
1071 } else {
1072 /* Read Permanent MAC address */
1073 memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
1074 }
1075 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
789fd7ad
MK		 1076 ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %pM\n",
1077 eeprom->mac_addr));
d3f4b828
LF		 1078}
1079
d3f4b828
LF		 1080static void
1081readAdapterInfo_8188EU(
1082 struct adapter *adapt
1083 )
1084{
1085 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1086
1087 /* parse the eeprom/efuse content */
1088 Hal_EfuseParseIDCode88E(adapt, eeprom->efuse_eeprom_data);
1089 Hal_EfuseParsePIDVID_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1090 Hal_EfuseParseMACAddr_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1091
1092 Hal_ReadPowerSavingMode88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1093 Hal_ReadTxPowerInfo88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1094 Hal_EfuseParseEEPROMVer88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1095 rtl8188e_EfuseParseChnlPlan(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1096 Hal_EfuseParseXtal_8188E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1097 Hal_EfuseParseCustomerID88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1098 Hal_ReadAntennaDiversity88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1099 Hal_EfuseParseBoardType88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1100 Hal_ReadThermalMeter_88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
d3f4b828
LF		 1101}
1102
1103static void _ReadPROMContent(
1104 struct adapter *Adapter
1105 )
1106{
1107 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(Adapter);
1108 u8 eeValue;
1109
1110 /* check system boot selection */
c7b2e995 1111 eeValue = usb_read8(Adapter, REG_9346CR);
d3f4b828
LF		 1112 eeprom->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1113 eeprom->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1114
1115 DBG_88E("Boot from %s, Autoload %s !\n", (eeprom->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1116 (eeprom->bautoload_fail_flag ? "Fail" : "OK"));
1117
1118 Hal_InitPGData88E(Adapter);
1119 readAdapterInfo_8188EU(Adapter);
1120}
1121
1122static void _ReadRFType(struct adapter *Adapter)
1123{
1124 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1125
1126 haldata->rf_chip = RF_6052;
1127}
1128
61e0c324 1129void rtw_hal_read_chip_info(struct adapter *Adapter)
d3f4b828 1130{
ed737494 1131 unsigned long start = jiffies;
d3f4b828
LF		 1132
1133 MSG_88E("====> %s\n", __func__);
1134
1135 _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
1136 _ReadPROMContent(Adapter);
1137
ed737494
RO		 1138 MSG_88E("<==== %s in %d ms\n", __func__,
1139 jiffies_to_msecs(jiffies - start));
d3f4b828
LF		 1140}
1141
1142#define GPIO_DEBUG_PORT_NUM 0
1143static void rtl8192cu_trigger_gpio_0(struct adapter *adapt)
1144{
1145}
1146
1147static void ResumeTxBeacon(struct adapter *adapt)
1148{
1149 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1150
1151 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1152 /* which should be read from register to a global variable. */
1153
9c68ed09
AB		 1154 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT(6));
1155 haldata->RegFwHwTxQCtrl |= BIT(6);
e76484d0 1156 usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0xff);
9c68ed09 1157 haldata->RegReg542 |= BIT(0);
e76484d0 1158 usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
d3f4b828
LF		 1159}
1160
1161static void StopTxBeacon(struct adapter *adapt)
1162{
1163 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1164
1165 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1166 /* which should be read from register to a global variable. */
1167
9c68ed09
AB		 1168 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT(6)));
1169 haldata->RegFwHwTxQCtrl &= (~BIT(6));
e76484d0 1170 usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0x64);
9c68ed09 1171 haldata->RegReg542 &= ~(BIT(0));
e76484d0 1172 usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
d3f4b828
LF		 1173
1174 /* todo: CheckFwRsvdPageContent(Adapter); 2010.06.23. Added by tynli. */
1175}
1176
1177static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val)
1178{
1179 u8 val8;
1180 u8 mode = *((u8 *)val);
1181
1182 /* disable Port0 TSF update */
9c68ed09 1183 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4));
d3f4b828
LF		 1184
1185 /* set net_type */
c7b2e995 1186 val8 = usb_read8(Adapter, MSR)&0x0c;
d3f4b828 1187 val8 |= mode;
e76484d0 1188 usb_write8(Adapter, MSR, val8);
d3f4b828
LF		 1189
1190 DBG_88E("%s()-%d mode = %d\n", __func__, __LINE__, mode);
1191
1192 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
1193 StopTxBeacon(Adapter);
1194
e76484d0 1195 usb_write8(Adapter, REG_BCN_CTRL, 0x19);/* disable atim wnd */
d5fdbca6 1196 } else if (mode == _HW_STATE_ADHOC_) {
d3f4b828 1197 ResumeTxBeacon(Adapter);
e76484d0 1198 usb_write8(Adapter, REG_BCN_CTRL, 0x1a);
d3f4b828
LF		 1199 } else if (mode == _HW_STATE_AP_) {
1200 ResumeTxBeacon(Adapter);
1201
e76484d0 1202 usb_write8(Adapter, REG_BCN_CTRL, 0x12);
d3f4b828
LF		 1203
1204 /* Set RCR */
fc158079 1205 usb_write32(Adapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0,reject ICV_ERR packet */
d3f4b828 1206 /* enable to rx data frame */
9764ed04 1207 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
d3f4b828 1208 /* enable to rx ps-poll */
9764ed04 1209 usb_write16(Adapter, REG_RXFLTMAP1, 0x0400);
d3f4b828
LF		 1210
1211 /* Beacon Control related register for first time */
e76484d0 1212 usb_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */
d3f4b828 1213
e76484d0 1214 usb_write8(Adapter, REG_ATIMWND, 0x0a); /* 10ms */
9764ed04 1215 usb_write16(Adapter, REG_BCNTCFG, 0x00);
1216 usb_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
1217 usb_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
d3f4b828
LF		 1218
1219 /* reset TSF */
e76484d0 1220 usb_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
d3f4b828
LF		 1221
1222 /* BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 */
c7b2e995 1223 usb_write8(Adapter, REG_MBID_NUM, usb_read8(Adapter, REG_MBID_NUM) | BIT(3) | BIT(4));
d3f4b828
LF		 1224
1225 /* enable BCN0 Function for if1 */
1226 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
e76484d0 1227 usb_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | BIT(1)));
d3f4b828
LF		 1228
1229 /* dis BCN1 ATIM WND if if2 is station */
c7b2e995 1230 usb_write8(Adapter, REG_BCN_CTRL_1, usb_read8(Adapter, REG_BCN_CTRL_1) | BIT(0));
d3f4b828
LF		 1231 }
1232}
1233
1234static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8 *val)
1235{
1236 u8 idx = 0;
1237 u32 reg_macid;
1238
1239 reg_macid = REG_MACID;
1240
1241 for (idx = 0; idx < 6; idx++)
e76484d0 1242 usb_write8(Adapter, (reg_macid+idx), val[idx]);
d3f4b828
LF		 1243}
1244
1245static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8 *val)
1246{
1247 u8 idx = 0;
1248 u32 reg_bssid;
1249
1250 reg_bssid = REG_BSSID;
1251
1252 for (idx = 0; idx < 6; idx++)
e76484d0 1253 usb_write8(Adapter, (reg_bssid+idx), val[idx]);
d3f4b828
LF		 1254}
1255
1256static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8 *val)
1257{
1258 u32 bcn_ctrl_reg;
1259
1260 bcn_ctrl_reg = REG_BCN_CTRL;
1261
1262 if (*((u8 *)val))
e76484d0 1263 usb_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
d3f4b828 1264 else
c7b2e995 1265 usb_write8(Adapter, bcn_ctrl_reg, usb_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
d3f4b828
LF		 1266}
1267
655266d5 1268void rtw_hal_set_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
d3f4b828
LF		 1269{
1270 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1271 struct dm_priv *pdmpriv = &haldata->dmpriv;
1272 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
d3f4b828
LF		 1273
1274 switch (variable) {
1275 case HW_VAR_MEDIA_STATUS:
1276 {
1277 u8 val8;
1278
c7b2e995 1279 val8 = usb_read8(Adapter, MSR)&0x0c;
d3f4b828 1280 val8 |= *((u8 *)val);
e76484d0 1281 usb_write8(Adapter, MSR, val8);
d3f4b828
LF		 1282 }
1283 break;
1284 case HW_VAR_MEDIA_STATUS1:
1285 {
1286 u8 val8;
1287
c7b2e995 1288 val8 = usb_read8(Adapter, MSR) & 0x03;
d3f4b828 1289 val8 |= *((u8 *)val) << 2;
e76484d0 1290 usb_write8(Adapter, MSR, val8);
d3f4b828
LF		 1291 }
1292 break;
1293 case HW_VAR_SET_OPMODE:
1294 hw_var_set_opmode(Adapter, variable, val);
1295 break;
1296 case HW_VAR_MAC_ADDR:
1297 hw_var_set_macaddr(Adapter, variable, val);
1298 break;
1299 case HW_VAR_BSSID:
1300 hw_var_set_bssid(Adapter, variable, val);
1301 break;
1302 case HW_VAR_BASIC_RATE:
1303 {
1304 u16 BrateCfg = 0;
1305 u8 RateIndex = 0;
1306
1307 /* 2007.01.16, by Emily */
1308 /* Select RRSR (in Legacy-OFDM and CCK) */
1309 /* For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. */
1310 /* We do not use other rates. */
1311 HalSetBrateCfg(Adapter, val, &BrateCfg);
1312 DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
1313
1314 /* 2011.03.30 add by Luke Lee */
1315 /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */
1316 /* because CCK 2M has poor TXEVM */
1317 /* CCK 5.5M & 11M ACK should be enabled for better performance */
1318
1319 BrateCfg = (BrateCfg | 0xd) & 0x15d;
1320 haldata->BasicRateSet = BrateCfg;
1321
1322 BrateCfg |= 0x01; /* default enable 1M ACK rate */
1323 /* Set RRSR rate table. */
e76484d0 1324 usb_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
1325 usb_write8(Adapter, REG_RRSR+1, (BrateCfg >> 8) & 0xff);
c7b2e995 1326 usb_write8(Adapter, REG_RRSR+2, usb_read8(Adapter, REG_RRSR+2)&0xf0);
d3f4b828
LF		 1327
1328 /* Set RTS initial rate */
1329 while (BrateCfg > 0x1) {
945f0185 1330 BrateCfg >>= 1;
d3f4b828
LF		 1331 RateIndex++;
1332 }
1333 /* Ziv - Check */
e76484d0 1334 usb_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
d3f4b828
LF		 1335 }
1336 break;
1337 case HW_VAR_TXPAUSE:
e76484d0 1338 usb_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
d3f4b828
LF		 1339 break;
1340 case HW_VAR_BCN_FUNC:
1341 hw_var_set_bcn_func(Adapter, variable, val);
1342 break;
1343 case HW_VAR_CORRECT_TSF:
1344 {
1345 u64 tsf;
1346 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
d5fdbca6 1347 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
d3f4b828
LF		 1348
1349 tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) - 1024; /* us */
1350
1351 if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1352 StopTxBeacon(Adapter);
1353
1354 /* disable related TSF function */
c7b2e995 1355 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
d3f4b828 1356
fc158079 1357 usb_write32(Adapter, REG_TSFTR, tsf);
1358 usb_write32(Adapter, REG_TSFTR+4, tsf>>32);
d3f4b828
LF		 1359
1360 /* enable related TSF function */
9c68ed09 1361 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(3));
d3f4b828
LF		 1362
1363 if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1364 ResumeTxBeacon(Adapter);
1365 }
1366 break;
1367 case HW_VAR_CHECK_BSSID:
1368 if (*((u8 *)val)) {
99ecfb06 1369 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
d3f4b828
LF		 1370 } else {
1371 u32 val32;
1372
99ecfb06 1373 val32 = usb_read32(Adapter, REG_RCR);
d3f4b828
LF		 1374
1375 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1376
fc158079 1377 usb_write32(Adapter, REG_RCR, val32);
d3f4b828
LF		 1378 }
1379 break;
1380 case HW_VAR_MLME_DISCONNECT:
1381 /* Set RCR to not to receive data frame when NO LINK state */
1382 /* reject all data frames */
9764ed04 1383 usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
d3f4b828
LF		 1384
1385 /* reset TSF */
9c68ed09 1386 usb_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
d3f4b828
LF		 1387
1388 /* disable update TSF */
9c68ed09 1389 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4));
d3f4b828
LF		 1390 break;
1391 case HW_VAR_MLME_SITESURVEY:
1392 if (*((u8 *)val)) { /* under sitesurvey */
1393 /* config RCR to receive different BSSID & not to receive data frame */
99ecfb06 1394 u32 v = usb_read32(Adapter, REG_RCR);
d3f4b828 1395 v &= ~(RCR_CBSSID_BCN);
fc158079 1396 usb_write32(Adapter, REG_RCR, v);
d3f4b828 1397 /* reject all data frame */
9764ed04 1398 usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
d3f4b828
LF		 1399
1400 /* disable update TSF */
9c68ed09 1401 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4));
d3f4b828
LF		 1402 } else { /* sitesurvey done */
1403 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
d5fdbca6 1404 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
d3f4b828
LF		 1405
1406 if ((is_client_associated_to_ap(Adapter)) ||
1407 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) {
1408 /* enable to rx data frame */
9764ed04 1409 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
d3f4b828
LF		 1410
1411 /* enable update TSF */
c7b2e995 1412 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
d3f4b828 1413 } else if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
9764ed04 1414 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
d3f4b828 1415 /* enable update TSF */
c7b2e995 1416 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
d3f4b828 1417 }
2104905a
IS		 1418
1419 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
d3f4b828
LF		 1420 }
1421 break;
1422 case HW_VAR_MLME_JOIN:
1423 {
1424 u8 RetryLimit = 0x30;
1425 u8 type = *((u8 *)val);
1426 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1427
1428 if (type == 0) { /* prepare to join */
1429 /* enable to rx data frame.Accept all data frame */
9764ed04 1430 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
d3f4b828 1431
2104905a 1432 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
d3f4b828
LF		 1433
1434 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
1435 RetryLimit = (haldata->CustomerID == RT_CID_CCX) ? 7 : 48;
1436 else /* Ad-hoc Mode */
1437 RetryLimit = 0x7;
1438 } else if (type == 1) {
1439 /* joinbss_event call back when join res < 0 */
9764ed04 1440 usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
d3f4b828
LF		 1441 } else if (type == 2) {
1442 /* sta add event call back */
1443 /* enable update TSF */
c7b2e995 1444 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
d3f4b828
LF		 1445
1446 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
1447 RetryLimit = 0x7;
1448 }
9764ed04 1449 usb_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
d3f4b828
LF		 1450 }
1451 break;
1452 case HW_VAR_BEACON_INTERVAL:
9764ed04 1453 usb_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
d3f4b828
LF		 1454 break;
1455 case HW_VAR_SLOT_TIME:
1456 {
1457 u8 u1bAIFS, aSifsTime;
1458 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
d5fdbca6 1459 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
d3f4b828 1460
e76484d0 1461 usb_write8(Adapter, REG_SLOT, val[0]);
d3f4b828
LF		 1462
1463 if (pmlmeinfo->WMM_enable == 0) {
1464 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
1465 aSifsTime = 10;
1466 else
1467 aSifsTime = 16;
1468
1469 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
1470
1471 /* <Roger_EXP> Temporary removed, 2008.06.20. */
e76484d0 1472 usb_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
1473 usb_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
1474 usb_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
1475 usb_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
d3f4b828
LF		 1476 }
1477 }
1478 break;
1479 case HW_VAR_RESP_SIFS:
1480 /* RESP_SIFS for CCK */
e76484d0 1481 usb_write8(Adapter, REG_R2T_SIFS, val[0]); /* SIFS_T2T_CCK (0x08) */
1482 usb_write8(Adapter, REG_R2T_SIFS+1, val[1]); /* SIFS_R2T_CCK(0x08) */
d3f4b828 1483 /* RESP_SIFS for OFDM */
e76484d0 1484 usb_write8(Adapter, REG_T2T_SIFS, val[2]); /* SIFS_T2T_OFDM (0x0a) */
1485 usb_write8(Adapter, REG_T2T_SIFS+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
d3f4b828
LF		 1486 break;
1487 case HW_VAR_ACK_PREAMBLE:
1488 {
1489 u8 regTmp;
1490 u8 bShortPreamble = *((bool *)val);
1491 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
1492 regTmp = (haldata->nCur40MhzPrimeSC)<<5;
1493 if (bShortPreamble)
1494 regTmp |= 0x80;
1495
e76484d0 1496 usb_write8(Adapter, REG_RRSR+2, regTmp);
d3f4b828
LF		 1497 }
1498 break;
1499 case HW_VAR_SEC_CFG:
e76484d0 1500 usb_write8(Adapter, REG_SECCFG, *((u8 *)val));
d3f4b828
LF		 1501 break;
1502 case HW_VAR_DM_FLAG:
1503 podmpriv->SupportAbility = *((u8 *)val);
1504 break;
1505 case HW_VAR_DM_FUNC_OP:
1506 if (val[0])
1507 podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
1508 else
1509 podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
1510 break;
1511 case HW_VAR_DM_FUNC_SET:
1512 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1513 pdmpriv->DMFlag = pdmpriv->InitDMFlag;
1514 podmpriv->SupportAbility = pdmpriv->InitODMFlag;
1515 } else {
1516 podmpriv->SupportAbility |= *((u32 *)val);
1517 }
1518 break;
1519 case HW_VAR_DM_FUNC_CLR:
1520 podmpriv->SupportAbility &= *((u32 *)val);
1521 break;
1522 case HW_VAR_CAM_EMPTY_ENTRY:
1523 {
1524 u8 ucIndex = *((u8 *)val);
1525 u8 i;
1526 u32 ulCommand = 0;
1527 u32 ulContent = 0;
1528 u32 ulEncAlgo = CAM_AES;
1529
1530 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
1531 /* filled id in CAM config 2 byte */
1532 if (i == 0)
1533 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
1534 else
1535 ulContent = 0;
1536 /* polling bit, and No Write enable, and address */
1537 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
1538 ulCommand = ulCommand | CAM_POLLINIG|CAM_WRITE;
1539 /* write content 0 is equall to mark invalid */
fc158079 1540 usb_write32(Adapter, WCAMI, ulContent); /* delay_ms(40); */
1541 usb_write32(Adapter, RWCAM, ulCommand); /* delay_ms(40); */
d3f4b828
LF		 1542 }
1543 }
1544 break;
1545 case HW_VAR_CAM_INVALID_ALL:
9c68ed09 1546 usb_write32(Adapter, RWCAM, BIT(31) | BIT(30));
d3f4b828
LF		 1547 break;
1548 case HW_VAR_CAM_WRITE:
1549 {
1550 u32 cmd;
1551 u32 *cam_val = (u32 *)val;
fc158079 1552 usb_write32(Adapter, WCAMI, cam_val[0]);
d3f4b828
LF		 1553
1554 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
fc158079 1555 usb_write32(Adapter, RWCAM, cmd);
d3f4b828
LF		 1556 }
1557 break;
1558 case HW_VAR_AC_PARAM_VO:
fc158079 1559 usb_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
d3f4b828
LF		 1560 break;
1561 case HW_VAR_AC_PARAM_VI:
fc158079 1562 usb_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
d3f4b828
LF		 1563 break;
1564 case HW_VAR_AC_PARAM_BE:
1565 haldata->AcParam_BE = ((u32 *)(val))[0];
fc158079 1566 usb_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
d3f4b828
LF		 1567 break;
1568 case HW_VAR_AC_PARAM_BK:
fc158079 1569 usb_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
d3f4b828
LF		 1570 break;
1571 case HW_VAR_ACM_CTRL:
1572 {
1573 u8 acm_ctrl = *((u8 *)val);
c7b2e995 1574 u8 AcmCtrl = usb_read8(Adapter, REG_ACMHWCTRL);
d3f4b828
LF		 1575
1576 if (acm_ctrl > 1)
1577 AcmCtrl = AcmCtrl | 0x1;
1578
1579 if (acm_ctrl & BIT(3))
1580 AcmCtrl |= AcmHw_VoqEn;
1581 else
1582 AcmCtrl &= (~AcmHw_VoqEn);
1583
1584 if (acm_ctrl & BIT(2))
1585 AcmCtrl |= AcmHw_ViqEn;
1586 else
1587 AcmCtrl &= (~AcmHw_ViqEn);
1588
1589 if (acm_ctrl & BIT(1))
1590 AcmCtrl |= AcmHw_BeqEn;
1591 else
1592 AcmCtrl &= (~AcmHw_BeqEn);
1593
1594 DBG_88E("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
e76484d0 1595 usb_write8(Adapter, REG_ACMHWCTRL, AcmCtrl);
d3f4b828
LF		 1596 }
1597 break;
1598 case HW_VAR_AMPDU_MIN_SPACE:
1599 {
1600 u8 MinSpacingToSet;
1601 u8 SecMinSpace;
1602
1603 MinSpacingToSet = *((u8 *)val);
1604 if (MinSpacingToSet <= 7) {
1605 switch (Adapter->securitypriv.dot11PrivacyAlgrthm) {
1606 case _NO_PRIVACY_:
1607 case _AES_:
1608 SecMinSpace = 0;
1609 break;
1610 case _WEP40_:
1611 case _WEP104_:
1612 case _TKIP_:
1613 case _TKIP_WTMIC_:
1614 SecMinSpace = 6;
1615 break;
1616 default:
1617 SecMinSpace = 7;
1618 break;
1619 }
1620 if (MinSpacingToSet < SecMinSpace)
1621 MinSpacingToSet = SecMinSpace;
c7b2e995 1622 usb_write8(Adapter, REG_AMPDU_MIN_SPACE, (usb_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
d3f4b828
LF		 1623 }
1624 }
1625 break;
1626 case HW_VAR_AMPDU_FACTOR:
1627 {
1628 u8 RegToSet_Normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1629 u8 FactorToSet;
1630 u8 *pRegToSet;
1631 u8 index = 0;
1632
1633 pRegToSet = RegToSet_Normal; /* 0xb972a841; */
1634 FactorToSet = *((u8 *)val);
1635 if (FactorToSet <= 3) {
1d06bb4e 1636 FactorToSet = 1 << (FactorToSet + 2);
d3f4b828
LF		 1637 if (FactorToSet > 0xf)
1638 FactorToSet = 0xf;
1639
1640 for (index = 0; index < 4; index++) {
1641 if ((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
1642 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
1643
1644 if ((pRegToSet[index] & 0x0f) > FactorToSet)
1645 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
1646
e76484d0 1647 usb_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
d3f4b828
LF		 1648 }
1649 }
1650 }
1651 break;
1652 case HW_VAR_RXDMA_AGG_PG_TH:
1653 {
1654 u8 threshold = *((u8 *)val);
1655 if (threshold == 0)
1656 threshold = haldata->UsbRxAggPageCount;
e76484d0 1657 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
d3f4b828
LF		 1658 }
1659 break;
1660 case HW_VAR_SET_RPWM:
1661 break;
1662 case HW_VAR_H2C_FW_PWRMODE:
1663 {
1664 u8 psmode = (*(u8 *)val);
1665
1666 /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
1667 /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
e827aeed 1668 if (psmode != PS_MODE_ACTIVE)
d3f4b828
LF		 1669 ODM_RF_Saving(podmpriv, true);
1670 rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
1671 }
1672 break;
1673 case HW_VAR_H2C_FW_JOINBSSRPT:
1674 {
1675 u8 mstatus = (*(u8 *)val);
1676 rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
1677 }
1678 break;
d3f4b828
LF		 1679 case HW_VAR_INITIAL_GAIN:
1680 {
1681 struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
1682 u32 rx_gain = ((u32 *)(val))[0];
1683
1684 if (rx_gain == 0xff) {/* restore rx gain */
1685 ODM_Write_DIG(podmpriv, pDigTable->BackupIGValue);
1686 } else {
1687 pDigTable->BackupIGValue = pDigTable->CurIGValue;
1688 ODM_Write_DIG(podmpriv, rx_gain);
1689 }
1690 }
1691 break;
1692 case HW_VAR_TRIGGER_GPIO_0:
1693 rtl8192cu_trigger_gpio_0(Adapter);
1694 break;
1695 case HW_VAR_RPT_TIMER_SETTING:
1696 {
1697 u16 min_rpt_time = (*(u16 *)val);
1698 ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
1699 }
1700 break;
1701 case HW_VAR_ANTENNA_DIVERSITY_SELECT:
1702 {
1703 u8 Optimum_antenna = (*(u8 *)val);
1704 u8 Ant;
1705 /* switch antenna to Optimum_antenna */
1706 if (haldata->CurAntenna != Optimum_antenna) {
1707 Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT;
052a806d 1708 rtl88eu_dm_update_rx_idle_ant(&haldata->odmpriv, Ant);
d3f4b828
LF		 1709
1710 haldata->CurAntenna = Optimum_antenna;
1711 }
1712 }
1713 break;
1714 case HW_VAR_EFUSE_BYTES: /* To set EFUE total used bytes, added by Roger, 2008.12.22. */
1715 haldata->EfuseUsedBytes = *((u16 *)val);
1716 break;
1717 case HW_VAR_FIFO_CLEARN_UP:
1718 {
1719 struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
1720 u8 trycnt = 100;
1721
1722 /* pause tx */
e76484d0 1723 usb_write8(Adapter, REG_TXPAUSE, 0xff);
d3f4b828
LF		 1724
1725 /* keep sn */
551a3972 1726 Adapter->xmitpriv.nqos_ssn = usb_read16(Adapter, REG_NQOS_SEQ);
d3f4b828
LF		 1727
1728 if (!pwrpriv->bkeepfwalive) {
1729 /* RX DMA stop */
99ecfb06 1730 usb_write32(Adapter, REG_RXPKT_NUM, (usb_read32(Adapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
d3f4b828 1731 do {
99ecfb06 1732 if (!(usb_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE))
d3f4b828
LF		 1733 break;
1734 } while (trycnt--);
1735 if (trycnt == 0)
1736 DBG_88E("Stop RX DMA failed......\n");
1737
1738 /* RQPN Load 0 */
9764ed04 1739 usb_write16(Adapter, REG_RQPN_NPQ, 0x0);
fc158079 1740 usb_write32(Adapter, REG_RQPN, 0x80000000);
4063642b 1741 mdelay(10);
d3f4b828
LF		 1742 }
1743 }
1744 break;
1745 case HW_VAR_CHECK_TXBUF:
1746 break;
1747 case HW_VAR_APFM_ON_MAC:
1748 haldata->bMacPwrCtrlOn = *val;
1749 DBG_88E("%s: bMacPwrCtrlOn=%d\n", __func__, haldata->bMacPwrCtrlOn);
1750 break;
1751 case HW_VAR_TX_RPT_MAX_MACID:
1752 {
1753 u8 maxMacid = *val;
1754 DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid+1);
e76484d0 1755 usb_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
d3f4b828
LF		 1756 }
1757 break;
1758 case HW_VAR_H2C_MEDIA_STATUS_RPT:
9cb2dbf3 1759 rtl8188e_set_FwMediaStatus_cmd(Adapter, (*(__le16 *)val));
d3f4b828
LF		 1760 break;
1761 case HW_VAR_BCN_VALID:
1762 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
9c68ed09 1763 usb_write8(Adapter, REG_TDECTRL+2, usb_read8(Adapter, REG_TDECTRL+2) | BIT(0));
d3f4b828
LF		 1764 break;
1765 default:
1766 break;
1767 }
d3f4b828
LF		 1768}
1769
385b452c 1770void rtw_hal_get_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
d3f4b828
LF		 1771{
1772 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1773 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
d3f4b828
LF		 1774
1775 switch (variable) {
1776 case HW_VAR_BASIC_RATE:
1777 *((u16 *)(val)) = haldata->BasicRateSet;
1778 case HW_VAR_TXPAUSE:
c7b2e995 1779 val[0] = usb_read8(Adapter, REG_TXPAUSE);
d3f4b828
LF		 1780 break;
1781 case HW_VAR_BCN_VALID:
1782 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
9c68ed09 1783 val[0] = (BIT(0) & usb_read8(Adapter, REG_TDECTRL+2)) ? true : false;
d3f4b828
LF		 1784 break;
1785 case HW_VAR_DM_FLAG:
1786 val[0] = podmpriv->SupportAbility;
1787 break;
1788 case HW_VAR_RF_TYPE:
1789 val[0] = haldata->rf_type;
1790 break;
1791 case HW_VAR_FWLPS_RF_ON:
1792 {
1793 /* When we halt NIC, we should check if FW LPS is leave. */
1794 if (Adapter->pwrctrlpriv.rf_pwrstate == rf_off) {
1795 /* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
1796 /* because Fw is unload. */
1797 val[0] = true;
1798 } else {
1799 u32 valRCR;
99ecfb06 1800 valRCR = usb_read32(Adapter, REG_RCR);
d3f4b828
LF		 1801 valRCR &= 0x00070000;
1802 if (valRCR)
1803 val[0] = false;
1804 else
1805 val[0] = true;
1806 }
1807 }
1808 break;
1809 case HW_VAR_CURRENT_ANTENNA:
1810 val[0] = haldata->CurAntenna;
1811 break;
1812 case HW_VAR_EFUSE_BYTES: /* To get EFUE total used bytes, added by Roger, 2008.12.22. */
1813 *((u16 *)(val)) = haldata->EfuseUsedBytes;
1814 break;
1815 case HW_VAR_APFM_ON_MAC:
1816 *val = haldata->bMacPwrCtrlOn;
1817 break;
1818 case HW_VAR_CHK_HI_QUEUE_EMPTY:
99ecfb06 1819 *val = ((usb_read32(Adapter, REG_HGQ_INFORMATION)&0x0000ff00) == 0) ? true : false;
d3f4b828
LF		 1820 break;
1821 default:
1822 break;
1823 }
d3f4b828
LF		 1824}
1825
1826/* */
1827/* Description: */
1828/* Query setting of specified variable. */
1829/* */
359d9612 1830u8 rtw_hal_get_def_var(
d3f4b828
LF		 1831 struct adapter *Adapter,
1832 enum hal_def_variable eVariable,
1833 void *pValue
1834 )
1835{
1836 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1837 u8 bResult = _SUCCESS;
1838
1839 switch (eVariable) {
1840 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1841 {
1842 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1843 struct sta_priv *pstapriv = &Adapter->stapriv;
1844 struct sta_info *psta;
1845 psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1846 if (psta)
1847 *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1848 }
1849 break;
1850 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1851 *((u8 *)pValue) = (haldata->AntDivCfg == 0) ? false : true;
1852 break;
1853 case HAL_DEF_CURRENT_ANTENNA:
1854 *((u8 *)pValue) = haldata->CurAntenna;
1855 break;
1856 case HAL_DEF_DRVINFO_SZ:
1857 *((u32 *)pValue) = DRVINFO_SZ;
1858 break;
1859 case HAL_DEF_MAX_RECVBUF_SZ:
1860 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1861 break;
1862 case HAL_DEF_RX_PACKET_OFFSET:
1863 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1864 break;
1865 case HAL_DEF_DBG_DM_FUNC:
1866 *((u32 *)pValue) = haldata->odmpriv.SupportAbility;
1867 break;
1868 case HAL_DEF_RA_DECISION_RATE:
1869 {
1870 u8 MacID = *((u8 *)pValue);
d5fdbca6 1871 *((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, MacID);
d3f4b828
LF		 1872 }
1873 break;
1874 case HAL_DEF_RA_SGI:
1875 {
1876 u8 MacID = *((u8 *)pValue);
d5fdbca6 1877 *((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&haldata->odmpriv, MacID);
d3f4b828
LF		 1878 }
1879 break;
1880 case HAL_DEF_PT_PWR_STATUS:
1881 {
1882 u8 MacID = *((u8 *)pValue);
d5fdbca6 1883 *((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, MacID);
d3f4b828
LF		 1884 }
1885 break;
1886 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1887 *((u32 *)pValue) = MAX_AMPDU_FACTOR_64K;
1888 break;
1889 case HW_DEF_RA_INFO_DUMP:
1890 {
1891 u8 entry_id = *((u8 *)pValue);
1892 if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) {
1893 DBG_88E("============ RA status check ===================\n");
1894 DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
1895 entry_id,
1896 haldata->odmpriv.RAInfo[entry_id].RateID,
1897 haldata->odmpriv.RAInfo[entry_id].RAUseRate,
1898 haldata->odmpriv.RAInfo[entry_id].RateSGI,
1899 haldata->odmpriv.RAInfo[entry_id].DecisionRate,
1900 haldata->odmpriv.RAInfo[entry_id].PTStage);
1901 }
1902 }
1903 break;
1904 case HW_DEF_ODM_DBG_FLAG:
1905 {
d5fdbca6 1906 struct odm_dm_struct *dm_ocm = &haldata->odmpriv;
d3f4b828
LF		 1907 pr_info("dm_ocm->DebugComponents = 0x%llx\n", dm_ocm->DebugComponents);
1908 }
1909 break;
1910 case HAL_DEF_DBG_DUMP_RXPKT:
1911 *((u8 *)pValue) = haldata->bDumpRxPkt;
1912 break;
1913 case HAL_DEF_DBG_DUMP_TXPKT:
1914 *((u8 *)pValue) = haldata->bDumpTxPkt;
1915 break;
1916 default:
1917 bResult = _FAIL;
1918 break;
1919 }
1920
1921 return bResult;
1922}
1923
90c69b7a 1924void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level)
d3f4b828
LF		 1925{
1926 u8 init_rate = 0;
1927 u8 networkType, raid;
1928 u32 mask, rate_bitmap;
1929 u8 shortGIrate = false;
1930 int supportRateNum = 0;
1931 struct sta_info *psta;
1932 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1933 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
d5fdbca6
JB		 1934 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1935 struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
d3f4b828
LF		 1936
1937 if (mac_id >= NUM_STA) /* CAM_SIZE */
1938 return;
1939 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
1940 if (psta == NULL)
1941 return;
1942 switch (mac_id) {
1943 case 0:/* for infra mode */
1944 supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
1945 networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf;
1946 raid = networktype_to_raid(networkType);
1947 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
d5fdbca6
JB		 1948 mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&pmlmeinfo->HT_caps) : 0;
1949 if (support_short_GI(adapt, &pmlmeinfo->HT_caps))
d3f4b828
LF		 1950 shortGIrate = true;
1951 break;
1952 case 1:/* for broadcast/multicast */
1953 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1954 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
1955 networkType = WIRELESS_11B;
1956 else
1957 networkType = WIRELESS_11G;
1958 raid = networktype_to_raid(networkType);
1959 mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
1960 break;
1961 default: /* for each sta in IBSS */
1962 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1963 networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
1964 raid = networktype_to_raid(networkType);
1965 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
1966
1967 /* todo: support HT in IBSS */
1968 break;
1969 }
1970
d3f4b828
LF		 1971 rate_bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, mac_id, mask, rssi_level);
1972 DBG_88E("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
1973 __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
1974
1975 mask &= rate_bitmap;
1976
1977 init_rate = get_highest_rate_idx(mask)&0x3f;
1978
3abf4f98
JS		 1979 ODM_RA_UpdateRateInfo_8188E(&haldata->odmpriv, mac_id,
1980 raid, mask, shortGIrate);
d3f4b828 1981
d3f4b828
LF		 1982 /* set ra_id */
1983 psta->raid = raid;
1984 psta->init_rate = init_rate;
1985}
1986
0e1e385a 1987void rtw_hal_bcn_related_reg_setting(struct adapter *adapt)
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LF		 1988{
1989 u32 value32;
d5fdbca6
JB		 1990 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
1991 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
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LF		 1992 u32 bcn_ctrl_reg = REG_BCN_CTRL;
1993 /* reset TSF, enable update TSF, correcting TSF On Beacon */
1994
1995 /* BCN interval */
9764ed04 1996 usb_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
e76484d0 1997 usb_write8(adapt, REG_ATIMWND, 0x02);/* 2ms */
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LF		 1998
1999 _InitBeaconParameters(adapt);
2000
e76484d0 2001 usb_write8(adapt, REG_SLOT, 0x09);
d3f4b828 2002
99ecfb06 2003 value32 = usb_read32(adapt, REG_TCR);
d3f4b828 2004 value32 &= ~TSFRST;
fc158079 2005 usb_write32(adapt, REG_TCR, value32);
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LF		 2006
2007 value32 |= TSFRST;
fc158079 2008 usb_write32(adapt, REG_TCR, value32);
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LF		 2009
2010 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
e76484d0 2011 usb_write8(adapt, REG_RXTSF_OFFSET_CCK, 0x50);
2012 usb_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50);
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LF		 2013
2014 _BeaconFunctionEnable(adapt, true, true);
2015
2016 ResumeTxBeacon(adapt);
2017
9c68ed09 2018 usb_write8(adapt, bcn_ctrl_reg, usb_read8(adapt, bcn_ctrl_reg) | BIT(1));
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LF		 2019}
2020
2d91255a 2021void rtw_hal_def_value_init(struct adapter *adapt)
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LF		 2022{
2023 struct hal_data_8188e *haldata;
2024 struct pwrctrl_priv *pwrctrlpriv;
2025 u8 i;
2026
2027 haldata = GET_HAL_DATA(adapt);
2028 pwrctrlpriv = &adapt->pwrctrlpriv;
2029
2030 /* init default value */
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LF		 2031 if (!pwrctrlpriv->bkeepfwalive)
2032 haldata->LastHMEBoxNum = 0;
2033
2034 /* init dm default value */
2035 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
2036 haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/* for IQK */
2037 haldata->pwrGroupCnt = 0;
2038 haldata->PGMaxGroup = 13;
2039 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
2040 for (i = 0; i < HP_THERMAL_NUM; i++)
2041 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
2042}
2043
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LF		 2044void rtl8188eu_set_hal_ops(struct adapter *adapt)
2045{
6982f867 2046 adapt->HalData = kzalloc(sizeof(struct hal_data_8188e), GFP_KERNEL);
f3e80d80 2047 if (!adapt->HalData)
d3f4b828 2048 DBG_88E("cant not alloc memory for HAL DATA\n");
d3f4b828 2049}
Linux kernel - Deliverables
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