[deliverable/linux.git] / drivers / staging / rtl8188eu / include / Hal8188EPhyCfg.h

/******************************************************************************
 *
 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 ******************************************************************************/
#ifndef __INC_HAL8188EPHYCFG_H__
#define __INC_HAL8188EPHYCFG_H__


/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT			5
#define MAX_STALL_TIME			50		/* us */
#define AntennaDiversityValue		0x80
#define MAX_TXPWR_IDX_NMODE_92S		63
#define Reset_Cnt_Limit			3

#define IQK_MAC_REG_NUM			4
#define IQK_ADDA_REG_NUM		16
#define IQK_BB_REG_NUM			9
#define HP_THERMAL_NUM			8

#define MAX_AGGR_NUM			0x07


/*--------------------------Define Parameters-------------------------------*/


/*------------------------------Define structure----------------------------*/
enum sw_chnl_cmd_id {
	CmdID_End,
	CmdID_SetTxPowerLevel,
	CmdID_BBRegWrite10,
	CmdID_WritePortUlong,
	CmdID_WritePortUshort,
	CmdID_WritePortUchar,
	CmdID_RF_WriteReg,
};

/* 1. Switch channel related */
struct sw_chnl_cmd {
	enum sw_chnl_cmd_id CmdID;
	u32 Para1;
	u32 Para2;
	u32 msDelay;
};

enum hw90_block {
	HW90_BLOCK_MAC = 0,
	HW90_BLOCK_PHY0 = 1,
	HW90_BLOCK_PHY1 = 2,
	HW90_BLOCK_RF = 3,
	HW90_BLOCK_MAXIMUM = 4, /*  Never use this */
};

enum rf_radio_path {
	RF_PATH_A = 0,			/* Radio Path A */
	RF_PATH_B = 1,			/* Radio Path B */
};

#define MAX_PG_GROUP 13

#define	RF_PATH_MAX			2
#define		MAX_RF_PATH		RF_PATH_MAX
#define		MAX_TX_COUNT		4 /* path numbers */

#define CHANNEL_MAX_NUMBER		14	/*  14 is the max chnl number */
#define MAX_CHNL_GROUP_24G		6	/*  ch1~2, ch3~5, ch6~8,
						 *ch9~11, ch12~13, CH 14
						 * total three groups */
#define CHANNEL_GROUP_MAX_88E		6

enum wireless_mode {
	WIRELESS_MODE_UNKNOWN = 0x00,
	WIRELESS_MODE_A			= BIT(2),
	WIRELESS_MODE_B			= BIT(0),
	WIRELESS_MODE_G			= BIT(1),
	WIRELESS_MODE_AUTO		= BIT(5),
	WIRELESS_MODE_N_24G		= BIT(3),
	WIRELESS_MODE_N_5G		= BIT(4),
	WIRELESS_MODE_AC		= BIT(6)
};

enum phy_rate_tx_offset_area {
	RA_OFFSET_LEGACY_OFDM1,
	RA_OFFSET_LEGACY_OFDM2,
	RA_OFFSET_HT_OFDM1,
	RA_OFFSET_HT_OFDM2,
	RA_OFFSET_HT_OFDM3,
	RA_OFFSET_HT_OFDM4,
	RA_OFFSET_HT_CCK,
};

/* BB/RF related */
enum RF_TYPE_8190P {
	RF_TYPE_MIN,		/*  0 */
	RF_8225 = 1,		/*  1 11b/g RF for verification only */
	RF_8256 = 2,		/*  2 11b/g/n */
	RF_8258 = 3,		/*  3 11a/b/g/n RF */
	RF_6052 = 4,		/*  4 11b/g/n RF */
	/*  TODO: We should remove this psudo PHY RF after we get new RF. */
	RF_PSEUDO_11N = 5,	/*  5, It is a temporality RF. */
};

struct bb_reg_def {
	u32 rfintfs;		/*  set software control: */
				/*	0x870~0x877[8 bytes] */
	u32 rfintfi;		/*  readback data: */
				/*	0x8e0~0x8e7[8 bytes] */
	u32 rfintfo;		/*  output data: */
				/*	0x860~0x86f [16 bytes] */
	u32 rfintfe;		/*  output enable: */
				/*	0x860~0x86f [16 bytes] */
	u32 rf3wireOffset;	/*  LSSI data: */
				/*	0x840~0x84f [16 bytes] */
	u32 rfLSSI_Select;	/*  BB Band Select: */
				/*	0x878~0x87f [8 bytes] */
	u32 rfTxGainStage;	/*  Tx gain stage: */
				/*	0x80c~0x80f [4 bytes] */
	u32 rfHSSIPara1;	/*  wire parameter control1 : */
				/*	0x820~0x823,0x828~0x82b,
				 *	0x830~0x833, 0x838~0x83b [16 bytes] */
	u32 rfHSSIPara2;	/*  wire parameter control2 : */
				/*	0x824~0x827,0x82c~0x82f, 0x834~0x837,
				 *	0x83c~0x83f [16 bytes] */
	u32 rfSwitchControl;	/* Tx Rx antenna control : */
				/*	0x858~0x85f [16 bytes] */
	u32 rfAGCControl1;	/* AGC parameter control1 : */
				/*	0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
				 * 0xc68~0xc6b [16 bytes] */
	u32 rfAGCControl2;	/* AGC parameter control2 : */
				/*	0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
				 *	0xc6c~0xc6f [16 bytes] */
	u32 rfRxIQImbalance;	/* OFDM Rx IQ imbalance matrix : */
				/*	0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
				 *	0xc2c~0xc2f [16 bytes] */
	u32 rfRxAFE;		/* Rx IQ DC ofset and Rx digital filter,
				 * Rx DC notch filter : */
				/*	0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
				 *	0xc28~0xc2b [16 bytes] */
	u32 rfTxIQImbalance;	/* OFDM Tx IQ imbalance matrix */
				/*	0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
				 *	 0xc98~0xc9b [16 bytes] */
	u32 rfTxAFE;		/* Tx IQ DC Offset and Tx DFIR type */
				/*	0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
				 *	0xc9c~0xc9f [16 bytes] */
	u32 rfLSSIReadBack;	/* LSSI RF readback data SI mode */
				/*	0x8a0~0x8af [16 bytes] */
	u32 rfLSSIReadBackPi;	/* LSSI RF readback data PI mode 0x8b8-8bc for
				 * Path A and B */
};

/*------------------------------Define structure----------------------------*/


/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/


/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/


/*--------------------------Exported Function prototype---------------------*/
/*  */
/*  BB and RF register read/write */
/*  */

/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);

/*  BB TX Power R/W */
void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel);

void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);

/*  Call after initialization */
void ChkFwCmdIoDone(struct adapter *adapter);

/*  BB/MAC/RF other monitor API */
void PHY_SetRFPathSwitch_8188E(struct adapter *adapter,	bool main);

void PHY_SwitchEphyParameter(struct adapter *adapter);

void PHY_EnableHostClkReq(struct adapter *adapter);

bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);

/*--------------------------Exported Function prototype---------------------*/

#define PHY_SetMacReg	PHY_SetBBReg

#define	SIC_HW_SUPPORT			0

#define	SIC_MAX_POLL_CNT		5

#define	SIC_CMD_READY			0
#define	SIC_CMD_WRITE			1
#define	SIC_CMD_READ			2

#define	SIC_CMD_REG			0x1EB		/*  1byte */
#define	SIC_ADDR_REG			0x1E8		/*  1b9~1ba, 2 bytes */
#define	SIC_DATA_REG			0x1EC		/*  1bc~1bf */

#endif	/*  __INC_HAL8192CPHYCFG_H */
Commit	Line	Data
b1da99bb LF	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
b1da99bb LF	14	******************************************************************************/
	15	#ifndef __INC_HAL8188EPHYCFG_H__
	16	#define __INC_HAL8188EPHYCFG_H__
	17
	18
	19	/--------------------------Define Parameters-------------------------------/
	20	#define LOOP_LIMIT 5
	21	#define MAX_STALL_TIME 50 /* us */
	22	#define AntennaDiversityValue 0x80
	23	#define MAX_TXPWR_IDX_NMODE_92S 63
	24	#define Reset_Cnt_Limit 3
	25
	26	#define IQK_MAC_REG_NUM 4
	27	#define IQK_ADDA_REG_NUM 16
	28	#define IQK_BB_REG_NUM 9
	29	#define HP_THERMAL_NUM 8
	30
	31	#define MAX_AGGR_NUM 0x07
	32
	33
	34	/--------------------------Define Parameters-------------------------------/
	35
	36
	37	/------------------------------Define structure----------------------------/
	38	enum sw_chnl_cmd_id {
	39	CmdID_End,
	40	CmdID_SetTxPowerLevel,
	41	CmdID_BBRegWrite10,
	42	CmdID_WritePortUlong,
	43	CmdID_WritePortUshort,
	44	CmdID_WritePortUchar,
	45	CmdID_RF_WriteReg,
	46	};
	47
	48	/* 1. Switch channel related */
	49	struct sw_chnl_cmd {
	50	enum sw_chnl_cmd_id CmdID;
	51	u32 Para1;
	52	u32 Para2;
	53	u32 msDelay;
	54	};
	55
	56	enum hw90_block {
	57	HW90_BLOCK_MAC = 0,
	58	HW90_BLOCK_PHY0 = 1,
	59	HW90_BLOCK_PHY1 = 2,
	60	HW90_BLOCK_RF = 3,
	61	HW90_BLOCK_MAXIMUM = 4, /* Never use this */
	62	};
	63
	64	enum rf_radio_path {
	65	RF_PATH_A = 0, /* Radio Path A */
	66	RF_PATH_B = 1, /* Radio Path B */
b1da99bb LF	67	};
	68
	69	#define MAX_PG_GROUP 13
	70
d9b36d52	71	#define RF_PATH_MAX 2
b1da99bb LF	72	#define MAX_RF_PATH RF_PATH_MAX
	73	#define MAX_TX_COUNT 4 /* path numbers */
	74
	75	#define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */
	76	#define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8,
	77	*ch9~11, ch12~13, CH 14
	78	* total three groups */
	79	#define CHANNEL_GROUP_MAX_88E 6
	80
	81	enum wireless_mode {
	82	WIRELESS_MODE_UNKNOWN = 0x00,
9c68ed09 AB	83	WIRELESS_MODE_A = BIT(2),
	84	WIRELESS_MODE_B = BIT(0),
	85	WIRELESS_MODE_G = BIT(1),
	86	WIRELESS_MODE_AUTO = BIT(5),
	87	WIRELESS_MODE_N_24G = BIT(3),
	88	WIRELESS_MODE_N_5G = BIT(4),
	89	WIRELESS_MODE_AC = BIT(6)
b1da99bb LF	90	};
	91
	92	enum phy_rate_tx_offset_area {
	93	RA_OFFSET_LEGACY_OFDM1,
	94	RA_OFFSET_LEGACY_OFDM2,
	95	RA_OFFSET_HT_OFDM1,
	96	RA_OFFSET_HT_OFDM2,
	97	RA_OFFSET_HT_OFDM3,
	98	RA_OFFSET_HT_OFDM4,
	99	RA_OFFSET_HT_CCK,
	100	};
	101
	102	/* BB/RF related */
	103	enum RF_TYPE_8190P {
	104	RF_TYPE_MIN, /* 0 */
	105	RF_8225 = 1, /* 1 11b/g RF for verification only */
	106	RF_8256 = 2, /* 2 11b/g/n */
	107	RF_8258 = 3, /* 3 11a/b/g/n RF */
	108	RF_6052 = 4, /* 4 11b/g/n RF */
	109	/* TODO: We should remove this psudo PHY RF after we get new RF. */
	110	RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */
	111	};
	112
	113	struct bb_reg_def {
	114	u32 rfintfs; /* set software control: */
	115	/* 0x870~0x877[8 bytes] */
	116	u32 rfintfi; /* readback data: */
	117	/* 0x8e0~0x8e7[8 bytes] */
	118	u32 rfintfo; /* output data: */
	119	/* 0x860~0x86f [16 bytes] */
	120	u32 rfintfe; /* output enable: */
	121	/* 0x860~0x86f [16 bytes] */
	122	u32 rf3wireOffset; /* LSSI data: */
	123	/* 0x840~0x84f [16 bytes] */
	124	u32 rfLSSI_Select; /* BB Band Select: */
	125	/* 0x878~0x87f [8 bytes] */
	126	u32 rfTxGainStage; /* Tx gain stage: */
	127	/* 0x80c~0x80f [4 bytes] */
	128	u32 rfHSSIPara1; /* wire parameter control1 : */
	129	/* 0x820~0x823,0x828~0x82b,
	130	* 0x830~0x833, 0x838~0x83b [16 bytes] */
	131	u32 rfHSSIPara2; /* wire parameter control2 : */
	132	/* 0x824~0x827,0x82c~0x82f, 0x834~0x837,
	133	* 0x83c~0x83f [16 bytes] */
	134	u32 rfSwitchControl; /* Tx Rx antenna control : */
	135	/* 0x858~0x85f [16 bytes] */
	136	u32 rfAGCControl1; /* AGC parameter control1 : */
	137	/* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
	138	* 0xc68~0xc6b [16 bytes] */
	139	u32 rfAGCControl2; /* AGC parameter control2 : */
	140	/* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
	141	* 0xc6c~0xc6f [16 bytes] */
	142	u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
	143	/* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
	144	* 0xc2c~0xc2f [16 bytes] */
	145	u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter,
	146	* Rx DC notch filter : */
	147	/* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
	148	* 0xc28~0xc2b [16 bytes] */
	149	u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
	150	/* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
	151	* 0xc98~0xc9b [16 bytes] */
	152	u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
	153	/* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
154	* 0xc9c~0xc9f [16 bytes] */
155	u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
156	/* 0x8a0~0x8af [16 bytes] */
157	u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for
158	* Path A and B */
159	};
160
b1da99bb LF	161	/------------------------------Define structure----------------------------/
	162
	163
	164	/------------------------Export global variable----------------------------/
	165	/------------------------Export global variable----------------------------/
	166
	167
	168	/------------------------Export Marco Definition---------------------------/
	169	/------------------------Export Marco Definition---------------------------/
	170
	171
	172	/--------------------------Exported Function prototype---------------------/
	173	/* */
	174	/* BB and RF register read/write */
	175	/* */
b1da99bb	176
b1da99bb LF	177	/* Read initi reg value for tx power setting. */
	178	void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);
	179
	180	/* BB TX Power R/W */
	181	void PHY_GetTxPowerLevel8188E(struct adapter adapter, u32 powerlevel);
b1da99bb LF	182
	183	void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
	184
b1da99bb LF	185	/* Call after initialization */
	186	void ChkFwCmdIoDone(struct adapter *adapter);
	187
	188	/* BB/MAC/RF other monitor API */
	189	void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main);
	190
	191	void PHY_SwitchEphyParameter(struct adapter *adapter);
	192
	193	void PHY_EnableHostClkReq(struct adapter *adapter);
	194
	195	bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);
	196
b1da99bb LF	197	/--------------------------Exported Function prototype---------------------/
b1da99bb LF	198
b1da99bb LF	199	#define PHY_SetMacReg PHY_SetBBReg
	200
	201	#define SIC_HW_SUPPORT 0
	202
	203	#define SIC_MAX_POLL_CNT 5
	204
	205	#define SIC_CMD_READY 0
	206	#define SIC_CMD_WRITE 1
	207	#define SIC_CMD_READ 2
	208
	209	#define SIC_CMD_REG 0x1EB /* 1byte */
	210	#define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
	211	#define SIC_DATA_REG 0x1EC /* 1bc~1bf */
	212
	213	#endif /* __INC_HAL8192CPHYCFG_H */