[deliverable/linux.git] / drivers / staging / rtl8188eu / include / rtl8188e_hal.h

/******************************************************************************
 *
 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 ******************************************************************************/
#ifndef __RTL8188E_HAL_H__
#define __RTL8188E_HAL_H__


/* include HAL Related header after HAL Related compiling flags */
#include "rtl8188e_spec.h"
#include "Hal8188EPhyReg.h"
#include "Hal8188EPhyCfg.h"
#include "rtl8188e_dm.h"
#include "rtl8188e_recv.h"
#include "rtl8188e_xmit.h"
#include "rtl8188e_cmd.h"
#include "pwrseq.h"
#include "rtw_efuse.h"
#include "rtw_sreset.h"
#include "odm_precomp.h"

/*  Fw Array */
#define Rtl8188E_FwImageArray		Rtl8188EFwImgArray
#define Rtl8188E_FWImgArrayLength	Rtl8188EFWImgArrayLength

#define RTL8188E_FW_UMC_IMG			"rtl8188E\\rtl8188efw.bin"
#define RTL8188E_PHY_REG			"rtl8188E\\PHY_REG_1T.txt"
#define RTL8188E_PHY_RADIO_A			"rtl8188E\\radio_a_1T.txt"
#define RTL8188E_PHY_RADIO_B			"rtl8188E\\radio_b_1T.txt"
#define RTL8188E_AGC_TAB			"rtl8188E\\AGC_TAB_1T.txt"
#define RTL8188E_PHY_MACREG			"rtl8188E\\MAC_REG.txt"
#define RTL8188E_PHY_REG_PG			"rtl8188E\\PHY_REG_PG.txt"
#define RTL8188E_PHY_REG_MP			"rtl8188E\\PHY_REG_MP.txt"

/* 		RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
#define Rtl8188E_NIC_PWR_ON_FLOW		rtl8188E_power_on_flow
#define Rtl8188E_NIC_RF_OFF_FLOW		rtl8188E_radio_off_flow
#define Rtl8188E_NIC_DISABLE_FLOW		rtl8188E_card_disable_flow
#define Rtl8188E_NIC_ENABLE_FLOW		rtl8188E_card_enable_flow
#define Rtl8188E_NIC_SUSPEND_FLOW		rtl8188E_suspend_flow
#define Rtl8188E_NIC_RESUME_FLOW		rtl8188E_resume_flow
#define Rtl8188E_NIC_PDN_FLOW			rtl8188E_hwpdn_flow
#define Rtl8188E_NIC_LPS_ENTER_FLOW		rtl8188E_enter_lps_flow
#define Rtl8188E_NIC_LPS_LEAVE_FLOW		rtl8188E_leave_lps_flow

#define DRVINFO_SZ	4 /*  unit is 8bytes */
#define PageNum_128(_Len)	(u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))

/*  download firmware related data structure */
#define FW_8188E_SIZE			0x4000 /* 16384,16k */
#define FW_8188E_START_ADDRESS		0x1000
#define FW_8188E_END_ADDRESS		0x1FFF /* 0x5FFF */

#define MAX_PAGE_SIZE			4096	/*  @ page : 4k bytes */

#define IS_FW_HEADER_EXIST(_pFwHdr)				\
	((le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x92C0 ||	\
	(le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88C0 ||	\
	(le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x2300 ||	\
	(le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88E0)

#define DRIVER_EARLY_INT_TIME		0x05
#define BCN_DMA_ATIME_INT_TIME		0x02

enum usb_rx_agg_mode {
	USB_RX_AGG_DISABLE,
	USB_RX_AGG_DMA,
	USB_RX_AGG_USB,
	USB_RX_AGG_MIX
};

#define MAX_RX_DMA_BUFFER_SIZE_88E				\
      0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
	      * WOLPattern(16*24)) */

#define MAX_TX_REPORT_BUFFER_SIZE		0x0400 /*  1k */


/*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
#define MAX_TX_QUEUE			9

#define TX_SELE_HQ			BIT(0)		/*  High Queue */
#define TX_SELE_LQ			BIT(1)		/*  Low Queue */
#define TX_SELE_NQ			BIT(2)		/*  Normal Queue */

/*  Note: We will divide number of page equally for each queue other
 *  than public queue! */
/*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
/*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
/*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
 *  null-data */

#define TX_TOTAL_PAGE_NUMBER_88E		0xA9/*   169 (21632=> 21k) */

#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)

/* Note: For Normal Chip Setting ,modify later */
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER			\
	TX_TOTAL_PAGE_NUMBER_88E  /* 0xA9 , 0xb0=>176=>22k */
#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E			\
	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */

/* 	Chip specific */
#define CHIP_BONDING_IDENTIFIER(_value)	(((_value)>>22)&0x3)
#define CHIP_BONDING_92C_1T2R	0x1
#define CHIP_BONDING_88C_USB_MCARD	0x2
#define CHIP_BONDING_88C_USB_HP	0x1
#include "HalVerDef.h"
#include "hal_com.h"

/* 	Channel Plan */
enum ChannelPlan {
	CHPL_FCC	= 0,
	CHPL_IC		= 1,
	CHPL_ETSI	= 2,
	CHPL_SPA	= 3,
	CHPL_FRANCE	= 4,
	CHPL_MKK	= 5,
	CHPL_MKK1	= 6,
	CHPL_ISRAEL	= 7,
	CHPL_TELEC	= 8,
	CHPL_GLOBAL	= 9,
	CHPL_WORLD	= 10,
};

struct txpowerinfo24g {
	u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
	/* If only one tx, only BW20 and OFDM are used. */
	s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
};

#define EFUSE_REAL_CONTENT_LEN		512
#define EFUSE_MAX_SECTION		16
#define EFUSE_IC_ID_OFFSET		506 /* For some inferior IC purpose*/
#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN)
/*  To prevent out of boundary programming case, */
/*  leave 1byte and program full section */
/*  9bytes + 1byt + 5bytes and pre 1byte. */
/*  For worst case: */
/*  | 1byte|----8bytes----|1byte|--5bytes--| */
/*  |         |            Reserved(14bytes)	      | */

/*  PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */
#define EFUSE_OOB_PROTECT_BYTES			15

#define		HWSET_MAX_SIZE_88E		512

#define		EFUSE_REAL_CONTENT_LEN_88E	256
#define		EFUSE_MAP_LEN_88E		512
#define EFUSE_MAP_LEN			EFUSE_MAP_LEN_88E
#define		EFUSE_MAX_SECTION_88E		64
#define		EFUSE_MAX_WORD_UNIT_88E		4
#define		EFUSE_IC_ID_OFFSET_88E		506
#define		AVAILABLE_EFUSE_ADDR_88E(addr)			\
	(addr < EFUSE_REAL_CONTENT_LEN_88E)
/*  To prevent out of boundary programming case, leave 1byte and program
 *  full section */
/*  9bytes + 1byt + 5bytes and pre 1byte. */
/*  For worst case: */
/*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
/*  PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */
#define		EFUSE_OOB_PROTECT_BYTES_88E	18
#define		EFUSE_PROTECT_BYTES_BANK_88E	16

/* 			EFUSE for BT definition */
#define EFUSE_BT_REAL_CONTENT_LEN	1536	/*  512*3 */
#define EFUSE_BT_MAP_LEN		1024	/*  1k bytes */
#define EFUSE_BT_MAX_SECTION		128	/*  1024/8 */

#define EFUSE_PROTECT_BYTES_BANK	16

struct hal_data_8188e {
	struct HAL_VERSION	VersionID;
	u16	CustomerID;
	u16	FirmwareVersion;
	u16	FirmwareVersionRev;
	u16	FirmwareSubVersion;
	u16	FirmwareSignature;
	u8	PGMaxGroup;
	/* current WIFI_PHY values */
	u32	ReceiveConfig;
	enum wireless_mode CurrentWirelessMode;
	enum ht_channel_width CurrentChannelBW;
	u8	CurrentChannel;
	u8	nCur40MhzPrimeSC;/*  Control channel sub-carrier */

	u16	BasicRateSet;

	/* rf_ctrl */
	u8	rf_chip;
	u8	rf_type;
	u8	NumTotalRFPath;

	u8	BoardType;

	/*  EEPROM setting. */
	u16	EEPROMVID;
	u16	EEPROMPID;
	u16	EEPROMSVID;
	u16	EEPROMSDID;
	u8	EEPROMCustomerID;
	u8	EEPROMSubCustomerID;
	u8	EEPROMVersion;
	u8	EEPROMRegulatory;

	u8	bTXPowerDataReadFromEEPORM;
	u8	EEPROMThermalMeter;
	u8	bAPKThermalMeterIgnore;

	bool	EepromOrEfuse;
	/* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
	u8	EfuseMap[2][HWSET_MAX_SIZE_512];
	u8	EfuseUsedPercentage;
	struct efuse_hal	EfuseHal;

	u8	Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
	u8	Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
	/* If only one tx, only BW20 and OFDM are used. */
	s8	CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	s8	OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	s8	BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	s8	BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];

	u8	TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	/*  For HT 40MHZ pwr */
	u8	TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	/*  For HT 40MHZ pwr */
	u8	TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	/*  HT 20<->40 Pwr diff */
	u8	TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	/*  For HT<->legacy pwr diff */
	u8	TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	/*  For power group */
	u8	PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	u8	PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];

	u8	LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
	/*  The current Tx Power Level */
	u8	CurrentCckTxPwrIdx;
	u8	CurrentOfdm24GTxPwrIdx;
	u8	CurrentBW2024GTxPwrIdx;
	u8	CurrentBW4024GTxPwrIdx;


	/*  Read/write are allow for following hardware information variables */
	u8	framesync;
	u32	framesyncC34;
	u8	framesyncMonitor;
	u8	DefaultInitialGain[4];
	u8	pwrGroupCnt;
	u32	MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
	u32	CCKTxPowerLevelOriginalOffset;

	u8	CrystalCap;
	u32	AntennaTxPath;			/*  Antenna path Tx */
	u32	AntennaRxPath;			/*  Antenna path Rx */
	u8	BluetoothCoexist;
	u8	ExternalPA;

	u8	bLedOpenDrain; /* Open-drain support for controlling the LED.*/

	u8	b1x1RecvCombine;	/*  for 1T1R receive combining */

	u32	AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */

	struct bb_reg_def PHYRegDef[4];	/* Radio A/B/C/D */

	u32	RfRegChnlVal[2];

	/* RDG enable */
	bool	 bRDGEnable;

	/* for host message to fw */
	u8	LastHMEBoxNum;

	u8	RegTxPause;
	/*  Beacon function related global variable. */
	u32	RegBcnCtrlVal;
	u8	RegFwHwTxQCtrl;
	u8	RegReg542;
	u8	RegCR_1;

	struct dm_priv	dmpriv;
	struct odm_dm_struct odmpriv;
	struct sreset_priv srestpriv;

	u8	CurAntenna;
	u8	AntDivCfg;
	u8	TRxAntDivType;


	u8	bDumpRxPkt;/* for debug */
	u8	bDumpTxPkt;/* for debug */
	u8	FwRsvdPageStartOffset; /* Reserve page start offset except
					*  beacon in TxQ. */

	/*  2010/08/09 MH Add CU power down mode. */
	bool		pwrdown;

	/*  Add for dual MAC  0--Mac0 1--Mac1 */
	u32	interfaceIndex;

	u8	OutEpQueueSel;
	u8	OutEpNumber;

	/*  Add for USB aggreation mode dynamic shceme. */
	bool		UsbRxHighSpeedMode;

	/*  2010/11/22 MH Add for slim combo debug mode selective. */
	/*  This is used for fix the drawback of CU TSMC-A/UMC-A cut.
	 * HW auto suspend ability. Close BT clock. */
	bool		SlimComboDbg;

	u16	EfuseUsedBytes;

	/*  Auto FSM to Turn On, include clock, isolation, power control
	 *  for MAC only */
	u8	bMacPwrCtrlOn;

	u32	UsbBulkOutSize;

	/*  Interrupt relatd register information. */
	u32	IntArray[3];/* HISR0,HISR1,HSISR */
	u32	IntrMask[3];
	u8	C2hArray[16];
	u8	UsbTxAggMode;
	u8	UsbTxAggDescNum;
	u16	HwRxPageSize;		/*  Hardware setting */
	u32	MaxUsbRxAggBlock;

	enum usb_rx_agg_mode UsbRxAggMode;
	u8	UsbRxAggBlockCount;	/*  USB Block count. Block size is
					 * 512-byte in high speed and 64-byte
					 * in full speed */
	u8	UsbRxAggBlockTimeout;
	u8	UsbRxAggPageCount;	/*  8192C DMA page count */
	u8	UsbRxAggPageTimeout;
};

#define GET_HAL_DATA(__pAdapter)				\
	((struct hal_data_8188e *)((__pAdapter)->HalData))
#define GET_RF_TYPE(priv)		(GET_HAL_DATA(priv)->rf_type)

/*  rtl8188e_hal_init.c */
void _8051Reset88E(struct adapter *padapter);
void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);


s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);

/*  EFuse */
void Hal_InitPGData88E(struct adapter *padapter);
void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
			    bool AutoLoadFail);

void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
				bool AutoLoadFail);
void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
				 bool AutoLoadFail);
void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
				 bool AutoLoadFail);
void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent,
				 bool AutoLoadFail);
void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent,
			      bool AutoloadFail);
void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
			      bool AutoLoadFail);
void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
				bool AutoLoadFail);
void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
				bool AutoLoadFail);

/*  register */

void rtl8188e_start_thread(struct adapter *padapter);
void rtl8188e_stop_thread(struct adapter *padapter);

s32 iol_execute(struct adapter *padapter, u8 control);
void iol_mode_enable(struct adapter *padapter, u8 enable);
s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
void rtw_cancel_all_timer(struct adapter *padapter);

#endif /* __RTL8188E_HAL_H__ */
Commit	Line	Data
58c43401 LF	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
58c43401 LF	14	******************************************************************************/
	15	#ifndef __RTL8188E_HAL_H__
	16	#define __RTL8188E_HAL_H__
	17
	18
	19	/* include HAL Related header after HAL Related compiling flags */
	20	#include "rtl8188e_spec.h"
	21	#include "Hal8188EPhyReg.h"
	22	#include "Hal8188EPhyCfg.h"
58c43401 LF	23	#include "rtl8188e_dm.h"
	24	#include "rtl8188e_recv.h"
	25	#include "rtl8188e_xmit.h"
	26	#include "rtl8188e_cmd.h"
1c2775ec	27	#include "pwrseq.h"
58c43401	28	#include "rtw_efuse.h"
a70e4034	29	#include "rtw_sreset.h"
58c43401 LF	30	#include "odm_precomp.h"
	31
	32	/* Fw Array */
	33	#define Rtl8188E_FwImageArray Rtl8188EFwImgArray
	34	#define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength
	35
	36	#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin"
	37	#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt"
	38	#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt"
	39	#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt"
	40	#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt"
	41	#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt"
	42	#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt"
	43	#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt"
	44
	45	/* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
	46	#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
	47	#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
	48	#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
	49	#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
	50	#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
	51	#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
	52	#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
	53	#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
	54	#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
	55
	56	#define DRVINFO_SZ 4 /* unit is 8bytes */
	57	#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
	58
	59	/* download firmware related data structure */
	60	#define FW_8188E_SIZE 0x4000 /* 16384,16k */
	61	#define FW_8188E_START_ADDRESS 0x1000
	62	#define FW_8188E_END_ADDRESS 0x1FFF /* 0x5FFF */
	63
	64	#define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */
	65
	66	#define IS_FW_HEADER_EXIST(_pFwHdr) \
d6c28c23	67	((le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x92C0 \|\| \
	68	(le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88C0 \|\| \
	69	(le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x2300 \|\| \
	70	(le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88E0)
58c43401 LF	71
	72	#define DRIVER_EARLY_INT_TIME 0x05
	73	#define BCN_DMA_ATIME_INT_TIME 0x02
	74
	75	enum usb_rx_agg_mode {
	76	USB_RX_AGG_DISABLE,
	77	USB_RX_AGG_DMA,
	78	USB_RX_AGG_USB,
	79	USB_RX_AGG_MIX
	80	};
	81
	82	#define MAX_RX_DMA_BUFFER_SIZE_88E \
	83	0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
	84	* WOLPattern(1624)) /
	85
	86	#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */
	87
	88
	89	/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
	90	#define MAX_TX_QUEUE 9
	91
	92	#define TX_SELE_HQ BIT(0) /* High Queue */
	93	#define TX_SELE_LQ BIT(1) /* Low Queue */
	94	#define TX_SELE_NQ BIT(2) /* Normal Queue */
	95
	96	/* Note: We will divide number of page equally for each queue other
	97	* than public queue! */
	98	/* 22k = 22528 bytes = 176 pages (@page = 128 bytes) */
	99	/* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) */
	100	/* 2BCN / 1ps-poll / 1null-data /1prob_rsp /1QOS null-data /1BT QOS
	101	* null-data */
	102
	103	#define TX_TOTAL_PAGE_NUMBER_88E 0xA9/* 169 (21632=> 21k) */
	104
	105	#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
	106
	107	/* Note: For Normal Chip Setting ,modify later */
	108	#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER \
	109	TX_TOTAL_PAGE_NUMBER_88E /* 0xA9 , 0xb0=>176=>22k */
	110	#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E \
	111	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
	112
	113	/* Chip specific */
	114	#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
	115	#define CHIP_BONDING_92C_1T2R 0x1
	116	#define CHIP_BONDING_88C_USB_MCARD 0x2
	117	#define CHIP_BONDING_88C_USB_HP 0x1
	118	#include "HalVerDef.h"
	119	#include "hal_com.h"
	120
	121	/* Channel Plan */
	122	enum ChannelPlan {
	123	CHPL_FCC = 0,
	124	CHPL_IC = 1,
	125	CHPL_ETSI = 2,
	126	CHPL_SPA = 3,
	127	CHPL_FRANCE = 4,
	128	CHPL_MKK = 5,
	129	CHPL_MKK1 = 6,
	130	CHPL_ISRAEL = 7,
	131	CHPL_TELEC = 8,
	132	CHPL_GLOBAL = 9,
	133	CHPL_WORLD = 10,
	134	};
135
136	struct txpowerinfo24g {
137	u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
df80fb63	138	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
58c43401 LF	139	/* If only one tx, only BW20 and OFDM are used. */
	140	s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	141	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	142	s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	143	s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	144	};
	145
	146	#define EFUSE_REAL_CONTENT_LEN 512
58c43401 LF	147	#define EFUSE_MAX_SECTION 16
	148	#define EFUSE_IC_ID_OFFSET 506 /* For some inferior IC purpose*/
	149	#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
	150	/* To prevent out of boundary programming case, */
	151	/* leave 1byte and program full section */
	152	/* 9bytes + 1byt + 5bytes and pre 1byte. */
	153	/* For worst case: */
	154	/* \| 1byte\|----8bytes----\|1byte\|--5bytes--\| */
	155	/* \| \| Reserved(14bytes) \| */
	156
69e98df7	157	/* PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */
58c43401 LF	158	#define EFUSE_OOB_PROTECT_BYTES 15
	159
	160	#define HWSET_MAX_SIZE_88E 512
	161
	162	#define EFUSE_REAL_CONTENT_LEN_88E 256
	163	#define EFUSE_MAP_LEN_88E 512
40fac5a1	164	#define EFUSE_MAP_LEN EFUSE_MAP_LEN_88E
58c43401 LF	165	#define EFUSE_MAX_SECTION_88E 64
	166	#define EFUSE_MAX_WORD_UNIT_88E 4
	167	#define EFUSE_IC_ID_OFFSET_88E 506
	168	#define AVAILABLE_EFUSE_ADDR_88E(addr) \
	169	(addr < EFUSE_REAL_CONTENT_LEN_88E)
	170	/* To prevent out of boundary programming case, leave 1byte and program
	171	* full section */
	172	/* 9bytes + 1byt + 5bytes and pre 1byte. */
	173	/* For worst case: */
	174	/* \| 2byte\|----8bytes----\|1byte\|--7bytes--\| 92D */
69e98df7	175	/* PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */
58c43401 LF	176	#define EFUSE_OOB_PROTECT_BYTES_88E 18
	177	#define EFUSE_PROTECT_BYTES_BANK_88E 16
	178
	179	/* EFUSE for BT definition */
	180	#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 5123 /
	181	#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
	182	#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */
	183
	184	#define EFUSE_PROTECT_BYTES_BANK 16
	185
58c43401 LF	186	struct hal_data_8188e {
58c43401 LF	187	struct HAL_VERSION VersionID;
58c43401	188	u16 CustomerID;
58c43401 LF	189	u16 FirmwareVersion;
	190	u16 FirmwareVersionRev;
	191	u16 FirmwareSubVersion;
	192	u16 FirmwareSignature;
	193	u8 PGMaxGroup;
	194	/* current WIFI_PHY values */
	195	u32 ReceiveConfig;
	196	enum wireless_mode CurrentWirelessMode;
	197	enum ht_channel_width CurrentChannelBW;
	198	u8 CurrentChannel;
	199	u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */
	200
	201	u16 BasicRateSet;
	202
	203	/* rf_ctrl */
	204	u8 rf_chip;
	205	u8 rf_type;
	206	u8 NumTotalRFPath;
	207
	208	u8 BoardType;
	209
	210	/* EEPROM setting. */
	211	u16 EEPROMVID;
	212	u16 EEPROMPID;
	213	u16 EEPROMSVID;
	214	u16 EEPROMSDID;
	215	u8 EEPROMCustomerID;
	216	u8 EEPROMSubCustomerID;
	217	u8 EEPROMVersion;
	218	u8 EEPROMRegulatory;
	219
	220	u8 bTXPowerDataReadFromEEPORM;
	221	u8 EEPROMThermalMeter;
	222	u8 bAPKThermalMeterIgnore;
	223
	224	bool EepromOrEfuse;
	225	/* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
	226	u8 EfuseMap[2][HWSET_MAX_SIZE_512];
	227	u8 EfuseUsedPercentage;
	228	struct efuse_hal EfuseHal;
	229
	230	u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
	231	u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
	232	/* If only one tx, only BW20 and OFDM are used. */
	233	s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	234	s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	235	s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	236	s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
	237
	238	u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	239	/* For HT 40MHZ pwr */
	240	u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	241	/* For HT 40MHZ pwr */
	242	u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	243	/* HT 20<->40 Pwr diff */
	244	u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	245	/* For HT<->legacy pwr diff */
	246	u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	247	/* For power group */
	248	u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	249	u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
	250
	251	u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */
	252	/* The current Tx Power Level */
253	u8 CurrentCckTxPwrIdx;
254	u8 CurrentOfdm24GTxPwrIdx;
255	u8 CurrentBW2024GTxPwrIdx;
256	u8 CurrentBW4024GTxPwrIdx;
257
258
259	/* Read/write are allow for following hardware information variables */
260	u8 framesync;
261	u32 framesyncC34;
262	u8 framesyncMonitor;
263	u8 DefaultInitialGain[4];
264	u8 pwrGroupCnt;
265	u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
266	u32 CCKTxPowerLevelOriginalOffset;
267
268	u8 CrystalCap;
269	u32 AntennaTxPath; /* Antenna path Tx */
270	u32 AntennaRxPath; /* Antenna path Rx */
271	u8 BluetoothCoexist;
272	u8 ExternalPA;
273
274	u8 bLedOpenDrain; /* Open-drain support for controlling the LED.*/
275
276	u8 b1x1RecvCombine; /* for 1T1R receive combining */
277
278	u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
279
280	struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */
281
282	u32 RfRegChnlVal[2];
283
284	/* RDG enable */
285	bool bRDGEnable;
286
287	/* for host message to fw */
288	u8 LastHMEBoxNum;
289
58c43401 LF	290	u8 RegTxPause;
	291	/* Beacon function related global variable. */
	292	u32 RegBcnCtrlVal;
	293	u8 RegFwHwTxQCtrl;
	294	u8 RegReg542;
	295	u8 RegCR_1;
	296
	297	struct dm_priv dmpriv;
	298	struct odm_dm_struct odmpriv;
	299	struct sreset_priv srestpriv;
	300
	301	u8 CurAntenna;
	302	u8 AntDivCfg;
	303	u8 TRxAntDivType;
	304
	305
	306	u8 bDumpRxPkt;/* for debug */
	307	u8 bDumpTxPkt;/* for debug */
	308	u8 FwRsvdPageStartOffset; /* Reserve page start offset except
	309	* beacon in TxQ. */
	310
	311	/* 2010/08/09 MH Add CU power down mode. */
	312	bool pwrdown;
	313
	314	/* Add for dual MAC 0--Mac0 1--Mac1 */
	315	u32 interfaceIndex;
	316
	317	u8 OutEpQueueSel;
	318	u8 OutEpNumber;
	319
	320	/* Add for USB aggreation mode dynamic shceme. */
	321	bool UsbRxHighSpeedMode;
	322
	323	/* 2010/11/22 MH Add for slim combo debug mode selective. */
	324	/* This is used for fix the drawback of CU TSMC-A/UMC-A cut.
	325	* HW auto suspend ability. Close BT clock. */
	326	bool SlimComboDbg;
	327
	328	u16 EfuseUsedBytes;
	329
58c43401 LF	330	/* Auto FSM to Turn On, include clock, isolation, power control
	331	* for MAC only */
	332	u8 bMacPwrCtrlOn;
	333
	334	u32 UsbBulkOutSize;
	335
	336	/* Interrupt relatd register information. */
	337	u32 IntArray[3];/* HISR0,HISR1,HSISR */
	338	u32 IntrMask[3];
	339	u8 C2hArray[16];
	340	u8 UsbTxAggMode;
	341	u8 UsbTxAggDescNum;
	342	u16 HwRxPageSize; /* Hardware setting */
	343	u32 MaxUsbRxAggBlock;
	344
	345	enum usb_rx_agg_mode UsbRxAggMode;
	346	u8 UsbRxAggBlockCount; /* USB Block count. Block size is
	347	* 512-byte in high speed and 64-byte
	348	* in full speed */
	349	u8 UsbRxAggBlockTimeout;
	350	u8 UsbRxAggPageCount; /* 8192C DMA page count */
	351	u8 UsbRxAggPageTimeout;
	352	};
	353
	354	#define GET_HAL_DATA(__pAdapter) \
	355	((struct hal_data_8188e *)((__pAdapter)->HalData))
	356	#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
	357
58c43401	358	/* rtl8188e_hal_init.c */
58c43401 LF	359	void _8051Reset88E(struct adapter *padapter);
	360	void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
	361
	362
	363	s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
	364
	365	/* EFuse */
58c43401 LF	366	void Hal_InitPGData88E(struct adapter *padapter);
	367	void Hal_EfuseParseIDCode88E(struct adapter padapter, u8 hwinfo);
	368	void Hal_ReadTxPowerInfo88E(struct adapter padapter, u8 hwinfo,
	369	bool AutoLoadFail);
	370
	371	void Hal_EfuseParseEEPROMVer88E(struct adapter padapter, u8 hwinfo,
	372	bool AutoLoadFail);
	373	void rtl8188e_EfuseParseChnlPlan(struct adapter padapter, u8 hwinfo,
	374	bool AutoLoadFail);
	375	void Hal_EfuseParseCustomerID88E(struct adapter padapter, u8 hwinfo,
	376	bool AutoLoadFail);
3f35c7ff	377	void Hal_ReadAntennaDiversity88E(struct adapter pAdapter, u8 PROMContent,
58c43401	378	bool AutoLoadFail);
c7333c11	379	void Hal_ReadThermalMeter_88E(struct adapter dapter, u8 PROMContent,
58c43401 LF	380	bool AutoloadFail);
	381	void Hal_EfuseParseXtal_8188E(struct adapter pAdapter, u8 hwinfo,
	382	bool AutoLoadFail);
	383	void Hal_EfuseParseBoardType88E(struct adapter pAdapter, u8 hwinfo,
	384	bool AutoLoadFail);
	385	void Hal_ReadPowerSavingMode88E(struct adapter pAdapter, u8 hwinfo,
	386	bool AutoLoadFail);
	387
58c43401	388	/* register */
58c43401	389
58c43401 LF	390	void rtl8188e_start_thread(struct adapter *padapter);
	391	void rtl8188e_stop_thread(struct adapter *padapter);
	392
ee5f8a43	393	s32 iol_execute(struct adapter *padapter, u8 control);
ee5f8a43	394	void iol_mode_enable(struct adapter *padapter, u8 enable);
58c43401 LF	395	s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
58c43401 LF	396	void rtw_cancel_all_timer(struct adapter *padapter);
58c43401 LF	397
58c43401 LF	398	#endif /* __RTL8188E_HAL_H__ */