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1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2009-2010 Realtek Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * The full GNU General Public License is included in this distribution in the | |
15 | * file called LICENSE. | |
16 | * | |
17 | * Contact Information: | |
18 | * wlanfae <wlanfae@realtek.com> | |
19 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
20 | * Hsinchu 300, Taiwan. | |
21 | * | |
22 | * Larry Finger <Larry.Finger@lwfinger.net> | |
23 | * | |
24 | *****************************************************************************/ | |
25 | ||
26 | #ifndef __RTL_WIFI_H__ | |
27 | #define __RTL_WIFI_H__ | |
28 | ||
29 | #include <linux/interrupt.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/firmware.h> | |
78de2c06 LF |
32 | #include <linux/etherdevice.h> |
33 | #include <net/mac80211.h> | |
34 | #include "debug.h" | |
35 | ||
36 | ||
37 | #define RF_CHANGE_BY_INIT 0 | |
38 | #define RF_CHANGE_BY_IPS BIT(28) | |
39 | #define RF_CHANGE_BY_PS BIT(29) | |
40 | #define RF_CHANGE_BY_HW BIT(30) | |
41 | #define RF_CHANGE_BY_SW BIT(31) | |
42 | ||
43 | #define IQK_ADDA_REG_NUM 16 | |
44 | #define IQK_MAC_REG_NUM 4 | |
45 | #define IQK_THRESHOLD 8 | |
46 | ||
47 | #define MAX_KEY_LEN 61 | |
48 | #define KEY_BUF_SIZE 5 | |
49 | ||
50 | /* QoS related. */ | |
51 | /*aci: 0x00 Best Effort*/ | |
52 | /*aci: 0x01 Background*/ | |
53 | /*aci: 0x10 Video*/ | |
54 | /*aci: 0x11 Voice*/ | |
55 | /*Max: define total number.*/ | |
56 | #define AC0_BE 0 | |
57 | #define AC1_BK 1 | |
58 | #define AC2_VI 2 | |
59 | #define AC3_VO 3 | |
60 | #define AC_MAX 4 | |
61 | #define QOS_QUEUE_NUM 4 | |
62 | #define RTL_MAC80211_NUM_QUEUE 5 | |
63 | ||
64 | #define QBSS_LOAD_SIZE 5 | |
65 | #define MAX_WMMELE_LENGTH 64 | |
66 | ||
67 | #define TOTAL_CAM_ENTRY 32 | |
68 | ||
69 | /*slot time for 11g. */ | |
70 | #define RTL_SLOT_TIME_9 9 | |
71 | #define RTL_SLOT_TIME_20 20 | |
72 | ||
73 | /*related with tcp/ip. */ | |
74 | /*if_ehther.h*/ | |
75 | #define ETH_P_PAE 0x888E /*Port Access Entity | |
76 | *(IEEE 802.1X) */ | |
77 | #define ETH_P_IP 0x0800 /*Internet Protocol packet */ | |
78 | #define ETH_P_ARP 0x0806 /*Address Resolution packet */ | |
79 | #define SNAP_SIZE 6 | |
80 | #define PROTOC_TYPE_SIZE 2 | |
81 | ||
82 | /*related with 802.11 frame*/ | |
83 | #define MAC80211_3ADDR_LEN 24 | |
84 | #define MAC80211_4ADDR_LEN 30 | |
85 | ||
86 | #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max | |
87 | * channel number */ | |
88 | #define CHANNEL_MAX_NUMBER_2G 14 | |
89 | #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to | |
90 | *"phy_GetChnlGroup8812A" and | |
91 | * "Hal_ReadTxPowerInfo8812A"*/ | |
92 | ||
93 | #define MAX_REGULATION_NUM 4 | |
94 | #define MAX_RF_PATH_NUM 2 | |
95 | #define MAX_RATE_SECTION_NUM 6 | |
96 | #define MAX_2_4G_BANDWITH_NUM 2 | |
97 | #define MAX_5G_BANDWITH_NUM 4 | |
98 | ||
99 | ||
100 | ||
101 | ||
102 | #define CHANNEL_MAX_NUMBER_5G_80M 7 | |
103 | #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, ch4~9, ch10~14 | |
104 | * total three groups */ | |
105 | #define MAX_PG_GROUP 13 | |
106 | #define CHANNEL_GROUP_MAX_2G 3 | |
107 | #define CHANNEL_GROUP_IDX_5GL 3 | |
108 | #define CHANNEL_GROUP_IDX_5GM 6 | |
109 | #define CHANNEL_GROUP_IDX_5GH 9 | |
110 | #define CHANNEL_GROUP_MAX_5G 9 | |
111 | #define CHANNEL_MAX_NUMBER_2G 14 | |
112 | #define AVG_THERMAL_NUM 8 | |
113 | #define AVG_THERMAL_NUM_92E 4 | |
114 | #define AVG_THERMAL_NUM_88E 4 | |
115 | #define AVG_THERMAL_NUM_8723BE 4 | |
116 | #define MAX_TID_COUNT 9 | |
117 | #define MAX_NUM_RATES 264 | |
118 | ||
119 | /*for 88E use*/ | |
120 | /*It must always set to 4, otherwise read efuse table secquence will be wrong.*/ | |
121 | #define MAX_TX_COUNT 4 | |
122 | #define MAX_RF_PATH 4 | |
123 | #define MAX_CHNL_GROUP_24G 6 | |
124 | #define MAX_CHNL_GROUP_5G 14 | |
125 | ||
126 | /* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */ | |
127 | #define MAX_TX_QUEUE 9 | |
128 | ||
129 | #define TX_PWR_BY_RATE_NUM_BAND 2 | |
130 | #define TX_PWR_BY_RATE_NUM_RF 4 | |
131 | #define TX_PWR_BY_RATE_NUM_SECTION 12 | |
132 | #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 | |
133 | #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 | |
134 | ||
135 | #define DELTA_SWINGIDX_SIZE 30 | |
136 | #define BAND_NUM 3 | |
137 | /*Now, it's just for 8192ee | |
138 | *not OK yet, keep it 0*/ | |
139 | #define DMA_IS_64BIT 0 | |
140 | #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ | |
141 | ||
142 | ||
143 | #define PACKET_NORMAL 0 | |
144 | #define PACKET_DHCP 1 | |
145 | #define PACKET_ARP 2 | |
146 | #define PACKET_EAPOL 3 | |
147 | ||
148 | #define MAX_SUPPORT_WOL_PATTERN_NUM 16 | |
149 | #define RSVD_WOL_PATTERN_NUM 1 | |
150 | #define WKFMCAM_ADDR_NUM 6 | |
151 | #define WKFMCAM_SIZE 24 | |
152 | ||
153 | #define MAX_WOL_BIT_MASK_SIZE 16 | |
154 | /* MIN LEN keeps 13 here */ | |
155 | #define MIN_WOL_PATTERN_SIZE 13 | |
156 | #define MAX_WOL_PATTERN_SIZE 128 | |
157 | ||
158 | #define WAKE_ON_MAGIC_PACKET BIT(0) | |
159 | #define WAKE_ON_PATTERN_MATCH BIT(1) | |
160 | ||
161 | #define WOL_REASON_PTK_UPDATE BIT(0) | |
162 | #define WOL_REASON_GTK_UPDATE BIT(1) | |
163 | #define WOL_REASON_DISASSOC BIT(2) | |
164 | #define WOL_REASON_DEAUTH BIT(3) | |
165 | #define WOL_REASON_AP_LOST BIT(4) | |
166 | #define WOL_REASON_MAGIC_PKT BIT(5) | |
167 | #define WOL_REASON_UNICAST_PKT BIT(6) | |
168 | #define WOL_REASON_PATTERN_PKT BIT(7) | |
169 | #define WOL_REASON_RTD3_SSID_MATCH BIT(8) | |
170 | #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) | |
171 | #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) | |
172 | ||
173 | struct txpower_info_2g { | |
174 | u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; | |
175 | u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; | |
176 | /*If only one tx, only BW20 and OFDM are used.*/ | |
177 | u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
178 | u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
179 | u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
180 | u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
181 | }; | |
182 | ||
183 | struct txpower_info_5g { | |
184 | u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; | |
185 | /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ | |
186 | u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
187 | u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
188 | u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
189 | u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
190 | u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
191 | }; | |
192 | ||
193 | ||
194 | /* for early mode */ | |
195 | #define EM_HDR_LEN 8 | |
196 | #define FCS_LEN 4 | |
197 | ||
198 | #define MAX_VIRTUAL_MAC 1 | |
199 | ||
200 | enum rf_tx_num { | |
201 | RF_1TX = 0, | |
202 | RF_2TX, | |
203 | RF_MAX_TX_NUM, | |
204 | RF_TX_NUM_NONIMPLEMENT, | |
205 | }; | |
206 | ||
207 | enum rate_section { | |
208 | CCK = 0, | |
209 | OFDM, | |
210 | HT_MCS0_MCS7, | |
211 | HT_MCS8_MCS15, | |
212 | VHT_1SSMCS0_1SSMCS9, | |
213 | VHT_2SSMCS0_2SSMCS9, | |
214 | }; | |
215 | ||
216 | enum intf_type { | |
217 | INTF_PCI = 0, | |
218 | INTF_USB = 1, | |
219 | }; | |
220 | ||
221 | enum radio_path { | |
222 | RF90_PATH_A = 0, | |
223 | RF90_PATH_B = 1, | |
224 | RF90_PATH_C = 2, | |
225 | RF90_PATH_D = 3, | |
226 | }; | |
227 | ||
228 | enum regulation_txpwr_lmt { | |
229 | TXPWR_LMT_FCC = 0, | |
230 | TXPWR_LMT_MKK = 1, | |
231 | TXPWR_LMT_ETSI = 2, | |
232 | TXPWR_LMT_WW = 3, | |
233 | ||
234 | TXPWR_LMT_MAX_REGULATION_NUM = 4 | |
235 | }; | |
236 | ||
237 | ||
238 | enum rt_eeprom_type { | |
239 | EEPROM_93C46, | |
240 | EEPROM_93C56, | |
241 | EEPROM_BOOT_EFUSE, | |
242 | }; | |
243 | ||
244 | enum rtl_status { | |
245 | RTL_STATUS_INTERFACE_START = 0, | |
246 | }; | |
247 | ||
248 | enum hardware_type { | |
249 | HARDWARE_TYPE_RTL8192E, | |
250 | HARDWARE_TYPE_RTL8192U, | |
251 | HARDWARE_TYPE_RTL8192SE, | |
252 | HARDWARE_TYPE_RTL8192SU, | |
253 | HARDWARE_TYPE_RTL8192CE, | |
254 | HARDWARE_TYPE_RTL8192CU, | |
255 | HARDWARE_TYPE_RTL8192DE, | |
256 | HARDWARE_TYPE_RTL8192DU, | |
257 | HARDWARE_TYPE_RTL8723AE, | |
258 | HARDWARE_TYPE_RTL8188EE, | |
259 | HARDWARE_TYPE_RTL8723BE, | |
260 | HARDWARE_TYPE_RTL8192EE, | |
261 | HARDWARE_TYPE_RTL8821AE, | |
262 | HARDWARE_TYPE_RTL8812AE, | |
263 | /* keep it last */ | |
264 | HARDWARE_TYPE_NUM | |
265 | }; | |
266 | ||
267 | enum scan_operation_backup_opt { | |
268 | SCAN_OPT_BACKUP_BAND0 = 0, | |
269 | SCAN_OPT_BACKUP_BAND1, | |
270 | SCAN_OPT_RESTORE, | |
271 | SCAN_OPT_MAX | |
272 | }; | |
273 | ||
274 | /*RF state.*/ | |
275 | enum rf_pwrstate { | |
276 | ERFON, | |
277 | ERFSLEEP, | |
278 | ERFOFF | |
279 | }; | |
280 | ||
281 | struct bb_reg_def { | |
282 | u32 rfintfs; | |
283 | u32 rfintfi; | |
284 | u32 rfintfo; | |
285 | u32 rfintfe; | |
286 | u32 rf3wire_offset; | |
287 | u32 rflssi_select; | |
288 | u32 rftxgain_stage; | |
289 | u32 rfhssi_para1; | |
290 | u32 rfhssi_para2; | |
291 | u32 rfswitch_control; | |
292 | u32 rfagc_control1; | |
293 | u32 rfagc_control2; | |
294 | u32 rfrxiq_imbalance; | |
295 | u32 rfrx_afe; | |
296 | u32 rftxiq_imbalance; | |
297 | u32 rftx_afe; | |
298 | u32 rflssi_readback; | |
299 | u32 rflssi_readbackpi; | |
300 | }; | |
301 | ||
302 | enum io_type { | |
303 | IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, | |
304 | IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, | |
305 | IO_CMD_RESUME_DM_BY_SCAN = 2, | |
306 | }; | |
307 | ||
308 | enum hw_variables { | |
309 | HW_VAR_ETHER_ADDR, | |
310 | HW_VAR_MULTICAST_REG, | |
311 | HW_VAR_BASIC_RATE, | |
312 | HW_VAR_BSSID, | |
313 | HW_VAR_MEDIA_STATUS, | |
314 | HW_VAR_SECURITY_CONF, | |
315 | HW_VAR_BEACON_INTERVAL, | |
316 | HW_VAR_ATIM_WINDOW, | |
317 | HW_VAR_LISTEN_INTERVAL, | |
318 | HW_VAR_CS_COUNTER, | |
319 | HW_VAR_DEFAULTKEY0, | |
320 | HW_VAR_DEFAULTKEY1, | |
321 | HW_VAR_DEFAULTKEY2, | |
322 | HW_VAR_DEFAULTKEY3, | |
323 | HW_VAR_SIFS, | |
324 | HW_VAR_R2T_SIFS, | |
325 | HW_VAR_DIFS, | |
326 | HW_VAR_EIFS, | |
327 | HW_VAR_SLOT_TIME, | |
328 | HW_VAR_ACK_PREAMBLE, | |
329 | HW_VAR_CW_CONFIG, | |
330 | HW_VAR_CW_VALUES, | |
331 | HW_VAR_RATE_FALLBACK_CONTROL, | |
332 | HW_VAR_CONTENTION_WINDOW, | |
333 | HW_VAR_RETRY_COUNT, | |
334 | HW_VAR_TR_SWITCH, | |
335 | HW_VAR_COMMAND, | |
336 | HW_VAR_WPA_CONFIG, | |
337 | HW_VAR_AMPDU_MIN_SPACE, | |
338 | HW_VAR_SHORTGI_DENSITY, | |
339 | HW_VAR_AMPDU_FACTOR, | |
340 | HW_VAR_MCS_RATE_AVAILABLE, | |
341 | HW_VAR_AC_PARAM, | |
342 | HW_VAR_ACM_CTRL, | |
343 | HW_VAR_DIS_Req_Qsize, | |
344 | HW_VAR_CCX_CHNL_LOAD, | |
345 | HW_VAR_CCX_NOISE_HISTOGRAM, | |
346 | HW_VAR_CCX_CLM_NHM, | |
347 | HW_VAR_TxOPLimit, | |
348 | HW_VAR_TURBO_MODE, | |
349 | HW_VAR_RF_STATE, | |
350 | HW_VAR_RF_OFF_BY_HW, | |
351 | HW_VAR_BUS_SPEED, | |
352 | HW_VAR_SET_DEV_POWER, | |
353 | ||
354 | HW_VAR_RCR, | |
355 | HW_VAR_RATR_0, | |
356 | HW_VAR_RRSR, | |
357 | HW_VAR_CPU_RST, | |
358 | HW_VAR_CECHK_BSSID, | |
359 | HW_VAR_LBK_MODE, | |
360 | HW_VAR_AES_11N_FIX, | |
361 | HW_VAR_USB_RX_AGGR, | |
362 | HW_VAR_USER_CONTROL_TURBO_MODE, | |
363 | HW_VAR_RETRY_LIMIT, | |
364 | HW_VAR_INIT_TX_RATE, | |
365 | HW_VAR_TX_RATE_REG, | |
366 | HW_VAR_EFUSE_USAGE, | |
367 | HW_VAR_EFUSE_BYTES, | |
368 | HW_VAR_AUTOLOAD_STATUS, | |
369 | HW_VAR_RF_2R_DISABLE, | |
370 | HW_VAR_SET_RPWM, | |
371 | HW_VAR_H2C_FW_PWRMODE, | |
372 | HW_VAR_H2C_FW_JOINBSSRPT, | |
373 | HW_VAR_H2C_FW_MEDIASTATUSRPT, | |
374 | HW_VAR_H2C_FW_P2P_PS_OFFLOAD, | |
375 | HW_VAR_FW_PSMODE_STATUS, | |
376 | HW_VAR_INIT_RTS_RATE, | |
377 | HW_VAR_RESUME_CLK_ON, | |
378 | HW_VAR_FW_LPS_ACTION, | |
379 | HW_VAR_1X1_RECV_COMBINE, | |
380 | HW_VAR_STOP_SEND_BEACON, | |
381 | HW_VAR_TSF_TIMER, | |
382 | HW_VAR_IO_CMD, | |
383 | ||
384 | HW_VAR_RF_RECOVERY, | |
385 | HW_VAR_H2C_FW_UPDATE_GTK, | |
386 | HW_VAR_WF_MASK, | |
387 | HW_VAR_WF_CRC, | |
388 | HW_VAR_WF_IS_MAC_ADDR, | |
389 | HW_VAR_H2C_FW_OFFLOAD, | |
390 | HW_VAR_RESET_WFCRC, | |
391 | ||
392 | HW_VAR_HANDLE_FW_C2H, | |
393 | HW_VAR_DL_FW_RSVD_PAGE, | |
394 | HW_VAR_AID, | |
395 | HW_VAR_HW_SEQ_ENABLE, | |
396 | HW_VAR_CORRECT_TSF, | |
397 | HW_VAR_BCN_VALID, | |
398 | HW_VAR_FWLPS_RF_ON, | |
399 | HW_VAR_DUAL_TSF_RST, | |
400 | HW_VAR_SWITCH_EPHY_WoWLAN, | |
401 | HW_VAR_INT_MIGRATION, | |
402 | HW_VAR_INT_AC, | |
403 | HW_VAR_RF_TIMING, | |
404 | ||
405 | HAL_DEF_WOWLAN, | |
406 | HW_VAR_MRC, | |
407 | HW_VAR_KEEP_ALIVE, | |
408 | HW_VAR_NAV_UPPER, | |
409 | }; | |
410 | ||
411 | enum rt_media_status { | |
412 | RT_MEDIA_DISCONNECT = 0, | |
413 | RT_MEDIA_CONNECT = 1 | |
414 | }; | |
415 | ||
416 | enum rt_oem_id { | |
417 | RT_CID_DEFAULT = 0, | |
418 | RT_CID_8187_ALPHA0 = 1, | |
419 | RT_CID_8187_SERCOMM_PS = 2, | |
420 | RT_CID_8187_HW_LED = 3, | |
421 | RT_CID_8187_NETGEAR = 4, | |
422 | RT_CID_WHQL = 5, | |
423 | RT_CID_819x_CAMEO = 6, | |
424 | RT_CID_819x_RUNTOP = 7, | |
425 | RT_CID_819x_Senao = 8, | |
426 | RT_CID_TOSHIBA = 9, | |
427 | RT_CID_819x_Netcore = 10, | |
428 | RT_CID_Nettronix = 11, | |
429 | RT_CID_DLINK = 12, | |
430 | RT_CID_PRONET = 13, | |
431 | RT_CID_COREGA = 14, | |
432 | RT_CID_819x_ALPHA = 15, | |
433 | RT_CID_819x_Sitecom = 16, | |
434 | RT_CID_CCX = 17, | |
435 | RT_CID_819x_Lenovo = 18, | |
436 | RT_CID_819x_QMI = 19, | |
437 | RT_CID_819x_Edimax_Belkin = 20, | |
438 | RT_CID_819x_Sercomm_Belkin = 21, | |
439 | RT_CID_819x_CAMEO1 = 22, | |
440 | RT_CID_819x_MSI = 23, | |
441 | RT_CID_819x_Acer = 24, | |
442 | RT_CID_819x_HP = 27, | |
443 | RT_CID_819x_CLEVO = 28, | |
444 | RT_CID_819x_Arcadyan_Belkin = 29, | |
445 | RT_CID_819x_SAMSUNG = 30, | |
446 | RT_CID_819x_WNC_COREGA = 31, | |
447 | RT_CID_819x_Foxcoon = 32, | |
448 | RT_CID_819x_DELL = 33, | |
449 | RT_CID_819x_PRONETS = 34, | |
450 | RT_CID_819x_Edimax_ASUS = 35, | |
451 | RT_CID_NETGEAR = 36, | |
452 | RT_CID_PLANEX = 37, | |
453 | RT_CID_CC_C = 38, | |
454 | }; | |
455 | ||
456 | enum hw_descs { | |
457 | HW_DESC_OWN, | |
458 | HW_DESC_RXOWN, | |
459 | HW_DESC_TX_NEXTDESC_ADDR, | |
460 | HW_DESC_TXBUFF_ADDR, | |
461 | HW_DESC_RXBUFF_ADDR, | |
462 | HW_DESC_RXPKT_LEN, | |
463 | HW_DESC_RXERO, | |
464 | HW_DESC_RX_PREPARE, | |
465 | }; | |
466 | ||
467 | enum prime_sc { | |
468 | PRIME_CHNL_OFFSET_DONT_CARE = 0, | |
469 | PRIME_CHNL_OFFSET_LOWER = 1, | |
470 | PRIME_CHNL_OFFSET_UPPER = 2, | |
471 | }; | |
472 | ||
473 | enum rf_type { | |
474 | RF_1T1R = 0, | |
475 | RF_1T2R = 1, | |
476 | RF_2T2R = 2, | |
477 | RF_2T2R_GREEN = 3, | |
478 | }; | |
479 | ||
480 | enum ht_channel_width { | |
481 | HT_CHANNEL_WIDTH_20 = 0, | |
482 | HT_CHANNEL_WIDTH_20_40 = 1, | |
483 | HT_CHANNEL_WIDTH_80 = 2, | |
484 | }; | |
485 | ||
486 | /* Ref: 802.11i sepc D10.0 7.3.2.25.1 | |
487 | Cipher Suites Encryption Algorithms */ | |
488 | enum rt_enc_alg { | |
489 | NO_ENCRYPTION = 0, | |
490 | WEP40_ENCRYPTION = 1, | |
491 | TKIP_ENCRYPTION = 2, | |
492 | RSERVED_ENCRYPTION = 3, | |
493 | AESCCMP_ENCRYPTION = 4, | |
494 | WEP104_ENCRYPTION = 5, | |
495 | AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ | |
496 | }; | |
497 | ||
498 | enum rtl_hal_state { | |
499 | _HAL_STATE_STOP = 0, | |
500 | _HAL_STATE_START = 1, | |
501 | }; | |
502 | ||
503 | enum rtl_var_map { | |
504 | /*reg map */ | |
505 | SYS_ISO_CTRL = 0, | |
506 | SYS_FUNC_EN, | |
507 | SYS_CLK, | |
508 | MAC_RCR_AM, | |
509 | MAC_RCR_AB, | |
510 | MAC_RCR_ACRC32, | |
511 | MAC_RCR_ACF, | |
512 | MAC_RCR_AAP, | |
513 | MAC_HIMR, | |
514 | MAC_HIMRE, | |
515 | MAC_HSISR, | |
516 | ||
517 | /*efuse map */ | |
518 | EFUSE_TEST, | |
519 | EFUSE_CTRL, | |
520 | EFUSE_CLK, | |
521 | EFUSE_CLK_CTRL, | |
522 | EFUSE_PWC_EV12V, | |
523 | EFUSE_FEN_ELDR, | |
524 | EFUSE_LOADER_CLK_EN, | |
525 | EFUSE_ANA8M, | |
526 | EFUSE_HWSET_MAX_SIZE, | |
527 | EFUSE_MAX_SECTION_MAP, | |
528 | EFUSE_REAL_CONTENT_SIZE, | |
529 | EFUSE_OOB_PROTECT_BYTES_LEN, | |
530 | EFUSE_ACCESS, | |
531 | /*CAM map */ | |
532 | RWCAM, | |
533 | WCAMI, | |
534 | RCAMO, | |
535 | CAMDBG, | |
536 | SECR, | |
537 | SEC_CAM_NONE, | |
538 | SEC_CAM_WEP40, | |
539 | SEC_CAM_TKIP, | |
540 | SEC_CAM_AES, | |
541 | SEC_CAM_WEP104, | |
542 | ||
543 | /*IMR map */ | |
544 | RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ | |
545 | RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ | |
546 | RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ | |
547 | RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ | |
548 | RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ | |
549 | RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ | |
550 | RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ | |
551 | RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ | |
552 | RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ | |
553 | RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ | |
554 | RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ | |
555 | RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ | |
556 | RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ | |
557 | RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ | |
558 | RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ | |
559 | RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ | |
560 | RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ | |
561 | RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ | |
562 | RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */ | |
563 | RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ | |
564 | RTL_IMR_RDU, /*Receive Descriptor Unavailable */ | |
565 | RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ | |
566 | RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ | |
567 | RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ | |
568 | RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ | |
569 | RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ | |
570 | RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ | |
571 | RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ | |
572 | RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ | |
573 | RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ | |
574 | RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ | |
575 | RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ | |
576 | RTL_IMR_ROK, /*Receive DMA OK Interrupt */ | |
577 | RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ | |
578 | RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK | | |
579 | * RTL_IMR_TBDER) */ | |
580 | RTL_IMR_C2HCMD, /*fw interrupt*/ | |
581 | ||
582 | /*CCK Rates, TxHT = 0 */ | |
583 | RTL_RC_CCK_RATE1M, | |
584 | RTL_RC_CCK_RATE2M, | |
585 | RTL_RC_CCK_RATE5_5M, | |
586 | RTL_RC_CCK_RATE11M, | |
587 | ||
588 | /*OFDM Rates, TxHT = 0 */ | |
589 | RTL_RC_OFDM_RATE6M, | |
590 | RTL_RC_OFDM_RATE9M, | |
591 | RTL_RC_OFDM_RATE12M, | |
592 | RTL_RC_OFDM_RATE18M, | |
593 | RTL_RC_OFDM_RATE24M, | |
594 | RTL_RC_OFDM_RATE36M, | |
595 | RTL_RC_OFDM_RATE48M, | |
596 | RTL_RC_OFDM_RATE54M, | |
597 | ||
598 | RTL_RC_HT_RATEMCS7, | |
599 | RTL_RC_HT_RATEMCS15, | |
600 | ||
601 | RTL_RC_VHT_RATE_1SS_MCS7, | |
602 | RTL_RC_VHT_RATE_1SS_MCS8, | |
603 | RTL_RC_VHT_RATE_1SS_MCS9, | |
604 | RTL_RC_VHT_RATE_2SS_MCS7, | |
605 | RTL_RC_VHT_RATE_2SS_MCS8, | |
606 | RTL_RC_VHT_RATE_2SS_MCS9, | |
607 | ||
608 | /*keep it last */ | |
609 | RTL_VAR_MAP_MAX, | |
610 | }; | |
611 | ||
612 | /*Firmware PS mode for control LPS.*/ | |
613 | enum _fw_ps_mode { | |
614 | FW_PS_ACTIVE_MODE = 0, | |
615 | FW_PS_MIN_MODE = 1, | |
616 | FW_PS_MAX_MODE = 2, | |
617 | FW_PS_DTIM_MODE = 3, | |
618 | FW_PS_VOIP_MODE = 4, | |
619 | FW_PS_UAPSD_WMM_MODE = 5, | |
620 | FW_PS_UAPSD_MODE = 6, | |
621 | FW_PS_IBSS_MODE = 7, | |
622 | FW_PS_WWLAN_MODE = 8, | |
623 | FW_PS_PM_Radio_Off = 9, | |
624 | FW_PS_PM_Card_Disable = 10, | |
625 | }; | |
626 | ||
627 | enum rt_psmode { | |
628 | EACTIVE, /*Active/Continuous access. */ | |
629 | EMAXPS, /*Max power save mode. */ | |
630 | EFASTPS, /*Fast power save mode. */ | |
631 | EAUTOPS, /*Auto power save mode. */ | |
632 | }; | |
633 | ||
634 | /*LED related.*/ | |
635 | enum led_ctl_mode { | |
636 | LED_CTL_POWER_ON = 1, | |
637 | LED_CTL_LINK = 2, | |
638 | LED_CTL_NO_LINK = 3, | |
639 | LED_CTL_TX = 4, | |
640 | LED_CTL_RX = 5, | |
641 | LED_CTL_SITE_SURVEY = 6, | |
642 | LED_CTL_POWER_OFF = 7, | |
643 | LED_CTL_START_TO_LINK = 8, | |
644 | LED_CTL_START_WPS = 9, | |
645 | LED_CTL_STOP_WPS = 10, | |
646 | }; | |
647 | ||
648 | enum rtl_led_pin { | |
649 | LED_PIN_GPIO0, | |
650 | LED_PIN_LED0, | |
651 | LED_PIN_LED1, | |
652 | LED_PIN_LED2 | |
653 | }; | |
654 | ||
655 | /*QoS related.*/ | |
656 | /*acm implementation method.*/ | |
657 | enum acm_method { | |
658 | eAcmWay0_SwAndHw = 0, | |
659 | eAcmWay1_HW = 1, | |
660 | eAcmWay2_SW = 2, | |
661 | }; | |
662 | ||
663 | enum macphy_mode { | |
664 | SINGLEMAC_SINGLEPHY = 0, | |
665 | DUALMAC_DUALPHY, | |
666 | DUALMAC_SINGLEPHY, | |
667 | }; | |
668 | ||
669 | enum band_type { | |
670 | BAND_ON_2_4G = 0, | |
671 | BAND_ON_5G, | |
672 | BAND_ON_BOTH, | |
673 | BANDMAX | |
674 | }; | |
675 | ||
676 | /*aci/aifsn Field. | |
677 | Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ | |
678 | union aci_aifsn { | |
679 | u8 char_data; | |
680 | ||
681 | struct { | |
682 | u8 aifsn:4; | |
683 | u8 acm:1; | |
684 | u8 aci:2; | |
685 | u8 reserved:1; | |
686 | } f; /* Field */ | |
687 | }; | |
688 | ||
689 | /*mlme related.*/ | |
690 | enum wireless_mode { | |
691 | WIRELESS_MODE_UNKNOWN = 0x00, | |
692 | WIRELESS_MODE_A = 0x01, | |
693 | WIRELESS_MODE_B = 0x02, | |
694 | WIRELESS_MODE_G = 0x04, | |
695 | WIRELESS_MODE_AUTO = 0x08, | |
696 | WIRELESS_MODE_N_24G = 0x10, | |
697 | WIRELESS_MODE_N_5G = 0x20, | |
698 | WIRELESS_MODE_AC_5G = 0x40, | |
699 | WIRELESS_MODE_AC_24G = 0x80, | |
700 | WIRELESS_MODE_AC_ONLY = 0x100, | |
701 | WIRELESS_MODE_MAX = 0x800 | |
702 | }; | |
703 | ||
704 | enum ratr_table_mode { | |
705 | RATR_INX_WIRELESS_NGB = 0, | |
706 | RATR_INX_WIRELESS_NG = 1, | |
707 | RATR_INX_WIRELESS_NB = 2, | |
708 | RATR_INX_WIRELESS_N = 3, | |
709 | RATR_INX_WIRELESS_GB = 4, | |
710 | RATR_INX_WIRELESS_G = 5, | |
711 | RATR_INX_WIRELESS_B = 6, | |
712 | RATR_INX_WIRELESS_MC = 7, | |
713 | RATR_INX_WIRELESS_AC_5N = 8, | |
714 | RATR_INX_WIRELESS_AC_24N = 9, | |
715 | }; | |
716 | ||
717 | enum rtl_link_state { | |
718 | MAC80211_NOLINK = 0, | |
719 | MAC80211_LINKING = 1, | |
720 | MAC80211_LINKED = 2, | |
721 | MAC80211_LINKED_SCANNING = 3, | |
722 | }; | |
723 | ||
724 | enum act_category { | |
725 | ACT_CAT_QOS = 1, | |
726 | ACT_CAT_DLS = 2, | |
727 | ACT_CAT_BA = 3, | |
728 | ACT_CAT_HT = 7, | |
729 | ACT_CAT_WMM = 17, | |
730 | }; | |
731 | ||
732 | enum ba_action { | |
733 | ACT_ADDBAREQ = 0, | |
734 | ACT_ADDBARSP = 1, | |
735 | ACT_DELBA = 2, | |
736 | }; | |
737 | ||
738 | enum rt_polarity_ctl { | |
739 | RT_POLARITY_LOW_ACT = 0, | |
740 | RT_POLARITY_HIGH_ACT = 1, | |
741 | }; | |
742 | ||
743 | /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ | |
744 | enum fw_wow_reason_v2 { | |
745 | FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, | |
746 | FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, | |
747 | FW_WOW_V2_DISASSOC_EVENT = 0x04, | |
748 | FW_WOW_V2_DEAUTH_EVENT = 0x08, | |
749 | FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, | |
750 | FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, | |
751 | FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, | |
752 | FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, | |
753 | FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, | |
754 | FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, | |
755 | FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, | |
756 | FW_WOW_V2_REASON_MAX = 0xff, | |
757 | }; | |
758 | ||
759 | enum wolpattern_type { | |
760 | UNICAST_PATTERN = 0, | |
761 | MULTICAST_PATTERN = 1, | |
762 | BROADCAST_PATTERN = 2, | |
763 | DONT_CARE_DA = 3, | |
764 | UNKNOWN_TYPE = 4, | |
765 | }; | |
766 | ||
767 | struct octet_string { | |
768 | u8 *octet; | |
769 | u16 length; | |
770 | }; | |
771 | ||
772 | struct rtl_hdr_3addr { | |
773 | __le16 frame_ctl; | |
774 | __le16 duration_id; | |
775 | u8 addr1[ETH_ALEN]; | |
776 | u8 addr2[ETH_ALEN]; | |
777 | u8 addr3[ETH_ALEN]; | |
778 | __le16 seq_ctl; | |
779 | u8 payload[0]; | |
780 | } __packed; | |
781 | ||
782 | struct rtl_info_element { | |
783 | u8 id; | |
784 | u8 len; | |
785 | u8 data[0]; | |
786 | } __packed; | |
787 | ||
788 | struct rtl_probe_rsp { | |
789 | struct rtl_hdr_3addr header; | |
790 | u32 time_stamp[2]; | |
791 | __le16 beacon_interval; | |
792 | __le16 capability; | |
793 | /*SSID, supported rates, FH params, DS params, | |
794 | CF params, IBSS params, TIM (if beacon), RSN */ | |
795 | struct rtl_info_element info_element[0]; | |
796 | } __packed; | |
797 | ||
798 | /*LED related.*/ | |
799 | /*ledpin Identify how to implement this SW led.*/ | |
800 | struct rtl_led { | |
801 | void *hw; | |
802 | enum rtl_led_pin ledpin; | |
803 | bool b_ledon; | |
804 | }; | |
805 | ||
806 | struct rtl_led_ctl { | |
807 | bool bled_opendrain; | |
808 | struct rtl_led sw_led0; | |
809 | struct rtl_led sw_led1; | |
810 | }; | |
811 | ||
812 | struct rtl_qos_parameters { | |
813 | __le16 cw_min; | |
814 | __le16 cw_max; | |
815 | u8 aifs; | |
816 | u8 flag; | |
817 | __le16 tx_op; | |
818 | } __packed; | |
819 | ||
820 | struct rt_smooth_data { | |
821 | u32 elements[100]; /*array to store values */ | |
822 | u32 index; /*index to current array to store */ | |
823 | u32 total_num; /*num of valid elements */ | |
824 | u32 total_val; /*sum of valid elements */ | |
825 | }; | |
826 | ||
827 | struct rtl_ht_agg { | |
828 | u16 txq_id; | |
829 | u16 wait_for_ba; | |
830 | u16 start_idx; | |
831 | u64 bitmap; | |
832 | u32 rate_n_flags; | |
833 | u8 agg_state; | |
834 | u8 rx_agg_state; | |
835 | }; | |
836 | ||
837 | struct rtl_tid_data { | |
838 | u16 seq_number; | |
839 | struct rtl_ht_agg agg; | |
840 | }; | |
841 | ||
842 | struct rssi_sta { | |
843 | long undecorated_smoothed_pwdb; | |
844 | }; | |
845 | ||
846 | struct rtl_sta_info { | |
847 | struct list_head list; | |
848 | u8 ratr_index; | |
849 | u8 wireless_mode; | |
850 | u8 mimo_ps; | |
851 | u8 mac_addr[6]; | |
852 | struct rtl_tid_data tids[MAX_TID_COUNT]; | |
853 | ||
854 | /* just used for ap adhoc or mesh*/ | |
855 | struct rssi_sta rssi_stat; | |
856 | } __packed; | |
857 | ||
858 | struct false_alarm_statistics { | |
859 | u32 cnt_parity_fail; | |
860 | u32 cnt_rate_illegal; | |
861 | u32 cnt_crc8_fail; | |
862 | u32 cnt_mcs_fail; | |
863 | u32 cnt_fast_fsync_fail; | |
864 | u32 cnt_sb_search_fail; | |
865 | u32 cnt_ofdm_fail; | |
866 | u32 cnt_cck_fail; | |
867 | u32 cnt_all; | |
868 | u32 cnt_ofdm_cca; | |
869 | u32 cnt_cck_cca; | |
870 | u32 cnt_cca_all; | |
871 | u32 cnt_bw_usc; | |
872 | u32 cnt_bw_lsc; | |
873 | }; | |
874 | ||
875 | struct init_gain { | |
876 | u8 xaagccore1; | |
877 | u8 xbagccore1; | |
878 | u8 xcagccore1; | |
879 | u8 xdagccore1; | |
880 | u8 cca; | |
881 | ||
882 | }; | |
883 | ||
884 | struct wireless_stats { | |
885 | unsigned long txbytesunicast; | |
886 | unsigned long txbytesmulticast; | |
887 | unsigned long txbytesbroadcast; | |
888 | unsigned long rxbytesunicast; | |
889 | ||
890 | long rx_snr_db[4]; | |
891 | /*Correct smoothed ss in Dbm, only used | |
892 | in driver to report real power now. */ | |
893 | long recv_signal_power; | |
894 | long signal_quality; | |
895 | long last_sigstrength_inpercent; | |
896 | ||
897 | u32 rssi_calculate_cnt; | |
898 | u32 pwdb_all_cnt; | |
899 | ||
900 | /*Transformed, in dbm. Beautified signal | |
901 | strength for UI, not correct. */ | |
902 | long signal_strength; | |
903 | ||
904 | u8 rx_rssi_percentage[4]; | |
905 | u8 rx_evm_dbm[4]; | |
906 | u8 rx_evm_percentage[2]; | |
907 | ||
908 | u16 rx_cfo_short[4]; | |
909 | u16 rx_cfo_tail[4]; | |
910 | ||
911 | struct rt_smooth_data ui_rssi; | |
912 | struct rt_smooth_data ui_link_quality; | |
913 | }; | |
914 | ||
915 | struct rate_adaptive { | |
916 | u8 rate_adaptive_disabled; | |
917 | u8 ratr_state; | |
918 | u16 reserve; | |
919 | ||
920 | u32 high_rssi_thresh_for_ra; | |
921 | u32 high2low_rssi_thresh_for_ra; | |
922 | u8 low2high_rssi_thresh_for_ra; | |
923 | u32 low_rssi_thresh_for_ra; | |
924 | u32 upper_rssi_threshold_ratr; | |
925 | u32 middleupper_rssi_threshold_ratr; | |
926 | u32 middle_rssi_threshold_ratr; | |
927 | u32 middlelow_rssi_threshold_ratr; | |
928 | u32 low_rssi_threshold_ratr; | |
929 | u32 ultralow_rssi_threshold_ratr; | |
930 | u32 low_rssi_threshold_ratr_40m; | |
931 | u32 low_rssi_threshold_ratr_20m; | |
932 | u8 ping_rssi_enable; | |
933 | u32 ping_rssi_ratr; | |
934 | u32 ping_rssi_thresh_for_ra; | |
935 | u32 last_ratr; | |
936 | u8 pre_ratr_state; | |
937 | u8 ldpc_thres; | |
938 | bool use_ldpc; | |
939 | bool lower_rts_rate; | |
940 | bool is_special_data; | |
941 | }; | |
942 | ||
943 | struct regd_pair_mapping { | |
944 | u16 reg_dmnenum; | |
945 | u16 reg_5ghz_ctl; | |
946 | u16 reg_2ghz_ctl; | |
947 | }; | |
948 | ||
949 | struct dynamic_primary_cca { | |
950 | u8 pricca_flag; | |
951 | u8 intf_flag; | |
952 | u8 intf_type; | |
953 | u8 dup_rts_flag; | |
954 | u8 monitor_flag; | |
955 | u8 ch_offset; | |
956 | u8 mf_state; | |
957 | }; | |
958 | ||
959 | struct rtl_regulatory { | |
960 | char alpha2[2]; | |
961 | u16 country_code; | |
962 | u16 max_power_level; | |
963 | u32 tp_scale; | |
964 | u16 current_rd; | |
965 | u16 current_rd_ext; | |
966 | int16_t power_limit; | |
967 | struct regd_pair_mapping *regpair; | |
968 | }; | |
969 | ||
970 | struct rtl_rfkill { | |
971 | bool rfkill_state; /*0 is off, 1 is on */ | |
972 | }; | |
973 | ||
974 | /*for P2P PS**/ | |
975 | #define P2P_MAX_NOA_NUM 2 | |
976 | ||
977 | enum p2p_role { | |
978 | P2P_ROLE_DISABLE = 0, | |
979 | P2P_ROLE_DEVICE = 1, | |
980 | P2P_ROLE_CLIENT = 2, | |
981 | P2P_ROLE_GO = 3 | |
982 | }; | |
983 | ||
984 | enum p2p_ps_state { | |
985 | P2P_PS_DISABLE = 0, | |
986 | P2P_PS_ENABLE = 1, | |
987 | P2P_PS_SCAN = 2, | |
988 | P2P_PS_SCAN_DONE = 3, | |
989 | P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ | |
990 | }; | |
991 | ||
992 | enum p2p_ps_mode { | |
993 | P2P_PS_NONE = 0, | |
994 | P2P_PS_CTWINDOW = 1, | |
995 | P2P_PS_NOA = 2, | |
996 | P2P_PS_MIX = 3, /* CTWindow and NoA*/ | |
997 | }; | |
998 | ||
999 | struct rtl_p2p_ps_info { | |
1000 | enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ | |
1001 | enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ | |
1002 | u8 noa_index; /* Identifies and instance of Notice of Absence timing. */ | |
1003 | /* Client traffic window. A period of time in TU after TBTT. */ | |
1004 | u8 ctwindow; | |
1005 | u8 opp_ps; /* opportunistic power save. */ | |
1006 | u8 noa_num; /* number of NoA descriptor in P2P IE. */ | |
1007 | /* Count for owner, Type of client. */ | |
1008 | u8 noa_count_type[P2P_MAX_NOA_NUM]; | |
1009 | /* Max duration for owner, preferred or | |
1010 | * min acceptable duration for client. */ | |
1011 | u32 noa_duration[P2P_MAX_NOA_NUM]; | |
1012 | /* Length of interval for owner, preferred or | |
1013 | * max acceptable interval of client. */ | |
1014 | u32 noa_interval[P2P_MAX_NOA_NUM]; | |
1015 | /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */ | |
1016 | u32 noa_start_time[P2P_MAX_NOA_NUM]; | |
1017 | }; | |
1018 | ||
1019 | struct p2p_ps_offload_t { | |
1020 | u8 Offload_En:1; | |
1021 | u8 role:1; /* 1: Owner, 0: Client */ | |
1022 | u8 CTWindow_En:1; | |
1023 | u8 NoA0_En:1; | |
1024 | u8 NoA1_En:1; | |
1025 | u8 AllStaSleep:1; | |
1026 | u8 discovery:1; | |
1027 | u8 reserved:1; | |
1028 | }; | |
1029 | ||
1030 | #define IQK_MATRIX_REG_NUM 8 | |
1031 | /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ | |
1032 | #define IQK_MATRIX_SETTINGS_NUM (14 + 24 + 21) | |
1033 | struct iqk_matrix_regs { | |
1034 | bool b_iqk_done; | |
1035 | long value[1][IQK_MATRIX_REG_NUM]; | |
1036 | }; | |
1037 | ||
1038 | struct rtl_phy { | |
1039 | struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ | |
1040 | struct init_gain initgain_backup; | |
1041 | enum io_type current_io_type; | |
1042 | ||
1043 | u8 rf_mode; | |
1044 | u8 rf_type; | |
1045 | u8 current_chan_bw; | |
1046 | u8 set_bwmode_inprogress; | |
1047 | u8 sw_chnl_inprogress; | |
1048 | u8 sw_chnl_stage; | |
1049 | u8 sw_chnl_step; | |
1050 | u8 current_channel; | |
1051 | u8 h2c_box_num; | |
1052 | u8 set_io_inprogress; | |
1053 | u8 lck_inprogress; | |
1054 | bool iqk_inprogress; | |
1055 | ||
1056 | /* record for power tracking */ | |
1057 | s32 reg_e94; | |
1058 | s32 reg_e9c; | |
1059 | s32 reg_ea4; | |
1060 | s32 reg_eac; | |
1061 | s32 reg_eb4; | |
1062 | s32 reg_ebc; | |
1063 | s32 reg_ec4; | |
1064 | s32 reg_ecc; | |
1065 | u8 rfpienable; | |
1066 | u8 reserve_0; | |
1067 | u16 reserve_1; | |
1068 | u32 reg_c04, reg_c08, reg_874; | |
1069 | u32 adda_backup[16]; | |
1070 | u32 iqk_mac_backup[IQK_MAC_REG_NUM]; | |
1071 | u32 iqk_bb_backup[10]; | |
1072 | bool iqk_initialized; | |
1073 | ||
1074 | bool rfpath_rx_enable[MAX_RF_PATH]; | |
1075 | /*Jaguar*/ | |
1076 | u8 reg_837; | |
1077 | /* Dul mac */ | |
1078 | bool b_need_iqk; | |
1079 | struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM]; | |
1080 | ||
1081 | bool b_rfpi_enable; | |
1082 | ||
1083 | u8 pwrgroup_cnt; | |
1084 | u8 bcck_high_power; | |
1085 | /* this is for 88E & 8723A */ | |
1086 | u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; | |
1087 | /* this is for 92EE */ | |
1088 | u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] | |
1089 | [TX_PWR_BY_RATE_NUM_RF] | |
1090 | [TX_PWR_BY_RATE_NUM_RF] | |
1091 | [TX_PWR_BY_RATE_NUM_SECTION]; | |
1092 | u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] | |
1093 | [TX_PWR_BY_RATE_NUM_RF] | |
1094 | [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; | |
1095 | ||
1096 | u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] | |
1097 | [TX_PWR_BY_RATE_NUM_RF] | |
1098 | [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; | |
1099 | u8 default_initialgain[4]; | |
1100 | ||
1101 | /* the current Tx power level */ | |
1102 | u8 cur_cck_txpwridx; | |
1103 | u8 cur_ofdm24g_txpwridx; | |
1104 | u8 cur_bw20_txpwridx; | |
1105 | u8 cur_bw40_txpwridx; | |
1106 | ||
1107 | char txpwr_limit_2_4g[MAX_REGULATION_NUM] | |
1108 | [MAX_2_4G_BANDWITH_NUM] | |
1109 | [MAX_RATE_SECTION_NUM] | |
1110 | [CHANNEL_MAX_NUMBER_2G] | |
1111 | [MAX_RF_PATH_NUM]; | |
1112 | char txpwr_limit_5g[MAX_REGULATION_NUM] | |
1113 | [MAX_5G_BANDWITH_NUM] | |
1114 | [MAX_RATE_SECTION_NUM] | |
1115 | [CHANNEL_MAX_NUMBER_5G] | |
1116 | [MAX_RF_PATH_NUM]; | |
1117 | ||
1118 | u32 rfreg_chnlval[2]; | |
1119 | bool b_apk_done; | |
1120 | u32 reg_rf3c[2]; /* pathA / pathB */ | |
1121 | ||
1122 | u32 backup_rf_0x1a;/*92ee*/ | |
1123 | /* bfsync */ | |
1124 | u8 framesync; | |
1125 | u32 framesync_c34; | |
1126 | ||
1127 | u8 num_total_rfpath; | |
1128 | u16 rf_pathmap; | |
1129 | ||
1130 | enum rt_polarity_ctl polarity_ctl; | |
1131 | }; | |
1132 | ||
1133 | #define RTL_AGG_STOP 0 | |
1134 | #define RTL_AGG_PROGRESS 1 | |
1135 | #define RTL_AGG_START 2 | |
1136 | #define RTL_AGG_OPERATIONAL 3 | |
1137 | #define RTL_RX_AGG_START 1 | |
1138 | #define RTL_RX_AGG_STOP 0 | |
1139 | ||
1140 | struct rtl_priv; | |
1141 | struct rtl_io { | |
1142 | struct device *dev; | |
1143 | ||
1144 | /*PCI MEM map */ | |
1145 | unsigned long pci_mem_end; /*shared mem end */ | |
1146 | unsigned long pci_mem_start; /*shared mem start */ | |
1147 | ||
1148 | /*PCI IO map */ | |
1149 | unsigned long pci_base_addr; /*device I/O address */ | |
1150 | ||
1151 | void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val); | |
1152 | void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val); | |
1153 | void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val); | |
1154 | ||
1155 | u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr); | |
1156 | u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr); | |
1157 | u32 (*read32_sync)(struct rtl_priv *rtlpriv, u32 addr); | |
1158 | ||
1159 | }; | |
1160 | ||
1161 | struct rtl_mac { | |
1162 | u8 mac_addr[ETH_ALEN]; | |
1163 | u8 mac80211_registered; | |
1164 | u8 beacon_enabled; | |
1165 | ||
1166 | u32 tx_ss_num; | |
1167 | u32 rx_ss_num; | |
1168 | ||
1169 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; | |
1170 | struct ieee80211_hw *hw; | |
1171 | struct ieee80211_vif *vif; | |
1172 | enum nl80211_iftype opmode; | |
1173 | ||
1174 | /*Probe Beacon management */ | |
1175 | enum rtl_link_state link_state; | |
1176 | ||
1177 | int n_channels; | |
1178 | int n_bitrates; | |
1179 | ||
1180 | bool offchan_deley; | |
1181 | u8 p2p; /*using p2p role*/ | |
1182 | bool p2p_in_use; | |
1183 | ||
1184 | /*filters */ | |
1185 | u32 rx_conf; | |
1186 | ||
1187 | bool act_scanning; | |
1188 | u8 cnt_after_linked; | |
1189 | bool skip_scan; | |
1190 | ||
1191 | /* early mode */ | |
1192 | /* skb wait queue */ | |
1193 | struct sk_buff_head skb_waitq[MAX_TID_COUNT]; | |
1194 | ||
1195 | /*RDG*/ | |
1196 | bool rdg_en; | |
1197 | ||
1198 | u8 ht_stbc_cap; | |
1199 | u8 ht_cur_stbc; | |
1200 | ||
1201 | /*vht support*/ | |
1202 | u8 vht_enable; | |
1203 | u8 bw_80; | |
1204 | u8 vht_cur_ldpc; | |
1205 | u8 vht_cur_stbc; | |
1206 | u8 vht_stbc_cap; | |
1207 | u8 vht_ldpc_cap; | |
1208 | ||
1209 | /*AP*/ | |
1210 | u8 bssid[6]; | |
1211 | u32 vendor; | |
1212 | u32 basic_rates; /* b/g rates */ | |
1213 | u8 ht_enable; | |
1214 | u8 bw_40; | |
1215 | u8 mode; /* wireless mode */ | |
1216 | u8 slot_time; | |
1217 | u8 short_preamble; | |
1218 | u8 use_cts_protect; | |
1219 | u8 cur_40_prime_sc; | |
1220 | u8 cur_40_prime_sc_bk; | |
1221 | u8 cur_80_prime_sc; | |
1222 | u64 tsf; | |
1223 | u8 retry_short; | |
1224 | u8 retry_long; | |
1225 | u16 assoc_id; | |
1226 | bool bhiddenssid; | |
1227 | ||
1228 | /*IBSS*/ | |
1229 | int beacon_interval; | |
1230 | ||
1231 | /*AMPDU*/ | |
1232 | u8 min_space_cfg; /*For Min spacing configurations */ | |
1233 | u8 max_mss_density; | |
1234 | u8 current_ampdu_factor; | |
1235 | u8 current_ampdu_density; | |
1236 | ||
1237 | /*QOS & EDCA */ | |
1238 | struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; | |
1239 | struct rtl_qos_parameters ac[AC_MAX]; | |
1240 | }; | |
1241 | ||
1242 | struct rtl_hal { | |
1243 | struct ieee80211_hw *hw; | |
1244 | ||
1245 | bool driver_is_goingto_unload; | |
1246 | bool up_first_time; | |
1247 | bool bfirst_init; | |
1248 | bool being_init_adapter; | |
1249 | bool b_bbrf_ready; | |
1250 | bool b_mac_func_enable; | |
1251 | bool b_pre_edcca_enable; | |
1252 | ||
1253 | enum intf_type interface; | |
1254 | u16 hw_type; /*92c or 92d or 92s and so on */ | |
1255 | u8 ic_class; | |
1256 | u8 oem_id; | |
1257 | u32 version; /*version of chip */ | |
1258 | u8 state; /*stop 0, start 1 */ | |
1259 | u8 boad_type; | |
1260 | ||
1261 | u8 pa_mode; | |
1262 | u8 pa_type_2g; | |
1263 | u8 pa_type_5g; | |
1264 | u8 lna_type_2g; | |
1265 | u8 lna_type_5g; | |
1266 | u8 external_pa_2g; | |
1267 | u8 external_lna_2g; | |
1268 | u8 external_pa_5g; | |
1269 | u8 external_lna_5g; | |
1270 | u8 rfe_type; | |
1271 | ||
1272 | /*firmware */ | |
1273 | u32 fwsize; | |
1274 | u8 *pfirmware; | |
1275 | u16 fw_version; | |
1276 | u16 fw_subversion; | |
1277 | bool b_h2c_setinprogress; | |
1278 | u8 last_hmeboxnum; | |
1279 | bool bfw_ready; | |
1280 | ||
1281 | /*Reserve page start offset except beacon in TxQ. */ | |
1282 | u8 fw_rsvdpage_startoffset; | |
1283 | u8 h2c_txcmd_seq; | |
1284 | u8 current_ra_rate; | |
1285 | ||
1286 | /* FW Cmd IO related */ | |
1287 | u16 fwcmd_iomap; | |
1288 | u32 fwcmd_ioparam; | |
1289 | bool set_fwcmd_inprogress; | |
1290 | u8 current_fwcmd_io; | |
1291 | ||
1292 | bool bfw_clk_change_in_progress; | |
1293 | bool ballow_sw_to_change_hwclc; | |
1294 | u8 fw_ps_state; | |
1295 | struct p2p_ps_offload_t p2p_ps_offload; | |
1296 | /**/ | |
1297 | bool driver_going2unload; | |
1298 | ||
1299 | /*AMPDU init min space*/ | |
1300 | u8 minspace_cfg; /*For Min spacing configurations */ | |
1301 | ||
1302 | /* Dul mac */ | |
1303 | enum macphy_mode macphymode; | |
1304 | enum band_type current_bandtype; /* 0:2.4G, 1:5G */ | |
1305 | enum band_type current_bandtypebackup; | |
1306 | enum band_type bandset; | |
1307 | /* dual MAC 0--Mac0 1--Mac1 */ | |
1308 | u32 interfaceindex; | |
1309 | /* just for DulMac S3S4 */ | |
1310 | u8 macphyctl_reg; | |
1311 | bool b_earlymode_enable; | |
1312 | u8 max_earlymode_num; | |
1313 | /* Dul mac*/ | |
1314 | bool during_mac0init_radiob; | |
1315 | bool during_mac1init_radioa; | |
1316 | bool reloadtxpowerindex; | |
1317 | /* True if IMR or IQK have done | |
1318 | for 2.4G in scan progress */ | |
1319 | bool b_load_imrandiqk_setting_for2g; | |
1320 | ||
1321 | bool disable_amsdu_8k; | |
1322 | bool bmaster_of_dmsp; | |
1323 | bool bslave_of_dmsp; | |
1324 | ||
1325 | u16 rx_tag;/*for 92ee*/ | |
1326 | u8 rts_en; | |
1327 | ||
1328 | /*for wowlan*/ | |
1329 | bool wow_enable; | |
1330 | bool b_enter_pnp_sleep; | |
1331 | bool b_wake_from_pnp_sleep; | |
1332 | bool wow_enabled; | |
1333 | __kernel_time_t last_suspend_sec; | |
1334 | u32 wowlan_fwsize; | |
1335 | u8 *p_wowlan_firmware; | |
1336 | ||
1337 | u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ | |
1338 | ||
1339 | bool real_wow_v2_enable; | |
1340 | bool re_init_llt_table; | |
1341 | }; | |
1342 | ||
1343 | struct rtl_security { | |
1344 | /*default 0 */ | |
1345 | bool use_sw_sec; | |
1346 | ||
1347 | bool being_setkey; | |
1348 | bool use_defaultkey; | |
1349 | /*Encryption Algorithm for Unicast Packet */ | |
1350 | enum rt_enc_alg pairwise_enc_algorithm; | |
1351 | /*Encryption Algorithm for Brocast/Multicast */ | |
1352 | enum rt_enc_alg group_enc_algorithm; | |
1353 | /*Cam Entry Bitmap */ | |
1354 | u32 hwsec_cam_bitmap; | |
1355 | u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; | |
1356 | /*local Key buffer, indx 0 is for | |
1357 | pairwise key 1-4 is for agoup key. */ | |
1358 | u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; | |
1359 | u8 key_len[KEY_BUF_SIZE]; | |
1360 | ||
1361 | /*The pointer of Pairwise Key, | |
1362 | it always points to KeyBuf[4] */ | |
1363 | u8 *pairwise_key; | |
1364 | }; | |
1365 | ||
1366 | struct rtl_dig { | |
1367 | u8 dig_enable_flag; | |
1368 | u8 dig_ext_port_stage; | |
1369 | ||
1370 | u32 rssi_lowthresh; | |
1371 | u32 rssi_highthresh; | |
1372 | ||
1373 | u32 fa_lowthresh; | |
1374 | u32 fa_highthresh; | |
1375 | ||
1376 | u8 cursta_connectstate; | |
1377 | u8 presta_connectstate; | |
1378 | u8 curmultista_connectstate; | |
1379 | ||
1380 | u8 pre_igvalue; | |
1381 | u8 cur_igvalue; | |
1382 | ||
1383 | char backoff_val; | |
1384 | char backoff_val_range_max; | |
1385 | char backoff_val_range_min; | |
1386 | u8 rx_gain_range_max; | |
1387 | u8 rx_gain_range_min; | |
1388 | u8 rssi_val_min; | |
1389 | u8 min_undecorated_pwdb_for_dm; | |
1390 | long last_min_undecorated_pwdb_for_dm; | |
1391 | ||
1392 | u8 pre_cck_pd_state; | |
1393 | u8 cur_cck_pd_state; | |
1394 | ||
1395 | u8 large_fa_hit; | |
1396 | u8 forbidden_igi; | |
1397 | u32 recover_cnt; | |
1398 | ||
1399 | }; | |
1400 | ||
1401 | struct rtl_pstbl { | |
1402 | u8 pre_ccastate; | |
1403 | u8 cur_ccasate; | |
1404 | ||
1405 | u8 pre_rfstate; | |
1406 | u8 cur_rfstate; | |
1407 | ||
1408 | long rssi_val_min; | |
1409 | ||
1410 | }; | |
1411 | ||
1412 | #define ASSOCIATE_ENTRY_NUM (32 + 1) | |
1413 | ||
1414 | struct fast_ant_trainning { | |
1415 | u8 bssid[6]; | |
1416 | u8 antsel_rx_keep_0; | |
1417 | u8 antsel_rx_keep_1; | |
1418 | u8 antsel_rx_keep_2; | |
1419 | u32 ant_sum_rssi[7]; | |
1420 | u32 ant_rssi_cnt[7]; | |
1421 | u32 ant_ave_rssi[7]; | |
1422 | u8 fat_state; | |
1423 | u32 train_idx; | |
1424 | u8 antsel_a[ASSOCIATE_ENTRY_NUM]; | |
1425 | u8 antsel_b[ASSOCIATE_ENTRY_NUM]; | |
1426 | u8 antsel_c[ASSOCIATE_ENTRY_NUM]; | |
1427 | u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; | |
1428 | u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; | |
1429 | u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; | |
1430 | u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; | |
1431 | u8 rx_idle_ant; | |
1432 | bool b_becomelinked; | |
1433 | }; | |
1434 | ||
1435 | struct dm_phy_dbg_info { | |
1436 | char rx_snrdb[4]; | |
1437 | u64 num_qry_phy_status; | |
1438 | u64 num_qry_phy_status_cck; | |
1439 | u64 num_qry_phy_status_ofdm; | |
1440 | u16 num_qry_beacon_pkt; | |
1441 | u16 num_non_be_pkt; | |
1442 | s32 rx_evm[4]; | |
1443 | }; | |
1444 | ||
1445 | struct rtl_dm { | |
1446 | /*PHY status for DM */ | |
1447 | long entry_min_undecoratedsmoothed_pwdb; | |
1448 | long undecorated_smoothed_pwdb; /*out dm */ | |
1449 | long entry_max_undecoratedsmoothed_pwdb; | |
1450 | bool b_dm_initialgain_enable; | |
1451 | bool bdynamic_txpower_enable; | |
1452 | bool bcurrent_turbo_edca; | |
1453 | bool bis_any_nonbepkts; /*out dm */ | |
1454 | bool bis_cur_rdlstate; | |
1455 | bool btxpower_trackinginit; | |
1456 | bool b_disable_framebursting; | |
1457 | bool b_cck_inch14; | |
1458 | bool btxpower_tracking; | |
1459 | bool b_useramask; | |
1460 | bool brfpath_rxenable[4]; | |
1461 | bool binform_fw_driverctrldm; | |
1462 | bool bcurrent_mrc_switch; | |
1463 | u8 txpowercount; | |
1464 | ||
1465 | u8 thermalvalue_rxgain; | |
1466 | u8 thermalvalue_iqk; | |
1467 | u8 thermalvalue_lck; | |
1468 | u8 thermalvalue; | |
1469 | u8 thermalvalue_avg[AVG_THERMAL_NUM]; | |
1470 | u8 thermalvalue_avg_index; | |
1471 | bool bdone_txpower; | |
1472 | u8 last_dtp_lvl; | |
1473 | u8 dynamic_txhighpower_lvl; /*Tx high power level */ | |
1474 | u8 dm_flag; /*Indicate if each dynamic mechanism's status. */ | |
1475 | u8 dm_type; | |
1476 | u8 txpower_track_control; | |
1477 | bool binterrupt_migration; | |
1478 | bool bdisable_tx_int; | |
1479 | char ofdm_index[MAX_RF_PATH]; | |
1480 | char cck_index; | |
1481 | u8 default_ofdm_index; | |
1482 | u8 default_cck_index; | |
1483 | char delta_power_index[MAX_RF_PATH]; | |
1484 | char delta_power_index_last[MAX_RF_PATH]; | |
1485 | char power_index_offset[MAX_RF_PATH]; | |
1486 | char aboslute_ofdm_swing_idx[MAX_RF_PATH]; | |
1487 | char remnant_ofdm_swing_idx[MAX_RF_PATH]; | |
1488 | char remnant_cck_idx; | |
1489 | bool modify_txagc_flag_path_a; | |
1490 | bool modify_txagc_flag_path_b; | |
1491 | ||
1492 | bool b_one_entry_only; | |
1493 | struct dm_phy_dbg_info dbginfo; | |
1494 | /* Dynamic ATC switch */ | |
1495 | ||
1496 | bool atc_status; | |
1497 | bool large_cfo_hit; | |
1498 | bool is_freeze; | |
1499 | int cfo_tail[2]; | |
1500 | int cfo_ave_pre; | |
1501 | int crystal_cap; | |
1502 | u8 cfo_threshold; | |
1503 | u32 packet_count; | |
1504 | u32 packet_count_pre; | |
1505 | u8 tx_rate; | |
1506 | ||
1507 | ||
1508 | /*88e tx power tracking*/ | |
1509 | u8 bb_swing_idx_ofdm[2]; | |
1510 | u8 bb_swing_idx_ofdm_current; | |
1511 | u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; | |
1512 | bool bb_swing_flag_Ofdm; | |
1513 | u8 bb_swing_idx_cck; | |
1514 | u8 bb_swing_idx_cck_current; | |
1515 | u8 bb_swing_idx_cck_base; | |
1516 | bool bb_swing_flag_cck; | |
1517 | ||
1518 | char bb_swing_diff_2g; | |
1519 | char bb_swing_diff_5g; | |
1520 | ||
1521 | /* DMSP */ | |
1522 | bool supp_phymode_switch; | |
1523 | ||
1524 | /* DulMac */ | |
1525 | struct rtl_dig dm_digtable; | |
1526 | struct rtl_pstbl dm_pstable; | |
1527 | struct fast_ant_trainning fat_table; | |
1528 | ||
1529 | u8 linked_interval; | |
1530 | ||
1531 | u64 last_tx_ok_cnt; | |
1532 | u64 last_rx_ok_cnt; | |
1533 | ||
1534 | bool cck_high_power; | |
1535 | }; | |
1536 | ||
1537 | #define EFUSE_MAX_LOGICAL_SIZE 256 | |
1538 | ||
1539 | struct rtl_efuse { | |
1540 | bool bautoLoad_ok; | |
1541 | bool bootfromefuse; | |
1542 | u16 max_physical_size; | |
1543 | ||
1544 | u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; | |
1545 | u16 efuse_usedbytes; | |
1546 | u8 efuse_usedpercentage; | |
1547 | u8 autoload_failflag; | |
1548 | u8 autoload_status; | |
1549 | ||
1550 | short epromtype; | |
1551 | u16 eeprom_vid; | |
1552 | u16 eeprom_did; | |
1553 | u16 eeprom_svid; | |
1554 | u16 eeprom_smid; | |
1555 | u8 eeprom_oemid; | |
1556 | u16 eeprom_channelplan; | |
1557 | u8 eeprom_version; | |
1558 | ||
1559 | u8 dev_addr[6]; | |
1560 | u8 board_type; | |
1561 | u8 wowlan_enable; | |
1562 | u8 antenna_div_cfg; | |
1563 | u8 antenna_div_type; | |
1564 | ||
1565 | bool b_txpwr_fromeprom; | |
1566 | u8 eeprom_crystalcap; | |
1567 | u8 eeprom_tssi[2]; | |
1568 | u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ | |
1569 | u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; | |
1570 | u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; | |
1571 | u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G]; | |
1572 | u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX]; | |
1573 | u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX]; | |
1574 | ||
1575 | ||
1576 | u8 internal_pa_5g[2]; /* pathA / pathB */ | |
1577 | u8 eeprom_c9; | |
1578 | u8 eeprom_cc; | |
1579 | ||
1580 | /*For power group */ | |
1581 | u8 eeprom_pwrgroup[2][3]; | |
1582 | u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; | |
1583 | u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; | |
1584 | ||
1585 | u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; | |
1586 | /*For HT 40MHZ pwr */ | |
1587 | u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1588 | /*For HT 40MHZ pwr */ | |
1589 | u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1590 | ||
1591 | /*--------------------------------------------------------* | |
1592 | * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, | |
1593 | * other ICs (8188EE\8723BE\8192EE\8812AE...) | |
1594 | * define new arrays in Windows code. | |
1595 | * BUT, in linux code, we use the same array for all ICs. | |
1596 | * | |
1597 | * The Correspondance relation between two arrays is: | |
1598 | * txpwr_cckdiff[][] == CCK_24G_Diff[][] | |
1599 | * txpwr_ht20diff[][] == BW20_24G_Diff[][] | |
1600 | * txpwr_ht40diff[][] == BW40_24G_Diff[][] | |
1601 | * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] | |
1602 | * | |
1603 | * Sizes of these arrays are decided by the larger ones. | |
1604 | */ | |
1605 | char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1606 | char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1607 | char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1608 | char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1609 | /*--------------------------------------------------------*/ | |
1610 | ||
1611 | u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1612 | u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; | |
1613 | char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; | |
1614 | char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
1615 | char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
1616 | char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
1617 | ||
1618 | u8 txpwr_safetyflag; /* Band edge enable flag */ | |
1619 | u16 eeprom_txpowerdiff; | |
1620 | u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ | |
1621 | u8 antenna_txpwdiff[3]; | |
1622 | ||
1623 | u8 eeprom_regulatory; | |
1624 | u8 eeprom_thermalmeter; | |
1625 | u8 thermalmeter[2];/*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ | |
1626 | u16 tssi_13dbm; | |
1627 | u8 crystalcap; /* CrystalCap. */ | |
1628 | u8 delta_iqk; | |
1629 | u8 delta_lck; | |
1630 | ||
1631 | u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ | |
1632 | bool b_apk_thermalmeterignore; | |
1633 | ||
1634 | bool b1x1_recvcombine; | |
1635 | bool b1ss_support; | |
1636 | ||
1637 | /*channel plan */ | |
1638 | u8 channel_plan; | |
1639 | }; | |
1640 | ||
1641 | struct rtl_ps_ctl { | |
1642 | bool pwrdomain_protect; | |
1643 | bool b_in_powersavemode; | |
1644 | bool rfchange_inprogress; | |
1645 | bool b_swrf_processing; | |
1646 | bool b_hwradiooff; | |
1647 | /* | |
1648 | * just for PCIE ASPM | |
1649 | * If it supports ASPM, Offset[560h] = 0x40, | |
1650 | * otherwise Offset[560h] = 0x00. | |
1651 | * */ | |
1652 | bool b_support_aspm; | |
1653 | bool b_support_backdoor; | |
1654 | ||
1655 | /*for LPS */ | |
1656 | enum rt_psmode dot11_psmode; /*Power save mode configured. */ | |
1657 | bool b_swctrl_lps; | |
1658 | bool b_fwctrl_lps; | |
1659 | u8 fwctrl_psmode; | |
1660 | /*For Fw control LPS mode */ | |
1661 | u8 b_reg_fwctrl_lps; | |
1662 | /*Record Fw PS mode status. */ | |
1663 | bool b_fw_current_inpsmode; | |
1664 | u8 reg_max_lps_awakeintvl; | |
1665 | bool report_linked; | |
1666 | bool b_low_power_enable;/*for 32k*/ | |
1667 | ||
1668 | /*for IPS */ | |
1669 | bool b_inactiveps; | |
1670 | ||
1671 | u32 rfoff_reason; | |
1672 | ||
1673 | /*RF OFF Level */ | |
1674 | u32 cur_ps_level; | |
1675 | u32 reg_rfps_level; | |
1676 | ||
1677 | /*just for PCIE ASPM */ | |
1678 | u8 const_amdpci_aspm; | |
1679 | ||
1680 | enum rf_pwrstate inactive_pwrstate; | |
1681 | enum rf_pwrstate rfpwr_state; /*cur power state */ | |
1682 | ||
1683 | /* for SW LPS*/ | |
1684 | bool sw_ps_enabled; | |
1685 | bool state; | |
1686 | bool state_inap; | |
1687 | bool multi_buffered; | |
1688 | u16 nullfunc_seq; | |
1689 | unsigned int dtim_counter; | |
1690 | unsigned int sleep_ms; | |
1691 | unsigned long last_sleep_jiffies; | |
1692 | unsigned long last_awake_jiffies; | |
1693 | unsigned long last_delaylps_stamp_jiffies; | |
1694 | unsigned long last_dtim; | |
1695 | unsigned long last_beacon; | |
1696 | unsigned long last_action; | |
1697 | unsigned long last_slept; | |
1698 | ||
1699 | /*For P2P PS */ | |
1700 | struct rtl_p2p_ps_info p2p_ps_info; | |
1701 | u8 pwr_mode; | |
1702 | u8 smart_ps; | |
1703 | ||
1704 | /* wake up on line */ | |
1705 | u8 wo_wlan_mode; | |
1706 | u8 arp_offload_enable; | |
1707 | u8 gtk_offload_enable; | |
1708 | /* Used for WOL, indicates the reason for waking event.*/ | |
1709 | u32 wakeup_reason; | |
1710 | /* Record the last waking time for comparison with setting key. */ | |
1711 | u64 last_wakeup_time; | |
1712 | }; | |
1713 | ||
1714 | struct rtl_stats { | |
1715 | u8 psaddr[ETH_ALEN]; | |
1716 | u32 mac_time[2]; | |
1717 | s8 rssi; | |
1718 | u8 signal; | |
1719 | u8 noise; | |
1720 | u8 rate; /* hw desc rate */ | |
1721 | u8 rawdata; | |
1722 | u8 received_channel; | |
1723 | u8 control; | |
1724 | u8 mask; | |
1725 | u8 freq; | |
1726 | u16 len; | |
1727 | u64 tsf; | |
1728 | u32 beacon_time; | |
1729 | u8 nic_type; | |
1730 | u16 length; | |
1731 | u8 signalquality; /*in 0-100 index. */ | |
1732 | /* | |
1733 | * Real power in dBm for this packet, | |
1734 | * no beautification and aggregation. | |
1735 | * */ | |
1736 | s32 recvsignalpower; | |
1737 | s8 rxpower; /*in dBm Translate from PWdB */ | |
1738 | u8 signalstrength; /*in 0-100 index. */ | |
1739 | u16 b_hwerror:1; | |
1740 | u16 b_crc:1; | |
1741 | u16 b_icv:1; | |
1742 | u16 b_shortpreamble:1; | |
1743 | u16 antenna:1; | |
1744 | u16 decrypted:1; | |
1745 | u16 wakeup:1; | |
1746 | u32 timestamp_low; | |
1747 | u32 timestamp_high; | |
1748 | bool b_shift; | |
1749 | ||
1750 | u8 rx_drvinfo_size; | |
1751 | u8 rx_bufshift; | |
1752 | bool b_isampdu; | |
1753 | bool b_isfirst_ampdu; | |
1754 | bool rx_is40Mhzpacket; | |
1755 | u8 rx_packet_bw; | |
1756 | u32 rx_pwdb_all; | |
1757 | u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ | |
1758 | s8 rx_mimo_signalquality[4]; | |
1759 | u8 rx_mimo_evm_dbm[4]; | |
1760 | u16 cfo_short[4]; /* per-path's Cfo_short */ | |
1761 | u16 cfo_tail[4]; | |
1762 | ||
1763 | u8 rx_pwr[4]; /* per-path's pwdb */ | |
1764 | u8 rx_snr[4]; /* per-path's SNR */ | |
1765 | u8 bandwidth; | |
1766 | u8 bt_coex_pwr_adjust; | |
1767 | bool b_packet_matchbssid; | |
1768 | bool b_is_cck; | |
1769 | bool b_is_ht; | |
1770 | bool b_packet_toself; | |
1771 | bool b_packet_beacon; /*for rssi */ | |
1772 | char cck_adc_pwdb[4]; /*for rx path selection */ | |
1773 | ||
1774 | bool b_is_vht; | |
1775 | bool b_is_short_gi; | |
1776 | u8 vht_nss; | |
1777 | ||
1778 | u8 packet_report_type; | |
1779 | ||
1780 | u32 macid; | |
1781 | u8 wake_match; | |
1782 | u32 bt_rx_rssi_percentage; | |
1783 | u32 macid_valid_entry[2]; | |
1784 | }; | |
1785 | ||
1786 | struct rt_link_detect { | |
1787 | /* count for raoming */ | |
1788 | u32 bcn_rx_inperiod; | |
1789 | u32 roam_times; | |
1790 | ||
1791 | u32 num_tx_in4period[4]; | |
1792 | u32 num_rx_in4period[4]; | |
1793 | ||
1794 | u32 num_tx_inperiod; | |
1795 | u32 num_rx_inperiod; | |
1796 | ||
1797 | bool b_busytraffic; | |
1798 | bool b_tx_busy_traffic; | |
1799 | bool b_rx_busy_traffic; | |
1800 | bool b_higher_busytraffic; | |
1801 | bool b_higher_busyrxtraffic; | |
1802 | ||
1803 | u32 tidtx_in4period[MAX_TID_COUNT][4]; | |
1804 | u32 tidtx_inperiod[MAX_TID_COUNT]; | |
1805 | bool higher_busytxtraffic[MAX_TID_COUNT]; | |
1806 | }; | |
1807 | ||
1808 | struct rtl_tcb_desc { | |
1809 | u8 packet_bw:2; | |
1810 | u8 b_multicast:1; | |
1811 | u8 b_broadcast:1; | |
1812 | ||
1813 | u8 b_rts_stbc:1; | |
1814 | u8 b_rts_enable:1; | |
1815 | u8 b_cts_enable:1; | |
1816 | u8 b_rts_use_shortpreamble:1; | |
1817 | u8 b_rts_use_shortgi:1; | |
1818 | u8 rts_sc:1; | |
1819 | u8 b_rts_bw:1; | |
1820 | u8 rts_rate; | |
1821 | ||
1822 | u8 use_shortgi:1; | |
1823 | u8 use_shortpreamble:1; | |
1824 | u8 use_driver_rate:1; | |
1825 | u8 disable_ratefallback:1; | |
1826 | ||
1827 | u8 ratr_index; | |
1828 | u8 mac_id; | |
1829 | u8 hw_rate; | |
1830 | ||
1831 | u8 b_last_inipkt:1; | |
1832 | u8 b_cmd_or_init:1; | |
1833 | u8 queue_index; | |
1834 | ||
1835 | /* early mode */ | |
1836 | u8 empkt_num; | |
1837 | /* The max value by HW */ | |
1838 | u32 empkt_len[10]; | |
1839 | bool btx_enable_sw_calc_duration; | |
1840 | /* used for hal construct pkt, | |
1841 | * we may set desc when tx */ | |
1842 | u8 self_desc; | |
1843 | }; | |
1844 | ||
1845 | struct rtl_wow_pattern { | |
1846 | u8 type; | |
1847 | u16 crc; | |
1848 | u32 mask[4]; | |
1849 | }; | |
1850 | ||
1851 | struct proxim { | |
1852 | bool proxim_on; | |
1853 | ||
1854 | void *proximity_priv; | |
1855 | int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, | |
1856 | struct sk_buff *skb); | |
1857 | u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); | |
1858 | }; | |
1859 | ||
1860 | struct rtl_hal_ops { | |
1861 | int (*init_sw_vars)(struct ieee80211_hw *hw); | |
1862 | void (*deinit_sw_vars)(struct ieee80211_hw *hw); | |
1863 | void (*read_eeprom_info)(struct ieee80211_hw *hw); | |
1864 | void (*interrupt_recognized)(struct ieee80211_hw *hw, | |
1865 | u32 *p_inta, u32 *p_intb); | |
1866 | int (*hw_init)(struct ieee80211_hw *hw); | |
1867 | void (*hw_disable)(struct ieee80211_hw *hw); | |
1868 | void (*hw_suspend)(struct ieee80211_hw *hw); | |
1869 | void (*hw_resume)(struct ieee80211_hw *hw); | |
1870 | void (*enable_interrupt)(struct ieee80211_hw *hw); | |
1871 | void (*disable_interrupt)(struct ieee80211_hw *hw); | |
1872 | int (*set_network_type)(struct ieee80211_hw *hw, | |
1873 | enum nl80211_iftype type); | |
1874 | void (*set_chk_bssid)(struct ieee80211_hw *hw, | |
1875 | bool check_bssid); | |
1876 | void (*set_bw_mode)(struct ieee80211_hw *hw, | |
1877 | enum nl80211_channel_type ch_type); | |
1878 | u8 (*switch_channel)(struct ieee80211_hw *hw); | |
1879 | void (*set_qos)(struct ieee80211_hw *hw, int aci); | |
1880 | void (*set_bcn_reg)(struct ieee80211_hw *hw); | |
1881 | void (*set_bcn_intv)(struct ieee80211_hw *hw); | |
1882 | void (*update_interrupt_mask)(struct ieee80211_hw *hw, | |
1883 | u32 add_msr, u32 rm_msr); | |
1884 | void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val); | |
1885 | void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val); | |
1886 | void (*update_rate_tbl)(struct ieee80211_hw *hw, | |
1887 | struct ieee80211_sta *sta, u8 rssi_level); | |
1888 | void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, | |
1889 | u8 *desc, u8 queue_index, | |
1890 | struct sk_buff *skb, dma_addr_t addr); | |
1891 | u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, | |
1892 | u8 queue_index); | |
1893 | void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, | |
1894 | u8 queue_index); | |
1895 | void (*fill_tx_desc)(struct ieee80211_hw *hw, | |
1896 | struct ieee80211_hdr *hdr, | |
1897 | u8 *pdesc_tx, u8 *pbd_desc, | |
1898 | struct ieee80211_tx_info *info, | |
1899 | struct ieee80211_sta *sta, | |
1900 | struct sk_buff *skb, u8 hw_queue, | |
1901 | struct rtl_tcb_desc *ptcb_desc); | |
1902 | void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc, | |
1903 | bool b_firstseg, bool b_lastseg, | |
1904 | struct sk_buff *skb); | |
1905 | bool (*query_rx_desc)(struct ieee80211_hw *hw, | |
1906 | struct rtl_stats *status, | |
1907 | struct ieee80211_rx_status *rx_status, | |
1908 | u8 *pdesc, struct sk_buff *skb); | |
1909 | void (*set_channel_access)(struct ieee80211_hw *hw); | |
1910 | bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid); | |
1911 | void (*dm_watchdog)(struct ieee80211_hw *hw); | |
1912 | void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation); | |
1913 | bool (*set_rf_power_state)(struct ieee80211_hw *hw, | |
1914 | enum rf_pwrstate rfpwr_state); | |
1915 | void (*led_control)(struct ieee80211_hw *hw, | |
1916 | enum led_ctl_mode ledaction); | |
1917 | void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, | |
1918 | u8 desc_name, u8 *val); | |
1919 | u32 (*get_desc)(u8 *pdesc, bool istx, u8 desc_name); | |
1920 | bool (*is_tx_desc_closed)(struct ieee80211_hw *hw, | |
1921 | u8 hw_queue, u16 index); | |
1922 | void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue); | |
1923 | void (*enable_hw_sec)(struct ieee80211_hw *hw); | |
1924 | void (*set_key)(struct ieee80211_hw *hw, u32 key_index, | |
1925 | u8 *p_macaddr, bool is_group, u8 enc_algo, | |
1926 | bool is_wepkey, bool clear_all); | |
1927 | void (*init_sw_leds)(struct ieee80211_hw *hw); | |
1928 | u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); | |
1929 | void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, | |
1930 | u32 data); | |
1931 | u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath, | |
1932 | u32 regaddr, u32 bitmask); | |
1933 | void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath, | |
1934 | u32 regaddr, u32 bitmask, u32 data); | |
1935 | void (*allow_all_destaddr)(struct ieee80211_hw *hw, | |
1936 | bool allow_all_da, bool write_into_reg); | |
1937 | void (*linked_set_reg)(struct ieee80211_hw *hw); | |
1938 | void (*check_switch_to_dmdp)(struct ieee80211_hw *hw); | |
1939 | void (*dualmac_easy_concurrent)(struct ieee80211_hw *hw); | |
1940 | void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw); | |
1941 | void (*c2h_command_handle)(struct ieee80211_hw *hw); | |
1942 | void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw, | |
1943 | bool mstate); | |
1944 | void (*bt_turn_off_bt_coexist_before_enter_lps)(struct ieee80211_hw *w); | |
1945 | void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id, | |
1946 | u32 cmd_len, u8 *p_cmdbuffer); | |
1947 | bool (*get_btc_status)(void); | |
1948 | u32 (*rx_command_packet)(struct ieee80211_hw *hw, | |
1949 | struct rtl_stats status, struct sk_buff *skb); | |
1950 | void (*add_wowlan_pattern)(struct ieee80211_hw *hw, | |
1951 | struct rtl_wow_pattern *rtl_pattern, | |
1952 | u8 index); | |
1953 | }; | |
1954 | ||
1955 | struct rtl_intf_ops { | |
1956 | /*com */ | |
1957 | void (*read92e_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, | |
1958 | u8 *pbuf); | |
1959 | int (*adapter_start)(struct ieee80211_hw *hw); | |
1960 | void (*adapter_stop)(struct ieee80211_hw *hw); | |
1961 | bool (*check_buddy_priv)(struct ieee80211_hw *hw, | |
1962 | struct rtl_priv **buddy_priv); | |
1963 | ||
1964 | int (*adapter_tx)(struct ieee80211_hw *hw, | |
1965 | struct ieee80211_sta *sta, | |
1966 | struct sk_buff *skb, | |
1967 | struct rtl_tcb_desc *ptcb_desc); | |
1968 | void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); | |
1969 | int (*reset_trx_ring)(struct ieee80211_hw *hw); | |
1970 | bool (*waitq_insert)(struct ieee80211_hw *hw, | |
1971 | struct ieee80211_sta *sta, | |
1972 | struct sk_buff *skb); | |
1973 | ||
1974 | /*pci */ | |
1975 | void (*disable_aspm)(struct ieee80211_hw *hw); | |
1976 | void (*enable_aspm)(struct ieee80211_hw *hw); | |
1977 | ||
1978 | /*usb */ | |
1979 | }; | |
1980 | ||
1981 | struct rtl_mod_params { | |
1982 | /* default: 0 = using hardware encryption */ | |
1983 | bool sw_crypto; | |
1984 | ||
1985 | /* default: 0 = DBG_EMERG (0)*/ | |
1986 | int debug; | |
1987 | ||
1988 | /* default: 1 = using no linked power save */ | |
1989 | bool b_inactiveps; | |
1990 | ||
1991 | /* default: 1 = using linked sw power save */ | |
1992 | bool b_swctrl_lps; | |
1993 | ||
1994 | /* default: 1 = using linked fw power save */ | |
1995 | bool b_fwctrl_lps; | |
1996 | }; | |
1997 | ||
1998 | struct rtl_hal_cfg { | |
1999 | u8 bar_id; | |
2000 | bool write_readback; | |
2001 | char *name; | |
2002 | char *fw_name; | |
2003 | struct rtl_hal_ops *ops; | |
2004 | struct rtl_mod_params *mod_params; | |
2005 | ||
2006 | /*this map used for some registers or vars | |
2007 | defined int HAL but used in MAIN */ | |
2008 | u32 maps[RTL_VAR_MAP_MAX]; | |
2009 | ||
2010 | }; | |
2011 | ||
2012 | struct rtl_locks { | |
2013 | /* mutex */ | |
2014 | struct mutex conf_mutex; | |
2015 | ||
2016 | /*spin lock */ | |
2017 | spinlock_t ips_lock; | |
2018 | spinlock_t irq_th_lock; | |
2019 | spinlock_t h2c_lock; | |
2020 | spinlock_t rf_ps_lock; | |
2021 | spinlock_t rf_lock; | |
2022 | spinlock_t lps_lock; | |
2023 | spinlock_t waitq_lock; | |
2024 | spinlock_t entry_list_lock; | |
2025 | ||
2026 | /*FW clock change */ | |
2027 | spinlock_t fw_ps_lock; | |
2028 | ||
2029 | /*Dul mac*/ | |
2030 | spinlock_t cck_and_rw_pagea_lock; | |
2031 | ||
2032 | /*Easy concurrent*/ | |
2033 | spinlock_t check_sendpkt_lock; | |
2034 | ||
2035 | spinlock_t iqk_lock; | |
2036 | }; | |
2037 | ||
2038 | struct rtl_works { | |
2039 | struct ieee80211_hw *hw; | |
2040 | ||
2041 | /*timer */ | |
2042 | struct timer_list watchdog_timer; | |
2043 | struct timer_list dualmac_easyconcurrent_retrytimer; | |
2044 | struct timer_list fw_clockoff_timer; | |
2045 | struct timer_list fast_antenna_trainning_timer; | |
2046 | /*task */ | |
2047 | struct tasklet_struct irq_tasklet; | |
2048 | struct tasklet_struct irq_prepare_bcn_tasklet; | |
2049 | ||
2050 | /*work queue */ | |
2051 | struct workqueue_struct *rtl_wq; | |
2052 | struct delayed_work watchdog_wq; | |
2053 | struct delayed_work ips_nic_off_wq; | |
2054 | ||
2055 | /* For SW LPS */ | |
2056 | struct delayed_work ps_work; | |
2057 | struct delayed_work ps_rfon_wq; | |
2058 | struct delayed_work fwevt_wq; | |
2059 | }; | |
2060 | ||
2061 | struct rtl_debug { | |
2062 | u32 dbgp_type[DBGP_TYPE_MAX]; | |
2063 | u32 global_debuglevel; | |
2064 | u64 global_debugcomponents; | |
2065 | ||
2066 | /* add for proc debug */ | |
2067 | struct proc_dir_entry *proc_dir; | |
2068 | char proc_name[20]; | |
2069 | }; | |
2070 | ||
2071 | #define MIMO_PS_STATIC 0 | |
2072 | #define MIMO_PS_DYNAMIC 1 | |
2073 | #define MIMO_PS_NOLIMIT 3 | |
2074 | ||
2075 | struct rtl_dualmac_easy_concurrent_ctl { | |
2076 | enum band_type currentbandtype_backfordmdp; | |
2077 | bool bclose_bbandrf_for_dmsp; | |
2078 | bool bchange_to_dmdp; | |
2079 | bool bchange_to_dmsp; | |
2080 | bool bswitch_in_process; | |
2081 | }; | |
2082 | ||
2083 | struct rtl_dmsp_ctl { | |
2084 | bool bactivescan_for_slaveofdmsp; | |
2085 | bool bscan_for_anothermac_fordmsp; | |
2086 | bool bscan_for_itself_fordmsp; | |
2087 | bool bwritedig_for_anothermacofdmsp; | |
2088 | u32 curdigvalue_for_anothermacofdmsp; | |
2089 | bool bchangecckpdstate_for_anothermacofdmsp; | |
2090 | u8 curcckpdstate_for_anothermacofdmsp; | |
2091 | bool bchangetxhighpowerlvl_for_anothermacofdmsp; | |
2092 | u8 curtxhighlvl_for_anothermacofdmsp; | |
2093 | long rssivalmin_for_anothermacofdmsp; | |
2094 | }; | |
2095 | ||
2096 | struct rtl_global_var { | |
2097 | /* from this list we can get | |
2098 | * other adapter's rtl_priv */ | |
2099 | struct list_head glb_priv_list; | |
2100 | spinlock_t glb_list_lock; | |
2101 | }; | |
2102 | ||
2103 | struct rtl_btc_info { | |
2104 | u8 bt_type; | |
2105 | u8 btcoexist; | |
2106 | u8 ant_num; | |
2107 | }; | |
2108 | ||
2109 | struct rtl_btc_ops { | |
2110 | void (*btc_init_variables)(struct rtl_priv *rtlpriv); | |
2111 | void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv); | |
2112 | void (*btc_init_hw_config)(struct rtl_priv *rtlpriv); | |
2113 | void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type); | |
2114 | void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); | |
2115 | void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype); | |
2116 | void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action); | |
2117 | void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv, | |
2118 | enum rt_media_status mstatus); | |
2119 | void (*btc_periodical)(struct rtl_priv *rtlpriv); | |
2120 | void (*btc_halt_notify)(void); | |
2121 | void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv, | |
2122 | u8 *tmp_buf, u8 length); | |
2123 | bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv); | |
2124 | bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv); | |
2125 | bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv); | |
2126 | void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, | |
2127 | u8 pkt_type); | |
2128 | }; | |
2129 | ||
2130 | struct rtl_bt_coexist { | |
2131 | struct rtl_btc_ops *btc_ops; | |
2132 | struct rtl_btc_info btc_info; | |
2133 | }; | |
2134 | ||
2135 | ||
2136 | struct rtl_priv { | |
2137 | struct list_head list; | |
2138 | struct rtl_priv *buddy_priv; | |
2139 | struct rtl_global_var *glb_var; | |
2140 | struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; | |
2141 | struct rtl_dmsp_ctl dmsp_ctl; | |
2142 | struct rtl_locks locks; | |
2143 | struct rtl_works works; | |
2144 | struct rtl_mac mac80211; | |
2145 | struct rtl_hal rtlhal; | |
2146 | struct rtl_regulatory regd; | |
2147 | struct rtl_rfkill rfkill; | |
2148 | struct rtl_io io; | |
2149 | struct rtl_phy phy; | |
2150 | struct rtl_dm dm; | |
2151 | struct rtl_security sec; | |
2152 | struct rtl_efuse efuse; | |
2153 | ||
2154 | struct rtl_ps_ctl psc; | |
2155 | struct rate_adaptive ra; | |
2156 | struct dynamic_primary_cca primarycca; | |
2157 | struct wireless_stats stats; | |
2158 | struct rt_link_detect link_info; | |
2159 | struct false_alarm_statistics falsealm_cnt; | |
2160 | ||
2161 | struct rtl_rate_priv *rate_priv; | |
2162 | ||
2163 | struct rtl_debug dbg; | |
2164 | ||
2165 | /* sta entry list for ap adhoc or mesh */ | |
2166 | struct list_head entry_list; | |
2167 | ||
2168 | /* | |
2169 | *hal_cfg : for diff cards | |
2170 | *intf_ops : for diff interrface usb/pcie | |
2171 | */ | |
2172 | struct rtl_hal_cfg *cfg; | |
2173 | struct rtl_intf_ops *intf_ops; | |
2174 | ||
2175 | /*this var will be set by set_bit, | |
2176 | and was used to indicate status of | |
2177 | interface or hardware */ | |
2178 | unsigned long status; | |
2179 | ||
2180 | /* intel Proximity, should be alloc mem | |
2181 | * in intel Proximity module and can only | |
2182 | * be used in intel Proximity mode */ | |
2183 | struct proxim proximity; | |
2184 | ||
2185 | /*for bt coexist use*/ | |
2186 | struct rtl_bt_coexist btcoexist; | |
2187 | ||
2188 | /* seperate 92ee from other ICs, | |
2189 | * 92ee use new trx flow. */ | |
2190 | bool use_new_trx_flow; | |
2191 | ||
2192 | #ifdef CONFIG_PM | |
2193 | struct wiphy_wowlan_support wowlan; | |
2194 | #endif | |
2195 | /*This must be the last item so | |
2196 | that it points to the data allocated | |
2197 | beyond this structure like: | |
2198 | rtl_pci_priv or rtl_usb_priv */ | |
2199 | u8 priv[0]; | |
2200 | }; | |
2201 | ||
2202 | #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) | |
2203 | #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) | |
2204 | #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) | |
2205 | #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) | |
2206 | #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) | |
2207 | #define rtl_sec(rtlpriv) (&((rtlpriv)->sec)) | |
2208 | #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) | |
2209 | /*************************************** | |
2210 | Bluetooth Co-existance Related | |
2211 | ****************************************/ | |
2212 | ||
2213 | enum bt_ant_num { | |
2214 | ANT_X2 = 0, | |
2215 | ANT_X1 = 1, | |
2216 | }; | |
2217 | ||
2218 | enum bt_co_type { | |
2219 | BT_2WIRE = 0, | |
2220 | BT_ISSC_3WIRE = 1, | |
2221 | BT_ACCEL = 2, | |
2222 | BT_CSR_BC4 = 3, | |
2223 | BT_CSR_BC8 = 4, | |
2224 | BT_RTL8756 = 5, | |
2225 | BT_RTL8723A = 6, | |
2226 | BT_RTL8821A = 7, | |
2227 | BT_RTL8723B = 8, | |
2228 | BT_RTL8192E = 9, | |
2229 | BT_RTL8812A = 11, | |
2230 | }; | |
2231 | ||
2232 | enum bt_total_ant_num { | |
2233 | ANT_TOTAL_X2 = 0, | |
2234 | ANT_TOTAL_X1 = 1 | |
2235 | }; | |
2236 | ||
2237 | enum bt_cur_state { | |
2238 | BT_OFF = 0, | |
2239 | BT_ON = 1, | |
2240 | }; | |
2241 | ||
2242 | enum bt_service_type { | |
2243 | BT_SCO = 0, | |
2244 | BT_A2DP = 1, | |
2245 | BT_HID = 2, | |
2246 | BT_HID_IDLE = 3, | |
2247 | BT_SCAN = 4, | |
2248 | BT_IDLE = 5, | |
2249 | BT_OTHER_ACTION = 6, | |
2250 | BT_BUSY = 7, | |
2251 | BT_OTHERBUSY = 8, | |
2252 | BT_PAN = 9, | |
2253 | }; | |
2254 | ||
2255 | enum bt_radio_shared { | |
2256 | BT_RADIO_SHARED = 0, | |
2257 | BT_RADIO_INDIVIDUAL = 1, | |
2258 | }; | |
2259 | ||
2260 | struct bt_coexist_info { | |
2261 | /* EEPROM BT info. */ | |
2262 | u8 eeprom_bt_coexist; | |
2263 | u8 eeprom_bt_type; | |
2264 | u8 eeprom_bt_ant_num; | |
2265 | u8 eeprom_bt_ant_isolation; | |
2266 | u8 eeprom_bt_radio_shared; | |
2267 | ||
2268 | u8 bt_coexistence; | |
2269 | u8 bt_ant_num; | |
2270 | u8 bt_coexist_type; | |
2271 | u8 bt_state; | |
2272 | u8 bt_cur_state; /* 0:on, 1:off */ | |
2273 | u8 bt_ant_isolation; /* 0:good, 1:bad */ | |
2274 | u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ | |
2275 | u8 bt_service; | |
2276 | u8 bt_radio_shared_type; | |
2277 | u8 bt_rfreg_origin_1e; | |
2278 | u8 bt_rfreg_origin_1f; | |
2279 | u8 bt_rssi_state; | |
2280 | u32 ratio_tx; | |
2281 | u32 ratio_pri; | |
2282 | u32 bt_edca_ul; | |
2283 | u32 bt_edca_dl; | |
2284 | ||
2285 | bool b_init_set; | |
2286 | bool b_bt_busy_traffic; | |
2287 | bool b_bt_traffic_mode_set; | |
2288 | bool b_bt_non_traffic_mode_set; | |
2289 | ||
2290 | bool b_fw_coexist_all_off; | |
2291 | bool b_sw_coexist_all_off; | |
2292 | bool b_hw_coexist_all_off; | |
2293 | u32 current_state; | |
2294 | u32 previous_state; | |
2295 | u32 current_state_h; | |
2296 | u32 previous_state_h; | |
2297 | ||
2298 | u8 bt_pre_rssi_state; | |
2299 | u8 bt_pre_rssi_state1; | |
2300 | ||
2301 | u8 b_reg_bt_iso; | |
2302 | u8 b_reg_bt_sco; | |
2303 | bool b_balance_on; | |
2304 | u8 bt_active_zero_cnt; | |
2305 | bool b_cur_bt_disabled; | |
2306 | bool b_pre_bt_disabled; | |
2307 | ||
2308 | u8 bt_profile_case; | |
2309 | u8 bt_profile_action; | |
2310 | bool b_bt_busy; | |
2311 | bool b_hold_for_bt_operation; | |
2312 | u8 lps_counter; | |
2313 | }; | |
2314 | ||
2315 | /**************************************** | |
2316 | mem access macro define start | |
2317 | Call endian free function when | |
2318 | 1. Read/write packet content. | |
2319 | 2. Before write integer to IO. | |
2320 | 3. After read integer from IO. | |
2321 | ****************************************/ | |
2322 | /* Convert little data endian to host ordering */ | |
2323 | #define EF1BYTE(_val) \ | |
2324 | ((u8)(_val)) | |
2325 | #define EF2BYTE(_val) \ | |
2326 | (le16_to_cpu(_val)) | |
2327 | #define EF4BYTE(_val) \ | |
2328 | (le32_to_cpu(_val)) | |
2329 | ||
2330 | /* Read data from memory */ | |
2331 | #define READEF1BYTE(_ptr) \ | |
2332 | EF1BYTE(*((u8 *)(_ptr))) | |
2333 | /* Read le16 data from memory and convert to host ordering */ | |
2334 | #define READEF2BYTE(_ptr) \ | |
2335 | EF2BYTE(*(_ptr)) | |
2336 | #define READEF4BYTE(_ptr) \ | |
2337 | EF4BYTE(*(_ptr)) | |
2338 | ||
2339 | /* Write data to memory */ | |
2340 | #define WRITEEF1BYTE(_ptr, _val) \ | |
2341 | (*((u8 *)(_ptr))) = EF1BYTE(_val) | |
2342 | /* Write le16 data to memory in host ordering */ | |
2343 | #define WRITEEF2BYTE(_ptr, _val) \ | |
2344 | (*((u16 *)(_ptr))) = EF2BYTE(_val) | |
2345 | #define WRITEEF4BYTE(_ptr, _val) \ | |
2346 | (*((u32 *)(_ptr))) = EF2BYTE(_val) | |
2347 | ||
2348 | /* Create a bit mask | |
2349 | * Examples: | |
2350 | * BIT_LEN_MASK_32(0) => 0x00000000 | |
2351 | * BIT_LEN_MASK_32(1) => 0x00000001 | |
2352 | * BIT_LEN_MASK_32(2) => 0x00000003 | |
2353 | * BIT_LEN_MASK_32(32) => 0xFFFFFFFF | |
2354 | */ | |
2355 | #define BIT_LEN_MASK_32(__bitlen) \ | |
2356 | (0xFFFFFFFF >> (32 - (__bitlen))) | |
2357 | #define BIT_LEN_MASK_16(__bitlen) \ | |
2358 | (0xFFFF >> (16 - (__bitlen))) | |
2359 | #define BIT_LEN_MASK_8(__bitlen) \ | |
2360 | (0xFF >> (8 - (__bitlen))) | |
2361 | ||
2362 | /* Create an offset bit mask | |
2363 | * Examples: | |
2364 | * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 | |
2365 | * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 | |
2366 | */ | |
2367 | #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ | |
2368 | (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) | |
2369 | #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ | |
2370 | (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) | |
2371 | #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ | |
2372 | (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) | |
2373 | ||
2374 | /*Description: | |
2375 | * Return 4-byte value in host byte ordering from | |
2376 | * 4-byte pointer in little-endian system. | |
2377 | */ | |
2378 | #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ | |
2379 | (EF4BYTE(*((__le32 *)(__pstart)))) | |
2380 | #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ | |
2381 | (EF2BYTE(*((__le16 *)(__pstart)))) | |
2382 | #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ | |
2383 | (EF1BYTE(*((u8 *)(__pstart)))) | |
2384 | ||
2385 | /*Description: | |
2386 | Translate subfield (continuous bits in little-endian) of 4-byte | |
2387 | value to host byte ordering.*/ | |
2388 | #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ | |
2389 | ( \ | |
2390 | (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ | |
2391 | BIT_LEN_MASK_32(__bitlen) \ | |
2392 | ) | |
2393 | #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ | |
2394 | ( \ | |
2395 | (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ | |
2396 | BIT_LEN_MASK_16(__bitlen) \ | |
2397 | ) | |
2398 | #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ | |
2399 | ( \ | |
2400 | (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ | |
2401 | BIT_LEN_MASK_8(__bitlen) \ | |
2402 | ) | |
2403 | ||
2404 | /* Description: | |
2405 | * Mask subfield (continuous bits in little-endian) of 4-byte value | |
2406 | * and return the result in 4-byte value in host byte ordering. | |
2407 | */ | |
2408 | #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ | |
2409 | ( \ | |
2410 | LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ | |
2411 | (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ | |
2412 | ) | |
2413 | #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ | |
2414 | ( \ | |
2415 | LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ | |
2416 | (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ | |
2417 | ) | |
2418 | #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ | |
2419 | ( \ | |
2420 | LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ | |
2421 | (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ | |
2422 | ) | |
2423 | ||
2424 | /* Description: | |
2425 | * Set subfield of little-endian 4-byte value to specified value. | |
2426 | */ | |
2427 | #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ | |
2428 | *((u32 *)(__pstart)) = \ | |
2429 | ( \ | |
2430 | LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ | |
2431 | ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ | |
2432 | ); | |
2433 | #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ | |
2434 | *((u16 *)(__pstart)) = \ | |
2435 | ( \ | |
2436 | LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ | |
2437 | ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ | |
2438 | ); | |
2439 | #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ | |
2440 | *((u8 *)(__pstart)) = EF1BYTE \ | |
2441 | ( \ | |
2442 | LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ | |
2443 | ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ | |
2444 | ); | |
2445 | ||
2446 | #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ | |
2447 | (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) | |
2448 | ||
2449 | /**************************************** | |
2450 | mem access macro define end | |
2451 | ****************************************/ | |
2452 | ||
2453 | #define byte(x , n) ((x >> (8 * n)) & 0xff) | |
2454 | ||
2455 | #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) | |
2456 | #define RTL_WATCH_DOG_TIME 2000 | |
2457 | #define MSECS(t) msecs_to_jiffies(t) | |
2458 | #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) | |
2459 | #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) | |
2460 | #define WLAN_FC_GET_STYPE(fc) (le16_to_cou(fc) & IEEE80211_FCTL_STYPE) | |
2461 | #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) | |
2462 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) | |
2463 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
2464 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
2465 | ||
2466 | #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ | |
2467 | #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ | |
2468 | #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ | |
2469 | /*NIC halt, re-initialize hw parameters*/ | |
2470 | #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) | |
2471 | #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ | |
2472 | #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ | |
2473 | /*Always enable ASPM and Clock Req in initialization.*/ | |
2474 | #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) | |
2475 | /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ | |
2476 | #define RT_PS_LEVEL_ASPM BIT(7) | |
2477 | /*When LPS is on, disable 2R if no packet is received or transmittd.*/ | |
2478 | #define RT_RF_LPS_DISALBE_2R BIT(30) | |
2479 | #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ | |
2480 | #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ | |
2481 | ((ppsc->cur_ps_level & _ps_flg) ? true : false) | |
2482 | #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ | |
2483 | (ppsc->cur_ps_level &= (~(_ps_flg))) | |
2484 | #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ | |
2485 | (ppsc->cur_ps_level |= _ps_flg) | |
2486 | ||
2487 | #define container_of_dwork_rtl(x , y , z) \ | |
2488 | container_of(container_of(x, struct delayed_work, work), y, z) | |
2489 | ||
2490 | #define FILL_OCTET_STRING(_os , _octet , _len) \ | |
2491 | (_os).octet = (u8 *)(_octet); \ | |
2492 | (_os).length = (_len); | |
2493 | ||
2494 | #define CP_MACADDR(des , src) \ | |
2495 | ((des)[0] = (src)[0] , (des)[1] = (src)[1],\ | |
2496 | (des)[2] = (src)[2] , (des)[3] = (src)[3],\ | |
2497 | (des)[4] = (src)[4] , (des)[5] = (src)[5]) | |
2498 | ||
2499 | #define LDPC_HT_ENABLE_RX BIT(0) | |
2500 | #define LDPC_HT_ENABLE_TX BIT(1) | |
2501 | #define LDPC_HT_TEST_TX_ENABLE BIT(2) | |
2502 | #define LDPC_HT_CAP_TX BIT(3) | |
2503 | ||
2504 | #define STBC_HT_ENABLE_RX BIT(0) | |
2505 | #define STBC_HT_ENABLE_TX BIT(1) | |
2506 | #define STBC_HT_TEST_TX_ENABLE BIT(2) | |
2507 | #define STBC_HT_CAP_TX BIT(3) | |
2508 | ||
2509 | ||
2510 | #define LDPC_VHT_ENABLE_RX BIT(0) | |
2511 | #define LDPC_VHT_ENABLE_TX BIT(1) | |
2512 | #define LDPC_VHT_TEST_TX_ENABLE BIT(2) | |
2513 | #define LDPC_VHT_CAP_TX BIT(3) | |
2514 | ||
2515 | #define STBC_VHT_ENABLE_RX BIT(0) | |
2516 | #define STBC_VHT_ENABLE_TX BIT(1) | |
2517 | #define STBC_VHT_TEST_TX_ENABLE BIT(2) | |
2518 | #define STBC_VHT_CAP_TX BIT(3) | |
2519 | ||
2520 | ||
2521 | static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) | |
2522 | { | |
2523 | return rtlpriv->io.read8_sync(rtlpriv, addr); | |
2524 | } | |
2525 | ||
2526 | static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) | |
2527 | { | |
2528 | return rtlpriv->io.read16_sync(rtlpriv, addr); | |
2529 | } | |
2530 | ||
2531 | static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) | |
2532 | { | |
2533 | return rtlpriv->io.read32_sync(rtlpriv, addr); | |
2534 | } | |
2535 | ||
2536 | static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) | |
2537 | { | |
2538 | rtlpriv->io.write8_async(rtlpriv, addr, val8); | |
2539 | ||
2540 | if (rtlpriv->cfg->write_readback) | |
2541 | rtlpriv->io.read8_sync(rtlpriv, addr); | |
2542 | } | |
2543 | ||
2544 | static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) | |
2545 | { | |
2546 | rtlpriv->io.write16_async(rtlpriv, addr, val16); | |
2547 | ||
2548 | if (rtlpriv->cfg->write_readback) | |
2549 | rtlpriv->io.read16_sync(rtlpriv, addr); | |
2550 | } | |
2551 | ||
2552 | static inline void rtl_write_dword(struct rtl_priv *rtlpriv, | |
2553 | u32 addr, u32 val32) | |
2554 | { | |
2555 | rtlpriv->io.write32_async(rtlpriv, addr, val32); | |
2556 | ||
2557 | if (rtlpriv->cfg->write_readback) | |
2558 | rtlpriv->io.read32_sync(rtlpriv, addr); | |
2559 | } | |
2560 | ||
2561 | static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, | |
2562 | u32 regaddr, u32 bitmask) | |
2563 | { | |
2564 | return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw, | |
2565 | regaddr, | |
2566 | bitmask); | |
2567 | } | |
2568 | ||
2569 | static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, | |
2570 | u32 bitmask, u32 data) | |
2571 | { | |
2572 | struct rtl_priv *rtlpriv = hw->priv; | |
2573 | ||
2574 | rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); | |
2575 | } | |
2576 | ||
2577 | static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, | |
2578 | enum radio_path rfpath, u32 regaddr, | |
2579 | u32 bitmask) | |
2580 | { | |
2581 | return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw, | |
2582 | rfpath, | |
2583 | regaddr, | |
2584 | bitmask); | |
2585 | } | |
2586 | ||
2587 | static inline void rtl_set_rfreg(struct ieee80211_hw *hw, | |
2588 | enum radio_path rfpath, u32 regaddr, | |
2589 | u32 bitmask, u32 data) | |
2590 | { | |
2591 | ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw, | |
2592 | rfpath, regaddr, | |
2593 | bitmask, data); | |
2594 | } | |
2595 | ||
2596 | static inline bool is_hal_stop(struct rtl_hal *rtlhal) | |
2597 | { | |
2598 | return _HAL_STATE_STOP == rtlhal->state; | |
2599 | } | |
2600 | ||
2601 | static inline void set_hal_start(struct rtl_hal *rtlhal) | |
2602 | { | |
2603 | rtlhal->state = _HAL_STATE_START; | |
2604 | } | |
2605 | ||
2606 | static inline void set_hal_stop(struct rtl_hal *rtlhal) | |
2607 | { | |
2608 | rtlhal->state = _HAL_STATE_STOP; | |
2609 | } | |
2610 | ||
2611 | static inline u8 get_rf_type(struct rtl_phy *rtlphy) | |
2612 | { | |
2613 | return rtlphy->rf_type; | |
2614 | } | |
2615 | ||
2616 | static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) | |
2617 | { | |
2618 | return (struct ieee80211_hdr *)(skb->data); | |
2619 | } | |
2620 | ||
2621 | static inline __le16 rtl_get_fc(struct sk_buff *skb) | |
2622 | { | |
2623 | return rtl_get_hdr(skb)->frame_control; | |
2624 | } | |
2625 | ||
2626 | static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) | |
2627 | { | |
2628 | return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; | |
2629 | } | |
2630 | ||
2631 | static inline u16 rtl_get_tid(struct sk_buff *skb) | |
2632 | { | |
2633 | return rtl_get_tid_h(rtl_get_hdr(skb)); | |
2634 | } | |
2635 | ||
2636 | static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, | |
2637 | u8 *mac_addr) | |
2638 | { | |
2639 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2640 | return ieee80211_find_sta(mac->vif, mac_addr); | |
2641 | } | |
2642 | ||
2643 | struct ieee80211_hw *rtl_pci_get_hw_pointer(void); | |
2644 | #endif |