Commit | Line | Data |
---|---|---|
8fc8598e JC |
1 | /* |
2 | This files contains card eeprom (93c46 or 93c56) programming routines, | |
3 | memory is addressed by 16 bits words. | |
4 | ||
5 | This is part of rtl8180 OpenSource driver. | |
559a4c31 | 6 | Copyright (C) Andrea Merello 2004 <andrea.merello@gmail.com> |
8fc8598e JC |
7 | Released under the terms of GPL (General Public Licence) |
8 | ||
9 | Parts of this driver are based on the GPL part of the | |
10 | official realtek driver. | |
11 | ||
12 | Parts of this driver are based on the rtl8180 driver skeleton | |
13 | from Patric Schenke & Andres Salomon. | |
14 | ||
15 | Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver. | |
16 | ||
ffae3055 | 17 | We want to thank the Authors of those projects and the Ndiswrapper |
8fc8598e JC |
18 | project Authors. |
19 | */ | |
20 | ||
21 | #include "r8180_93cx6.h" | |
22 | ||
f6bd19e0 | 23 | static void eprom_cs(struct net_device *dev, short bit) |
8fc8598e | 24 | { |
b3d42bf1 XR |
25 | u8 cmdreg; |
26 | ||
27 | read_nic_byte_E(dev, EPROM_CMD, &cmdreg); | |
fcd9f359 | 28 | if (bit) |
b3d42bf1 XR |
29 | /* enable EPROM */ |
30 | write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CS_BIT); | |
8fc8598e | 31 | else |
b3d42bf1 XR |
32 | /* disable EPROM */ |
33 | write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CS_BIT); | |
8fc8598e JC |
34 | |
35 | force_pci_posting(dev); | |
36 | udelay(EPROM_DELAY); | |
37 | } | |
38 | ||
39 | ||
f6bd19e0 | 40 | static void eprom_ck_cycle(struct net_device *dev) |
8fc8598e | 41 | { |
b3d42bf1 XR |
42 | u8 cmdreg; |
43 | ||
44 | read_nic_byte_E(dev, EPROM_CMD, &cmdreg); | |
45 | write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CK_BIT); | |
8fc8598e JC |
46 | force_pci_posting(dev); |
47 | udelay(EPROM_DELAY); | |
b3d42bf1 XR |
48 | |
49 | read_nic_byte_E(dev, EPROM_CMD, &cmdreg); | |
50 | write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CK_BIT); | |
8fc8598e JC |
51 | force_pci_posting(dev); |
52 | udelay(EPROM_DELAY); | |
53 | } | |
54 | ||
55 | ||
6371f210 | 56 | static void eprom_w(struct net_device *dev, short bit) |
8fc8598e | 57 | { |
b3d42bf1 XR |
58 | u8 cmdreg; |
59 | ||
60 | read_nic_byte_E(dev, EPROM_CMD, &cmdreg); | |
fcd9f359 | 61 | if (bit) |
b3d42bf1 | 62 | write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_W_BIT); |
8fc8598e | 63 | else |
b3d42bf1 | 64 | write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_W_BIT); |
8fc8598e JC |
65 | |
66 | force_pci_posting(dev); | |
67 | udelay(EPROM_DELAY); | |
68 | } | |
69 | ||
70 | ||
f6bd19e0 | 71 | static short eprom_r(struct net_device *dev) |
8fc8598e | 72 | { |
b3d42bf1 | 73 | u8 bit; |
8fc8598e | 74 | |
b3d42bf1 | 75 | read_nic_byte_E(dev, EPROM_CMD, &bit); |
8fc8598e JC |
76 | udelay(EPROM_DELAY); |
77 | ||
b3d42bf1 XR |
78 | if (bit & EPROM_R_BIT) |
79 | return 1; | |
80 | ||
8fc8598e JC |
81 | return 0; |
82 | } | |
83 | ||
84 | ||
f6bd19e0 | 85 | static void eprom_send_bits_string(struct net_device *dev, short b[], int len) |
8fc8598e JC |
86 | { |
87 | int i; | |
88 | ||
6371f210 | 89 | for (i = 0; i < len; i++) { |
8fc8598e JC |
90 | eprom_w(dev, b[i]); |
91 | eprom_ck_cycle(dev); | |
92 | } | |
93 | } | |
94 | ||
95 | ||
96 | u32 eprom_read(struct net_device *dev, u32 addr) | |
97 | { | |
98 | struct r8192_priv *priv = ieee80211_priv(dev); | |
6371f210 | 99 | short read_cmd[] = {1, 1, 0}; |
8fc8598e JC |
100 | short addr_str[8]; |
101 | int i; | |
102 | int addr_len; | |
103 | u32 ret; | |
104 | ||
6371f210 | 105 | ret = 0; |
2ad99c50 | 106 | /* enable EPROM programming */ |
8fc8598e JC |
107 | write_nic_byte_E(dev, EPROM_CMD, |
108 | (EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT)); | |
109 | force_pci_posting(dev); | |
110 | udelay(EPROM_DELAY); | |
111 | ||
6371f210 CH |
112 | if (priv->epromtype == EPROM_93c56) { |
113 | addr_str[7] = addr & 1; | |
114 | addr_str[6] = addr & (1<<1); | |
115 | addr_str[5] = addr & (1<<2); | |
116 | addr_str[4] = addr & (1<<3); | |
117 | addr_str[3] = addr & (1<<4); | |
118 | addr_str[2] = addr & (1<<5); | |
119 | addr_str[1] = addr & (1<<6); | |
120 | addr_str[0] = addr & (1<<7); | |
121 | addr_len = 8; | |
122 | } else { | |
123 | addr_str[5] = addr & 1; | |
124 | addr_str[4] = addr & (1<<1); | |
125 | addr_str[3] = addr & (1<<2); | |
126 | addr_str[2] = addr & (1<<3); | |
127 | addr_str[1] = addr & (1<<4); | |
128 | addr_str[0] = addr & (1<<5); | |
129 | addr_len = 6; | |
8fc8598e JC |
130 | } |
131 | eprom_cs(dev, 1); | |
132 | eprom_ck_cycle(dev); | |
133 | eprom_send_bits_string(dev, read_cmd, 3); | |
134 | eprom_send_bits_string(dev, addr_str, addr_len); | |
135 | ||
2ad99c50 SS |
136 | /* |
137 | * keep chip pin D to low state while reading. | |
138 | * I'm unsure if it is necessary, but anyway shouldn't hurt | |
139 | */ | |
8fc8598e JC |
140 | eprom_w(dev, 0); |
141 | ||
6371f210 | 142 | for (i = 0; i < 16; i++) { |
2ad99c50 SS |
143 | /* eeprom needs a clk cycle between writing opcode&adr |
144 | * and reading data. (eeprom outs a dummy 0) | |
145 | */ | |
8fc8598e JC |
146 | eprom_ck_cycle(dev); |
147 | ret |= (eprom_r(dev)<<(15-i)); | |
148 | } | |
149 | ||
150 | eprom_cs(dev, 0); | |
151 | eprom_ck_cycle(dev); | |
152 | ||
2ad99c50 | 153 | /* disable EPROM programming */ |
8fc8598e JC |
154 | write_nic_byte_E(dev, EPROM_CMD, |
155 | (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT)); | |
156 | return ret; | |
157 | } |