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8fc8598e JC |
1 | /* |
2 | This is part of rtl8187 OpenSource driver. | |
3 | Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> | |
4 | Released under the terms of GPL (General Public Licence) | |
5 | ||
6 | Parts of this driver are based on the GPL part of the | |
7 | official realtek driver | |
8 | ||
9 | Parts of this driver are based on the rtl8192 driver skeleton | |
10 | from Patric Schenke & Andres Salomon | |
11 | ||
12 | Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver | |
13 | ||
14 | We want to tanks the Authors of those projects and the Ndiswrapper | |
15 | project Authors. | |
16 | */ | |
17 | ||
18 | #ifndef R819xU_H | |
19 | #define R819xU_H | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/kernel.h> | |
23 | //#include <linux/config.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/netdevice.h> | |
30 | //#include <linux/pci.h> | |
31 | #include <linux/usb.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/rtnetlink.h> //for rtnl_lock() | |
35 | #include <linux/wireless.h> | |
36 | #include <linux/timer.h> | |
37 | #include <linux/proc_fs.h> // Necessary because we use the proc fs | |
38 | #include <linux/if_arp.h> | |
39 | #include <linux/random.h> | |
40 | #include <linux/version.h> | |
41 | #include <asm/io.h> | |
2addf798 | 42 | #include "ieee80211/ieee80211.h" |
8fc8598e JC |
43 | |
44 | #define RTL8192U | |
45 | #define RTL819xU_MODULE_NAME "rtl819xU" | |
46 | //added for HW security, john.0629 | |
47 | #define FALSE 0 | |
48 | #define TRUE 1 | |
49 | #define MAX_KEY_LEN 61 | |
50 | #define KEY_BUF_SIZE 5 | |
51 | ||
52 | #define BIT0 0x00000001 | |
53 | #define BIT1 0x00000002 | |
54 | #define BIT2 0x00000004 | |
55 | #define BIT3 0x00000008 | |
56 | #define BIT4 0x00000010 | |
57 | #define BIT5 0x00000020 | |
58 | #define BIT6 0x00000040 | |
59 | #define BIT7 0x00000080 | |
60 | #define BIT8 0x00000100 | |
61 | #define BIT9 0x00000200 | |
62 | #define BIT10 0x00000400 | |
63 | #define BIT11 0x00000800 | |
64 | #define BIT12 0x00001000 | |
65 | #define BIT13 0x00002000 | |
66 | #define BIT14 0x00004000 | |
67 | #define BIT15 0x00008000 | |
68 | #define BIT16 0x00010000 | |
69 | #define BIT17 0x00020000 | |
70 | #define BIT18 0x00040000 | |
71 | #define BIT19 0x00080000 | |
72 | #define BIT20 0x00100000 | |
73 | #define BIT21 0x00200000 | |
74 | #define BIT22 0x00400000 | |
75 | #define BIT23 0x00800000 | |
76 | #define BIT24 0x01000000 | |
77 | #define BIT25 0x02000000 | |
78 | #define BIT26 0x04000000 | |
79 | #define BIT27 0x08000000 | |
80 | #define BIT28 0x10000000 | |
81 | #define BIT29 0x20000000 | |
82 | #define BIT30 0x40000000 | |
83 | #define BIT31 0x80000000 | |
84 | ||
85 | // Rx smooth factor | |
86 | #define Rx_Smooth_Factor 20 | |
8fc8598e JC |
87 | #define DMESG(x,a...) |
88 | #define DMESGW(x,a...) | |
89 | #define DMESGE(x,a...) | |
90 | extern u32 rt_global_debug_component; | |
91 | #define RT_TRACE(component, x, args...) \ | |
92 | do { if(rt_global_debug_component & component) \ | |
93 | printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \ | |
94 | ##args);\ | |
95 | }while(0); | |
96 | ||
97 | #define COMP_TRACE BIT0 // For function call tracing. | |
98 | #define COMP_DBG BIT1 // Only for temporary debug message. | |
99 | #define COMP_INIT BIT2 // during driver initialization / halt / reset. | |
100 | ||
101 | ||
102 | #define COMP_RECV BIT3 // Reveive part data path. | |
103 | #define COMP_SEND BIT4 // Send part path. | |
104 | #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02. | |
105 | #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related. | |
106 | #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS. | |
107 | #define COMP_SWBW BIT8 // For bandwidth switch. | |
108 | #define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING | |
109 | #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21. | |
110 | #define COMP_QOS BIT11 // For QoS. | |
111 | #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. | |
112 | #define COMP_RM BIT13 // For Radio Measurement. | |
113 | #define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko. | |
114 | #define COMP_PHY BIT15 | |
115 | #define COMP_CH BIT16 //channel setting debug | |
116 | #define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko. | |
117 | #define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko. | |
118 | #define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko. | |
119 | #define COMP_SEC BIT20 // Event handling | |
120 | #define COMP_LED BIT21 // For LED. | |
121 | #define COMP_RF BIT22 // For RF. | |
122 | //1!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
123 | #define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15. | |
124 | //1//1Attention Please!!!<11n or 8190 specific code should be put below this line> | |
125 | //1!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
126 | ||
127 | #define COMP_FIRMWARE BIT24 //for firmware downloading | |
128 | #define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11 | |
129 | #define COMP_AMSDU BIT26 // For A-MSDU Debugging | |
130 | ||
131 | #define COMP_SCAN BIT27 | |
132 | //#define COMP_RESET BIT28 | |
133 | #define COMP_DOWN BIT29 //for rm driver module | |
134 | #define COMP_RESET BIT30 //for silent reset | |
135 | #define COMP_ERR BIT31 //for error out, always on | |
8fc8598e JC |
136 | |
137 | #define RTL819x_DEBUG | |
138 | #ifdef RTL819x_DEBUG | |
139 | #define assert(expr) \ | |
140 | if (!(expr)) { \ | |
141 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
142 | #expr,__FILE__,__FUNCTION__,__LINE__); \ | |
143 | } | |
144 | //wb added to debug out data buf | |
145 | //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA | |
146 | #define RT_DEBUG_DATA(level, data, datalen) \ | |
147 | do{ if ((rt_global_debug_component & (level)) == (level)) \ | |
148 | { \ | |
149 | int i; \ | |
150 | u8* pdata = (u8*) data; \ | |
151 | printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \ | |
152 | for(i=0; i<(int)(datalen); i++) \ | |
153 | { \ | |
154 | printk("%2x ", pdata[i]); \ | |
155 | if ((i+1)%16 == 0) printk("\n"); \ | |
156 | } \ | |
157 | printk("\n"); \ | |
158 | } \ | |
159 | } while (0) | |
160 | #else | |
161 | #define assert(expr) do {} while (0) | |
162 | #define RT_DEBUG_DATA(level, data, datalen) do {} while(0) | |
163 | #endif /* RTL8169_DEBUG */ | |
164 | ||
165 | ||
166 | // | |
167 | // Queue Select Value in TxDesc | |
168 | // | |
169 | #define QSLT_BK 0x1 | |
170 | #define QSLT_BE 0x0 | |
171 | #define QSLT_VI 0x4 | |
172 | #define QSLT_VO 0x6 | |
173 | #define QSLT_BEACON 0x10 | |
174 | #define QSLT_HIGH 0x11 | |
175 | #define QSLT_MGNT 0x12 | |
176 | #define QSLT_CMD 0x13 | |
177 | ||
178 | #define DESC90_RATE1M 0x00 | |
179 | #define DESC90_RATE2M 0x01 | |
180 | #define DESC90_RATE5_5M 0x02 | |
181 | #define DESC90_RATE11M 0x03 | |
182 | #define DESC90_RATE6M 0x04 | |
183 | #define DESC90_RATE9M 0x05 | |
184 | #define DESC90_RATE12M 0x06 | |
185 | #define DESC90_RATE18M 0x07 | |
186 | #define DESC90_RATE24M 0x08 | |
187 | #define DESC90_RATE36M 0x09 | |
188 | #define DESC90_RATE48M 0x0a | |
189 | #define DESC90_RATE54M 0x0b | |
190 | #define DESC90_RATEMCS0 0x00 | |
191 | #define DESC90_RATEMCS1 0x01 | |
192 | #define DESC90_RATEMCS2 0x02 | |
193 | #define DESC90_RATEMCS3 0x03 | |
194 | #define DESC90_RATEMCS4 0x04 | |
195 | #define DESC90_RATEMCS5 0x05 | |
196 | #define DESC90_RATEMCS6 0x06 | |
197 | #define DESC90_RATEMCS7 0x07 | |
198 | #define DESC90_RATEMCS8 0x08 | |
199 | #define DESC90_RATEMCS9 0x09 | |
200 | #define DESC90_RATEMCS10 0x0a | |
201 | #define DESC90_RATEMCS11 0x0b | |
202 | #define DESC90_RATEMCS12 0x0c | |
203 | #define DESC90_RATEMCS13 0x0d | |
204 | #define DESC90_RATEMCS14 0x0e | |
205 | #define DESC90_RATEMCS15 0x0f | |
206 | #define DESC90_RATEMCS32 0x20 | |
207 | ||
208 | #define RTL819X_DEFAULT_RF_TYPE RF_1T2R | |
209 | ||
210 | #define IEEE80211_WATCH_DOG_TIME 2000 | |
211 | #define PHY_Beacon_RSSI_SLID_WIN_MAX 10 | |
212 | //for txpowertracking by amy | |
213 | #define OFDM_Table_Length 19 | |
214 | #define CCK_Table_length 12 | |
215 | ||
216 | /* for rtl819x */ | |
217 | typedef struct _tx_desc_819x_usb { | |
218 | //DWORD 0 | |
219 | u16 PktSize; | |
220 | u8 Offset; | |
221 | u8 Reserved0:3; | |
222 | u8 CmdInit:1; | |
223 | u8 LastSeg:1; | |
224 | u8 FirstSeg:1; | |
225 | u8 LINIP:1; | |
226 | u8 OWN:1; | |
227 | ||
228 | //DWORD 1 | |
229 | u8 TxFWInfoSize; | |
230 | u8 RATid:3; | |
231 | u8 DISFB:1; | |
232 | u8 USERATE:1; | |
233 | u8 MOREFRAG:1; | |
234 | u8 NoEnc:1; | |
235 | u8 PIFS:1; | |
236 | u8 QueueSelect:5; | |
237 | u8 NoACM:1; | |
238 | u8 Reserved1:2; | |
239 | u8 SecCAMID:5; | |
240 | u8 SecDescAssign:1; | |
241 | u8 SecType:2; | |
242 | ||
243 | //DWORD 2 | |
244 | u16 TxBufferSize; | |
245 | //u16 Reserved2; | |
246 | u8 ResvForPaddingLen:7; | |
247 | u8 Reserved3:1; | |
248 | u8 Reserved4; | |
249 | ||
250 | //DWORD 3, 4, 5 | |
251 | u32 Reserved5; | |
252 | u32 Reserved6; | |
253 | u32 Reserved7; | |
254 | }tx_desc_819x_usb, *ptx_desc_819x_usb; | |
255 | ||
256 | #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE | |
257 | typedef struct _tx_desc_819x_usb_aggr_subframe { | |
258 | //DWORD 0 | |
259 | u16 PktSize; | |
260 | u8 Offset; | |
261 | u8 TxFWInfoSize; | |
262 | ||
263 | //DWORD 1 | |
264 | u8 RATid:3; | |
265 | u8 DISFB:1; | |
266 | u8 USERATE:1; | |
267 | u8 MOREFRAG:1; | |
268 | u8 NoEnc:1; | |
269 | u8 PIFS:1; | |
270 | u8 QueueSelect:5; | |
271 | u8 NoACM:1; | |
272 | u8 Reserved1:2; | |
273 | u8 SecCAMID:5; | |
274 | u8 SecDescAssign:1; | |
275 | u8 SecType:2; | |
276 | u8 PacketID:7; | |
277 | u8 OWN:1; | |
278 | }tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe; | |
279 | #endif | |
280 | ||
281 | ||
282 | ||
283 | typedef struct _tx_desc_cmd_819x_usb { | |
284 | //DWORD 0 | |
285 | u16 Reserved0; | |
286 | u8 Reserved1; | |
287 | u8 Reserved2:3; | |
288 | u8 CmdInit:1; | |
289 | u8 LastSeg:1; | |
290 | u8 FirstSeg:1; | |
291 | u8 LINIP:1; | |
292 | u8 OWN:1; | |
293 | ||
294 | //DOWRD 1 | |
295 | //u32 Reserved3; | |
296 | u8 TxFWInfoSize; | |
297 | u8 Reserved3; | |
298 | u8 QueueSelect; | |
299 | u8 Reserved4; | |
300 | ||
301 | //DOWRD 2 | |
302 | u16 TxBufferSize; | |
303 | u16 Reserved5; | |
304 | ||
305 | //DWORD 3,4,5 | |
306 | //u32 TxBufferAddr; | |
307 | //u32 NextDescAddress; | |
308 | u32 Reserved6; | |
309 | u32 Reserved7; | |
310 | u32 Reserved8; | |
311 | }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb; | |
312 | ||
313 | ||
314 | typedef struct _tx_fwinfo_819x_usb { | |
315 | //DOWRD 0 | |
316 | u8 TxRate:7; | |
317 | u8 CtsEnable:1; | |
318 | u8 RtsRate:7; | |
319 | u8 RtsEnable:1; | |
320 | u8 TxHT:1; | |
321 | u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS | |
322 | u8 TxBandwidth:1; // This is used for HT MCS rate only. | |
323 | u8 TxSubCarrier:2; // This is used for legacy OFDM rate only. | |
324 | u8 STBC:2; | |
325 | u8 AllowAggregation:1; | |
326 | u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate | |
327 | u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS | |
328 | u8 RtsBandwidth:1; // This is used for HT MCS rate only. | |
329 | u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only. | |
330 | u8 RtsSTBC:2; | |
331 | u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration | |
332 | ||
333 | //DWORD 1 | |
334 | u32 RxMF:2; | |
335 | u32 RxAMD:3; | |
336 | u32 TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd | |
337 | u32 Reserved1:2; | |
338 | u32 TxAGCOffSet:4; | |
339 | u32 TxAGCSign:1; | |
340 | u32 Tx_INFO_RSVD:6; | |
341 | u32 PacketID:13; | |
342 | //u32 Reserved; | |
343 | }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb; | |
344 | ||
345 | typedef struct rtl8192_rx_info { | |
346 | struct urb *urb; | |
347 | struct net_device *dev; | |
348 | u8 out_pipe; | |
349 | }rtl8192_rx_info ; | |
350 | ||
351 | typedef struct rx_desc_819x_usb{ | |
352 | //DOWRD 0 | |
353 | u16 Length:14; | |
354 | u16 CRC32:1; | |
355 | u16 ICV:1; | |
356 | u8 RxDrvInfoSize; | |
357 | u8 Shift:2; | |
358 | u8 PHYStatus:1; | |
359 | u8 SWDec:1; | |
360 | //u8 LastSeg:1; | |
361 | //u8 FirstSeg:1; | |
362 | //u8 EOR:1; | |
363 | //u8 OWN:1; | |
364 | u8 Reserved1:4; | |
365 | ||
366 | //DWORD 1 | |
367 | u32 Reserved2; | |
368 | ||
369 | //DWORD 2 | |
370 | //u32 Reserved3; | |
371 | ||
372 | //DWORD 3 | |
373 | //u32 BufferAddress; | |
374 | ||
375 | }rx_desc_819x_usb, *prx_desc_819x_usb; | |
376 | ||
377 | #ifdef USB_RX_AGGREGATION_SUPPORT | |
378 | typedef struct _rx_desc_819x_usb_aggr_subframe{ | |
379 | //DOWRD 0 | |
380 | u16 Length:14; | |
381 | u16 CRC32:1; | |
382 | u16 ICV:1; | |
383 | u8 Offset; | |
384 | u8 RxDrvInfoSize; | |
385 | //DOWRD 1 | |
386 | u8 Shift:2; | |
387 | u8 PHYStatus:1; | |
388 | u8 SWDec:1; | |
389 | u8 Reserved1:4; | |
390 | u8 Reserved2; | |
391 | u16 Reserved3; | |
392 | //DWORD 2 | |
393 | //u4Byte Reserved3; | |
394 | //DWORD 3 | |
395 | //u4Byte BufferAddress; | |
396 | }rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe; | |
397 | #endif | |
398 | ||
399 | typedef struct rx_drvinfo_819x_usb{ | |
400 | //DWORD 0 | |
401 | u16 Reserved1:12; | |
402 | u16 PartAggr:1; | |
403 | u16 FirstAGGR:1; | |
404 | u16 Reserved2:2; | |
405 | ||
406 | u8 RxRate:7; | |
407 | u8 RxHT:1; | |
408 | ||
409 | u8 BW:1; | |
410 | u8 SPLCP:1; | |
411 | u8 Reserved3:2; | |
412 | u8 PAM:1; | |
413 | u8 Mcast:1; | |
414 | u8 Bcast:1; | |
415 | u8 Reserved4:1; | |
416 | ||
417 | //DWORD 1 | |
418 | u32 TSFL; | |
419 | ||
420 | }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb; | |
421 | ||
422 | ||
423 | #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */ | |
424 | #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/ | |
425 | #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE) | |
426 | #define ENCRYPTION_MAX_OVERHEAD 128 | |
427 | #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb) | |
428 | #define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb)) | |
429 | #define MAX_FRAGMENT_COUNT 8 | |
430 | #ifdef RTL8192U | |
431 | #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE | |
432 | #define MAX_TRANSMIT_BUFFER_SIZE 32000 | |
433 | #else | |
434 | #define MAX_TRANSMIT_BUFFER_SIZE 8000 | |
435 | #endif | |
436 | #else | |
437 | #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT) | |
438 | #endif | |
439 | #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE | |
440 | #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb)) | |
441 | #endif | |
442 | #define scrclng 4 // octets for crc32 (FCS, ICV) | |
443 | ||
444 | typedef enum rf_optype | |
445 | { | |
446 | RF_OP_By_SW_3wire = 0, | |
447 | RF_OP_By_FW, | |
448 | RF_OP_MAX | |
449 | }rf_op_type; | |
450 | /* 8190 Loopback Mode definition */ | |
451 | typedef enum _rtl819xUsb_loopback{ | |
452 | RTL819xU_NO_LOOPBACK = 0, | |
453 | RTL819xU_MAC_LOOPBACK = 1, | |
454 | RTL819xU_DMA_LOOPBACK = 2, | |
455 | RTL819xU_CCK_LOOPBACK = 3, | |
456 | }rtl819xUsb_loopback_e; | |
457 | ||
458 | /* due to rtl8192 firmware */ | |
459 | typedef enum _desc_packet_type_e{ | |
460 | DESC_PACKET_TYPE_INIT = 0, | |
461 | DESC_PACKET_TYPE_NORMAL = 1, | |
462 | }desc_packet_type_e; | |
463 | ||
8fc8598e JC |
464 | typedef enum _firmware_status{ |
465 | FW_STATUS_0_INIT = 0, | |
466 | FW_STATUS_1_MOVE_BOOT_CODE = 1, | |
467 | FW_STATUS_2_MOVE_MAIN_CODE = 2, | |
468 | FW_STATUS_3_TURNON_CPU = 3, | |
469 | FW_STATUS_4_MOVE_DATA_CODE = 4, | |
470 | FW_STATUS_5_READY = 5, | |
471 | }firmware_status_e; | |
472 | ||
473 | typedef struct _rt_firmare_seg_container { | |
474 | u16 seg_size; | |
475 | u8 *seg_ptr; | |
476 | }fw_seg_container, *pfw_seg_container; | |
477 | typedef struct _rt_firmware{ | |
478 | firmware_status_e firmware_status; | |
479 | u16 cmdpacket_frag_thresold; | |
480 | #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k | |
481 | u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE]; | |
482 | u16 firmware_buf_size; | |
483 | }rt_firmware, *prt_firmware; | |
484 | ||
485 | //+by amy 080507 | |
486 | #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP | |
487 | ||
488 | typedef struct _rt_firmware_info_819xUsb{ | |
489 | u8 sz_info[16]; | |
490 | }rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb; | |
491 | ||
492 | /* Firmware Queue Layout */ | |
493 | #define NUM_OF_FIRMWARE_QUEUE 10 | |
494 | #define NUM_OF_PAGES_IN_FW 0x100 | |
495 | ||
496 | #ifdef USE_ONE_PIPE | |
497 | #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x000 | |
498 | #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x000 | |
499 | #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x0ff | |
500 | #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x000 | |
501 | #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 | |
502 | #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0 | |
503 | #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x00 | |
504 | #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 | |
505 | #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x0 | |
506 | #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x00 | |
507 | #else | |
508 | ||
509 | #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020 | |
510 | #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020 | |
511 | #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040 | |
512 | #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040 | |
513 | #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 | |
514 | #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4 | |
515 | #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20 | |
516 | #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 | |
517 | #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 | |
518 | #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18 | |
519 | ||
520 | #endif | |
521 | ||
522 | #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 | |
523 | #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 | |
524 | #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 | |
525 | #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 | |
526 | #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 | |
527 | #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 | |
528 | #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08 | |
529 | #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 | |
530 | #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 | |
531 | //================================================================= | |
532 | //================================================================= | |
533 | ||
534 | #define EPROM_93c46 0 | |
535 | #define EPROM_93c56 1 | |
536 | ||
537 | #define DEFAULT_FRAG_THRESHOLD 2342U | |
538 | #define MIN_FRAG_THRESHOLD 256U | |
539 | #define DEFAULT_BEACONINTERVAL 0x64U | |
540 | #define DEFAULT_BEACON_ESSID "Rtl819xU" | |
541 | ||
542 | #define DEFAULT_SSID "" | |
543 | #define DEFAULT_RETRY_RTS 7 | |
544 | #define DEFAULT_RETRY_DATA 7 | |
545 | #define PRISM_HDR_SIZE 64 | |
546 | ||
547 | #define PHY_RSSI_SLID_WIN_MAX 100 | |
548 | ||
549 | ||
550 | typedef enum _WIRELESS_MODE { | |
551 | WIRELESS_MODE_UNKNOWN = 0x00, | |
552 | WIRELESS_MODE_A = 0x01, | |
553 | WIRELESS_MODE_B = 0x02, | |
554 | WIRELESS_MODE_G = 0x04, | |
555 | WIRELESS_MODE_AUTO = 0x08, | |
556 | WIRELESS_MODE_N_24G = 0x10, | |
557 | WIRELESS_MODE_N_5G = 0x20 | |
558 | } WIRELESS_MODE; | |
559 | ||
560 | ||
561 | #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30 | |
562 | ||
563 | typedef struct buffer | |
564 | { | |
565 | struct buffer *next; | |
566 | u32 *buf; | |
567 | ||
568 | } buffer; | |
569 | ||
570 | typedef struct rtl_reg_debug{ | |
571 | unsigned int cmd; | |
572 | struct { | |
573 | unsigned char type; | |
574 | unsigned char addr; | |
575 | unsigned char page; | |
576 | unsigned char length; | |
577 | } head; | |
578 | unsigned char buf[0xff]; | |
579 | }rtl_reg_debug; | |
580 | ||
581 | ||
582 | ||
583 | ||
584 | ||
8fc8598e JC |
585 | |
586 | typedef struct _rt_9x_tx_rate_history { | |
587 | u32 cck[4]; | |
588 | u32 ofdm[8]; | |
589 | // HT_MCS[0][]: BW=0 SG=0 | |
590 | // HT_MCS[1][]: BW=1 SG=0 | |
591 | // HT_MCS[2][]: BW=0 SG=1 | |
592 | // HT_MCS[3][]: BW=1 SG=1 | |
593 | u32 ht_mcs[4][16]; | |
594 | }rt_tx_rahis_t, *prt_tx_rahis_t; | |
595 | typedef struct _RT_SMOOTH_DATA_4RF { | |
596 | char elements[4][100];//array to store values | |
597 | u32 index; //index to current array to store | |
598 | u32 TotalNum; //num of valid elements | |
599 | u32 TotalVal[4]; //sum of valid elements | |
600 | }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF; | |
601 | ||
602 | #define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size | |
603 | //stats seems messed up, clean it ASAP | |
604 | typedef struct Stats | |
605 | { | |
606 | unsigned long txrdu; | |
607 | // unsigned long rxrdu; | |
608 | //unsigned long rxnolast; | |
609 | //unsigned long rxnodata; | |
610 | // unsigned long rxreset; | |
611 | // unsigned long rxnopointer; | |
612 | unsigned long rxok; | |
613 | unsigned long rxframgment; | |
614 | unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query | |
615 | unsigned long rxurberr; | |
616 | unsigned long rxstaterr; | |
617 | unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa | |
618 | unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI | |
619 | unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) | |
620 | unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40) | |
621 | unsigned long numpacket_matchbssid; // debug use only. | |
622 | unsigned long numpacket_toself; // debug use only. | |
623 | unsigned long num_process_phyinfo; // debug use only. | |
624 | unsigned long numqry_phystatus; | |
625 | unsigned long numqry_phystatusCCK; | |
626 | unsigned long numqry_phystatusHT; | |
627 | unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate | |
628 | unsigned long txnperr; | |
629 | unsigned long txnpdrop; | |
630 | unsigned long txresumed; | |
631 | // unsigned long rxerr; | |
632 | // unsigned long rxoverflow; | |
633 | // unsigned long rxint; | |
634 | unsigned long txnpokint; | |
635 | // unsigned long txhpokint; | |
636 | // unsigned long txhperr; | |
637 | // unsigned long ints; | |
638 | // unsigned long shints; | |
639 | unsigned long txoverflow; | |
640 | // unsigned long rxdmafail; | |
641 | // unsigned long txbeacon; | |
642 | // unsigned long txbeaconerr; | |
643 | unsigned long txlpokint; | |
644 | unsigned long txlpdrop; | |
645 | unsigned long txlperr; | |
646 | unsigned long txbeokint; | |
647 | unsigned long txbedrop; | |
648 | unsigned long txbeerr; | |
649 | unsigned long txbkokint; | |
650 | unsigned long txbkdrop; | |
651 | unsigned long txbkerr; | |
652 | unsigned long txviokint; | |
653 | unsigned long txvidrop; | |
654 | unsigned long txvierr; | |
655 | unsigned long txvookint; | |
656 | unsigned long txvodrop; | |
657 | unsigned long txvoerr; | |
658 | unsigned long txbeaconokint; | |
659 | unsigned long txbeacondrop; | |
660 | unsigned long txbeaconerr; | |
661 | unsigned long txmanageokint; | |
662 | unsigned long txmanagedrop; | |
663 | unsigned long txmanageerr; | |
664 | unsigned long txdatapkt; | |
665 | unsigned long txfeedback; | |
666 | unsigned long txfeedbackok; | |
667 | ||
668 | unsigned long txoktotal; | |
669 | unsigned long txokbytestotal; | |
670 | unsigned long txokinperiod; | |
671 | unsigned long txmulticast; | |
672 | unsigned long txbytesmulticast; | |
673 | unsigned long txbroadcast; | |
674 | unsigned long txbytesbroadcast; | |
675 | unsigned long txunicast; | |
676 | unsigned long txbytesunicast; | |
677 | ||
678 | unsigned long rxoktotal; | |
679 | unsigned long rxbytesunicast; | |
680 | unsigned long txfeedbackfail; | |
681 | unsigned long txerrtotal; | |
682 | unsigned long txerrbytestotal; | |
683 | unsigned long txerrmulticast; | |
684 | unsigned long txerrbroadcast; | |
685 | unsigned long txerrunicast; | |
686 | unsigned long txretrycount; | |
687 | unsigned long txfeedbackretry; | |
688 | u8 last_packet_rate; | |
689 | unsigned long slide_signal_strength[100]; | |
690 | unsigned long slide_evm[100]; | |
691 | unsigned long slide_rssi_total; // For recording sliding window's RSSI value | |
692 | unsigned long slide_evm_total; // For recording sliding window's EVM value | |
693 | long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct. | |
694 | long signal_quality; | |
695 | long last_signal_strength_inpercent; | |
696 | long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now. | |
697 | u8 rx_rssi_percentage[4]; | |
698 | u8 rx_evm_percentage[2]; | |
699 | long rxSNRdB[4]; | |
700 | rt_tx_rahis_t txrate; | |
701 | u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi | |
702 | u32 Slide_Beacon_Total; //cosa add for beacon rssi | |
703 | RT_SMOOTH_DATA_4RF cck_adc_pwdb; | |
704 | ||
705 | u32 CurrentShowTxate; | |
706 | } Stats; | |
707 | ||
708 | ||
709 | // Bandwidth Offset | |
710 | #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 | |
711 | #define HAL_PRIME_CHNL_OFFSET_LOWER 1 | |
712 | #define HAL_PRIME_CHNL_OFFSET_UPPER 2 | |
713 | ||
714 | //+by amy 080507 | |
715 | ||
716 | typedef struct ChnlAccessSetting { | |
717 | u16 SIFS_Timer; | |
718 | u16 DIFS_Timer; | |
719 | u16 SlotTimeTimer; | |
720 | u16 EIFS_Timer; | |
721 | u16 CWminIndex; | |
722 | u16 CWmaxIndex; | |
723 | }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING; | |
724 | ||
725 | typedef struct _BB_REGISTER_DEFINITION{ | |
726 | u32 rfintfs; // set software control: // 0x870~0x877[8 bytes] | |
727 | u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes] | |
728 | u32 rfintfo; // output data: // 0x860~0x86f [16 bytes] | |
729 | u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes] | |
730 | u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes] | |
731 | u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes] | |
732 | u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes] | |
733 | u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] | |
734 | u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] | |
735 | u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes] | |
736 | u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] | |
737 | u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] | |
738 | u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] | |
739 | u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] | |
740 | u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] | |
741 | u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] | |
742 | u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes] | |
743 | }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; | |
744 | ||
745 | typedef enum _RT_RF_TYPE_819xU{ | |
746 | RF_TYPE_MIN = 0, | |
747 | RF_8225, | |
748 | RF_8256, | |
749 | RF_8258, | |
750 | RF_PSEUDO_11N = 4, | |
751 | }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; | |
752 | ||
753 | typedef struct _rate_adaptive | |
754 | { | |
755 | u8 rate_adaptive_disabled; | |
756 | u8 ratr_state; | |
757 | u16 reserve; | |
758 | ||
759 | u32 high_rssi_thresh_for_ra; | |
760 | u32 high2low_rssi_thresh_for_ra; | |
761 | u8 low2high_rssi_thresh_for_ra40M; | |
762 | u32 low_rssi_thresh_for_ra40M; | |
763 | u8 low2high_rssi_thresh_for_ra20M; | |
764 | u32 low_rssi_thresh_for_ra20M; | |
765 | u32 upper_rssi_threshold_ratr; | |
766 | u32 middle_rssi_threshold_ratr; | |
767 | u32 low_rssi_threshold_ratr; | |
768 | u32 low_rssi_threshold_ratr_40M; | |
769 | u32 low_rssi_threshold_ratr_20M; | |
770 | u8 ping_rssi_enable; //cosa add for test | |
771 | u32 ping_rssi_ratr; //cosa add for test | |
772 | u32 ping_rssi_thresh_for_ra;//cosa add for test | |
773 | u32 last_ratr; | |
774 | ||
775 | } rate_adaptive, *prate_adaptive; | |
776 | ||
777 | #define TxBBGainTableLength 37 | |
778 | #define CCKTxBBGainTableLength 23 | |
779 | ||
780 | typedef struct _txbbgain_struct | |
781 | { | |
782 | long txbb_iq_amplifygain; | |
783 | u32 txbbgain_value; | |
784 | } txbbgain_struct, *ptxbbgain_struct; | |
785 | ||
786 | typedef struct _ccktxbbgain_struct | |
787 | { | |
788 | //The Value is from a22 to a29 one Byte one time is much Safer | |
789 | u8 ccktxbb_valuearray[8]; | |
790 | } ccktxbbgain_struct,*pccktxbbgain_struct; | |
791 | ||
792 | ||
793 | typedef struct _init_gain | |
794 | { | |
795 | u8 xaagccore1; | |
796 | u8 xbagccore1; | |
797 | u8 xcagccore1; | |
798 | u8 xdagccore1; | |
799 | u8 cca; | |
800 | ||
801 | } init_gain, *pinit_gain; | |
802 | //by amy 0606 | |
803 | ||
804 | typedef struct _phy_ofdm_rx_status_report_819xusb | |
805 | { | |
806 | u8 trsw_gain_X[4]; | |
807 | u8 pwdb_all; | |
808 | u8 cfosho_X[4]; | |
809 | u8 cfotail_X[4]; | |
810 | u8 rxevm_X[2]; | |
811 | u8 rxsnr_X[4]; | |
812 | u8 pdsnr_X[2]; | |
813 | u8 csi_current_X[2]; | |
814 | u8 csi_target_X[2]; | |
815 | u8 sigevm; | |
816 | u8 max_ex_pwr; | |
817 | u8 sgi_en; | |
818 | u8 rxsc_sgien_exflg; | |
819 | }phy_sts_ofdm_819xusb_t; | |
820 | ||
821 | typedef struct _phy_cck_rx_status_report_819xusb | |
822 | { | |
823 | /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend | |
824 | 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */ | |
825 | u8 adc_pwdb_X[4]; | |
826 | u8 sq_rpt; | |
827 | u8 cck_agc_rpt; | |
828 | }phy_sts_cck_819xusb_t; | |
829 | ||
830 | ||
831 | typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{ | |
832 | u8 reserved:4; | |
833 | u8 rxsc:2; | |
834 | u8 sgi_en:1; | |
835 | u8 ex_intf_flag:1; | |
836 | }phy_ofdm_rx_status_rxsc_sgien_exintfflag; | |
837 | ||
838 | typedef enum _RT_CUSTOMER_ID | |
839 | { | |
840 | RT_CID_DEFAULT = 0, | |
841 | RT_CID_8187_ALPHA0 = 1, | |
842 | RT_CID_8187_SERCOMM_PS = 2, | |
843 | RT_CID_8187_HW_LED = 3, | |
844 | RT_CID_8187_NETGEAR = 4, | |
845 | RT_CID_WHQL = 5, | |
846 | RT_CID_819x_CAMEO = 6, | |
847 | RT_CID_819x_RUNTOP = 7, | |
848 | RT_CID_819x_Senao = 8, | |
849 | RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. | |
850 | RT_CID_819x_Netcore = 10, | |
851 | RT_CID_Nettronix = 11, | |
852 | RT_CID_DLINK = 12, | |
853 | RT_CID_PRONET = 13, | |
854 | }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; | |
855 | ||
856 | //================================================================================ | |
857 | // LED customization. | |
858 | //================================================================================ | |
859 | ||
860 | typedef enum _LED_STRATEGY_8190{ | |
861 | SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. | |
862 | SW_LED_MODE1, // SW control for PCI Express | |
863 | SW_LED_MODE2, // SW control for Cameo. | |
864 | SW_LED_MODE3, // SW contorl for RunTop. | |
865 | SW_LED_MODE4, // SW control for Netcore | |
866 | HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) | |
867 | }LED_STRATEGY_8190, *PLED_STRATEGY_8190; | |
868 | ||
869 | typedef enum _RESET_TYPE { | |
870 | RESET_TYPE_NORESET = 0x00, | |
871 | RESET_TYPE_NORMAL = 0x01, | |
872 | RESET_TYPE_SILENT = 0x02 | |
873 | } RESET_TYPE; | |
874 | ||
875 | /* The simple tx command OP code. */ | |
876 | typedef enum _tag_TxCmd_Config_Index{ | |
877 | TXCMD_TXRA_HISTORY_CTRL = 0xFF900000, | |
878 | TXCMD_RESET_TX_PKT_BUFF = 0xFF900001, | |
879 | TXCMD_RESET_RX_PKT_BUFF = 0xFF900002, | |
880 | TXCMD_SET_TX_DURATION = 0xFF900003, | |
881 | TXCMD_SET_RX_RSSI = 0xFF900004, | |
882 | TXCMD_SET_TX_PWR_TRACKING = 0xFF900005, | |
883 | TXCMD_XXXX_CTRL, | |
884 | }DCMD_TXCMD_OP; | |
885 | ||
886 | typedef struct r8192_priv | |
887 | { | |
888 | struct usb_device *udev; | |
889 | //added for maintain info from eeprom | |
890 | short epromtype; | |
891 | u16 eeprom_vid; | |
892 | u16 eeprom_pid; | |
893 | u8 eeprom_CustomerID; | |
894 | u8 eeprom_ChannelPlan; | |
895 | RT_CUSTOMER_ID CustomerID; | |
896 | LED_STRATEGY_8190 LedStrategy; | |
897 | u8 txqueue_to_outpipemap[9]; | |
898 | int irq; | |
899 | struct ieee80211_device *ieee80211; | |
900 | ||
901 | short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */ | |
902 | u8 card_8192_version; /* if TCR reports card V B/C this discriminates */ | |
903 | // short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */ | |
904 | short enable_gpio0; | |
905 | enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type; | |
906 | short hw_plcp_len; | |
907 | short plcp_preamble_mode; | |
908 | ||
909 | spinlock_t irq_lock; | |
910 | // spinlock_t irq_th_lock; | |
911 | spinlock_t tx_lock; | |
8fc8598e | 912 | struct mutex mutex; |
8fc8598e JC |
913 | //spinlock_t rf_lock; //used to lock rf write operation added by wb |
914 | ||
915 | u16 irq_mask; | |
916 | // short irq_enabled; | |
917 | // struct net_device *dev; //comment this out. | |
918 | short chan; | |
919 | short sens; | |
920 | short max_sens; | |
921 | ||
922 | ||
923 | // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used | |
924 | // u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used | |
925 | // u8 cck_txpwr_base; | |
926 | // u8 ofdm_txpwr_base; | |
927 | // u8 challow[15]; //channels from 1 to 14, 0 not used | |
928 | short up; | |
929 | short crcmon; //if 1 allow bad crc frame reception in monitor mode | |
930 | // short prism_hdr; | |
931 | ||
932 | // struct timer_list scan_timer; | |
933 | /*short scanpending; | |
934 | short stopscan;*/ | |
935 | // spinlock_t scan_lock; | |
936 | // u8 active_probe; | |
937 | //u8 active_scan_num; | |
938 | struct semaphore wx_sem; | |
939 | struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david | |
940 | // short hw_wep; | |
941 | ||
942 | // short digphy; | |
943 | // short antb; | |
944 | // short diversity; | |
945 | // u8 cs_treshold; | |
946 | // short rcr_csense; | |
947 | u8 rf_type; //0 means 1T2R, 1 means 2T4R | |
948 | RT_RF_TYPE_819xU rf_chip; | |
949 | ||
950 | // u32 key0[4]; | |
951 | short (*rf_set_sens)(struct net_device *dev,short sens); | |
952 | u8 (*rf_set_chan)(struct net_device *dev,u8 ch); | |
953 | void (*rf_close)(struct net_device *dev); | |
954 | void (*rf_init)(struct net_device *dev); | |
955 | //short rate; | |
956 | short promisc; | |
957 | /*stats*/ | |
958 | struct Stats stats; | |
959 | struct iw_statistics wstats; | |
960 | struct proc_dir_entry *dir_dev; | |
961 | ||
962 | /*RX stuff*/ | |
963 | // u32 *rxring; | |
964 | // u32 *rxringtail; | |
965 | // dma_addr_t rxringdma; | |
966 | struct urb **rx_urb; | |
967 | struct urb **rx_cmd_urb; | |
968 | #ifdef THOMAS_BEACON | |
969 | u32 *oldaddr; | |
970 | #endif | |
971 | #ifdef THOMAS_TASKLET | |
972 | atomic_t irt_counter;//count for irq_rx_tasklet | |
973 | #endif | |
974 | #ifdef JACKSON_NEW_RX | |
975 | struct sk_buff **pp_rxskb; | |
976 | int rx_inx; | |
977 | #endif | |
978 | ||
979 | /* modified by davad for Rx process */ | |
980 | struct sk_buff_head rx_queue; | |
981 | struct sk_buff_head skb_queue; | |
8fc8598e | 982 | struct work_struct qos_activate; |
8fc8598e JC |
983 | short tx_urb_index; |
984 | atomic_t tx_pending[0x10];//UART_PRIORITY+1 | |
985 | ||
986 | ||
987 | struct tasklet_struct irq_rx_tasklet; | |
988 | struct urb *rxurb_task; | |
989 | ||
990 | //2 Tx Related variables | |
991 | u16 ShortRetryLimit; | |
992 | u16 LongRetryLimit; | |
993 | u32 TransmitConfig; | |
994 | u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27. | |
995 | ||
996 | u32 LastRxDescTSFHigh; | |
997 | u32 LastRxDescTSFLow; | |
998 | ||
999 | ||
1000 | //2 Rx Related variables | |
1001 | u16 EarlyRxThreshold; | |
1002 | u32 ReceiveConfig; | |
1003 | u8 AcmControl; | |
1004 | ||
1005 | u8 RFProgType; | |
1006 | ||
1007 | u8 retry_data; | |
1008 | u8 retry_rts; | |
1009 | u16 rts; | |
1010 | ||
1011 | struct ChnlAccessSetting ChannelAccessSetting; | |
8fc8598e | 1012 | struct work_struct reset_wq; |
8fc8598e JC |
1013 | |
1014 | /**********************************************************/ | |
1015 | //for rtl819xUsb | |
1016 | u16 basic_rate; | |
1017 | u8 short_preamble; | |
1018 | u8 slot_time; | |
1019 | bool bDcut; | |
1020 | bool bCurrentRxAggrEnable; | |
1021 | u8 Rf_Mode; //add for Firmware RF -R/W switch | |
1022 | prt_firmware pFirmware; | |
1023 | rtl819xUsb_loopback_e LoopbackMode; | |
8fc8598e JC |
1024 | u16 EEPROMTxPowerDiff; |
1025 | u8 EEPROMThermalMeter; | |
1026 | u8 EEPROMPwDiff; | |
1027 | u8 EEPROMCrystalCap; | |
1028 | u8 EEPROM_Def_Ver; | |
1029 | u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14 | |
1030 | u8 EEPROMTxPowerLevelCCK_V1[3]; | |
1031 | u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14 | |
1032 | u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G | |
1033 | ||
1034 | /*PHY related*/ | |
1035 | BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D | |
1036 | // Read/write are allow for following hardware information variables | |
1037 | u32 MCSTxPowerLevelOriginalOffset[6]; | |
1038 | u32 CCKTxPowerLevelOriginalOffset; | |
1039 | u8 TxPowerLevelCCK[14]; // CCK channel 1~14 | |
1040 | u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14 | |
1041 | u8 TxPowerLevelOFDM5G[14]; // OFDM 5G | |
1042 | u32 Pwr_Track; | |
1043 | u8 TxPowerDiff; | |
1044 | u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D | |
1045 | u8 CrystalCap; // CrystalCap. | |
1046 | u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 | |
1047 | ||
1048 | u8 CckPwEnl; | |
1049 | // Use to calculate PWBD. | |
1050 | u8 bCckHighPower; | |
1051 | long undecorated_smoothed_pwdb; | |
1052 | ||
1053 | //for set channel | |
1054 | u8 SwChnlInProgress; | |
1055 | u8 SwChnlStage; | |
1056 | u8 SwChnlStep; | |
1057 | u8 SetBWModeInProgress; | |
1058 | HT_CHANNEL_WIDTH CurrentChannelBW; | |
1059 | u8 ChannelPlan; | |
1060 | // 8190 40MHz mode | |
1061 | // | |
1062 | u8 nCur40MhzPrimeSC; // Control channel sub-carrier | |
1063 | // Joseph test for shorten RF configuration time. | |
1064 | // We save RF reg0 in this variable to reduce RF reading. | |
1065 | // | |
1066 | u32 RfReg0Value[4]; | |
1067 | u8 NumTotalRFPath; | |
1068 | bool brfpath_rxenable[4]; | |
1069 | //RF set related | |
1070 | bool SetRFPowerStateInProgress; | |
1071 | //+by amy 080507 | |
1072 | struct timer_list watch_dog_timer; | |
1073 | ||
1074 | //+by amy 080515 for dynamic mechenism | |
1075 | //Add by amy Tx Power Control for Near/Far Range 2008/05/15 | |
1076 | bool bdynamic_txpower; //bDynamicTxPower | |
1077 | bool bDynamicTxHighPower; // Tx high power state | |
1078 | bool bDynamicTxLowPower; // Tx low power state | |
1079 | bool bLastDTPFlag_High; | |
1080 | bool bLastDTPFlag_Low; | |
1081 | ||
1082 | bool bstore_last_dtpflag; | |
1083 | bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index | |
1084 | //Add by amy for Rate Adaptive | |
1085 | rate_adaptive rate_adaptive; | |
1086 | //Add by amy for TX power tracking | |
1087 | //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING | |
1088 | txbbgain_struct txbbgain_table[TxBBGainTableLength]; | |
1089 | u8 txpower_count;//For 6 sec do tracking again | |
1090 | bool btxpower_trackingInit; | |
1091 | u8 OFDM_index; | |
1092 | u8 CCK_index; | |
1093 | //2007/09/10 Mars Add CCK TX Power Tracking | |
1094 | ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength]; | |
1095 | ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength]; | |
1096 | u8 rfa_txpowertrackingindex; | |
1097 | u8 rfa_txpowertrackingindex_real; | |
1098 | u8 rfa_txpowertracking_default; | |
1099 | u8 rfc_txpowertrackingindex; | |
1100 | u8 rfc_txpowertrackingindex_real; | |
1101 | ||
1102 | s8 cck_present_attentuation; | |
1103 | u8 cck_present_attentuation_20Mdefault; | |
1104 | u8 cck_present_attentuation_40Mdefault; | |
1105 | char cck_present_attentuation_difference; | |
1106 | bool btxpower_tracking; | |
1107 | bool bcck_in_ch14; | |
1108 | bool btxpowerdata_readfromEEPORM; | |
1109 | u16 TSSI_13dBm; | |
1110 | //For Backup Initial Gain | |
1111 | init_gain initgain_backup; | |
1112 | u8 DefaultInitialGain[4]; | |
1113 | // For EDCA Turbo mode, Added by amy 080515. | |
1114 | bool bis_any_nonbepkts; | |
1115 | bool bcurrent_turbo_EDCA; | |
1116 | bool bis_cur_rdlstate; | |
1117 | struct timer_list fsync_timer; | |
1118 | bool bfsync_processing; // 500ms Fsync timer is active or not | |
1119 | u32 rate_record; | |
1120 | u32 rateCountDiffRecord; | |
1121 | u32 ContiuneDiffCount; | |
1122 | bool bswitch_fsync; | |
1123 | ||
1124 | u8 framesync; | |
1125 | u32 framesyncC34; | |
1126 | u8 framesyncMonitor; | |
1127 | //Added by amy 080516 for RX related | |
1128 | u16 nrxAMPDU_size; | |
1129 | u8 nrxAMPDU_aggr_num; | |
1130 | ||
1131 | //by amy for gpio | |
1132 | bool bHwRadioOff; | |
1133 | ||
1134 | //by amy for reset_count | |
1135 | u32 reset_count; | |
1136 | bool bpbc_pressed; | |
1137 | //by amy for debug | |
1138 | u32 txpower_checkcnt; | |
1139 | u32 txpower_tracking_callback_cnt; | |
1140 | u8 thermal_read_val[40]; | |
1141 | u8 thermal_readback_index; | |
1142 | u32 ccktxpower_adjustcnt_not_ch14; | |
1143 | u32 ccktxpower_adjustcnt_ch14; | |
1144 | u8 tx_fwinfo_force_subcarriermode; | |
1145 | u8 tx_fwinfo_force_subcarrierval; | |
1146 | //by amy for silent reset | |
1147 | RESET_TYPE ResetProgress; | |
1148 | bool bForcedSilentReset; | |
1149 | bool bDisableNormalResetCheck; | |
1150 | u16 TxCounter; | |
1151 | u16 RxCounter; | |
1152 | int IrpPendingCount; | |
1153 | bool bResetInProgress; | |
1154 | bool force_reset; | |
1155 | u8 InitialGainOperateType; | |
1156 | ||
1157 | u16 SifsTime; | |
1158 | ||
1159 | //define work item by amy 080526 | |
8fc8598e | 1160 | |
8fc8598e JC |
1161 | struct delayed_work update_beacon_wq; |
1162 | struct delayed_work watch_dog_wq; | |
1163 | struct delayed_work txpower_tracking_wq; | |
1164 | struct delayed_work rfpath_check_wq; | |
1165 | struct delayed_work gpio_change_rf_wq; | |
1166 | struct delayed_work initialgain_operate_wq; | |
8fc8598e | 1167 | struct workqueue_struct *priv_wq; |
8fc8598e JC |
1168 | }r8192_priv; |
1169 | ||
1170 | // for rtl8187 | |
1171 | // now mirging to rtl8187B | |
1172 | /* | |
1173 | typedef enum{ | |
1174 | LOW_PRIORITY = 0x02, | |
1175 | NORM_PRIORITY | |
1176 | } priority_t; | |
1177 | */ | |
1178 | //for rtl8187B | |
1179 | typedef enum{ | |
1180 | BULK_PRIORITY = 0x01, | |
1181 | //RSVD0, | |
1182 | //RSVD1, | |
1183 | LOW_PRIORITY, | |
1184 | NORM_PRIORITY, | |
1185 | VO_PRIORITY, | |
1186 | VI_PRIORITY, //0x05 | |
1187 | BE_PRIORITY, | |
1188 | BK_PRIORITY, | |
1189 | RSVD2, | |
1190 | RSVD3, | |
1191 | BEACON_PRIORITY, //0x0A | |
1192 | HIGH_PRIORITY, | |
1193 | MANAGE_PRIORITY, | |
1194 | RSVD4, | |
1195 | RSVD5, | |
1196 | UART_PRIORITY //0x0F | |
1197 | } priority_t; | |
1198 | ||
1199 | typedef enum{ | |
1200 | NIC_8192U = 1, | |
1201 | NIC_8190P = 2, | |
1202 | NIC_8192E = 3, | |
1203 | } nic_t; | |
1204 | ||
1205 | ||
8fc8598e JC |
1206 | #ifdef JOHN_HWSEC |
1207 | struct ssid_thread { | |
1208 | struct net_device *dev; | |
1209 | u8 name[IW_ESSID_MAX_SIZE + 1]; | |
1210 | }; | |
1211 | #endif | |
1212 | ||
1213 | bool init_firmware(struct net_device *dev); | |
1214 | short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb); | |
1215 | short rtl8192_tx(struct net_device *dev, struct sk_buff* skb); | |
1216 | ||
1217 | u32 read_cam(struct net_device *dev, u8 addr); | |
1218 | void write_cam(struct net_device *dev, u8 addr, u32 data); | |
1219 | ||
1220 | u8 read_nic_byte(struct net_device *dev, int x); | |
1221 | u8 read_nic_byte_E(struct net_device *dev, int x); | |
1222 | u32 read_nic_dword(struct net_device *dev, int x); | |
1223 | u16 read_nic_word(struct net_device *dev, int x) ; | |
1224 | void write_nic_byte(struct net_device *dev, int x,u8 y); | |
1225 | void write_nic_byte_E(struct net_device *dev, int x,u8 y); | |
1226 | void write_nic_word(struct net_device *dev, int x,u16 y); | |
1227 | void write_nic_dword(struct net_device *dev, int x,u32 y); | |
1228 | void force_pci_posting(struct net_device *dev); | |
1229 | ||
1230 | void rtl8192_rtx_disable(struct net_device *); | |
1231 | void rtl8192_rx_enable(struct net_device *); | |
1232 | void rtl8192_tx_enable(struct net_device *); | |
1233 | ||
1234 | void rtl8192_disassociate(struct net_device *dev); | |
1235 | //void fix_rx_fifo(struct net_device *dev); | |
1236 | void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a); | |
1237 | ||
1238 | void rtl8192_set_anaparam(struct net_device *dev,u32 a); | |
1239 | void rtl8185_set_anaparam2(struct net_device *dev,u32 a); | |
1240 | void rtl8192_update_msr(struct net_device *dev); | |
1241 | int rtl8192_down(struct net_device *dev); | |
1242 | int rtl8192_up(struct net_device *dev); | |
1243 | void rtl8192_commit(struct net_device *dev); | |
1244 | void rtl8192_set_chan(struct net_device *dev,short ch); | |
1245 | void write_phy(struct net_device *dev, u8 adr, u8 data); | |
1246 | void write_phy_cck(struct net_device *dev, u8 adr, u32 data); | |
1247 | void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data); | |
1248 | void rtl8185_tx_antenna(struct net_device *dev, u8 ant); | |
1249 | void rtl8192_set_rxconf(struct net_device *dev); | |
1250 | //short check_nic_enough_desc(struct net_device *dev, priority_t priority); | |
1251 | extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate); | |
1252 | ||
1253 | void EnableHWSecurityConfig8192(struct net_device *dev); | |
1254 | void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent ); | |
1255 | ||
1256 | ||
1257 | #endif |