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8fc8598e JC |
1 | #include "r8192U.h" |
2 | #include "r8192U_hw.h" | |
3 | #include "r819xU_phy.h" | |
4 | #include "r819xU_phyreg.h" | |
5 | #include "r8190_rtl8256.h" | |
6 | #include "r8192U_dm.h" | |
7 | #include "r819xU_firmware_img.h" | |
8 | ||
8fc8598e | 9 | #include "dot11d.h" |
391c72a3 XR |
10 | #include <linux/bitops.h> |
11 | ||
8fc8598e JC |
12 | static u32 RF_CHANNEL_TABLE_ZEBRA[] = { |
13 | 0, | |
5f2392b8 XR |
14 | 0x085c, /* 2412 1 */ |
15 | 0x08dc, /* 2417 2 */ | |
16 | 0x095c, /* 2422 3 */ | |
17 | 0x09dc, /* 2427 4 */ | |
18 | 0x0a5c, /* 2432 5 */ | |
19 | 0x0adc, /* 2437 6 */ | |
20 | 0x0b5c, /* 2442 7 */ | |
21 | 0x0bdc, /* 2447 8 */ | |
22 | 0x0c5c, /* 2452 9 */ | |
23 | 0x0cdc, /* 2457 10 */ | |
24 | 0x0d5c, /* 2462 11 */ | |
25 | 0x0ddc, /* 2467 12 */ | |
26 | 0x0e5c, /* 2472 13 */ | |
27 | 0x0f72, /* 2484 */ | |
8fc8598e JC |
28 | }; |
29 | ||
30 | ||
31 | #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray | |
32 | #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG | |
33 | #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array | |
34 | #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array | |
35 | #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array | |
36 | #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array | |
37 | #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array | |
38 | #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array | |
39 | ||
8fc8598e | 40 | /****************************************************************************** |
5f2392b8 XR |
41 | * function: This function checks different RF type to execute legal judgement. |
42 | * If RF Path is illegal, we will return false. | |
43 | * input: net_device *dev | |
44 | * u32 eRFPath | |
45 | * output: none | |
46 | * return: 0(illegal, false), 1(legal, true) | |
47 | *****************************************************************************/ | |
88d8fe29 | 48 | u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) |
8fc8598e JC |
49 | { |
50 | u8 ret = 1; | |
51 | struct r8192_priv *priv = ieee80211_priv(dev); | |
0081fcc6 | 52 | |
4a6094c3 | 53 | if (priv->rf_type == RF_2T4R) { |
8fc8598e | 54 | ret = 0; |
4a6094c3 | 55 | } else if (priv->rf_type == RF_1T2R) { |
8fc8598e JC |
56 | if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) |
57 | ret = 1; | |
58 | else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) | |
59 | ret = 0; | |
60 | } | |
61 | return ret; | |
62 | } | |
0081fcc6 | 63 | |
8fc8598e | 64 | /****************************************************************************** |
5f2392b8 XR |
65 | * function: This function sets specific bits to BB register |
66 | * input: net_device *dev | |
67 | * u32 reg_addr //target addr to be modified | |
68 | * u32 bitmask //taget bit pos to be modified | |
69 | * u32 data //value to be write | |
70 | * output: none | |
71 | * return: none | |
72 | * notice: | |
73 | ******************************************************************************/ | |
79931639 XR |
74 | void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask, |
75 | u32 data) | |
8fc8598e JC |
76 | { |
77 | ||
79931639 | 78 | u32 reg, bitshift; |
8fc8598e | 79 | |
5f2392b8 | 80 | if (bitmask != bMaskDWord) { |
79931639 | 81 | read_nic_dword(dev, reg_addr, ®); |
d2071984 | 82 | bitshift = ffs(bitmask) - 1; |
9f66ddb5 | 83 | reg &= ~bitmask; |
79931639 XR |
84 | reg |= data << bitshift; |
85 | write_nic_dword(dev, reg_addr, reg); | |
4a6094c3 | 86 | } else { |
79931639 | 87 | write_nic_dword(dev, reg_addr, data); |
4a6094c3 | 88 | } |
8fc8598e | 89 | } |
0081fcc6 | 90 | |
8fc8598e | 91 | /****************************************************************************** |
5f2392b8 XR |
92 | * function: This function reads specific bits from BB register |
93 | * input: net_device *dev | |
98bedd77 KS |
94 | * u32 reg_addr //target addr to be readback |
95 | * u32 bitmask //taget bit pos to be readback | |
5f2392b8 | 96 | * output: none |
98bedd77 | 97 | * return: u32 data //the readback register value |
5f2392b8 XR |
98 | * notice: |
99 | ******************************************************************************/ | |
79931639 | 100 | u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask) |
8fc8598e | 101 | { |
c4b5eb8c | 102 | u32 reg, bitshift; |
8fc8598e | 103 | |
79931639 | 104 | read_nic_dword(dev, reg_addr, ®); |
d2071984 | 105 | bitshift = ffs(bitmask) - 1; |
8fc8598e | 106 | |
c4b5eb8c | 107 | return (reg & bitmask) >> bitshift; |
8fc8598e | 108 | } |
0081fcc6 | 109 | |
442543d7 | 110 | static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
79931639 | 111 | u32 offset); |
8fc8598e | 112 | |
442543d7 | 113 | static void phy_FwRFSerialWrite(struct net_device *dev, |
79931639 XR |
114 | RF90_RADIO_PATH_E eRFPath, u32 offset, |
115 | u32 data); | |
8fc8598e JC |
116 | |
117 | /****************************************************************************** | |
5f2392b8 XR |
118 | * function: This function reads register from RF chip |
119 | * input: net_device *dev | |
120 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D | |
121 | * u32 offset //target address to be read | |
122 | * output: none | |
123 | * return: u32 readback value | |
124 | * notice: There are three types of serial operations: | |
125 | * (1) Software serial write. | |
126 | * (2)Hardware LSSI-Low Speed Serial Interface. | |
127 | * (3)Hardware HSSI-High speed serial write. | |
128 | * Driver here need to implement (1) and (2) | |
129 | * ---need more spec for this information. | |
130 | ******************************************************************************/ | |
c92f473d AR |
131 | static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, |
132 | RF90_RADIO_PATH_E eRFPath, u32 offset) | |
8fc8598e JC |
133 | { |
134 | struct r8192_priv *priv = ieee80211_priv(dev); | |
135 | u32 ret = 0; | |
79931639 | 136 | u32 new_offset = 0; |
88d8fe29 | 137 | BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; |
0081fcc6 | 138 | |
8fc8598e | 139 | rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); |
5f2392b8 | 140 | /* Make sure RF register offset is correct */ |
79931639 | 141 | offset &= 0x3f; |
8fc8598e | 142 | |
5f2392b8 | 143 | /* Switch page for 8256 RF IC */ |
4a6094c3 | 144 | if (priv->rf_chip == RF_8256) { |
79931639 | 145 | if (offset >= 31) { |
8fc8598e | 146 | priv->RfReg0Value[eRFPath] |= 0x140; |
5f2392b8 | 147 | /* Switch to Reg_Mode2 for Reg 31-45 */ |
1db5aa05 XR |
148 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
149 | bMaskDWord, | |
150 | priv->RfReg0Value[eRFPath]<<16); | |
5f2392b8 | 151 | /* Modify offset */ |
79931639 XR |
152 | new_offset = offset - 30; |
153 | } else if (offset >= 16) { | |
8fc8598e JC |
154 | priv->RfReg0Value[eRFPath] |= 0x100; |
155 | priv->RfReg0Value[eRFPath] &= (~0x40); | |
5f2392b8 | 156 | /* Switch to Reg_Mode1 for Reg16-30 */ |
1db5aa05 XR |
157 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
158 | bMaskDWord, | |
159 | priv->RfReg0Value[eRFPath]<<16); | |
8fc8598e | 160 | |
79931639 | 161 | new_offset = offset - 15; |
4a6094c3 | 162 | } else { |
79931639 | 163 | new_offset = offset; |
4a6094c3 XR |
164 | } |
165 | } else { | |
1db5aa05 XR |
166 | RT_TRACE((COMP_PHY|COMP_ERR), |
167 | "check RF type here, need to be 8256\n"); | |
79931639 | 168 | new_offset = offset; |
8fc8598e | 169 | } |
5f2392b8 | 170 | /* Put desired read addr to LSSI control Register */ |
1db5aa05 XR |
171 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, |
172 | new_offset); | |
5f2392b8 | 173 | /* Issue a posedge trigger */ |
8fc8598e JC |
174 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); |
175 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); | |
176 | ||
177 | ||
5f2392b8 | 178 | /* TODO: we should not delay such a long time. Ask for help from SD3 */ |
26f3561d | 179 | usleep_range(1000, 1000); |
8fc8598e | 180 | |
1db5aa05 XR |
181 | ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, |
182 | bLSSIReadBackData); | |
8fc8598e JC |
183 | |
184 | ||
5f2392b8 | 185 | /* Switch back to Reg_Mode0 */ |
1111b876 | 186 | if (priv->rf_chip == RF_8256) { |
8fc8598e JC |
187 | priv->RfReg0Value[eRFPath] &= 0xebf; |
188 | ||
1db5aa05 XR |
189 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, |
190 | priv->RfReg0Value[eRFPath] << 16); | |
8fc8598e JC |
191 | } |
192 | ||
193 | return ret; | |
8fc8598e JC |
194 | } |
195 | ||
196 | /****************************************************************************** | |
5f2392b8 XR |
197 | * function: This function writes data to RF register |
198 | * input: net_device *dev | |
199 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D | |
200 | * u32 offset //target address to be written | |
201 | * u32 data //the new register data to be written | |
202 | * output: none | |
203 | * return: none | |
204 | * notice: For RF8256 only. | |
205 | * =========================================================================== | |
206 | * Reg Mode RegCTL[1] RegCTL[0] Note | |
8fc8598e | 207 | * (Reg00[12]) (Reg00[10]) |
5f2392b8 XR |
208 | * =========================================================================== |
209 | * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf) | |
210 | * --------------------------------------------------------------------------- | |
211 | * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf) | |
212 | * --------------------------------------------------------------------------- | |
8fc8598e | 213 | * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) |
5f2392b8 XR |
214 | * --------------------------------------------------------------------------- |
215 | *****************************************************************************/ | |
c92f473d AR |
216 | static void rtl8192_phy_RFSerialWrite(struct net_device *dev, |
217 | RF90_RADIO_PATH_E eRFPath, u32 offset, | |
218 | u32 data) | |
8fc8598e JC |
219 | { |
220 | struct r8192_priv *priv = ieee80211_priv(dev); | |
79931639 | 221 | u32 DataAndAddr = 0, new_offset = 0; |
8fc8598e JC |
222 | BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; |
223 | ||
79931639 | 224 | offset &= 0x3f; |
4a6094c3 | 225 | if (priv->rf_chip == RF_8256) { |
8fc8598e | 226 | |
79931639 | 227 | if (offset >= 31) { |
8fc8598e | 228 | priv->RfReg0Value[eRFPath] |= 0x140; |
1db5aa05 XR |
229 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
230 | bMaskDWord, | |
231 | priv->RfReg0Value[eRFPath] << 16); | |
79931639 XR |
232 | new_offset = offset - 30; |
233 | } else if (offset >= 16) { | |
8fc8598e JC |
234 | priv->RfReg0Value[eRFPath] |= 0x100; |
235 | priv->RfReg0Value[eRFPath] &= (~0x40); | |
1db5aa05 XR |
236 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
237 | bMaskDWord, | |
238 | priv->RfReg0Value[eRFPath]<<16); | |
79931639 | 239 | new_offset = offset - 15; |
4a6094c3 | 240 | } else { |
79931639 | 241 | new_offset = offset; |
4a6094c3 XR |
242 | } |
243 | } else { | |
1db5aa05 XR |
244 | RT_TRACE((COMP_PHY|COMP_ERR), |
245 | "check RF type here, need to be 8256\n"); | |
79931639 | 246 | new_offset = offset; |
8fc8598e JC |
247 | } |
248 | ||
5f2392b8 | 249 | /* Put write addr in [5:0] and write data in [31:16] */ |
79931639 | 250 | DataAndAddr = (data<<16) | (new_offset&0x3f); |
8fc8598e | 251 | |
5f2392b8 | 252 | /* Write operation */ |
8fc8598e JC |
253 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); |
254 | ||
255 | ||
79931639 XR |
256 | if (offset == 0x0) |
257 | priv->RfReg0Value[eRFPath] = data; | |
8fc8598e | 258 | |
5f2392b8 | 259 | /* Switch back to Reg_Mode0 */ |
1111b876 | 260 | if (priv->rf_chip == RF_8256) { |
79931639 | 261 | if (offset != 0) { |
8fc8598e | 262 | priv->RfReg0Value[eRFPath] &= 0xebf; |
1db5aa05 XR |
263 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
264 | bMaskDWord, | |
265 | priv->RfReg0Value[eRFPath] << 16); | |
8fc8598e JC |
266 | } |
267 | } | |
8fc8598e JC |
268 | } |
269 | ||
270 | /****************************************************************************** | |
5f2392b8 XR |
271 | * function: This function set specific bits to RF register |
272 | * input: net_device dev | |
273 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D | |
274 | * u32 reg_addr //target addr to be modified | |
275 | * u32 bitmask //taget bit pos to be modified | |
276 | * u32 data //value to be written | |
277 | * output: none | |
278 | * return: none | |
279 | * notice: | |
280 | *****************************************************************************/ | |
442543d7 | 281 | void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
79931639 | 282 | u32 reg_addr, u32 bitmask, u32 data) |
8fc8598e JC |
283 | { |
284 | struct r8192_priv *priv = ieee80211_priv(dev); | |
79931639 | 285 | u32 reg, bitshift; |
8fc8598e JC |
286 | |
287 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | |
288 | return; | |
289 | ||
4a6094c3 | 290 | if (priv->Rf_Mode == RF_OP_By_FW) { |
5f2392b8 XR |
291 | if (bitmask != bMask12Bits) { |
292 | /* RF data is 12 bits only */ | |
79931639 | 293 | reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr); |
d2071984 | 294 | bitshift = ffs(bitmask) - 1; |
9f66ddb5 | 295 | reg &= ~bitmask; |
79931639 | 296 | reg |= data << bitshift; |
8fc8598e | 297 | |
79931639 | 298 | phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg); |
4a6094c3 | 299 | } else { |
79931639 | 300 | phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data); |
4a6094c3 | 301 | } |
8fc8598e JC |
302 | |
303 | udelay(200); | |
304 | ||
4a6094c3 | 305 | } else { |
5f2392b8 XR |
306 | if (bitmask != bMask12Bits) { |
307 | /* RF data is 12 bits only */ | |
79931639 | 308 | reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr); |
d2071984 | 309 | bitshift = ffs(bitmask) - 1; |
9f66ddb5 | 310 | reg &= ~bitmask; |
79931639 | 311 | reg |= data << bitshift; |
8fc8598e | 312 | |
79931639 | 313 | rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg); |
4a6094c3 | 314 | } else { |
79931639 | 315 | rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data); |
4a6094c3 | 316 | } |
8fc8598e | 317 | } |
8fc8598e JC |
318 | } |
319 | ||
320 | /****************************************************************************** | |
5f2392b8 XR |
321 | * function: This function reads specific bits from RF register |
322 | * input: net_device *dev | |
323 | * u32 reg_addr //target addr to be readback | |
324 | * u32 bitmask //taget bit pos to be readback | |
325 | * output: none | |
326 | * return: u32 data //the readback register value | |
327 | * notice: | |
328 | *****************************************************************************/ | |
442543d7 | 329 | u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
79931639 | 330 | u32 reg_addr, u32 bitmask) |
8fc8598e | 331 | { |
79931639 | 332 | u32 reg, bitshift; |
8fc8598e JC |
333 | struct r8192_priv *priv = ieee80211_priv(dev); |
334 | ||
335 | ||
336 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | |
337 | return 0; | |
4a6094c3 | 338 | if (priv->Rf_Mode == RF_OP_By_FW) { |
79931639 | 339 | reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr); |
8fc8598e | 340 | udelay(200); |
4a6094c3 | 341 | } else { |
79931639 | 342 | reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr); |
8fc8598e | 343 | } |
d2071984 | 344 | bitshift = ffs(bitmask) - 1; |
d0049dfc KS |
345 | reg = (reg & bitmask) >> bitshift; |
346 | return reg; | |
347 | ||
8fc8598e | 348 | } |
0081fcc6 | 349 | |
8fc8598e | 350 | /****************************************************************************** |
5f2392b8 XR |
351 | * function: We support firmware to execute RF-R/W. |
352 | * input: net_device *dev | |
353 | * RF90_RADIO_PATH_E eRFPath | |
354 | * u32 offset | |
355 | * output: none | |
356 | * return: u32 | |
357 | * notice: | |
358 | ****************************************************************************/ | |
442543d7 | 359 | static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
79931639 | 360 | u32 offset) |
8fc8598e | 361 | { |
07ecbbf1 | 362 | u32 reg = 0; |
79931639 | 363 | u32 data = 0; |
8fc8598e | 364 | u8 time = 0; |
b3d42bf1 | 365 | u32 tmp; |
0081fcc6 | 366 | |
5f2392b8 XR |
367 | /* Firmware RF Write control. |
368 | * We can not execute the scheme in the initial step. | |
369 | * Otherwise, RF-R/W will waste much time. | |
370 | * This is only for site survey. */ | |
371 | /* 1. Read operation need not insert data. bit 0-11 */ | |
372 | /* 2. Write RF register address. bit 12-19 */ | |
79931639 | 373 | data |= ((offset&0xFF)<<12); |
5f2392b8 | 374 | /* 3. Write RF path. bit 20-21 */ |
79931639 | 375 | data |= ((eRFPath&0x3)<<20); |
5f2392b8 XR |
376 | /* 4. Set RF read indicator. bit 22=0 */ |
377 | /* 5. Trigger Fw to operate the command. bit 31 */ | |
79931639 | 378 | data |= 0x80000000; |
5f2392b8 | 379 | /* 6. We can not execute read operation if bit 31 is 1. */ |
b3d42bf1 | 380 | read_nic_dword(dev, QPNR, &tmp); |
4a6094c3 | 381 | while (tmp & 0x80000000) { |
5f2392b8 XR |
382 | /* If FW can not finish RF-R/W for more than ?? times. |
383 | We must reset FW. */ | |
4a6094c3 | 384 | if (time++ < 100) { |
8fc8598e | 385 | udelay(10); |
b3d42bf1 | 386 | read_nic_dword(dev, QPNR, &tmp); |
4a6094c3 | 387 | } else { |
8fc8598e | 388 | break; |
4a6094c3 | 389 | } |
8fc8598e | 390 | } |
5f2392b8 | 391 | /* 7. Execute read operation. */ |
79931639 | 392 | write_nic_dword(dev, QPNR, data); |
5f2392b8 | 393 | /* 8. Check if firmware send back RF content. */ |
b3d42bf1 | 394 | read_nic_dword(dev, QPNR, &tmp); |
4a6094c3 | 395 | while (tmp & 0x80000000) { |
5f2392b8 XR |
396 | /* If FW can not finish RF-R/W for more than ?? times. |
397 | We must reset FW. */ | |
4a6094c3 | 398 | if (time++ < 100) { |
8fc8598e | 399 | udelay(10); |
b3d42bf1 | 400 | read_nic_dword(dev, QPNR, &tmp); |
4a6094c3 | 401 | } else { |
4c8dd926 | 402 | return 0; |
4a6094c3 | 403 | } |
8fc8598e | 404 | } |
07ecbbf1 | 405 | read_nic_dword(dev, RF_DATA, ®); |
8fc8598e | 406 | |
07ecbbf1 | 407 | return reg; |
5f2392b8 | 408 | } |
8fc8598e JC |
409 | |
410 | /****************************************************************************** | |
5f2392b8 XR |
411 | * function: We support firmware to execute RF-R/W. |
412 | * input: net_device *dev | |
413 | * RF90_RADIO_PATH_E eRFPath | |
414 | * u32 offset | |
415 | * u32 data | |
416 | * output: none | |
417 | * return: none | |
418 | * notice: | |
419 | ****************************************************************************/ | |
442543d7 | 420 | static void phy_FwRFSerialWrite(struct net_device *dev, |
79931639 | 421 | RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data) |
8fc8598e JC |
422 | { |
423 | u8 time = 0; | |
b3d42bf1 | 424 | u32 tmp; |
8fc8598e | 425 | |
5f2392b8 XR |
426 | /* Firmware RF Write control. |
427 | * We can not execute the scheme in the initial step. | |
428 | * Otherwise, RF-R/W will waste much time. | |
429 | * This is only for site survey. */ | |
8fc8598e | 430 | |
5f2392b8 XR |
431 | /* 1. Set driver write bit and 12 bit data. bit 0-11 */ |
432 | /* 2. Write RF register address. bit 12-19 */ | |
79931639 | 433 | data |= ((offset&0xFF)<<12); |
5f2392b8 | 434 | /* 3. Write RF path. bit 20-21 */ |
79931639 | 435 | data |= ((eRFPath&0x3)<<20); |
5f2392b8 | 436 | /* 4. Set RF write indicator. bit 22=1 */ |
79931639 | 437 | data |= 0x400000; |
5f2392b8 | 438 | /* 5. Trigger Fw to operate the command. bit 31=1 */ |
79931639 | 439 | data |= 0x80000000; |
8fc8598e | 440 | |
5f2392b8 | 441 | /* 6. Write operation. We can not write if bit 31 is 1. */ |
b3d42bf1 | 442 | read_nic_dword(dev, QPNR, &tmp); |
4a6094c3 | 443 | while (tmp & 0x80000000) { |
5f2392b8 XR |
444 | /* If FW can not finish RF-R/W for more than ?? times. |
445 | We must reset FW. */ | |
4a6094c3 | 446 | if (time++ < 100) { |
8fc8598e | 447 | udelay(10); |
b3d42bf1 | 448 | read_nic_dword(dev, QPNR, &tmp); |
4a6094c3 | 449 | } else { |
8fc8598e | 450 | break; |
4a6094c3 | 451 | } |
8fc8598e | 452 | } |
5f2392b8 XR |
453 | /* 7. No matter check bit. We always force the write. |
454 | Because FW will not accept the command. */ | |
79931639 | 455 | write_nic_dword(dev, QPNR, data); |
5f2392b8 | 456 | /* According to test, we must delay 20us to wait firmware |
8fc8598e | 457 | to finish RF write operation. */ |
5f2392b8 | 458 | /* We support delay in firmware side now. */ |
5f2392b8 | 459 | } |
8fc8598e | 460 | |
8fc8598e | 461 | /****************************************************************************** |
5f2392b8 XR |
462 | * function: This function reads BB parameters from header file we generate, |
463 | * and do register read/write | |
98bedd77 | 464 | * input: net_device *dev |
5f2392b8 XR |
465 | * output: none |
466 | * return: none | |
467 | * notice: BB parameters may change all the time, so please make | |
468 | * sure it has been synced with the newest. | |
469 | *****************************************************************************/ | |
88d8fe29 | 470 | void rtl8192_phy_configmac(struct net_device *dev) |
8fc8598e JC |
471 | { |
472 | u32 dwArrayLen = 0, i; | |
88d8fe29 | 473 | u32 *pdwArray = NULL; |
8fc8598e JC |
474 | struct r8192_priv *priv = ieee80211_priv(dev); |
475 | ||
1111b876 | 476 | if (priv->btxpowerdata_readfromEEPORM) { |
8fc8598e JC |
477 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); |
478 | dwArrayLen = MACPHY_Array_PGLength; | |
479 | pdwArray = rtl819XMACPHY_Array_PG; | |
480 | ||
4a6094c3 | 481 | } else { |
8fc8598e JC |
482 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); |
483 | dwArrayLen = MACPHY_ArrayLength; | |
484 | pdwArray = rtl819XMACPHY_Array; | |
485 | } | |
9d8e79ed | 486 | for (i = 0; i < dwArrayLen; i = i+3) { |
2930d0b9 | 487 | if (pdwArray[i] == 0x318) |
8fc8598e | 488 | pdwArray[i+2] = 0x00000800; |
8fc8598e | 489 | |
1db5aa05 XR |
490 | RT_TRACE(COMP_DBG, |
491 | "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n", | |
492 | pdwArray[i], pdwArray[i+1], pdwArray[i+2]); | |
493 | rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], | |
494 | pdwArray[i+2]); | |
8fc8598e | 495 | } |
8fc8598e JC |
496 | } |
497 | ||
498 | /****************************************************************************** | |
5f2392b8 XR |
499 | * function: This function does dirty work |
500 | * input: net_device *dev | |
501 | * u8 ConfigType | |
502 | * output: none | |
503 | * return: none | |
504 | * notice: BB parameters may change all the time, so please make | |
505 | * sure it has been synced with the newest. | |
506 | *****************************************************************************/ | |
88d8fe29 | 507 | void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) |
8fc8598e JC |
508 | { |
509 | u32 i; | |
510 | ||
511 | #ifdef TO_DO_LIST | |
512 | u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; | |
0081fcc6 | 513 | |
1111b876 | 514 | if (Adapter->bInHctTest) { |
8fc8598e JC |
515 | PHY_REGArrayLen = PHY_REGArrayLengthDTM; |
516 | AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; | |
517 | Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; | |
518 | Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; | |
519 | } | |
520 | #endif | |
4a6094c3 | 521 | if (ConfigType == BaseBand_Config_PHY_REG) { |
9d8e79ed | 522 | for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) { |
1db5aa05 XR |
523 | rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], |
524 | bMaskDWord, | |
525 | rtl819XPHY_REG_1T2RArray[i+1]); | |
526 | RT_TRACE(COMP_DBG, | |
527 | "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n", | |
528 | i, rtl819XPHY_REG_1T2RArray[i], | |
529 | rtl819XPHY_REG_1T2RArray[i+1]); | |
8fc8598e | 530 | } |
4a6094c3 | 531 | } else if (ConfigType == BaseBand_Config_AGC_TAB) { |
9d8e79ed | 532 | for (i = 0; i < AGCTAB_ArrayLength; i += 2) { |
1db5aa05 XR |
533 | rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], |
534 | bMaskDWord, rtl819XAGCTAB_Array[i+1]); | |
535 | RT_TRACE(COMP_DBG, | |
536 | "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n", | |
537 | i, rtl819XAGCTAB_Array[i], | |
538 | rtl819XAGCTAB_Array[i+1]); | |
8fc8598e JC |
539 | } |
540 | } | |
8fc8598e | 541 | } |
0081fcc6 | 542 | |
8fc8598e | 543 | /****************************************************************************** |
5f2392b8 XR |
544 | * function: This function initializes Register definition offset for |
545 | * Radio Path A/B/C/D | |
546 | * input: net_device *dev | |
547 | * output: none | |
548 | * return: none | |
549 | * notice: Initialization value here is constant and it should never | |
550 | * be changed | |
551 | *****************************************************************************/ | |
c92f473d | 552 | static void rtl8192_InitBBRFRegDef(struct net_device *dev) |
8fc8598e JC |
553 | { |
554 | struct r8192_priv *priv = ieee80211_priv(dev); | |
0081fcc6 | 555 | |
5f2392b8 XR |
556 | /* RF Interface Software Control */ |
557 | /* 16 LSBs if read 32-bit from 0x870 */ | |
558 | priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; | |
559 | /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ | |
560 | priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; | |
561 | /* 16 LSBs if read 32-bit from 0x874 */ | |
562 | priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; | |
563 | /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ | |
564 | priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; | |
565 | ||
566 | /* RF Interface Readback Value */ | |
567 | /* 16 LSBs if read 32-bit from 0x8E0 */ | |
568 | priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; | |
569 | /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ | |
570 | priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; | |
571 | /* 16 LSBs if read 32-bit from 0x8E4 */ | |
572 | priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; | |
573 | /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ | |
574 | priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; | |
575 | ||
576 | /* RF Interface Output (and Enable) */ | |
577 | /* 16 LSBs if read 32-bit from 0x860 */ | |
578 | priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; | |
579 | /* 16 LSBs if read 32-bit from 0x864 */ | |
580 | priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; | |
581 | /* 16 LSBs if read 32-bit from 0x868 */ | |
582 | priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; | |
583 | /* 16 LSBs if read 32-bit from 0x86C */ | |
584 | priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; | |
585 | ||
586 | /* RF Interface (Output and) Enable */ | |
587 | /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ | |
588 | priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; | |
589 | /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ | |
590 | priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; | |
591 | /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */ | |
592 | priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; | |
593 | /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */ | |
594 | priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; | |
595 | ||
596 | /* Addr of LSSI. Write RF register by driver */ | |
597 | priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; | |
8fc8598e JC |
598 | priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; |
599 | priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; | |
600 | priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; | |
601 | ||
5f2392b8 XR |
602 | /* RF parameter */ |
603 | /* BB Band Select */ | |
604 | priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; | |
8fc8598e JC |
605 | priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; |
606 | priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; | |
607 | priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; | |
608 | ||
5f2392b8 XR |
609 | /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ |
610 | priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; | |
611 | priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; | |
612 | priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; | |
613 | priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; | |
614 | ||
615 | /* Tranceiver A~D HSSI Parameter-1 */ | |
616 | /* wire control parameter1 */ | |
617 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; | |
618 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; | |
619 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; | |
620 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; | |
621 | ||
622 | /* Tranceiver A~D HSSI Parameter-2 */ | |
623 | /* wire control parameter2 */ | |
624 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; | |
625 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; | |
626 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; | |
627 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; | |
628 | ||
629 | /* RF Switch Control */ | |
630 | /* TR/Ant switch control */ | |
631 | priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; | |
8fc8598e JC |
632 | priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; |
633 | priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; | |
634 | priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; | |
635 | ||
5f2392b8 | 636 | /* AGC control 1 */ |
8fc8598e JC |
637 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; |
638 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; | |
639 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; | |
640 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; | |
641 | ||
5f2392b8 | 642 | /* AGC control 2 */ |
8fc8598e JC |
643 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; |
644 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; | |
645 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; | |
646 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; | |
647 | ||
5f2392b8 | 648 | /* RX AFE control 1 */ |
8fc8598e JC |
649 | priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; |
650 | priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; | |
651 | priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; | |
652 | priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; | |
653 | ||
5f2392b8 | 654 | /* RX AFE control 1 */ |
8fc8598e JC |
655 | priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; |
656 | priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; | |
657 | priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; | |
658 | priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; | |
659 | ||
5f2392b8 | 660 | /* Tx AFE control 1 */ |
8fc8598e JC |
661 | priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; |
662 | priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; | |
663 | priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; | |
664 | priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; | |
665 | ||
5f2392b8 | 666 | /* Tx AFE control 2 */ |
8fc8598e JC |
667 | priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; |
668 | priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; | |
669 | priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; | |
670 | priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; | |
671 | ||
5f2392b8 | 672 | /* Tranceiver LSSI Readback */ |
8fc8598e JC |
673 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; |
674 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; | |
675 | priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; | |
676 | priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; | |
8fc8598e | 677 | } |
0081fcc6 | 678 | |
8fc8598e | 679 | /****************************************************************************** |
5f2392b8 XR |
680 | * function: This function is to write register and then readback to make |
681 | * sure whether BB and RF is OK | |
682 | * input: net_device *dev | |
683 | * HW90_BLOCK_E CheckBlock | |
684 | * RF90_RADIO_PATH_E eRFPath //only used when checkblock is | |
685 | * //HW90_BLOCK_RF | |
686 | * output: none | |
687 | * return: return whether BB and RF is ok (0:OK, 1:Fail) | |
688 | * notice: This function may be removed in the ASIC | |
689 | ******************************************************************************/ | |
442543d7 XR |
690 | u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, |
691 | RF90_RADIO_PATH_E eRFPath) | |
8fc8598e | 692 | { |
8fc8598e | 693 | u8 ret = 0; |
a60d4d68 | 694 | u32 i, CheckTimes = 4, reg = 0; |
8fc8598e JC |
695 | u32 WriteAddr[4]; |
696 | u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; | |
0081fcc6 | 697 | |
5f2392b8 | 698 | /* Initialize register address offset to be checked */ |
8fc8598e JC |
699 | WriteAddr[HW90_BLOCK_MAC] = 0x100; |
700 | WriteAddr[HW90_BLOCK_PHY0] = 0x900; | |
701 | WriteAddr[HW90_BLOCK_PHY1] = 0x800; | |
702 | WriteAddr[HW90_BLOCK_RF] = 0x3; | |
08a4cdea | 703 | RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock); |
111857c9 | 704 | for (i = 0; i < CheckTimes; i++) { |
8fc8598e | 705 | |
5f2392b8 | 706 | /* Write data to register and readback */ |
4a6094c3 | 707 | switch (CheckBlock) { |
8fc8598e | 708 | case HW90_BLOCK_MAC: |
1db5aa05 | 709 | RT_TRACE(COMP_ERR, |
0081fcc6 | 710 | "PHY_CheckBBRFOK(): Never Write 0x100 here!\n"); |
8fc8598e JC |
711 | break; |
712 | ||
713 | case HW90_BLOCK_PHY0: | |
714 | case HW90_BLOCK_PHY1: | |
1db5aa05 XR |
715 | write_nic_dword(dev, WriteAddr[CheckBlock], |
716 | WriteData[i]); | |
a60d4d68 | 717 | read_nic_dword(dev, WriteAddr[CheckBlock], ®); |
8fc8598e JC |
718 | break; |
719 | ||
720 | case HW90_BLOCK_RF: | |
721 | WriteData[i] &= 0xfff; | |
1db5aa05 XR |
722 | rtl8192_phy_SetRFReg(dev, eRFPath, |
723 | WriteAddr[HW90_BLOCK_RF], | |
724 | bMask12Bits, WriteData[i]); | |
5f2392b8 XR |
725 | /* TODO: we should not delay for such a long time. |
726 | Ask SD3 */ | |
26f3561d | 727 | usleep_range(1000, 1000); |
a60d4d68 XR |
728 | reg = rtl8192_phy_QueryRFReg(dev, eRFPath, |
729 | WriteAddr[HW90_BLOCK_RF], | |
730 | bMask12Bits); | |
26f3561d | 731 | usleep_range(1000, 1000); |
8fc8598e JC |
732 | break; |
733 | ||
734 | default: | |
735 | ret = 1; | |
736 | break; | |
737 | } | |
738 | ||
739 | ||
5f2392b8 | 740 | /* Check whether readback data is correct */ |
a60d4d68 | 741 | if (reg != WriteData[i]) { |
1db5aa05 | 742 | RT_TRACE((COMP_PHY|COMP_ERR), |
a60d4d68 XR |
743 | "error reg: %x, WriteData: %x\n", |
744 | reg, WriteData[i]); | |
8fc8598e JC |
745 | ret = 1; |
746 | break; | |
747 | } | |
748 | } | |
749 | ||
750 | return ret; | |
751 | } | |
752 | ||
8fc8598e | 753 | /****************************************************************************** |
5f2392b8 XR |
754 | * function: This function initializes BB&RF |
755 | * input: net_device *dev | |
756 | * output: none | |
757 | * return: none | |
758 | * notice: Initialization value may change all the time, so please make | |
759 | * sure it has been synced with the newest. | |
760 | ******************************************************************************/ | |
c92f473d | 761 | static void rtl8192_BB_Config_ParaFile(struct net_device *dev) |
8fc8598e JC |
762 | { |
763 | struct r8192_priv *priv = ieee80211_priv(dev); | |
a60d4d68 | 764 | u8 reg_u8 = 0, eCheckItem = 0, status = 0; |
07ecbbf1 | 765 | u32 reg_u32 = 0; |
0081fcc6 | 766 | |
8fc8598e | 767 | /************************************** |
5f2392b8 XR |
768 | * <1> Initialize BaseBand |
769 | *************************************/ | |
8fc8598e | 770 | |
5f2392b8 | 771 | /* --set BB Global Reset-- */ |
07ecbbf1 | 772 | read_nic_byte(dev, BB_GLOBAL_RESET, ®_u8); |
83e6d9e2 | 773 | write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT)); |
8fc8598e | 774 | mdelay(50); |
5f2392b8 | 775 | /* ---set BB reset Active--- */ |
07ecbbf1 XR |
776 | read_nic_dword(dev, CPU_GEN, ®_u32); |
777 | write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST))); | |
8fc8598e | 778 | |
5f2392b8 XR |
779 | /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */ |
780 | /* TODO: this function should be removed on ASIC */ | |
1db5aa05 XR |
781 | for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0; |
782 | eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { | |
783 | /* don't care RF path */ | |
a60d4d68 XR |
784 | status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, |
785 | (RF90_RADIO_PATH_E)0); | |
786 | if (status != 0) { | |
1db5aa05 XR |
787 | RT_TRACE((COMP_ERR | COMP_PHY), |
788 | "PHY_RF8256_Config(): Check PHY%d Fail!!\n", | |
789 | eCheckItem-1); | |
111857c9 | 790 | return; |
8fc8598e JC |
791 | } |
792 | } | |
5f2392b8 | 793 | /* ---- Set CCK and OFDM Block "OFF"---- */ |
8fc8598e | 794 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); |
5f2392b8 XR |
795 | /* ----BB Register Initilazation---- */ |
796 | /* ==m==>Set PHY REG From Header<==m== */ | |
8fc8598e JC |
797 | rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); |
798 | ||
5f2392b8 | 799 | /* ----Set BB reset de-Active---- */ |
07ecbbf1 XR |
800 | read_nic_dword(dev, CPU_GEN, ®_u32); |
801 | write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST)); | |
8fc8598e | 802 | |
5f2392b8 XR |
803 | /* ----BB AGC table Initialization---- */ |
804 | /* ==m==>Set PHY REG From Header<==m== */ | |
8fc8598e JC |
805 | rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); |
806 | ||
5f2392b8 | 807 | /* ----Enable XSTAL ---- */ |
8fc8598e | 808 | write_nic_byte_E(dev, 0x5e, 0x00); |
4a6094c3 | 809 | if (priv->card_8192_version == (u8)VERSION_819xU_A) { |
5f2392b8 | 810 | /* Antenna gain offset from B/C/D to A */ |
2060f31a HM |
811 | reg_u32 = priv->AntennaTxPwDiff[1]<<4 | |
812 | priv->AntennaTxPwDiff[0]; | |
1db5aa05 XR |
813 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), |
814 | reg_u32); | |
8fc8598e | 815 | |
5f2392b8 | 816 | /* XSTALLCap */ |
07ecbbf1 | 817 | reg_u32 = priv->CrystalCap & 0xf; |
1db5aa05 XR |
818 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, |
819 | reg_u32); | |
8fc8598e JC |
820 | } |
821 | ||
5f2392b8 XR |
822 | /* Check if the CCK HighPower is turned ON. |
823 | This is used to calculate PWDB. */ | |
1db5aa05 XR |
824 | priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev, |
825 | rFPGA0_XA_HSSIParameter2, | |
826 | 0x200); | |
8fc8598e | 827 | } |
0081fcc6 | 828 | |
8fc8598e | 829 | /****************************************************************************** |
5f2392b8 XR |
830 | * function: This function initializes BB&RF |
831 | * input: net_device *dev | |
832 | * output: none | |
833 | * return: none | |
834 | * notice: Initialization value may change all the time, so please make | |
835 | * sure it has been synced with the newest. | |
836 | *****************************************************************************/ | |
88d8fe29 | 837 | void rtl8192_BBConfig(struct net_device *dev) |
8fc8598e JC |
838 | { |
839 | rtl8192_InitBBRFRegDef(dev); | |
5f2392b8 XR |
840 | /* config BB&RF. As hardCode based initialization has not been well |
841 | * implemented, so use file first. | |
842 | * FIXME: should implement it for hardcode? */ | |
8fc8598e | 843 | rtl8192_BB_Config_ParaFile(dev); |
8fc8598e JC |
844 | } |
845 | ||
0081fcc6 | 846 | |
8fc8598e | 847 | /****************************************************************************** |
5f2392b8 XR |
848 | * function: This function obtains the initialization value of Tx power Level |
849 | * offset | |
850 | * input: net_device *dev | |
851 | * output: none | |
852 | * return: none | |
853 | *****************************************************************************/ | |
88d8fe29 | 854 | void rtl8192_phy_getTxPower(struct net_device *dev) |
8fc8598e JC |
855 | { |
856 | struct r8192_priv *priv = ieee80211_priv(dev); | |
b3d42bf1 | 857 | u8 tmp; |
0081fcc6 | 858 | |
1db5aa05 XR |
859 | read_nic_dword(dev, rTxAGC_Rate18_06, |
860 | &priv->MCSTxPowerLevelOriginalOffset[0]); | |
861 | read_nic_dword(dev, rTxAGC_Rate54_24, | |
862 | &priv->MCSTxPowerLevelOriginalOffset[1]); | |
863 | read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, | |
864 | &priv->MCSTxPowerLevelOriginalOffset[2]); | |
865 | read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, | |
866 | &priv->MCSTxPowerLevelOriginalOffset[3]); | |
867 | read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, | |
868 | &priv->MCSTxPowerLevelOriginalOffset[4]); | |
869 | read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, | |
870 | &priv->MCSTxPowerLevelOriginalOffset[5]); | |
8fc8598e | 871 | |
5f2392b8 | 872 | /* Read rx initial gain */ |
b3d42bf1 XR |
873 | read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]); |
874 | read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]); | |
875 | read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]); | |
876 | read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]); | |
1db5aa05 XR |
877 | RT_TRACE(COMP_INIT, |
878 | "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", | |
879 | priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], | |
880 | priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); | |
8fc8598e | 881 | |
5f2392b8 | 882 | /* Read framesync */ |
b3d42bf1 XR |
883 | read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync); |
884 | read_nic_byte(dev, rOFDM0_RxDetector2, &tmp); | |
885 | priv->framesyncC34 = tmp; | |
d5133e75 | 886 | RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", |
8fc8598e JC |
887 | rOFDM0_RxDetector3, priv->framesync); |
888 | ||
5f2392b8 | 889 | /* Read SIFS (save the value read fome MACPHY_REG.txt) */ |
b3d42bf1 | 890 | read_nic_word(dev, SIFS, &priv->SifsTime); |
8fc8598e JC |
891 | } |
892 | ||
893 | /****************************************************************************** | |
5f2392b8 XR |
894 | * function: This function sets the initialization value of Tx power Level |
895 | * offset | |
896 | * input: net_device *dev | |
897 | * u8 channel | |
898 | * output: none | |
899 | * return: none | |
900 | ******************************************************************************/ | |
88d8fe29 | 901 | void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) |
8fc8598e JC |
902 | { |
903 | struct r8192_priv *priv = ieee80211_priv(dev); | |
904 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; | |
905 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | |
906 | ||
4a6094c3 | 907 | switch (priv->rf_chip) { |
8fc8598e | 908 | case RF_8256: |
1db5aa05 XR |
909 | /* need further implement */ |
910 | PHY_SetRF8256CCKTxPower(dev, powerlevel); | |
8fc8598e JC |
911 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); |
912 | break; | |
913 | default: | |
1db5aa05 XR |
914 | RT_TRACE((COMP_PHY|COMP_ERR), |
915 | "error RF chipID(8225 or 8258) in function %s()\n", | |
08a4cdea | 916 | __func__); |
8fc8598e JC |
917 | break; |
918 | } | |
8fc8598e JC |
919 | } |
920 | ||
921 | /****************************************************************************** | |
5f2392b8 XR |
922 | * function: This function checks Rf chip to do RF config |
923 | * input: net_device *dev | |
924 | * output: none | |
925 | * return: only 8256 is supported | |
926 | ******************************************************************************/ | |
88d8fe29 | 927 | void rtl8192_phy_RFConfig(struct net_device *dev) |
8fc8598e JC |
928 | { |
929 | struct r8192_priv *priv = ieee80211_priv(dev); | |
930 | ||
4a6094c3 | 931 | switch (priv->rf_chip) { |
16ec1a20 | 932 | case RF_8256: |
933 | PHY_RF8256_Config(dev); | |
934 | break; | |
935 | default: | |
936 | RT_TRACE(COMP_ERR, "error chip id\n"); | |
937 | break; | |
8fc8598e | 938 | } |
8fc8598e JC |
939 | } |
940 | ||
941 | /****************************************************************************** | |
5f2392b8 XR |
942 | * function: This function updates Initial gain |
943 | * input: net_device *dev | |
944 | * output: none | |
945 | * return: As Windows has not implemented this, wait for complement | |
946 | ******************************************************************************/ | |
88d8fe29 | 947 | void rtl8192_phy_updateInitGain(struct net_device *dev) |
8fc8598e | 948 | { |
8fc8598e JC |
949 | } |
950 | ||
951 | /****************************************************************************** | |
5f2392b8 XR |
952 | * function: This function read RF parameters from general head file, |
953 | * and do RF 3-wire | |
954 | * input: net_device *dev | |
955 | * RF90_RADIO_PATH_E eRFPath | |
956 | * output: none | |
957 | * return: return code show if RF configuration is successful(0:pass, 1:fail) | |
958 | * notice: Delay may be required for RF configuration | |
959 | *****************************************************************************/ | |
442543d7 XR |
960 | u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, |
961 | RF90_RADIO_PATH_E eRFPath) | |
8fc8598e JC |
962 | { |
963 | ||
964 | int i; | |
8fc8598e | 965 | |
4a6094c3 | 966 | switch (eRFPath) { |
24fbe875 | 967 | case RF90_PATH_A: |
9d8e79ed | 968 | for (i = 0; i < RadioA_ArrayLength; i = i+2) { |
8fc8598e | 969 | |
1111b876 | 970 | if (rtl819XRadioA_Array[i] == 0xfe) { |
1db5aa05 XR |
971 | mdelay(100); |
972 | continue; | |
8fc8598e | 973 | } |
1db5aa05 XR |
974 | rtl8192_phy_SetRFReg(dev, eRFPath, |
975 | rtl819XRadioA_Array[i], | |
976 | bMask12Bits, | |
977 | rtl819XRadioA_Array[i+1]); | |
24fbe875 | 978 | mdelay(1); |
8fc8598e | 979 | |
24fbe875 SH |
980 | } |
981 | break; | |
982 | case RF90_PATH_B: | |
9d8e79ed | 983 | for (i = 0; i < RadioB_ArrayLength; i = i+2) { |
8fc8598e | 984 | |
1111b876 | 985 | if (rtl819XRadioB_Array[i] == 0xfe) { |
1db5aa05 XR |
986 | mdelay(100); |
987 | continue; | |
8fc8598e | 988 | } |
1db5aa05 XR |
989 | rtl8192_phy_SetRFReg(dev, eRFPath, |
990 | rtl819XRadioB_Array[i], | |
991 | bMask12Bits, | |
992 | rtl819XRadioB_Array[i+1]); | |
24fbe875 | 993 | mdelay(1); |
8fc8598e | 994 | |
24fbe875 SH |
995 | } |
996 | break; | |
997 | case RF90_PATH_C: | |
9d8e79ed | 998 | for (i = 0; i < RadioC_ArrayLength; i = i+2) { |
8fc8598e | 999 | |
1111b876 | 1000 | if (rtl819XRadioC_Array[i] == 0xfe) { |
1db5aa05 XR |
1001 | mdelay(100); |
1002 | continue; | |
8fc8598e | 1003 | } |
1db5aa05 XR |
1004 | rtl8192_phy_SetRFReg(dev, eRFPath, |
1005 | rtl819XRadioC_Array[i], | |
1006 | bMask12Bits, | |
1007 | rtl819XRadioC_Array[i+1]); | |
24fbe875 | 1008 | mdelay(1); |
8fc8598e | 1009 | |
24fbe875 SH |
1010 | } |
1011 | break; | |
1012 | case RF90_PATH_D: | |
9d8e79ed | 1013 | for (i = 0; i < RadioD_ArrayLength; i = i+2) { |
8fc8598e | 1014 | |
1111b876 | 1015 | if (rtl819XRadioD_Array[i] == 0xfe) { |
1db5aa05 XR |
1016 | mdelay(100); |
1017 | continue; | |
8fc8598e | 1018 | } |
1db5aa05 XR |
1019 | rtl8192_phy_SetRFReg(dev, eRFPath, |
1020 | rtl819XRadioD_Array[i], | |
1021 | bMask12Bits, | |
1022 | rtl819XRadioD_Array[i+1]); | |
24fbe875 SH |
1023 | mdelay(1); |
1024 | ||
1025 | } | |
1026 | break; | |
1027 | default: | |
1028 | break; | |
8fc8598e JC |
1029 | } |
1030 | ||
4764ca98 | 1031 | return 0; |
8fc8598e JC |
1032 | |
1033 | } | |
0081fcc6 | 1034 | |
8fc8598e | 1035 | /****************************************************************************** |
5f2392b8 XR |
1036 | * function: This function sets Tx Power of the channel |
1037 | * input: net_device *dev | |
1038 | * u8 channel | |
1039 | * output: none | |
1040 | * return: none | |
1041 | * notice: | |
1042 | ******************************************************************************/ | |
c92f473d | 1043 | static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) |
8fc8598e JC |
1044 | { |
1045 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1046 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; | |
1047 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | |
1048 | ||
4a6094c3 | 1049 | switch (priv->rf_chip) { |
8fc8598e JC |
1050 | case RF_8225: |
1051 | #ifdef TO_DO_LIST | |
1052 | PHY_SetRF8225CckTxPower(Adapter, powerlevel); | |
1053 | PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); | |
1054 | #endif | |
1055 | break; | |
1056 | ||
1057 | case RF_8256: | |
1058 | PHY_SetRF8256CCKTxPower(dev, powerlevel); | |
1059 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); | |
1060 | break; | |
1061 | ||
1062 | case RF_8258: | |
1063 | break; | |
1064 | default: | |
1db5aa05 | 1065 | RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__); |
8fc8598e JC |
1066 | break; |
1067 | } | |
8fc8598e JC |
1068 | } |
1069 | ||
1070 | /****************************************************************************** | |
5f2392b8 XR |
1071 | * function: This function sets RF state on or off |
1072 | * input: net_device *dev | |
1073 | * RT_RF_POWER_STATE eRFPowerState //Power State to set | |
1074 | * output: none | |
1075 | * return: none | |
1076 | * notice: | |
1077 | *****************************************************************************/ | |
442543d7 XR |
1078 | bool rtl8192_SetRFPowerState(struct net_device *dev, |
1079 | RT_RF_POWER_STATE eRFPowerState) | |
8fc8598e JC |
1080 | { |
1081 | bool bResult = true; | |
8fc8598e JC |
1082 | struct r8192_priv *priv = ieee80211_priv(dev); |
1083 | ||
1111b876 | 1084 | if (eRFPowerState == priv->ieee80211->eRFPowerState) |
8fc8598e JC |
1085 | return false; |
1086 | ||
a0886f73 | 1087 | if (priv->SetRFPowerStateInProgress) |
8fc8598e JC |
1088 | return false; |
1089 | ||
1090 | priv->SetRFPowerStateInProgress = true; | |
1091 | ||
4a6094c3 | 1092 | switch (priv->rf_chip) { |
1db5aa05 | 1093 | case RF_8256: |
ceb56597 | 1094 | switch (eRFPowerState) { |
1db5aa05 XR |
1095 | case eRfOn: |
1096 | /* RF-A, RF-B */ | |
1097 | /* enable RF-Chip A/B - 0x860[4] */ | |
56b3152e | 1098 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), |
1db5aa05 XR |
1099 | 0x1); |
1100 | /* analog to digital on - 0x88c[9:8] */ | |
1101 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, | |
1102 | 0x3); | |
1103 | /* digital to analog on - 0x880[4:3] */ | |
1104 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, | |
1105 | 0x3); | |
1106 | /* rx antenna on - 0xc04[1:0] */ | |
1107 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); | |
1108 | /* rx antenna on - 0xd04[1:0] */ | |
1109 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); | |
1110 | /* analog to digital part2 on - 0x880[6:5] */ | |
1111 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, | |
1112 | 0x3); | |
8fc8598e | 1113 | |
1db5aa05 | 1114 | break; |
8fc8598e | 1115 | |
1db5aa05 | 1116 | case eRfSleep: |
8fc8598e | 1117 | |
1db5aa05 | 1118 | break; |
8fc8598e | 1119 | |
1db5aa05 XR |
1120 | case eRfOff: |
1121 | /* RF-A, RF-B */ | |
1122 | /* disable RF-Chip A/B - 0x860[4] */ | |
56b3152e | 1123 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), |
1db5aa05 XR |
1124 | 0x0); |
1125 | /* analog to digital off, for power save */ | |
1126 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, | |
1127 | 0x0); /* 0x88c[11:8] */ | |
1128 | /* digital to analog off, for power save - 0x880[4:3] */ | |
1129 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, | |
1130 | 0x0); | |
1131 | /* rx antenna off - 0xc04[3:0] */ | |
1132 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); | |
1133 | /* rx antenna off - 0xd04[3:0] */ | |
1134 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); | |
1135 | /* analog to digital part2 off, for power save */ | |
1136 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, | |
1137 | 0x0); /* 0x880[6:5] */ | |
8fc8598e | 1138 | |
8fc8598e | 1139 | break; |
1db5aa05 | 1140 | |
8fc8598e | 1141 | default: |
1db5aa05 XR |
1142 | bResult = false; |
1143 | RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n", | |
1144 | __func__, eRFPowerState); | |
8fc8598e | 1145 | break; |
1db5aa05 XR |
1146 | } |
1147 | break; | |
1148 | default: | |
1149 | RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); | |
1150 | break; | |
8fc8598e JC |
1151 | } |
1152 | #ifdef TO_DO_LIST | |
1111b876 | 1153 | if (bResult) { |
5f2392b8 | 1154 | /* Update current RF state variable. */ |
8fc8598e | 1155 | pHalData->eRFPowerState = eRFPowerState; |
ceb56597 | 1156 | switch (pHalData->RFChipID) { |
1db5aa05 XR |
1157 | case RF_8256: |
1158 | switch (pHalData->eRFPowerState) { | |
1159 | case eRfOff: | |
1160 | /* If Rf off reason is from IPS, | |
1161 | LED should blink with no link */ | |
1162 | if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS) | |
1163 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); | |
1164 | else | |
1165 | /* Turn off LED if RF is not ON. */ | |
1166 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); | |
8fc8598e JC |
1167 | break; |
1168 | ||
1db5aa05 XR |
1169 | case eRfOn: |
1170 | /* Turn on RF we are still linked, which might | |
1171 | happen when we quickly turn off and on HW RF. | |
1172 | */ | |
352e579d | 1173 | if (pMgntInfo->bMediaConnect) |
1db5aa05 XR |
1174 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); |
1175 | else | |
1176 | /* Turn off LED if RF is not ON. */ | |
1177 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); | |
1178 | break; | |
1179 | ||
1180 | default: | |
1181 | break; | |
8fc8598e | 1182 | } |
1db5aa05 XR |
1183 | break; |
1184 | ||
1185 | default: | |
1186 | RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n", | |
1187 | __func__); | |
1188 | break; | |
1189 | } | |
8fc8598e JC |
1190 | |
1191 | } | |
1192 | #endif | |
1193 | priv->SetRFPowerStateInProgress = false; | |
1194 | ||
1195 | return bResult; | |
1196 | } | |
1197 | ||
5f2392b8 XR |
1198 | /****************************************************************************** |
1199 | * function: This function sets command table variable (struct SwChnlCmd). | |
1200 | * input: SwChnlCmd *CmdTable //table to be set | |
1201 | * u32 CmdTableIdx //variable index in table to be set | |
1202 | * u32 CmdTableSz //table size | |
1203 | * SwChnlCmdID CmdID //command ID to set | |
1204 | * u32 Para1 | |
1205 | * u32 Para2 | |
1206 | * u32 msDelay | |
1207 | * output: | |
1208 | * return: true if finished, false otherwise | |
1209 | * notice: | |
1210 | ******************************************************************************/ | |
c92f473d AR |
1211 | static u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx, |
1212 | u32 CmdTableSz, SwChnlCmdID CmdID, | |
1213 | u32 Para1, u32 Para2, u32 msDelay) | |
8fc8598e | 1214 | { |
88d8fe29 | 1215 | SwChnlCmd *pCmd; |
8fc8598e | 1216 | |
1111b876 | 1217 | if (CmdTable == NULL) { |
1db5aa05 | 1218 | RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__); |
8fc8598e JC |
1219 | return false; |
1220 | } | |
1111b876 | 1221 | if (CmdTableIdx >= CmdTableSz) { |
1db5aa05 XR |
1222 | RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", |
1223 | __func__, CmdTableIdx, CmdTableSz); | |
8fc8598e JC |
1224 | return false; |
1225 | } | |
1226 | ||
1227 | pCmd = CmdTable + CmdTableIdx; | |
1228 | pCmd->CmdID = CmdID; | |
1229 | pCmd->Para1 = Para1; | |
1230 | pCmd->Para2 = Para2; | |
1231 | pCmd->msDelay = msDelay; | |
1232 | ||
1233 | return true; | |
1234 | } | |
0081fcc6 | 1235 | |
8fc8598e | 1236 | /****************************************************************************** |
5f2392b8 XR |
1237 | * function: This function sets channel step by step |
1238 | * input: net_device *dev | |
1239 | * u8 channel | |
1240 | * u8 *stage //3 stages | |
1241 | * u8 *step | |
1242 | * u32 *delay //whether need to delay | |
1243 | * output: store new stage, step and delay for next step | |
1244 | * (combine with function above) | |
1245 | * return: true if finished, false otherwise | |
1246 | * notice: Wait for simpler function to replace it | |
1247 | *****************************************************************************/ | |
c92f473d AR |
1248 | static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, |
1249 | u8 *stage, u8 *step, u32 *delay) | |
8fc8598e JC |
1250 | { |
1251 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1db5aa05 XR |
1252 | SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; |
1253 | u32 PreCommonCmdCnt; | |
1254 | SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; | |
1255 | u32 PostCommonCmdCnt; | |
1256 | SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; | |
1257 | u32 RfDependCmdCnt; | |
1258 | SwChnlCmd *CurrentCmd = NULL; | |
8fc8598e | 1259 | u8 eRFPath; |
8fc8598e | 1260 | |
1db5aa05 | 1261 | RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n", |
08a4cdea | 1262 | __func__, *stage, *step, channel); |
4a6094c3 | 1263 | if (!IsLegalChannel(priv->ieee80211, channel)) { |
1db5aa05 | 1264 | RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel); |
5f2392b8 XR |
1265 | /* return true to tell upper caller function this channel |
1266 | setting is finished! Or it will in while loop. */ | |
1267 | return true; | |
8fc8598e | 1268 | } |
1db5aa05 | 1269 | /* FIXME: need to check whether channel is legal or not here */ |
8fc8598e JC |
1270 | |
1271 | ||
1db5aa05 XR |
1272 | /* <1> Fill up pre common command. */ |
1273 | PreCommonCmdCnt = 0; | |
1274 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, | |
1275 | MAX_PRECMD_CNT, CmdID_SetTxPowerLevel, | |
1276 | 0, 0, 0); | |
1277 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, | |
1278 | MAX_PRECMD_CNT, CmdID_End, 0, 0, 0); | |
8fc8598e | 1279 | |
1db5aa05 XR |
1280 | /* <2> Fill up post common command. */ |
1281 | PostCommonCmdCnt = 0; | |
8fc8598e | 1282 | |
1db5aa05 XR |
1283 | rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, |
1284 | MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0); | |
8fc8598e | 1285 | |
1db5aa05 XR |
1286 | /* <3> Fill up RF dependent command. */ |
1287 | RfDependCmdCnt = 0; | |
1288 | switch (priv->rf_chip) { | |
1289 | case RF_8225: | |
1290 | if (!(channel >= 1 && channel <= 14)) { | |
1291 | RT_TRACE(COMP_ERR, | |
1292 | "illegal channel for Zebra 8225: %d\n", | |
1293 | channel); | |
1294 | return true; | |
1295 | } | |
1296 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, | |
1297 | MAX_RFDEPENDCMD_CNT, | |
1298 | CmdID_RF_WriteReg, | |
1299 | rZebra1_Channel, | |
1300 | RF_CHANNEL_TABLE_ZEBRA[channel], | |
1301 | 10); | |
1302 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, | |
1303 | MAX_RFDEPENDCMD_CNT, | |
1304 | CmdID_End, 0, 0, 0); | |
1305 | break; | |
8fc8598e | 1306 | |
1db5aa05 XR |
1307 | case RF_8256: |
1308 | /* TEST!! This is not the table for 8256!! */ | |
1309 | if (!(channel >= 1 && channel <= 14)) { | |
1310 | RT_TRACE(COMP_ERR, | |
1311 | "illegal channel for Zebra 8256: %d\n", | |
1312 | channel); | |
8fc8598e | 1313 | return true; |
8fc8598e | 1314 | } |
1db5aa05 XR |
1315 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, |
1316 | MAX_RFDEPENDCMD_CNT, | |
1317 | CmdID_RF_WriteReg, | |
1318 | rZebra1_Channel, channel, 10); | |
1319 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, | |
1320 | MAX_RFDEPENDCMD_CNT, | |
1321 | CmdID_End, 0, 0, 0); | |
1322 | break; | |
8fc8598e | 1323 | |
1db5aa05 XR |
1324 | case RF_8258: |
1325 | break; | |
8fc8598e | 1326 | |
1db5aa05 XR |
1327 | default: |
1328 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); | |
1329 | return true; | |
1db5aa05 | 1330 | } |
8fc8598e | 1331 | |
8fc8598e | 1332 | |
1db5aa05 XR |
1333 | do { |
1334 | switch (*stage) { | |
1335 | case 0: | |
1336 | CurrentCmd = &PreCommonCmd[*step]; | |
1337 | break; | |
1338 | case 1: | |
1339 | CurrentCmd = &RfDependCmd[*step]; | |
1340 | break; | |
1341 | case 2: | |
1342 | CurrentCmd = &PostCommonCmd[*step]; | |
1343 | break; | |
1344 | } | |
1345 | ||
1346 | if (CurrentCmd->CmdID == CmdID_End) { | |
1347 | if ((*stage) == 2) { | |
1348 | (*delay) = CurrentCmd->msDelay; | |
1349 | return true; | |
8fc8598e | 1350 | } |
bf1c66e8 KS |
1351 | (*stage)++; |
1352 | (*step) = 0; | |
1353 | continue; | |
1db5aa05 | 1354 | } |
8fc8598e | 1355 | |
1db5aa05 XR |
1356 | switch (CurrentCmd->CmdID) { |
1357 | case CmdID_SetTxPowerLevel: | |
1358 | if (priv->card_8192_version == (u8)VERSION_819xU_A) | |
1359 | /* consider it later! */ | |
1360 | rtl8192_SetTxPowerLevel(dev, channel); | |
8fc8598e | 1361 | break; |
1db5aa05 XR |
1362 | case CmdID_WritePortUlong: |
1363 | write_nic_dword(dev, CurrentCmd->Para1, | |
1364 | CurrentCmd->Para2); | |
1365 | break; | |
1366 | case CmdID_WritePortUshort: | |
1367 | write_nic_word(dev, CurrentCmd->Para1, | |
1368 | (u16)CurrentCmd->Para2); | |
1369 | break; | |
1370 | case CmdID_WritePortUchar: | |
1371 | write_nic_byte(dev, CurrentCmd->Para1, | |
1372 | (u8)CurrentCmd->Para2); | |
1373 | break; | |
1374 | case CmdID_RF_WriteReg: | |
1375 | for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) { | |
1376 | rtl8192_phy_SetRFReg(dev, | |
1377 | (RF90_RADIO_PATH_E)eRFPath, | |
1378 | CurrentCmd->Para1, | |
1379 | bZebra1_ChannelNum, | |
1380 | CurrentCmd->Para2); | |
1381 | } | |
1382 | break; | |
1383 | default: | |
1384 | break; | |
1385 | } | |
1386 | ||
1387 | break; | |
1388 | } while (true); | |
8fc8598e | 1389 | |
ec5d319b | 1390 | (*delay) = CurrentCmd->msDelay; |
8fc8598e JC |
1391 | (*step)++; |
1392 | return false; | |
1393 | } | |
1394 | ||
1395 | /****************************************************************************** | |
5f2392b8 XR |
1396 | * function: This function does actually set channel work |
1397 | * input: net_device *dev | |
1398 | * u8 channel | |
1399 | * output: none | |
1400 | * return: none | |
1401 | * notice: We should not call this function directly | |
1402 | *****************************************************************************/ | |
c92f473d | 1403 | static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) |
8fc8598e JC |
1404 | { |
1405 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1406 | u32 delay = 0; | |
1407 | ||
1db5aa05 XR |
1408 | while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, |
1409 | &priv->SwChnlStep, &delay)) { | |
1111b876 | 1410 | if (!priv->up) |
8fc8598e JC |
1411 | break; |
1412 | } | |
1413 | } | |
0081fcc6 | 1414 | |
8fc8598e | 1415 | /****************************************************************************** |
5f2392b8 XR |
1416 | * function: Callback routine of the work item for switch channel. |
1417 | * input: net_device *dev | |
8fc8598e | 1418 | * |
5f2392b8 XR |
1419 | * output: none |
1420 | * return: none | |
1421 | *****************************************************************************/ | |
8fc8598e JC |
1422 | void rtl8192_SwChnl_WorkItem(struct net_device *dev) |
1423 | { | |
1424 | ||
1425 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1426 | ||
1db5aa05 XR |
1427 | RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", |
1428 | priv->chan); | |
8fc8598e JC |
1429 | |
1430 | ||
83e6d9e2 | 1431 | rtl8192_phy_FinishSwChnlNow(dev, priv->chan); |
8fc8598e JC |
1432 | |
1433 | RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); | |
1434 | } | |
1435 | ||
1436 | /****************************************************************************** | |
5f2392b8 XR |
1437 | * function: This function scheduled actual work item to set channel |
1438 | * input: net_device *dev | |
1439 | * u8 channel //channel to set | |
1440 | * output: none | |
1441 | * return: return code show if workitem is scheduled (1:pass, 0:fail) | |
1442 | * notice: Delay may be required for RF configuration | |
1443 | ******************************************************************************/ | |
88d8fe29 | 1444 | u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) |
8fc8598e JC |
1445 | { |
1446 | struct r8192_priv *priv = ieee80211_priv(dev); | |
657eb979 | 1447 | |
08a4cdea | 1448 | RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__, |
1db5aa05 | 1449 | priv->SwChnlInProgress); |
1111b876 | 1450 | if (!priv->up) |
8fc8598e | 1451 | return false; |
1111b876 | 1452 | if (priv->SwChnlInProgress) |
8fc8598e JC |
1453 | return false; |
1454 | ||
5f2392b8 | 1455 | /* -------------------------------------------- */ |
4a6094c3 | 1456 | switch (priv->ieee80211->mode) { |
8fc8598e JC |
1457 | case WIRELESS_MODE_A: |
1458 | case WIRELESS_MODE_N_5G: | |
9d8e79ed | 1459 | if (channel <= 14) { |
0081fcc6 | 1460 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n"); |
8fc8598e JC |
1461 | return false; |
1462 | } | |
1463 | break; | |
1464 | case WIRELESS_MODE_B: | |
9d8e79ed | 1465 | if (channel > 14) { |
0081fcc6 | 1466 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n"); |
8fc8598e JC |
1467 | return false; |
1468 | } | |
1469 | break; | |
1470 | case WIRELESS_MODE_G: | |
1471 | case WIRELESS_MODE_N_24G: | |
9d8e79ed | 1472 | if (channel > 14) { |
0081fcc6 | 1473 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n"); |
8fc8598e JC |
1474 | return false; |
1475 | } | |
1476 | break; | |
1477 | } | |
5f2392b8 | 1478 | /* -------------------------------------------- */ |
8fc8598e JC |
1479 | |
1480 | priv->SwChnlInProgress = true; | |
1111b876 | 1481 | if (channel == 0) |
8fc8598e JC |
1482 | channel = 1; |
1483 | ||
ec5d319b | 1484 | priv->chan = channel; |
8fc8598e | 1485 | |
ec5d319b XR |
1486 | priv->SwChnlStage = 0; |
1487 | priv->SwChnlStep = 0; | |
d75340eb | 1488 | if (priv->up) |
1db5aa05 | 1489 | rtl8192_SwChnl_WorkItem(dev); |
8fc8598e JC |
1490 | |
1491 | priv->SwChnlInProgress = false; | |
1492 | return true; | |
1493 | } | |
1494 | ||
8fc8598e | 1495 | /****************************************************************************** |
5f2392b8 XR |
1496 | * function: Callback routine of the work item for set bandwidth mode. |
1497 | * input: net_device *dev | |
1498 | * output: none | |
1499 | * return: none | |
1500 | * notice: I doubt whether SetBWModeInProgress flag is necessary as we can | |
1501 | * test whether current work in the queue or not.//do I? | |
1502 | *****************************************************************************/ | |
8fc8598e JC |
1503 | void rtl8192_SetBWModeWorkItem(struct net_device *dev) |
1504 | { | |
1505 | ||
1506 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1507 | u8 regBwOpMode; | |
1508 | ||
1db5aa05 | 1509 | RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__, |
4a8d1135 | 1510 | priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); |
8fc8598e JC |
1511 | |
1512 | ||
1111b876 | 1513 | if (priv->rf_chip == RF_PSEUDO_11N) { |
ec5d319b | 1514 | priv->SetBWModeInProgress = false; |
8fc8598e JC |
1515 | return; |
1516 | } | |
1517 | ||
5f2392b8 | 1518 | /* <1> Set MAC register */ |
b3d42bf1 | 1519 | read_nic_byte(dev, BW_OPMODE, ®BwOpMode); |
8fc8598e | 1520 | |
4a6094c3 | 1521 | switch (priv->CurrentChannelBW) { |
1db5aa05 XR |
1522 | case HT_CHANNEL_WIDTH_20: |
1523 | regBwOpMode |= BW_OPMODE_20MHZ; | |
1524 | /* We have not verify whether this register works */ | |
1525 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); | |
1526 | break; | |
8fc8598e | 1527 | |
1db5aa05 XR |
1528 | case HT_CHANNEL_WIDTH_20_40: |
1529 | regBwOpMode &= ~BW_OPMODE_20MHZ; | |
1530 | /* We have not verify whether this register works */ | |
1531 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); | |
1532 | break; | |
8fc8598e | 1533 | |
1db5aa05 XR |
1534 | default: |
1535 | RT_TRACE(COMP_ERR, | |
1536 | "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", | |
1537 | priv->CurrentChannelBW); | |
1538 | break; | |
8fc8598e JC |
1539 | } |
1540 | ||
5f2392b8 | 1541 | /* <2> Set PHY related register */ |
4a6094c3 | 1542 | switch (priv->CurrentChannelBW) { |
1db5aa05 XR |
1543 | case HT_CHANNEL_WIDTH_20: |
1544 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); | |
1545 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); | |
1546 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, | |
1547 | 0x00100000, 1); | |
1548 | ||
1549 | /* Correct the tx power for CCK rate in 20M. */ | |
1550 | priv->cck_present_attentuation = | |
1551 | priv->cck_present_attentuation_20Mdefault + | |
1552 | priv->cck_present_attentuation_difference; | |
1553 | ||
1554 | if (priv->cck_present_attentuation > 22) | |
1555 | priv->cck_present_attentuation = 22; | |
1556 | if (priv->cck_present_attentuation < 0) | |
1557 | priv->cck_present_attentuation = 0; | |
1558 | RT_TRACE(COMP_INIT, | |
1559 | "20M, pHalData->CCKPresentAttentuation = %d\n", | |
1560 | priv->cck_present_attentuation); | |
1561 | ||
1562 | if (priv->chan == 14 && !priv->bcck_in_ch14) { | |
4b2faf80 | 1563 | priv->bcck_in_ch14 = true; |
1db5aa05 XR |
1564 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
1565 | } else if (priv->chan != 14 && priv->bcck_in_ch14) { | |
4b2faf80 | 1566 | priv->bcck_in_ch14 = false; |
1db5aa05 XR |
1567 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
1568 | } else { | |
1569 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1570 | } | |
8fc8598e | 1571 | |
1db5aa05 XR |
1572 | break; |
1573 | case HT_CHANNEL_WIDTH_20_40: | |
1574 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); | |
1575 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); | |
1576 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, | |
1577 | priv->nCur40MhzPrimeSC>>1); | |
1578 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); | |
1579 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, | |
1580 | priv->nCur40MhzPrimeSC); | |
1581 | priv->cck_present_attentuation = | |
1582 | priv->cck_present_attentuation_40Mdefault + | |
1583 | priv->cck_present_attentuation_difference; | |
1584 | ||
1585 | if (priv->cck_present_attentuation > 22) | |
1586 | priv->cck_present_attentuation = 22; | |
1587 | if (priv->cck_present_attentuation < 0) | |
1588 | priv->cck_present_attentuation = 0; | |
1589 | ||
1590 | RT_TRACE(COMP_INIT, | |
1591 | "40M, pHalData->CCKPresentAttentuation = %d\n", | |
1592 | priv->cck_present_attentuation); | |
1593 | if (priv->chan == 14 && !priv->bcck_in_ch14) { | |
1594 | priv->bcck_in_ch14 = true; | |
1595 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1596 | } else if (priv->chan != 14 && priv->bcck_in_ch14) { | |
1597 | priv->bcck_in_ch14 = false; | |
1598 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1599 | } else { | |
1600 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1601 | } | |
8fc8598e | 1602 | |
1db5aa05 XR |
1603 | break; |
1604 | default: | |
1605 | RT_TRACE(COMP_ERR, | |
1606 | "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", | |
1607 | priv->CurrentChannelBW); | |
1608 | break; | |
8fc8598e JC |
1609 | |
1610 | } | |
5f2392b8 XR |
1611 | /* Skip over setting of J-mode in BB register here. |
1612 | Default value is "None J mode". */ | |
8fc8598e | 1613 | |
5f2392b8 | 1614 | /* <3> Set RF related register */ |
ceb56597 | 1615 | switch (priv->rf_chip) { |
1db5aa05 | 1616 | case RF_8225: |
8fc8598e | 1617 | #ifdef TO_DO_LIST |
1db5aa05 | 1618 | PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); |
8fc8598e | 1619 | #endif |
1db5aa05 | 1620 | break; |
8fc8598e | 1621 | |
1db5aa05 XR |
1622 | case RF_8256: |
1623 | PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); | |
1624 | break; | |
8fc8598e | 1625 | |
1db5aa05 XR |
1626 | case RF_8258: |
1627 | break; | |
8fc8598e | 1628 | |
1db5aa05 XR |
1629 | case RF_PSEUDO_11N: |
1630 | break; | |
8fc8598e | 1631 | |
1db5aa05 XR |
1632 | default: |
1633 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); | |
1634 | break; | |
8fc8598e | 1635 | } |
ec5d319b | 1636 | priv->SetBWModeInProgress = false; |
8fc8598e | 1637 | |
0081fcc6 | 1638 | RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n", |
1db5aa05 | 1639 | atomic_read(&priv->ieee80211->atm_swbw)); |
8fc8598e JC |
1640 | } |
1641 | ||
1642 | /****************************************************************************** | |
5f2392b8 XR |
1643 | * function: This function schedules bandwidth switch work. |
1644 | * input: struct net_deviceq *dev | |
1645 | * HT_CHANNEL_WIDTH bandwidth //20M or 40M | |
1646 | * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care | |
1647 | * output: none | |
1648 | * return: none | |
1649 | * notice: I doubt whether SetBWModeInProgress flag is necessary as we can | |
1650 | * test whether current work in the queue or not.//do I? | |
1651 | *****************************************************************************/ | |
79931639 XR |
1652 | void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth, |
1653 | HT_EXTCHNL_OFFSET offset) | |
8fc8598e JC |
1654 | { |
1655 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1656 | ||
1111b876 | 1657 | if (priv->SetBWModeInProgress) |
8fc8598e | 1658 | return; |
ec5d319b | 1659 | priv->SetBWModeInProgress = true; |
8fc8598e | 1660 | |
79931639 | 1661 | priv->CurrentChannelBW = bandwidth; |
8fc8598e | 1662 | |
79931639 | 1663 | if (offset == HT_EXTCHNL_OFFSET_LOWER) |
8fc8598e | 1664 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; |
79931639 | 1665 | else if (offset == HT_EXTCHNL_OFFSET_UPPER) |
8fc8598e JC |
1666 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; |
1667 | else | |
1668 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; | |
1669 | ||
8fc8598e JC |
1670 | rtl8192_SetBWModeWorkItem(dev); |
1671 | ||
1672 | } | |
1673 | ||
1674 | void InitialGain819xUsb(struct net_device *dev, u8 Operation) | |
1675 | { | |
1676 | struct r8192_priv *priv = ieee80211_priv(dev); | |
1677 | ||
1678 | priv->InitialGainOperateType = Operation; | |
1679 | ||
1111b876 | 1680 | if (priv->up) |
83e6d9e2 | 1681 | queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0); |
8fc8598e JC |
1682 | } |
1683 | ||
a115ee41 | 1684 | void InitialGainOperateWorkItemCallBack(struct work_struct *work) |
8fc8598e | 1685 | { |
1db5aa05 XR |
1686 | struct delayed_work *dwork = container_of(work, struct delayed_work, |
1687 | work); | |
1688 | struct r8192_priv *priv = container_of(dwork, struct r8192_priv, | |
1689 | initialgain_operate_wq); | |
1690 | struct net_device *dev = priv->ieee80211->dev; | |
8fc8598e JC |
1691 | #define SCAN_RX_INITIAL_GAIN 0x17 |
1692 | #define POWER_DETECTION_TH 0x08 | |
9f66ddb5 | 1693 | u32 bitmask; |
8fc8598e JC |
1694 | u8 initial_gain; |
1695 | u8 Operation; | |
1696 | ||
1697 | Operation = priv->InitialGainOperateType; | |
1698 | ||
4a6094c3 | 1699 | switch (Operation) { |
1db5aa05 XR |
1700 | case IG_Backup: |
1701 | RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); | |
1702 | initial_gain = SCAN_RX_INITIAL_GAIN; | |
1703 | bitmask = bMaskByte0; | |
1704 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) | |
1705 | /* FW DIG OFF */ | |
1706 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); | |
1707 | priv->initgain_backup.xaagccore1 = | |
1708 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask); | |
1709 | priv->initgain_backup.xbagccore1 = | |
1710 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask); | |
1711 | priv->initgain_backup.xcagccore1 = | |
1712 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask); | |
1713 | priv->initgain_backup.xdagccore1 = | |
1714 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask); | |
1715 | bitmask = bMaskByte2; | |
1716 | priv->initgain_backup.cca = | |
1717 | (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask); | |
1718 | ||
1719 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n", | |
1720 | priv->initgain_backup.xaagccore1); | |
1721 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n", | |
1722 | priv->initgain_backup.xbagccore1); | |
1723 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n", | |
1724 | priv->initgain_backup.xcagccore1); | |
1725 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n", | |
1726 | priv->initgain_backup.xdagccore1); | |
1727 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n", | |
1728 | priv->initgain_backup.cca); | |
1729 | ||
d5133e75 | 1730 | RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", |
1db5aa05 XR |
1731 | initial_gain); |
1732 | write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); | |
1733 | write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); | |
1734 | write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); | |
1735 | write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); | |
d5133e75 | 1736 | RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", |
1db5aa05 XR |
1737 | POWER_DETECTION_TH); |
1738 | write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); | |
1739 | break; | |
1740 | case IG_Restore: | |
1741 | RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); | |
1742 | bitmask = 0x7f; /* Bit0 ~ Bit6 */ | |
1743 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) | |
1744 | /* FW DIG OFF */ | |
1745 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); | |
1746 | ||
1747 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask, | |
1748 | (u32)priv->initgain_backup.xaagccore1); | |
1749 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask, | |
1750 | (u32)priv->initgain_backup.xbagccore1); | |
1751 | rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask, | |
1752 | (u32)priv->initgain_backup.xcagccore1); | |
1753 | rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask, | |
1754 | (u32)priv->initgain_backup.xdagccore1); | |
1755 | bitmask = bMaskByte2; | |
1756 | rtl8192_setBBreg(dev, rCCK0_CCA, bitmask, | |
1757 | (u32)priv->initgain_backup.cca); | |
1758 | ||
1759 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n", | |
1760 | priv->initgain_backup.xaagccore1); | |
1761 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n", | |
1762 | priv->initgain_backup.xbagccore1); | |
1763 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n", | |
1764 | priv->initgain_backup.xcagccore1); | |
1765 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n", | |
1766 | priv->initgain_backup.xdagccore1); | |
1767 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n", | |
1768 | priv->initgain_backup.cca); | |
8fc8598e | 1769 | |
1db5aa05 | 1770 | rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel); |
8fc8598e | 1771 | |
1db5aa05 XR |
1772 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
1773 | /* FW DIG ON */ | |
1774 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); | |
1775 | break; | |
1776 | default: | |
d5133e75 | 1777 | RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); |
1db5aa05 | 1778 | break; |
8fc8598e JC |
1779 | } |
1780 | } |