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1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | *******************************************************************************/ | |
15 | #ifndef __RTL8723A_SPEC_H__ | |
16 | #define __RTL8723A_SPEC_H__ | |
17 | ||
18 | /* */ | |
19 | /* */ | |
20 | /* 0x0000h ~ 0x00FFh System Configuration */ | |
21 | /* */ | |
22 | /* */ | |
23 | #define REG_SYS_ISO_CTRL 0x0000 | |
24 | #define REG_SYS_FUNC_EN 0x0002 | |
25 | #define REG_APS_FSMCO 0x0004 | |
26 | #define REG_SYS_CLKR 0x0008 | |
27 | #define REG_9346CR 0x000A | |
28 | #define REG_EE_VPD 0x000C | |
29 | #define REG_AFE_MISC 0x0010 | |
30 | #define REG_SPS0_CTRL 0x0011 | |
31 | #define REG_SPS_OCP_CFG 0x0018 | |
32 | #define REG_RSV_CTRL 0x001C | |
33 | #define REG_RF_CTRL 0x001F | |
34 | #define REG_LDOA15_CTRL 0x0020 | |
35 | #define REG_LDOV12D_CTRL 0x0021 | |
36 | #define REG_LDOHCI12_CTRL 0x0022 | |
37 | #define REG_LPLDO_CTRL 0x0023 | |
38 | #define REG_AFE_XTAL_CTRL 0x0024 | |
39 | #define REG_AFE_PLL_CTRL 0x0028 | |
40 | #define REG_MAC_PHY_CTRL 0x002c | |
41 | #define REG_EFUSE_CTRL 0x0030 | |
42 | #define REG_EFUSE_TEST 0x0034 | |
43 | #define REG_PWR_DATA 0x0038 | |
44 | #define REG_CAL_TIMER 0x003C | |
45 | #define REG_ACLK_MON 0x003E | |
46 | #define REG_GPIO_MUXCFG 0x0040 | |
47 | #define REG_GPIO_IO_SEL 0x0042 | |
48 | #define REG_MAC_PINMUX_CFG 0x0043 | |
49 | #define REG_GPIO_PIN_CTRL 0x0044 | |
50 | #define REG_GPIO_INTM 0x0048 | |
51 | #define REG_LEDCFG0 0x004C | |
52 | #define REG_LEDCFG1 0x004D | |
53 | #define REG_LEDCFG2 0x004E | |
54 | #define REG_LEDCFG3 0x004F | |
55 | #define REG_LEDCFG REG_LEDCFG2 | |
56 | #define REG_FSIMR 0x0050 | |
57 | #define REG_FSISR 0x0054 | |
58 | #define REG_HSIMR 0x0058 | |
59 | #define REG_HSISR 0x005c | |
60 | /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ | |
61 | #define REG_GPIO_PIN_CTRL_2 0x0060 | |
62 | /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ | |
63 | #define REG_GPIO_IO_SEL_2 0x0062 | |
64 | /* RTL8723 WIFI/BT/GPS Multi-Function control source. */ | |
65 | #define REG_MULTI_FUNC_CTRL 0x0068 | |
66 | #define REG_MCUFWDL 0x0080 | |
67 | #define REG_HMEBOX_EXT_0 0x0088 | |
68 | #define REG_HMEBOX_EXT_1 0x008A | |
69 | #define REG_HMEBOX_EXT_2 0x008C | |
70 | #define REG_HMEBOX_EXT_3 0x008E | |
71 | /* Host suspend counter on FPGA platform */ | |
72 | #define REG_HOST_SUSP_CNT 0x00BC | |
73 | /* Efuse access protection for RTL8723 */ | |
74 | #define REG_EFUSE_ACCESS 0x00CF | |
75 | #define REG_BIST_SCAN 0x00D0 | |
76 | #define REG_BIST_RPT 0x00D4 | |
77 | #define REG_BIST_ROM_RPT 0x00D8 | |
78 | #define REG_USB_SIE_INTF 0x00E0 | |
79 | #define REG_PCIE_MIO_INTF 0x00E4 | |
80 | #define REG_PCIE_MIO_INTD 0x00E8 | |
81 | #define REG_HPON_FSM 0x00EC | |
82 | #define REG_SYS_CFG 0x00F0 | |
83 | #define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ | |
84 | ||
85 | /* */ | |
86 | /* */ | |
87 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ | |
88 | /* */ | |
89 | /* */ | |
90 | #define REG_CR 0x0100 | |
91 | #define REG_PBP 0x0104 | |
92 | #define REG_TRXDMA_CTRL 0x010C | |
93 | #define REG_TRXFF_BNDY 0x0114 | |
94 | #define REG_TRXFF_STATUS 0x0118 | |
95 | #define REG_RXFF_PTR 0x011C | |
96 | #define REG_HIMR 0x0120 | |
97 | #define REG_HISR 0x0124 | |
98 | #define REG_HIMRE 0x0128 | |
99 | #define REG_HISRE 0x012C | |
100 | #define REG_CPWM 0x012F | |
101 | #define REG_FWIMR 0x0130 | |
102 | #define REG_FWISR 0x0134 | |
103 | #define REG_PKTBUF_DBG_CTRL 0x0140 | |
104 | #define REG_PKTBUF_DBG_DATA_L 0x0144 | |
105 | #define REG_PKTBUF_DBG_DATA_H 0x0148 | |
106 | ||
107 | #define REG_TC0_CTRL 0x0150 | |
108 | #define REG_TC1_CTRL 0x0154 | |
109 | #define REG_TC2_CTRL 0x0158 | |
110 | #define REG_TC3_CTRL 0x015C | |
111 | #define REG_TC4_CTRL 0x0160 | |
112 | #define REG_TCUNIT_BASE 0x0164 | |
113 | #define REG_MBIST_START 0x0174 | |
114 | #define REG_MBIST_DONE 0x0178 | |
115 | #define REG_MBIST_FAIL 0x017C | |
116 | #define REG_C2HEVT_MSG_NORMAL 0x01A0 | |
117 | #define REG_C2HEVT_CLEAR 0x01AF | |
118 | #define REG_C2HEVT_MSG_TEST 0x01B8 | |
119 | #define REG_MCUTST_1 0x01c0 | |
120 | #define REG_FMETHR 0x01C8 | |
121 | #define REG_HMETFR 0x01CC | |
122 | #define REG_HMEBOX_0 0x01D0 | |
123 | #define REG_HMEBOX_1 0x01D4 | |
124 | #define REG_HMEBOX_2 0x01D8 | |
125 | #define REG_HMEBOX_3 0x01DC | |
126 | ||
127 | #define REG_LLT_INIT 0x01E0 | |
128 | #define REG_BB_ACCEESS_CTRL 0x01E8 | |
129 | #define REG_BB_ACCESS_DATA 0x01EC | |
130 | ||
131 | ||
132 | /* */ | |
133 | /* */ | |
134 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ | |
135 | /* */ | |
136 | /* */ | |
137 | #define REG_RQPN 0x0200 | |
138 | #define REG_FIFOPAGE 0x0204 | |
139 | #define REG_TDECTRL 0x0208 | |
140 | #define REG_TXDMA_OFFSET_CHK 0x020C | |
141 | #define REG_TXDMA_STATUS 0x0210 | |
142 | #define REG_RQPN_NPQ 0x0214 | |
143 | ||
144 | /* */ | |
145 | /* */ | |
146 | /* 0x0280h ~ 0x02FFh RXDMA Configuration */ | |
147 | /* */ | |
148 | /* */ | |
149 | #define REG_RXDMA_AGG_PG_TH 0x0280 | |
150 | #define REG_RXPKT_NUM 0x0284 | |
151 | #define REG_RXDMA_STATUS 0x0288 | |
152 | ||
153 | ||
154 | /* */ | |
155 | /* */ | |
156 | /* 0x0300h ~ 0x03FFh PCIe */ | |
157 | /* */ | |
158 | /* */ | |
159 | #define REG_PCIE_CTRL_REG 0x0300 | |
160 | #define REG_INT_MIG 0x0304 /* Interrupt Migration */ | |
161 | /* TX Beacon Descriptor Address */ | |
162 | #define REG_BCNQ_DESA 0x0308 | |
163 | /* TX High Queue Descriptor Address */ | |
164 | #define REG_HQ_DESA 0x0310 | |
165 | /* TX Manage Queue Descriptor Address */ | |
166 | #define REG_MGQ_DESA 0x0318 | |
167 | /* TX VO Queue Descriptor Address */ | |
168 | #define REG_VOQ_DESA 0x0320 | |
169 | /* TX VI Queue Descriptor Address */ | |
170 | #define REG_VIQ_DESA 0x0328 | |
171 | /* TX BE Queue Descriptor Address */ | |
172 | #define REG_BEQ_DESA 0x0330 | |
173 | /* TX BK Queue Descriptor Address */ | |
174 | #define REG_BKQ_DESA 0x0338 | |
175 | /* RX Queue Descriptor Address */ | |
176 | #define REG_RX_DESA 0x0340 | |
177 | /* Backdoor REG for Access Configuration */ | |
178 | #define REG_DBI 0x0348 | |
179 | /* MDIO for Access PCIE PHY */ | |
180 | #define REG_MDIO 0x0354 | |
181 | /* Debug Selection Register */ | |
182 | #define REG_DBG_SEL 0x0360 | |
183 | /* PCIe RPWM */ | |
184 | #define REG_PCIE_HRPWM 0x0361 | |
185 | /* PCIe CPWM */ | |
186 | #define REG_PCIE_HCPWM 0x0363 | |
187 | /* UART Control */ | |
188 | #define REG_UART_CTRL 0x0364 | |
189 | /* UART TX Descriptor Address */ | |
190 | #define REG_UART_TX_DESA 0x0370 | |
191 | /* UART Rx Descriptor Address */ | |
192 | #define REG_UART_RX_DESA 0x0378 | |
193 | ||
194 | ||
195 | /* spec version 11 */ | |
196 | /* */ | |
197 | /* */ | |
198 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ | |
199 | /* */ | |
200 | /* */ | |
201 | #define REG_VOQ_INFORMATION 0x0400 | |
202 | #define REG_VIQ_INFORMATION 0x0404 | |
203 | #define REG_BEQ_INFORMATION 0x0408 | |
204 | #define REG_BKQ_INFORMATION 0x040C | |
205 | #define REG_MGQ_INFORMATION 0x0410 | |
206 | #define REG_HGQ_INFORMATION 0x0414 | |
207 | #define REG_BCNQ_INFORMATION 0x0418 | |
208 | ||
209 | ||
210 | #define REG_CPU_MGQ_INFORMATION 0x041C | |
211 | #define REG_FWHW_TXQ_CTRL 0x0420 | |
212 | #define REG_HWSEQ_CTRL 0x0423 | |
213 | #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 | |
214 | #define REG_TXPKTBUF_MGQ_BDNY 0x0425 | |
215 | #define REG_LIFETIME_EN 0x0426 | |
216 | #define REG_MULTI_BCNQ_OFFSET 0x0427 | |
217 | #define REG_SPEC_SIFS 0x0428 | |
218 | #define REG_RL 0x042A | |
219 | #define REG_DARFRC 0x0430 | |
220 | #define REG_RARFRC 0x0438 | |
221 | #define REG_RRSR 0x0440 | |
222 | #define REG_ARFR0 0x0444 | |
223 | #define REG_ARFR1 0x0448 | |
224 | #define REG_ARFR2 0x044C | |
225 | #define REG_ARFR3 0x0450 | |
226 | #define REG_AGGLEN_LMT 0x0458 | |
227 | #define REG_AMPDU_MIN_SPACE 0x045C | |
228 | #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D | |
229 | #define REG_FAST_EDCA_CTRL 0x0460 | |
230 | #define REG_RD_RESP_PKT_TH 0x0463 | |
231 | #define REG_INIRTS_RATE_SEL 0x0480 | |
232 | #define REG_INIDATA_RATE_SEL 0x0484 | |
233 | ||
234 | ||
235 | #define REG_POWER_STATUS 0x04A4 | |
236 | #define REG_POWER_STAGE1 0x04B4 | |
237 | #define REG_POWER_STAGE2 0x04B8 | |
238 | #define REG_PKT_VO_VI_LIFE_TIME 0x04C0 | |
239 | #define REG_PKT_BE_BK_LIFE_TIME 0x04C2 | |
240 | #define REG_STBC_SETTING 0x04C4 | |
241 | #define REG_PROT_MODE_CTRL 0x04C8 | |
242 | #define REG_MAX_AGGR_NUM 0x04CA | |
243 | #define REG_RTS_MAX_AGGR_NUM 0x04CB | |
244 | #define REG_BAR_MODE_CTRL 0x04CC | |
245 | #define REG_RA_TRY_RATE_AGG_LMT 0x04CF | |
246 | #define REG_NQOS_SEQ 0x04DC | |
247 | #define REG_QOS_SEQ 0x04DE | |
248 | #define REG_NEED_CPU_HANDLE 0x04E0 | |
249 | #define REG_PKT_LOSE_RPT 0x04E1 | |
250 | #define REG_PTCL_ERR_STATUS 0x04E2 | |
251 | #define REG_DUMMY 0x04FC | |
252 | ||
253 | ||
254 | ||
255 | /* */ | |
256 | /* */ | |
257 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ | |
258 | /* */ | |
259 | /* */ | |
260 | #define REG_EDCA_VO_PARAM 0x0500 | |
261 | #define REG_EDCA_VI_PARAM 0x0504 | |
262 | #define REG_EDCA_BE_PARAM 0x0508 | |
263 | #define REG_EDCA_BK_PARAM 0x050C | |
264 | #define REG_BCNTCFG 0x0510 | |
265 | #define REG_PIFS 0x0512 | |
266 | #define REG_RDG_PIFS 0x0513 | |
267 | #define REG_SIFS_CCK 0x0514 | |
268 | #define REG_SIFS_OFDM 0x0516 | |
269 | #define REG_SIFS_CTX 0x0514 | |
270 | #define REG_SIFS_TRX 0x0516 | |
271 | #define REG_TSFTR_SYN_OFFSET 0x0518 | |
272 | #define REG_AGGR_BREAK_TIME 0x051A | |
273 | #define REG_SLOT 0x051B | |
274 | #define REG_TX_PTCL_CTRL 0x0520 | |
275 | #define REG_TXPAUSE 0x0522 | |
276 | #define REG_DIS_TXREQ_CLR 0x0523 | |
277 | #define REG_RD_CTRL 0x0524 | |
278 | #define REG_TBTT_PROHIBIT 0x0540 | |
279 | #define REG_RD_NAV_NXT 0x0544 | |
280 | #define REG_NAV_PROT_LEN 0x0546 | |
281 | #define REG_BCN_CTRL 0x0550 | |
282 | #define REG_BCN_CTRL_1 0x0551 | |
283 | #define REG_MBID_NUM 0x0552 | |
284 | #define REG_DUAL_TSF_RST 0x0553 | |
285 | /* The same as REG_MBSSID_BCN_SPACE */ | |
286 | #define REG_BCN_INTERVAL 0x0554 | |
287 | #define REG_MBSSID_BCN_SPACE 0x0554 | |
288 | #define REG_DRVERLYINT 0x0558 | |
289 | #define REG_BCNDMATIM 0x0559 | |
290 | #define REG_ATIMWND 0x055A | |
291 | #define REG_BCN_MAX_ERR 0x055D | |
292 | #define REG_RXTSF_OFFSET_CCK 0x055E | |
293 | #define REG_RXTSF_OFFSET_OFDM 0x055F | |
294 | #define REG_TSFTR 0x0560 | |
295 | #define REG_TSFTR1 0x0568 | |
296 | #define REG_INIT_TSFTR 0x0564 | |
297 | #define REG_ATIMWND_1 0x0570 | |
298 | #define REG_PSTIMER 0x0580 | |
299 | #define REG_TIMER0 0x0584 | |
300 | #define REG_TIMER1 0x0588 | |
301 | #define REG_ACMHWCTRL 0x05C0 | |
302 | #define REG_ACMRSTCTRL 0x05C1 | |
303 | #define REG_ACMAVG 0x05C2 | |
304 | #define REG_VO_ADMTIME 0x05C4 | |
305 | #define REG_VI_ADMTIME 0x05C6 | |
306 | #define REG_BE_ADMTIME 0x05C8 | |
307 | #define REG_EDCA_RANDOM_GEN 0x05CC | |
308 | #define REG_SCH_TXCMD 0x05D0 | |
309 | ||
310 | /* define REG_FW_TSF_SYNC_CNT 0x04A0 */ | |
311 | #define REG_FW_RESET_TSF_CNT_1 0x05FC | |
312 | #define REG_FW_RESET_TSF_CNT_0 0x05FD | |
313 | #define REG_FW_BCN_DIS_CNT 0x05FE | |
314 | ||
315 | /* */ | |
316 | /* */ | |
317 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ | |
318 | /* */ | |
319 | /* */ | |
320 | #define REG_APSD_CTRL 0x0600 | |
321 | #define REG_BWOPMODE 0x0603 | |
322 | #define REG_TCR 0x0604 | |
323 | #define REG_RCR 0x0608 | |
324 | #define REG_RX_PKT_LIMIT 0x060C | |
325 | #define REG_RX_DLK_TIME 0x060D | |
326 | #define REG_RX_DRVINFO_SZ 0x060F | |
327 | ||
328 | #define REG_MACID 0x0610 | |
329 | #define REG_BSSID 0x0618 | |
330 | #define REG_MAR 0x0620 | |
331 | #define REG_MBIDCAMCFG 0x0628 | |
332 | ||
333 | #define REG_USTIME_EDCA 0x0638 | |
334 | #define REG_MAC_SPEC_SIFS 0x063A | |
335 | ||
336 | /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ | |
337 | /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ | |
338 | #define REG_R2T_SIFS 0x063C | |
339 | /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ | |
340 | #define REG_T2T_SIFS 0x063E | |
341 | #define REG_ACKTO 0x0640 | |
342 | #define REG_CTS2TO 0x0641 | |
343 | #define REG_EIFS 0x0642 | |
344 | ||
345 | /* WMA, BA, CCX */ | |
346 | #define REG_NAV_CTRL 0x0650 | |
347 | #define REG_BACAMCMD 0x0654 | |
348 | #define REG_BACAMCONTENT 0x0658 | |
349 | #define REG_LBDLY 0x0660 | |
350 | #define REG_FWDLY 0x0661 | |
351 | #define REG_RXERR_RPT 0x0664 | |
352 | #define REG_WMAC_TRXPTCL_CTL 0x0668 | |
353 | ||
354 | ||
355 | /* Security */ | |
356 | #define REG_CAMCMD 0x0670 | |
357 | #define REG_CAMWRITE 0x0674 | |
358 | #define REG_CAMREAD 0x0678 | |
359 | #define REG_CAMDBG 0x067C | |
360 | #define REG_SECCFG 0x0680 | |
361 | ||
362 | /* Power */ | |
363 | #define REG_WOW_CTRL 0x0690 | |
364 | #define REG_PSSTATUS 0x0691 | |
365 | #define REG_PS_RX_INFO 0x0692 | |
366 | #define REG_LPNAV_CTRL 0x0694 | |
367 | #define REG_WKFMCAM_CMD 0x0698 | |
368 | #define REG_WKFMCAM_RWD 0x069C | |
369 | #define REG_RXFLTMAP0 0x06A0 | |
370 | #define REG_RXFLTMAP1 0x06A2 | |
371 | #define REG_RXFLTMAP2 0x06A4 | |
372 | #define REG_BCN_PSR_RPT 0x06A8 | |
373 | #define REG_CALB32K_CTRL 0x06AC | |
374 | #define REG_PKT_MON_CTRL 0x06B4 | |
375 | #define REG_BT_COEX_TABLE 0x06C0 | |
376 | #define REG_WMAC_RESP_TXINFO 0x06D8 | |
377 | ||
378 | #define REG_MACID1 0x0700 | |
379 | #define REG_BSSID1 0x0708 | |
380 | ||
381 | ||
382 | /* */ | |
383 | /* */ | |
384 | /* 0xFE00h ~ 0xFE55h USB Configuration */ | |
385 | /* */ | |
386 | /* */ | |
387 | #define REG_USB_INFO 0xFE17 | |
388 | #define REG_USB_SPECIAL_OPTION 0xFE55 | |
389 | #define REG_USB_DMA_AGG_TO 0xFE5B | |
390 | #define REG_USB_AGG_TO 0xFE5C | |
391 | #define REG_USB_AGG_TH 0xFE5D | |
392 | ||
393 | /* For test chip */ | |
394 | #define REG_TEST_USB_TXQS 0xFE48 | |
395 | #define REG_TEST_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ | |
396 | #define REG_TEST_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ | |
397 | #define REG_TEST_SIE_OPTIONAL 0xFE64 | |
398 | #define REG_TEST_SIE_CHIRP_K 0xFE65 | |
399 | #define REG_TEST_SIE_PHY 0xFE66 /* 0xFE66~0xFE6B */ | |
400 | #define REG_TEST_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ | |
401 | #define REG_TEST_SIE_STRING 0xFE80 /* 0xFE80~0xFEB9 */ | |
402 | ||
403 | ||
404 | /* For normal chip */ | |
405 | #define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ | |
406 | #define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ | |
407 | #define REG_NORMAL_SIE_OPTIONAL 0xFE64 | |
408 | #define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ | |
409 | #define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ | |
410 | #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C | |
411 | #define REG_NORMAL_SIE_GPS_EP 0xFE6D /* RTL8723 only */ | |
412 | #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ | |
413 | #define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ | |
414 | ||
415 | ||
416 | /* */ | |
417 | /* */ | |
418 | /* Redifine 8192C register definition for compatibility */ | |
419 | /* */ | |
420 | /* */ | |
421 | ||
422 | /* TODO: use these definition when using REG_xxx naming rule. */ | |
423 | /* NOTE: DO NOT Remove these definition. Use later. */ | |
424 | ||
425 | /* System Isolation Interface Control. */ | |
426 | #define SYS_ISO_CTRL REG_SYS_ISO_CTRL | |
427 | /* System Function Enable. */ | |
428 | #define SYS_FUNC_EN REG_SYS_FUNC_EN | |
429 | #define SYS_CLK REG_SYS_CLKR | |
430 | /* 93C46/93C56 Command Register. */ | |
431 | #define CR9346 REG_9346CR | |
432 | /* E-Fuse Control. */ | |
433 | #define EFUSE_CTRL REG_EFUSE_CTRL | |
434 | /* E-Fuse Test. */ | |
435 | #define EFUSE_TEST REG_EFUSE_TEST | |
436 | /* Media Status register */ | |
437 | #define MSR (REG_CR + 2) | |
438 | #define ISR REG_HISR | |
439 | /* Timing Sync Function Timer Register. */ | |
440 | #define TSFR REG_TSFTR | |
441 | ||
442 | /* MAC ID Register, Offset 0x0050-0x0053 */ | |
443 | #define MACIDR0 REG_MACID | |
444 | /* MAC ID Register, Offset 0x0054-0x0055 */ | |
445 | #define MACIDR4 (REG_MACID + 4) | |
446 | ||
447 | #define PBP REG_PBP | |
448 | ||
449 | /* Redifine MACID register, to compatible prior ICs. */ | |
450 | #define IDR0 MACIDR0 | |
451 | #define IDR4 MACIDR4 | |
452 | ||
453 | ||
454 | /* */ | |
455 | /* 9. Security Control Registers (Offset: ) */ | |
456 | /* */ | |
364e30eb LF |
457 | /* Software write CAM input content */ |
458 | #define WCAMI REG_CAMWRITE | |
459 | /* Software read/write CAM config */ | |
460 | #define RCAMO REG_CAMREAD | |
461 | #define CAMDBG REG_CAMDBG | |
462 | /* Security Configuration Register */ | |
463 | #define SECR REG_SECCFG | |
464 | ||
465 | /* Unused register */ | |
466 | #define UnusedRegister 0x1BF | |
467 | #define DCAM UnusedRegister | |
468 | #define PSR UnusedRegister | |
469 | #define BBAddr UnusedRegister | |
470 | #define PhyDataR UnusedRegister | |
471 | ||
472 | #define InvalidBBRFValue 0x12345678 | |
473 | ||
474 | /* Min Spacing related settings. */ | |
475 | #define MAX_MSS_DENSITY_2T 0x13 | |
476 | #define MAX_MSS_DENSITY_1T 0x0A | |
477 | ||
478 | /* */ | |
479 | /* 8192C Cmd9346CR bits (Offset 0xA, 16bit) */ | |
480 | /* */ | |
481 | /* EEPROM enable when set 1 */ | |
9c45c20d | 482 | #define CmdEEPROM_En BIT(5) |
364e30eb LF |
483 | /* System EEPROM select, 0: boot from E-FUSE, |
484 | 1: The EEPROM used is 9346 */ | |
9c45c20d JS |
485 | #define CmdEERPOMSEL BIT(4) |
486 | #define Cmd9346CR_9356SEL BIT(4) | |
364e30eb LF |
487 | #define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) |
488 | #define AutoLoadEFUSE CmdEEPROM_En | |
489 | ||
490 | /* */ | |
491 | /* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ | |
492 | /* */ | |
493 | #define GPIOSEL_GPIO 0 | |
9c45c20d | 494 | #define GPIOSEL_ENBT BIT(5) |
364e30eb LF |
495 | |
496 | /* */ | |
497 | /* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ | |
498 | /* */ | |
499 | /* GPIO pins input value */ | |
500 | #define GPIO_IN REG_GPIO_PIN_CTRL | |
501 | /* GPIO pins output value */ | |
502 | #define GPIO_OUT (REG_GPIO_PIN_CTRL+1) | |
503 | /* GPIO pins output enable when a bit is set to "1"; | |
504 | otherwise, input is configured. */ | |
505 | #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) | |
506 | #define GPIO_MOD (REG_GPIO_PIN_CTRL+3) | |
507 | ||
508 | /* */ | |
509 | /* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ | |
510 | /* */ | |
511 | /* | |
512 | Network Type | |
513 | 00: No link | |
514 | 01: Link in ad hoc network | |
515 | 10: Link in infrastructure network | |
516 | 11: AP mode | |
517 | Default: 00b. | |
518 | */ | |
519 | #define MSR_NOLINK 0x00 | |
520 | #define MSR_ADHOC 0x01 | |
521 | #define MSR_INFRA 0x02 | |
522 | #define MSR_AP 0x03 | |
523 | ||
524 | /* */ | |
525 | /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ | |
526 | /* */ | |
527 | /* */ | |
528 | /* 8192C Response Rate Set Register (offset 0x181, 24bits) */ | |
529 | /* */ | |
530 | #define RRSR_RSC_OFFSET 21 | |
531 | #define RRSR_SHORT_OFFSET 23 | |
532 | #define RRSR_RSC_BW_40M 0x600000 | |
533 | #define RRSR_RSC_UPSUBCHNL 0x400000 | |
534 | #define RRSR_RSC_LOWSUBCHNL 0x200000 | |
535 | #define RRSR_SHORT 0x800000 | |
9c45c20d JS |
536 | #define RRSR_1M BIT(0) |
537 | #define RRSR_2M BIT(1) | |
538 | #define RRSR_5_5M BIT(2) | |
539 | #define RRSR_11M BIT(3) | |
540 | #define RRSR_6M BIT(4) | |
541 | #define RRSR_9M BIT(5) | |
542 | #define RRSR_12M BIT(6) | |
543 | #define RRSR_18M BIT(7) | |
544 | #define RRSR_24M BIT(8) | |
545 | #define RRSR_36M BIT(9) | |
546 | #define RRSR_48M BIT(10) | |
547 | #define RRSR_54M BIT(11) | |
548 | #define RRSR_MCS0 BIT(12) | |
549 | #define RRSR_MCS1 BIT(13) | |
550 | #define RRSR_MCS2 BIT(14) | |
551 | #define RRSR_MCS3 BIT(15) | |
552 | #define RRSR_MCS4 BIT(16) | |
553 | #define RRSR_MCS5 BIT(17) | |
554 | #define RRSR_MCS6 BIT(18) | |
555 | #define RRSR_MCS7 BIT(19) | |
556 | #define BRSR_AckShortPmb BIT(23) | |
364e30eb LF |
557 | /* CCK ACK: use Short Preamble or not */ |
558 | ||
559 | /* */ | |
560 | /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ | |
561 | /* */ | |
9c45c20d JS |
562 | #define BW_OPMODE_20MHZ BIT(2) |
563 | #define BW_OPMODE_5G BIT(1) | |
564 | #define BW_OPMODE_11J BIT(0) | |
364e30eb LF |
565 | |
566 | ||
567 | /* */ | |
568 | /* 8192C CAM Config Setting (offset 0x250, 1 byte) */ | |
569 | /* */ | |
9c45c20d | 570 | #define CAM_VALID BIT(15) |
364e30eb | 571 | #define CAM_NOTVALID 0x0000 |
9c45c20d | 572 | #define CAM_USEDK BIT(5) |
364e30eb LF |
573 | |
574 | #define CAM_CONTENT_COUNT 8 | |
575 | ||
576 | #define CAM_NONE 0x0 | |
577 | #define CAM_WEP40 0x01 | |
578 | #define CAM_TKIP 0x02 | |
579 | #define CAM_AES 0x04 | |
580 | #define CAM_WEP104 0x05 | |
581 | ||
582 | #define TOTAL_CAM_ENTRY 32 | |
583 | #define HALF_CAM_ENTRY 16 | |
584 | ||
585 | #define CAM_CONFIG_USEDK true | |
586 | #define CAM_CONFIG_NO_USEDK false | |
587 | ||
9c45c20d | 588 | #define CAM_WRITE BIT(16) |
364e30eb | 589 | #define CAM_READ 0x00000000 |
9c45c20d | 590 | #define CAM_POLLINIG BIT(31) |
364e30eb LF |
591 | |
592 | #define SCR_UseDK 0x01 | |
593 | #define SCR_TxSecEnable 0x02 | |
594 | #define SCR_RxSecEnable 0x04 | |
595 | ||
596 | ||
597 | /* */ | |
598 | /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ | |
599 | /* */ | |
600 | /* */ | |
601 | /* 8190 IMR/ISR bits (offset 0xfd, 8bits) */ | |
602 | /* */ | |
603 | #define IMR8190_DISABLED 0x0 | |
604 | /* IMR DW0 Bit 0-31 */ | |
605 | ||
9c45c20d JS |
606 | #define IMR_BCNDMAINT6 BIT(31) /* Beacon DMA Interrupt 6 */ |
607 | #define IMR_BCNDMAINT5 BIT(30) /* Beacon DMA Interrupt 5 */ | |
608 | #define IMR_BCNDMAINT4 BIT(29) /* Beacon DMA Interrupt 4 */ | |
609 | #define IMR_BCNDMAINT3 BIT(28) /* Beacon DMA Interrupt 3 */ | |
610 | #define IMR_BCNDMAINT2 BIT(27) /* Beacon DMA Interrupt 2 */ | |
611 | #define IMR_BCNDMAINT1 BIT(26) /* Beacon DMA Interrupt 1 */ | |
612 | #define IMR_BCNDOK8 BIT(25) /* Beacon Queue DMA OK | |
364e30eb | 613 | Interrupt 8 */ |
9c45c20d | 614 | #define IMR_BCNDOK7 BIT(24) /* Beacon Queue DMA OK |
364e30eb | 615 | Interrupt 7 */ |
9c45c20d | 616 | #define IMR_BCNDOK6 BIT(23) /* Beacon Queue DMA OK |
364e30eb | 617 | Interrupt 6 */ |
9c45c20d | 618 | #define IMR_BCNDOK5 BIT(22) /* Beacon Queue DMA OK |
364e30eb | 619 | Interrupt 5 */ |
9c45c20d | 620 | #define IMR_BCNDOK4 BIT(21) /* Beacon Queue DMA OK |
364e30eb | 621 | Interrupt 4 */ |
9c45c20d | 622 | #define IMR_BCNDOK3 BIT(20) /* Beacon Queue DMA OK |
364e30eb | 623 | Interrupt 3 */ |
9c45c20d | 624 | #define IMR_BCNDOK2 BIT(19) /* Beacon Queue DMA OK |
364e30eb | 625 | Interrupt 2 */ |
9c45c20d | 626 | #define IMR_BCNDOK1 BIT(18) /* Beacon Queue DMA OK |
364e30eb | 627 | Interrupt 1 */ |
9c45c20d JS |
628 | #define IMR_TIMEOUT2 BIT(17) /* Timeout interrupt 2 */ |
629 | #define IMR_TIMEOUT1 BIT(16) /* Timeout interrupt 1 */ | |
630 | #define IMR_TXFOVW BIT(15) /* Transmit FIFO Overflow */ | |
631 | #define IMR_PSTIMEOUT BIT(14) /* Power save time out | |
364e30eb | 632 | interrupt */ |
9c45c20d JS |
633 | #define IMR_BcnInt BIT(13) /* Beacon DMA Interrupt 0 */ |
634 | #define IMR_RXFOVW BIT(12) /* Receive FIFO Overflow */ | |
635 | #define IMR_RDU BIT(11) /* Receive Descriptor | |
364e30eb | 636 | Unavailable */ |
9c45c20d | 637 | #define IMR_ATIMEND BIT(10) /* For 92C,ATIM Window |
364e30eb | 638 | End Interrupt */ |
9c45c20d | 639 | #define IMR_BDOK BIT(9) /* Beacon Queue DMA OK |
364e30eb | 640 | Interrup */ |
9c45c20d | 641 | #define IMR_HIGHDOK BIT(8) /* High Queue DMA OK |
364e30eb | 642 | Interrupt */ |
9c45c20d | 643 | #define IMR_TBDOK BIT(7) /* Transmit Beacon OK |
364e30eb | 644 | interrup */ |
9c45c20d | 645 | #define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK |
364e30eb | 646 | Interrupt */ |
9c45c20d | 647 | #define IMR_TBDER BIT(5) /* For 92C,Transmit Beacon |
364e30eb | 648 | Error Interrupt */ |
9c45c20d JS |
649 | #define IMR_BKDOK BIT(4) /* AC_BK DMA OK Interrupt */ |
650 | #define IMR_BEDOK BIT(3) /* AC_BE DMA OK Interrupt */ | |
651 | #define IMR_VIDOK BIT(2) /* AC_VI DMA OK Interrupt */ | |
652 | #define IMR_VODOK BIT(1) /* AC_VO DMA Interrupt */ | |
653 | #define IMR_ROK BIT(0) /* Receive DMA OK Interrupt */ | |
364e30eb LF |
654 | |
655 | #define IMR_RX_MASK (IMR_ROK|IMR_RDU|IMR_RXFOVW) | |
656 | #define IMR_TX_MASK (IMR_VODOK|IMR_VIDOK|IMR_BEDOK| \ | |
657 | IMR_BKDOK|IMR_MGNTDOK|IMR_HIGHDOK| \ | |
658 | IMR_BDOK) | |
659 | ||
660 | /* 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) */ | |
9c45c20d JS |
661 | #define IMR_BcnInt_E BIT(12) |
662 | #define IMR_TXERR BIT(11) | |
663 | #define IMR_RXERR BIT(10) | |
664 | #define IMR_C2HCMD BIT(9) | |
665 | #define IMR_CPWM BIT(8) | |
364e30eb | 666 | /* RSVD [2-7] */ |
9c45c20d JS |
667 | #define IMR_OCPINT BIT(1) |
668 | #define IMR_WLANOFF BIT(0) | |
364e30eb LF |
669 | |
670 | ||
671 | /* 8192C EEPROM/EFUSE share register definition. */ | |
672 | ||
673 | /* Default Value for EEPROM or EFUSE!!! */ | |
674 | #define EEPROM_Default_TSSI 0x0 | |
675 | #define EEPROM_Default_TxPowerDiff 0x0 | |
676 | #define EEPROM_Default_CrystalCap 0x5 | |
677 | /* Default: 2X2, RTL8192CE(QFPN68) */ | |
678 | #define EEPROM_Default_BoardType 0x02 | |
679 | #define EEPROM_Default_TxPower 0x1010 | |
680 | #define EEPROM_Default_HT2T_TxPwr 0x10 | |
681 | ||
682 | #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 | |
683 | #define EEPROM_Default_ThermalMeter 0x12 | |
684 | ||
685 | #define EEPROM_Default_AntTxPowerDiff 0x0 | |
686 | #define EEPROM_Default_TxPwDiff_CrystalCap 0x5 | |
687 | #define EEPROM_Default_TxPowerLevel 0x22 | |
688 | #define EEPROM_Default_HT40_2SDiff 0x0 | |
689 | /* HT20<->40 default Tx Power Index Difference */ | |
690 | #define EEPROM_Default_HT20_Diff 2 | |
691 | #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 | |
692 | #define EEPROM_Default_HT40_PwrMaxOffset 0 | |
693 | #define EEPROM_Default_HT20_PwrMaxOffset 0 | |
694 | ||
695 | /* For debug */ | |
696 | #define EEPROM_Default_PID 0x1234 | |
697 | #define EEPROM_Default_VID 0x5678 | |
698 | #define EEPROM_Default_CustomerID 0xAB | |
699 | #define EEPROM_Default_SubCustomerID 0xCD | |
700 | #define EEPROM_Default_Version 0 | |
701 | ||
702 | #define EEPROM_CHANNEL_PLAN_FCC 0x0 | |
703 | #define EEPROM_CHANNEL_PLAN_IC 0x1 | |
704 | #define EEPROM_CHANNEL_PLAN_ETSI 0x2 | |
705 | #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 | |
706 | #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 | |
707 | #define EEPROM_CHANNEL_PLAN_MKK 0x5 | |
708 | #define EEPROM_CHANNEL_PLAN_MKK1 0x6 | |
709 | #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 | |
710 | #define EEPROM_CHANNEL_PLAN_TELEC 0x8 | |
711 | #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 | |
712 | #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA | |
713 | #define EEPROM_CHANNEL_PLAN_NCC 0xB | |
714 | #define EEPROM_USB_OPTIONAL1 0xE | |
715 | #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 | |
716 | ||
717 | ||
718 | #define EEPROM_CID_DEFAULT 0x0 | |
719 | #define EEPROM_CID_TOSHIBA 0x4 | |
720 | /* CCX test. By Bruce, 2009-02-25. */ | |
721 | #define EEPROM_CID_CCX 0x10 | |
722 | #define EEPROM_CID_QMI 0x0D | |
723 | /* added by chiyoko for dtm, 20090108 */ | |
724 | #define EEPROM_CID_WHQL 0xFE | |
725 | ||
726 | ||
727 | #define RTL_EEPROM_ID 0x8129 | |
728 | ||
729 | #define SUPPORT_HW_RADIO_DETECT(pHalData) \ | |
730 | (pHalData->BoardType == BOARD_MINICARD || \ | |
731 | pHalData->BoardType == BOARD_USB_SOLO || \ | |
732 | pHalData->BoardType == BOARD_USB_COMBO) | |
733 | ||
734 | /* */ | |
735 | /* EEPROM address for Test chip */ | |
736 | /* */ | |
737 | #define EEPROM_TEST_USB_OPT 0x0E | |
738 | #define EEPROM_TEST_CHIRP_K 0x0F | |
739 | #define EEPROM_TEST_EP_SETTING 0x0E | |
740 | #define EEPROM_TEST_USB_PHY 0x10 | |
741 | ||
742 | ||
743 | /* */ | |
744 | /* EEPROM address for Normal chip */ | |
745 | /* */ | |
746 | #define EEPROM_NORMAL_USB_OPT 0x0E | |
747 | #define EEPROM_NORMAL_CHIRP_K 0x0E /* Changed */ | |
748 | #define EEPROM_NORMAL_EP_SETTING 0x0F /* Changed */ | |
749 | #define EEPROM_NORMAL_USB_PHY 0x12 /* Changed */ | |
750 | ||
751 | enum { | |
752 | BOARD_USB_DONGLE = 0, /* USB dongle */ | |
753 | BOARD_USB_High_PA = 1, /* USB dongle with high power PA */ | |
754 | BOARD_MINICARD = 2, /* Minicard */ | |
755 | BOARD_USB_SOLO = 3, /* USB solo-Slim module */ | |
756 | BOARD_USB_COMBO = 4, /* USB Combo-Slim module */ | |
757 | }; | |
758 | ||
759 | /* Test chip and normal chip common define */ | |
760 | /* */ | |
761 | /* EEPROM address for both */ | |
762 | /* */ | |
763 | #define EEPROM_ID0 0x00 | |
764 | #define EEPROM_ID1 0x01 | |
765 | #define EEPROM_RTK_RSV1 0x02 | |
766 | #define EEPROM_RTK_RSV2 0x03 | |
767 | #define EEPROM_RTK_RSV3 0x04 | |
768 | #define EEPROM_RTK_RSV4 0x05 | |
769 | #define EEPROM_RTK_RSV5 0x06 | |
770 | #define EEPROM_DBG_SEL 0x07 | |
771 | #define EEPROM_RTK_RSV6 0x08 | |
772 | #define EEPROM_VID 0x0A | |
773 | #define EEPROM_PID 0x0C | |
774 | ||
775 | #define EEPROM_MAC_ADDR 0x16 | |
776 | #define EEPROM_STRING 0x1C | |
777 | #define EEPROM_SUBCUSTOMER_ID 0x59 | |
778 | #define EEPROM_CCK_TX_PWR_INX 0x5A | |
779 | #define EEPROM_HT40_1S_TX_PWR_INX 0x60 | |
780 | #define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 | |
781 | #define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 | |
782 | #define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C | |
783 | #define EEPROM_HT40_MAX_PWR_OFFSET 0x6F | |
784 | #define EEPROM_HT20_MAX_PWR_OFFSET 0x72 | |
785 | ||
786 | #define EEPROM_CHANNEL_PLAN 0x75 | |
787 | #define EEPROM_TSSI_A 0x76 | |
788 | #define EEPROM_TSSI_B 0x77 | |
789 | #define EEPROM_THERMAL_METER 0x78 | |
790 | #define EEPROM_RF_OPT1 0x79 | |
791 | #define EEPROM_RF_OPT2 0x7A | |
792 | #define EEPROM_RF_OPT3 0x7B | |
793 | #define EEPROM_RF_OPT4 0x7C | |
794 | #define EEPROM_VERSION 0x7E | |
795 | #define EEPROM_CUSTOMER_ID 0x7F | |
796 | ||
797 | /* 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU */ | |
798 | #define EEPROM_BoardType 0x54 | |
799 | /* 0x5C-0x76, Tx Power index. */ | |
800 | #define EEPROM_TxPwIndex 0x5C | |
801 | /* Difference of gain index between legacy and high throughput OFDM. */ | |
802 | #define EEPROM_PwDiff 0x67 | |
803 | /* CCK Tx Power */ | |
804 | #define EEPROM_TxPowerCCK 0x5A | |
805 | ||
806 | /* 2009/02/09 Cosa Add for SD3 requirement */ | |
807 | /* HT20 Tx Power Index Difference */ | |
808 | #define EEPROM_TX_PWR_HT20_DIFF 0x6e | |
809 | /* HT20<->40 default Tx Power Index Difference */ | |
810 | #define DEFAULT_HT20_TXPWR_DIFF 2 | |
811 | /* OFDM Tx Power Index Difference */ | |
812 | #define EEPROM_TX_PWR_OFDM_DIFF 0x71 | |
813 | ||
814 | /* Power diff for channel group */ | |
815 | #define EEPROM_TxPWRGroup 0x73 | |
816 | /* Check if power safety is need */ | |
817 | #define EEPROM_Regulatory 0x79 | |
818 | ||
819 | /* 92cu, 0x7E[4] */ | |
820 | #define EEPROM_BLUETOOTH_COEXIST 0x7E | |
821 | #define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 /* 7:5] */ | |
822 | #define BOARD_TYPE_NORMAL_MASK 0xE0 | |
823 | #define BOARD_TYPE_TEST_MASK 0x0F | |
824 | /* BIT0 1 for build-in module, 0 for external dongle */ | |
825 | #define EEPROM_EASY_REPLACEMENT 0x50 | |
826 | /* */ | |
827 | /* EPROM content definitions */ | |
828 | /* */ | |
829 | #define OS_LINK_SPEED BIT(5) | |
830 | ||
831 | #define BOARD_TYPE_MASK 0xF | |
832 | ||
833 | #define BT_COEXISTENCE BIT(4) | |
834 | #define BT_CO_SHIFT 4 | |
835 | ||
836 | #define EP_NUMBER_MASK 0x30 /* bit 4:5 0Eh */ | |
837 | #define EP_NUMBER_SHIFT 4 | |
838 | ||
839 | ||
840 | #define USB_PHY_PARA_SIZE 5 | |
841 | ||
842 | ||
843 | /* */ | |
844 | /* \14EEPROM default value definitions */ | |
845 | /* */ | |
846 | /* Use 0xABCD instead of 0x8192 for debug */ | |
847 | #define EEPROM_DEF_ID_0 0xCD /* Byte 0x00 */ | |
848 | #define EEPROM_DEF_ID_1 0xAB /* Byte 0x01 */ | |
849 | ||
850 | #define EEPROM_DEF_RTK_RSV_A3 0x74 /* Byte 0x03 */ | |
851 | #define EEPROM_DEF_RTK_RSV_A4 0x6D /* Byte 0x04 */ | |
852 | #define EEPROM_DEF_RTK_RSV_A8 0xFF /* Byte 0x08 */ | |
853 | ||
854 | #define EEPROM_DEF_VID_0 0x0A /* Byte 0x0A */ | |
855 | #define EEPROM_DEF_VID_1 0x0B | |
856 | ||
857 | #define EEPROM_DEF_PID_0 0x92 /* Byte 0x0C */ | |
858 | #define EEPROM_DEF_PID_1 0x81 | |
859 | ||
860 | ||
861 | #define EEPROM_TEST_DEF_USB_OPT 0x80 /* Byte 0x0E */ | |
862 | #define EEPROM_NORMAL_DEF_USB_OPT 0x00 /* Byte 0x0E */ | |
863 | ||
864 | #define EEPROM_DEF_CHIRPK 0x15 /* Byte 0x0F */ | |
865 | ||
866 | #define EEPROM_DEF_USB_PHY_0 0x85 /* Byte 0x10 */ | |
867 | #define EEPROM_DEF_USB_PHY_1 0x62 /* Byte 0x11 */ | |
868 | #define EEPROM_DEF_USB_PHY_2 0x9E /* Byte 0x12 */ | |
869 | #define EEPROM_DEF_USB_PHY_3 0x06 /* Byte 0x13 */ | |
870 | ||
871 | #define EEPROM_DEF_TSSI_A 0x09 /* Byte 0x78 */ | |
872 | #define EEPROM_DEF_TSSI_B 0x09 /* Byte 0x79 */ | |
873 | ||
874 | ||
875 | #define EEPROM_DEF_THERMAL_METER 0x12 /* Byte 0x7A */ | |
876 | ||
877 | /* Check if power safety spec is need */ | |
878 | #define RF_OPTION1 0x79 | |
879 | #define RF_OPTION2 0x7A | |
880 | #define RF_OPTION3 0x7B | |
881 | #define RF_OPTION4 0x7C | |
882 | ||
883 | ||
884 | #define EEPROM_USB_SN BIT(0) | |
885 | #define EEPROM_USB_REMOTE_WAKEUP BIT(1) | |
886 | #define EEPROM_USB_DEVICE_PWR BIT(2) | |
887 | #define EEPROM_EP_NUMBER (BIT(3)|BIT(4)) | |
888 | ||
889 | /*=================================================================== | |
890 | ===================================================================== | |
891 | Here the register defines are for 92C. When the define is as same with 92C, | |
892 | we will use the 92C's define for the consistency | |
893 | So the following defines for 92C is not entire!!!!!! | |
894 | ===================================================================== | |
895 | =====================================================================*/ | |
896 | /* | |
897 | Based on Datasheet V33---090401 | |
898 | Register Summary | |
899 | Current IOREG MAP | |
900 | 0x0000h ~ 0x00FFh System Configuration (256 Bytes) | |
901 | 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) | |
902 | 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) | |
903 | 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) | |
904 | 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) | |
905 | 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) | |
906 | 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) | |
907 | 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) | |
908 | 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) | |
909 | */ | |
910 | ||
911 | /* */ | |
912 | /* 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ | |
913 | /* */ | |
9c45c20d JS |
914 | #define RCR_APPFCS BIT(31) /* WMAC append FCS after payload*/ |
915 | #define RCR_APP_MIC BIT(30) | |
916 | #define RCR_APP_PHYSTS BIT(28) | |
917 | #define RCR_APP_ICV BIT(29) | |
918 | #define RCR_APP_PHYST_RXFF BIT(28) | |
919 | #define RCR_APP_BA_SSN BIT(27) /* Accept BA SSN */ | |
920 | #define RCR_ENMBID BIT(24) /* Enable Multiple BssId. */ | |
921 | #define RCR_LSIGEN BIT(23) | |
922 | #define RCR_MFBEN BIT(22) | |
923 | #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ | |
924 | #define RCR_AMF BIT(13) /* Accept management type frame */ | |
925 | #define RCR_ACF BIT(12) /* Accept control type frame */ | |
926 | #define RCR_ADF BIT(11) /* Accept data type frame */ | |
927 | #define RCR_AICV BIT(9) /* Accept ICV error packet */ | |
928 | #define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */ | |
929 | #define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet | |
364e30eb | 930 | (Rx beacon, probe rsp) */ |
9c45c20d | 931 | #define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match packet |
364e30eb LF |
932 | (Data) */ |
933 | #define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match | |
934 | packet */ | |
9c45c20d | 935 | #define RCR_APWRMGT BIT(5) /* Accept power management |
364e30eb | 936 | packet */ |
9c45c20d | 937 | #define RCR_ADD3 BIT(4) /* Accept address 3 match |
364e30eb | 938 | packet */ |
9c45c20d JS |
939 | #define RCR_AB BIT(3) /* Accept broadcast packet */ |
940 | #define RCR_AM BIT(2) /* Accept multicast packet */ | |
941 | #define RCR_APM BIT(1) /* Accept physical match packet */ | |
942 | #define RCR_AAP BIT(0) /* Accept all unicast packet */ | |
364e30eb LF |
943 | #define RCR_MXDMA_OFFSET 8 |
944 | #define RCR_FIFO_OFFSET 13 | |
945 | ||
946 | ||
947 | ||
948 | /* */ | |
949 | /* 8192c USB specific Regsiter Offset and Content definition, */ | |
950 | /* 2009.08.18, added by vivi. for merge 92c and 92C into one driver */ | |
951 | /* */ | |
952 | /* define APS_FSMCO 0x0004 same with 92Ce */ | |
953 | #define RSV_CTRL 0x001C | |
954 | #define RD_CTRL 0x0524 | |
955 | ||
956 | /* */ | |
957 | /* */ | |
958 | /* 0xFE00h ~ 0xFE55h USB Configuration */ | |
959 | /* */ | |
960 | /* */ | |
961 | #define REG_USB_INFO 0xFE17 | |
962 | #define REG_USB_SPECIAL_OPTION 0xFE55 | |
963 | #define REG_USB_DMA_AGG_TO 0xFE5B | |
964 | #define REG_USB_AGG_TO 0xFE5C | |
965 | #define REG_USB_AGG_TH 0xFE5D | |
966 | ||
967 | #define REG_USB_VID 0xFE60 | |
968 | #define REG_USB_PID 0xFE62 | |
969 | #define REG_USB_OPTIONAL 0xFE64 | |
970 | #define REG_USB_CHIRP_K 0xFE65 | |
971 | #define REG_USB_PHY 0xFE66 | |
972 | #define REG_USB_MAC_ADDR 0xFE70 | |
973 | ||
974 | #define REG_USB_HRPWM 0xFE58 | |
975 | #define REG_USB_HCPWM 0xFE57 | |
976 | ||
977 | #define InvalidBBRFValue 0x12345678 | |
978 | ||
979 | /* */ | |
980 | /* 8192C Regsiter Bit and Content definition */ | |
981 | /* */ | |
982 | /* */ | |
983 | /* */ | |
984 | /* 0x0000h ~ 0x00FFh System Configuration */ | |
985 | /* */ | |
986 | /* */ | |
987 | ||
988 | /* 2 SPS0_CTRL */ | |
989 | #define SW18_FPWM BIT(3) | |
990 | ||
991 | ||
992 | /* 2 SYS_ISO_CTRL */ | |
993 | #define ISO_MD2PP BIT(0) | |
994 | #define ISO_UA2USB BIT(1) | |
995 | #define ISO_UD2CORE BIT(2) | |
996 | #define ISO_PA2PCIE BIT(3) | |
997 | #define ISO_PD2CORE BIT(4) | |
998 | #define ISO_IP2MAC BIT(5) | |
999 | #define ISO_DIOP BIT(6) | |
1000 | #define ISO_DIOE BIT(7) | |
1001 | #define ISO_EB2CORE BIT(8) | |
1002 | #define ISO_DIOR BIT(9) | |
1003 | ||
1004 | #define PWC_EV25V BIT(14) | |
1005 | #define PWC_EV12V BIT(15) | |
1006 | ||
1007 | ||
1008 | /* 2 SYS_FUNC_EN */ | |
1009 | #define FEN_BBRSTB BIT(0) | |
1010 | #define FEN_BB_GLB_RSTn BIT(1) | |
1011 | #define FEN_USBA BIT(2) | |
1012 | #define FEN_UPLL BIT(3) | |
1013 | #define FEN_USBD BIT(4) | |
1014 | #define FEN_DIO_PCIE BIT(5) | |
1015 | #define FEN_PCIEA BIT(6) | |
1016 | #define FEN_PPLL BIT(7) | |
1017 | #define FEN_PCIED BIT(8) | |
1018 | #define FEN_DIOE BIT(9) | |
1019 | #define FEN_CPUEN BIT(10) | |
1020 | #define FEN_DCORE BIT(11) | |
1021 | #define FEN_ELDR BIT(12) | |
1022 | #define FEN_DIO_RF BIT(13) | |
1023 | #define FEN_HWPDN BIT(14) | |
1024 | #define FEN_MREGEN BIT(15) | |
1025 | ||
1026 | /* 2 APS_FSMCO */ | |
1027 | #define PFM_LDALL BIT(0) | |
1028 | #define PFM_ALDN BIT(1) | |
1029 | #define PFM_LDKP BIT(2) | |
1030 | #define PFM_WOWL BIT(3) | |
1031 | #define EnPDN BIT(4) | |
1032 | #define PDN_PL BIT(5) | |
1033 | #define APFM_ONMAC BIT(8) | |
1034 | #define APFM_OFF BIT(9) | |
1035 | #define APFM_RSM BIT(10) | |
1036 | #define AFSM_HSUS BIT(11) | |
1037 | #define AFSM_PCIE BIT(12) | |
1038 | #define APDM_MAC BIT(13) | |
1039 | #define APDM_HOST BIT(14) | |
1040 | #define APDM_HPDN BIT(15) | |
1041 | #define RDY_MACON BIT(16) | |
1042 | #define SUS_HOST BIT(17) | |
1043 | #define ROP_ALD BIT(20) | |
1044 | #define ROP_PWR BIT(21) | |
1045 | #define ROP_SPS BIT(22) | |
1046 | #define SOP_MRST BIT(25) | |
1047 | #define SOP_FUSE BIT(26) | |
1048 | #define SOP_ABG BIT(27) | |
1049 | #define SOP_AMB BIT(28) | |
1050 | #define SOP_RCK BIT(29) | |
1051 | #define SOP_A8M BIT(30) | |
1052 | #define XOP_BTCK BIT(31) | |
1053 | ||
1054 | /* 2 SYS_CLKR */ | |
1055 | #define ANAD16V_EN BIT(0) | |
1056 | #define ANA8M BIT(1) | |
1057 | #define MACSLP BIT(4) | |
1058 | #define LOADER_CLK_EN BIT(5) | |
1059 | #define _80M_SSC_DIS BIT(7) | |
1060 | #define _80M_SSC_EN_HO BIT(8) | |
1061 | #define PHY_SSC_RSTB BIT(9) | |
1062 | #define SEC_CLK_EN BIT(10) | |
1063 | #define MAC_CLK_EN BIT(11) | |
1064 | #define SYS_CLK_EN BIT(12) | |
1065 | #define RING_CLK_EN BIT(13) | |
1066 | ||
1067 | ||
1068 | /* 2 9346CR */ | |
1069 | ||
1070 | ||
1071 | #define EEDO BIT(0) | |
1072 | #define EEDI BIT(1) | |
1073 | #define EESK BIT(2) | |
1074 | #define EECS BIT(3) | |
1075 | /* define EERPROMSEL BIT(4) */ | |
1076 | /* define EEPROM_EN BIT(5) */ | |
1077 | #define BOOT_FROM_EEPROM BIT(4) | |
1078 | #define EEPROM_EN BIT(5) | |
1079 | #define EEM0 BIT(6) | |
1080 | #define EEM1 BIT(7) | |
1081 | ||
1082 | ||
1083 | /* 2 AFE_MISC */ | |
1084 | #define AFE_BGEN BIT(0) | |
1085 | #define AFE_MBEN BIT(1) | |
1086 | #define MAC_ID_EN BIT(7) | |
1087 | ||
1088 | ||
1089 | /* 2 SPS0_CTRL */ | |
1090 | ||
1091 | ||
1092 | /* 2 SPS_OCP_CFG */ | |
1093 | ||
1094 | ||
1095 | /* 2 RSV_CTRL */ | |
1096 | #define WLOCK_ALL BIT(0) | |
1097 | #define WLOCK_00 BIT(1) | |
1098 | #define WLOCK_04 BIT(2) | |
1099 | #define WLOCK_08 BIT(3) | |
1100 | #define WLOCK_40 BIT(4) | |
1101 | #define R_DIS_PRST_0 BIT(5) | |
1102 | #define R_DIS_PRST_1 BIT(6) | |
1103 | #define LOCK_ALL_EN BIT(7) | |
1104 | ||
1105 | /* 2 RF_CTRL */ | |
1106 | #define RF_EN BIT(0) | |
1107 | #define RF_RSTB BIT(1) | |
1108 | #define RF_SDMRSTB BIT(2) | |
1109 | ||
1110 | ||
1111 | ||
1112 | /* 2 LDOA15_CTRL */ | |
1113 | #define LDA15_EN BIT(0) | |
1114 | #define LDA15_STBY BIT(1) | |
1115 | #define LDA15_OBUF BIT(2) | |
1116 | #define LDA15_REG_VOS BIT(3) | |
1117 | #define _LDA15_VOADJ(x) (((x) & 0x7) << 4) | |
1118 | ||
1119 | ||
1120 | ||
1121 | /* 2 LDOV12D_CTRL */ | |
1122 | #define LDV12_EN BIT(0) | |
1123 | #define LDV12_SDBY BIT(1) | |
1124 | #define LPLDO_HSM BIT(2) | |
1125 | #define LPLDO_LSM_DIS BIT(3) | |
1126 | #define _LDV12_VADJ(x) (((x) & 0xF) << 4) | |
1127 | ||
1128 | ||
1129 | /* 2 AFE_XTAL_CTRL */ | |
1130 | #define XTAL_EN BIT(0) | |
1131 | #define XTAL_BSEL BIT(1) | |
1132 | #define _XTAL_BOSC(x) (((x) & 0x3) << 2) | |
1133 | #define _XTAL_CADJ(x) (((x) & 0xF) << 4) | |
1134 | #define XTAL_GATE_USB BIT(8) | |
1135 | #define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) | |
1136 | #define XTAL_GATE_AFE BIT(11) | |
1137 | #define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) | |
1138 | #define XTAL_RF_GATE BIT(14) | |
1139 | #define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) | |
1140 | #define XTAL_GATE_DIG BIT(17) | |
1141 | #define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) | |
1142 | #define XTAL_BT_GATE BIT(20) | |
1143 | #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) | |
1144 | #define _XTAL_GPIO(x) (((x) & 0x7) << 23) | |
1145 | ||
1146 | ||
1147 | #define CKDLY_AFE BIT(26) | |
1148 | #define CKDLY_USB BIT(27) | |
1149 | #define CKDLY_DIG BIT(28) | |
1150 | #define CKDLY_BT BIT(29) | |
1151 | ||
1152 | ||
1153 | /* 2 AFE_PLL_CTRL */ | |
1154 | #define APLL_EN BIT(0) | |
1155 | #define APLL_320_EN BIT(1) | |
1156 | #define APLL_FREF_SEL BIT(2) | |
1157 | #define APLL_EDGE_SEL BIT(3) | |
1158 | #define APLL_WDOGB BIT(4) | |
1159 | #define APLL_LPFEN BIT(5) | |
1160 | ||
1161 | #define APLL_REF_CLK_13MHZ 0x1 | |
1162 | #define APLL_REF_CLK_19_2MHZ 0x2 | |
1163 | #define APLL_REF_CLK_20MHZ 0x3 | |
1164 | #define APLL_REF_CLK_25MHZ 0x4 | |
1165 | #define APLL_REF_CLK_26MHZ 0x5 | |
1166 | #define APLL_REF_CLK_38_4MHZ 0x6 | |
1167 | #define APLL_REF_CLK_40MHZ 0x7 | |
1168 | ||
1169 | #define APLL_320EN BIT(14) | |
1170 | #define APLL_80EN BIT(15) | |
1171 | #define APLL_1MEN BIT(24) | |
1172 | ||
1173 | ||
1174 | /* 2 EFUSE_CTRL */ | |
1175 | #define ALD_EN BIT(18) | |
1176 | #define EF_PD BIT(19) | |
1177 | #define EF_FLAG BIT(31) | |
1178 | ||
1179 | /* 2 EFUSE_TEST (For RTL8723 partially) */ | |
1180 | #define EF_TRPT BIT(7) | |
1181 | /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ | |
1182 | #define EF_CELL_SEL (BIT(8)|BIT(9)) | |
1183 | #define LDOE25_EN BIT(31) | |
1184 | #define EFUSE_SEL(x) (((x) & 0x3) << 8) | |
1185 | #define EFUSE_SEL_MASK 0x300 | |
1186 | #define EFUSE_WIFI_SEL_0 0x0 | |
1187 | #define EFUSE_BT_SEL_0 0x1 | |
1188 | #define EFUSE_BT_SEL_1 0x2 | |
1189 | #define EFUSE_BT_SEL_2 0x3 | |
1190 | ||
1191 | #define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ | |
1192 | #define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ | |
1193 | ||
1194 | /* 2 PWR_DATA */ | |
1195 | ||
1196 | /* 2 CAL_TIMER */ | |
1197 | ||
1198 | /* 2 ACLK_MON */ | |
1199 | #define RSM_EN BIT(0) | |
1200 | #define Timer_EN BIT(4) | |
1201 | ||
1202 | ||
1203 | /* 2 GPIO_MUXCFG */ | |
1204 | #define TRSW0EN BIT(2) | |
1205 | #define TRSW1EN BIT(3) | |
1206 | #define EROM_EN BIT(4) | |
1207 | #define EnBT BIT(5) | |
1208 | #define EnUart BIT(8) | |
1209 | #define Uart_910 BIT(9) | |
1210 | #define EnPMAC BIT(10) | |
1211 | #define SIC_SWRST BIT(11) | |
1212 | #define EnSIC BIT(12) | |
1213 | #define SIC_23 BIT(13) | |
1214 | #define EnHDP BIT(14) | |
1215 | #define SIC_LBK BIT(15) | |
1216 | ||
1217 | /* 2 GPIO_PIN_CTRL */ | |
1218 | ||
1219 | /* GPIO BIT */ | |
1220 | #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) | |
1221 | ||
1222 | /* 2 GPIO_INTM */ | |
1223 | ||
1224 | /* 2 LEDCFG */ | |
1225 | #define LED0PL BIT(4) | |
1226 | #define LED0DIS BIT(7) | |
1227 | #define LED1DIS BIT(15) | |
1228 | #define LED1PL BIT(12) | |
1229 | ||
1230 | #define SECCAM_CLR BIT(30) | |
1231 | ||
1232 | ||
1233 | /* 2 FSIMR */ | |
1234 | ||
1235 | /* 2 FSISR */ | |
1236 | ||
1237 | ||
1238 | /* 2 8051FWDL */ | |
1239 | /* 2 MCUFWDL */ | |
1240 | #define MCUFWDL_EN BIT(0) | |
1241 | #define MCUFWDL_RDY BIT(1) | |
1242 | #define FWDL_ChkSum_rpt BIT(2) | |
1243 | #define MACINI_RDY BIT(3) | |
1244 | #define BBINI_RDY BIT(4) | |
1245 | #define RFINI_RDY BIT(5) | |
1246 | #define WINTINI_RDY BIT(6) | |
1247 | #define CPRST BIT(23) | |
1248 | ||
1249 | /* 2REG_HPON_FSM */ | |
1250 | #define BOND92CE_1T2R_CFG BIT(22) | |
1251 | ||
1252 | ||
1253 | /* 2 REG_SYS_CFG */ | |
1254 | #define XCLK_VLD BIT(0) | |
1255 | #define ACLK_VLD BIT(1) | |
1256 | #define UCLK_VLD BIT(2) | |
1257 | #define PCLK_VLD BIT(3) | |
1258 | #define PCIRSTB BIT(4) | |
1259 | #define V15_VLD BIT(5) | |
1260 | #define TRP_B15V_EN BIT(7) | |
1261 | #define SIC_IDLE BIT(8) | |
1262 | #define BD_MAC2 BIT(9) | |
1263 | #define BD_MAC1 BIT(10) | |
1264 | #define IC_MACPHY_MODE BIT(11) | |
1265 | #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) | |
1266 | #define BT_FUNC BIT(16) | |
1267 | #define VENDOR_ID BIT(19) | |
1268 | #define PAD_HWPD_IDN BIT(22) | |
1269 | #define TRP_VAUX_EN BIT(23) | |
1270 | #define TRP_BT_EN BIT(24) | |
1271 | #define BD_PKG_SEL BIT(25) | |
1272 | #define BD_HCI_SEL BIT(26) | |
1273 | #define TYPE_ID BIT(27) | |
1274 | ||
1275 | #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ | |
1276 | #define CHIP_VER_RTL_SHIFT 12 | |
1277 | ||
1278 | /* 2REG_GPIO_OUTSTS (For RTL8723 only) */ | |
1279 | #define EFS_HCI_SEL (BIT(0)|BIT(1)) | |
1280 | #define PAD_HCI_SEL (BIT(2)|BIT(3)) | |
1281 | #define HCI_SEL (BIT(4)|BIT(5)) | |
1282 | #define PKG_SEL_HCI BIT(6) | |
1283 | #define FEN_GPS BIT(7) | |
1284 | #define FEN_BT BIT(8) | |
1285 | #define FEN_WL BIT(9) | |
1286 | #define FEN_PCI BIT(10) | |
1287 | #define FEN_USB BIT(11) | |
1288 | #define BTRF_HWPDN_N BIT(12) | |
1289 | #define WLRF_HWPDN_N BIT(13) | |
1290 | #define PDN_BT_N BIT(14) | |
1291 | #define PDN_GPS_N BIT(15) | |
1292 | #define BT_CTL_HWPDN BIT(16) | |
1293 | #define GPS_CTL_HWPDN BIT(17) | |
1294 | #define PPHY_SUSB BIT(20) | |
1295 | #define UPHY_SUSB BIT(21) | |
1296 | #define PCI_SUSEN BIT(22) | |
1297 | #define USB_SUSEN BIT(23) | |
1298 | #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) | |
1299 | ||
1300 | /* */ | |
1301 | /* */ | |
1302 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ | |
1303 | /* */ | |
1304 | /* */ | |
1305 | ||
1306 | ||
1307 | /* 2 Function Enable Registers */ | |
1308 | /* 2 CR */ | |
1309 | ||
1310 | #define REG_LBMODE (REG_CR + 3) | |
1311 | ||
1312 | ||
1313 | #define HCI_TXDMA_EN BIT(0) | |
1314 | #define HCI_RXDMA_EN BIT(1) | |
1315 | #define TXDMA_EN BIT(2) | |
1316 | #define RXDMA_EN BIT(3) | |
1317 | #define PROTOCOL_EN BIT(4) | |
1318 | #define SCHEDULE_EN BIT(5) | |
1319 | #define MACTXEN BIT(6) | |
1320 | #define MACRXEN BIT(7) | |
1321 | #define ENSWBCN BIT(8) | |
1322 | #define ENSEC BIT(9) | |
1323 | ||
364e30eb LF |
1324 | #define _LBMODE(x) (((x) & 0xF) << 24) |
1325 | #define MASK_LBMODE 0xF000000 | |
1326 | #define LOOPBACK_NORMAL 0x0 | |
1327 | #define LOOPBACK_IMMEDIATELY 0xB | |
1328 | #define LOOPBACK_MAC_DELAY 0x3 | |
1329 | #define LOOPBACK_PHY 0x1 | |
1330 | #define LOOPBACK_DMA 0x7 | |
1331 | ||
1332 | ||
1333 | /* 2 PBP - Page Size Register */ | |
1334 | #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) | |
1335 | #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) | |
1336 | #define _PSRX_MASK 0xF | |
1337 | #define _PSTX_MASK 0xF0 | |
1338 | #define _PSRX(x) (x) | |
1339 | #define _PSTX(x) ((x) << 4) | |
1340 | ||
1341 | #define PBP_64 0x0 | |
1342 | #define PBP_128 0x1 | |
1343 | #define PBP_256 0x2 | |
1344 | #define PBP_512 0x3 | |
1345 | #define PBP_1024 0x4 | |
1346 | ||
1347 | ||
1348 | /* 2 TX/RXDMA */ | |
1349 | #define RXDMA_ARBBW_EN BIT(0) | |
1350 | #define RXSHFT_EN BIT(1) | |
1351 | #define RXDMA_AGG_EN BIT(2) | |
1352 | #define QS_VO_QUEUE BIT(8) | |
1353 | #define QS_VI_QUEUE BIT(9) | |
1354 | #define QS_BE_QUEUE BIT(10) | |
1355 | #define QS_BK_QUEUE BIT(11) | |
1356 | #define QS_MANAGER_QUEUE BIT(12) | |
1357 | #define QS_HIGH_QUEUE BIT(13) | |
1358 | ||
1359 | #define HQSEL_VOQ BIT(0) | |
1360 | #define HQSEL_VIQ BIT(1) | |
1361 | #define HQSEL_BEQ BIT(2) | |
1362 | #define HQSEL_BKQ BIT(3) | |
1363 | #define HQSEL_MGTQ BIT(4) | |
1364 | #define HQSEL_HIQ BIT(5) | |
1365 | ||
1366 | /* For normal driver, 0x10C */ | |
1367 | #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) | |
1368 | #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) | |
1369 | #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) | |
1beda8d5 GD |
1370 | #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) |
1371 | #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) | |
1372 | #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) | |
364e30eb LF |
1373 | |
1374 | #define QUEUE_LOW 1 | |
1375 | #define QUEUE_NORMAL 2 | |
1376 | #define QUEUE_HIGH 3 | |
1377 | ||
1378 | ||
1379 | ||
1380 | /* 2 TRXFF_BNDY */ | |
1381 | ||
1382 | ||
1383 | /* 2 LLT_INIT */ | |
1384 | #define _LLT_NO_ACTIVE 0x0 | |
1385 | #define _LLT_WRITE_ACCESS 0x1 | |
1386 | #define _LLT_READ_ACCESS 0x2 | |
1387 | ||
1388 | #define _LLT_INIT_DATA(x) ((x) & 0xFF) | |
1389 | #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) | |
1390 | #define _LLT_OP(x) (((x) & 0x3) << 30) | |
1391 | #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) | |
1392 | ||
1393 | ||
1394 | /* 2 BB_ACCESS_CTRL */ | |
1395 | #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) | |
1396 | #define BB_WRITE_EN BIT(30) | |
1397 | #define BB_READ_EN BIT(31) | |
1398 | /* define BB_ADDR_MASK 0xFFF */ | |
1399 | /* define _BB_ADDR(x) ((x) & BB_ADDR_MASK) */ | |
1400 | ||
1401 | /* */ | |
1402 | /* */ | |
1403 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ | |
1404 | /* */ | |
1405 | /* */ | |
1406 | /* 2 RQPN */ | |
1407 | #define _HPQ(x) ((x) & 0xFF) | |
1408 | #define _LPQ(x) (((x) & 0xFF) << 8) | |
1409 | #define _PUBQ(x) (((x) & 0xFF) << 16) | |
1410 | /* NOTE: in RQPN_NPQ register */ | |
1411 | #define _NPQ(x) ((x) & 0xFF) | |
1412 | ||
1413 | ||
1414 | #define HPQ_PUBLIC_DIS BIT(24) | |
1415 | #define LPQ_PUBLIC_DIS BIT(25) | |
1416 | #define LD_RQPN BIT(31) | |
1417 | ||
1418 | ||
1419 | /* 2 TDECTRL */ | |
1420 | #define BCN_VALID BIT(16) | |
1421 | #define BCN_HEAD(x) (((x) & 0xFF) << 8) | |
1422 | #define BCN_HEAD_MASK 0xFF00 | |
1423 | ||
1424 | /* 2 TDECTL */ | |
1425 | #define BLK_DESC_NUM_SHIFT 4 | |
1426 | #define BLK_DESC_NUM_MASK 0xF | |
1427 | ||
1428 | ||
1429 | /* 2 TXDMA_OFFSET_CHK */ | |
1430 | #define DROP_DATA_EN BIT(9) | |
1431 | ||
1432 | /* */ | |
1433 | /* */ | |
1434 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ | |
1435 | /* */ | |
1436 | /* */ | |
1437 | /* 2 FWHW_TXQ_CTRL */ | |
1438 | #define EN_AMPDU_RTY_NEW BIT(7) | |
1439 | ||
1440 | /* 2 INIRTSMCS_SEL */ | |
1441 | #define _INIRTSMCS_SEL(x) ((x) & 0x3F) | |
1442 | ||
1443 | ||
1444 | /* 2 SPEC SIFS */ | |
1445 | #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) | |
1446 | #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) | |
1447 | ||
1448 | ||
1449 | /* 2 RRSR */ | |
1450 | ||
1451 | #define RATE_REG_BITMAP_ALL 0xFFFFF | |
1452 | ||
1453 | #define _RRSC_BITMAP(x) ((x) & 0xFFFFF) | |
1454 | ||
1455 | #define _RRSR_RSC(x) (((x) & 0x3) << 21) | |
1456 | #define RRSR_RSC_RESERVED 0x0 | |
1457 | #define RRSR_RSC_UPPER_SUBCHANNEL 0x1 | |
1458 | #define RRSR_RSC_LOWER_SUBCHANNEL 0x2 | |
1459 | #define RRSR_RSC_DUPLICATE_MODE 0x3 | |
1460 | ||
1461 | ||
1462 | /* 2 ARFR */ | |
1463 | #define USE_SHORT_G1 BIT(20) | |
1464 | ||
1465 | /* 2 AGGLEN_LMT_L */ | |
1466 | #define _AGGLMT_MCS0(x) ((x) & 0xF) | |
1467 | #define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) | |
1468 | #define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) | |
1469 | #define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) | |
1470 | #define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) | |
1471 | #define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) | |
1472 | #define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) | |
1473 | #define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) | |
1474 | ||
1475 | ||
1476 | /* 2 RL */ | |
1477 | #define RETRY_LIMIT_SHORT_SHIFT 8 | |
1478 | #define RETRY_LIMIT_LONG_SHIFT 0 | |
1479 | ||
1480 | ||
1481 | /* 2 DARFRC */ | |
1482 | #define _DARF_RC1(x) ((x) & 0x1F) | |
1483 | #define _DARF_RC2(x) (((x) & 0x1F) << 8) | |
1484 | #define _DARF_RC3(x) (((x) & 0x1F) << 16) | |
1485 | #define _DARF_RC4(x) (((x) & 0x1F) << 24) | |
1486 | /* NOTE: shift starting from address (DARFRC + 4) */ | |
1487 | #define _DARF_RC5(x) ((x) & 0x1F) | |
1488 | #define _DARF_RC6(x) (((x) & 0x1F) << 8) | |
1489 | #define _DARF_RC7(x) (((x) & 0x1F) << 16) | |
1490 | #define _DARF_RC8(x) (((x) & 0x1F) << 24) | |
1491 | ||
1492 | ||
1493 | /* 2 RARFRC */ | |
1494 | #define _RARF_RC1(x) ((x) & 0x1F) | |
1495 | #define _RARF_RC2(x) (((x) & 0x1F) << 8) | |
1496 | #define _RARF_RC3(x) (((x) & 0x1F) << 16) | |
1497 | #define _RARF_RC4(x) (((x) & 0x1F) << 24) | |
1498 | /* NOTE: shift starting from address (RARFRC + 4) */ | |
1499 | #define _RARF_RC5(x) ((x) & 0x1F) | |
1500 | #define _RARF_RC6(x) (((x) & 0x1F) << 8) | |
1501 | #define _RARF_RC7(x) (((x) & 0x1F) << 16) | |
1502 | #define _RARF_RC8(x) (((x) & 0x1F) << 24) | |
1503 | ||
1504 | ||
1505 | /* */ | |
1506 | /* */ | |
1507 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ | |
1508 | /* */ | |
1509 | /* */ | |
1510 | ||
1511 | ||
1512 | ||
1513 | /* 2 EDCA setting */ | |
1514 | #define AC_PARAM_TXOP_LIMIT_OFFSET 16 | |
1515 | #define AC_PARAM_ECW_MAX_OFFSET 12 | |
1516 | #define AC_PARAM_ECW_MIN_OFFSET 8 | |
1517 | #define AC_PARAM_AIFS_OFFSET 0 | |
1518 | ||
1519 | ||
1520 | /* 2 EDCA_VO_PARAM */ | |
1521 | #define _AIFS(x) (x) | |
1522 | #define _ECW_MAX_MIN(x) ((x) << 8) | |
1523 | #define _TXOP_LIMIT(x) ((x) << 16) | |
1524 | ||
1525 | ||
1526 | #define _BCNIFS(x) ((x) & 0xFF) | |
1527 | #define _BCNECW(x) (((x) & 0xF))<< 8) | |
1528 | ||
1529 | ||
1530 | #define _LRL(x) ((x) & 0x3F) | |
1531 | #define _SRL(x) (((x) & 0x3F) << 8) | |
1532 | ||
1533 | ||
1534 | /* 2 SIFS_CCK */ | |
1535 | #define _SIFS_CCK_CTX(x) ((x) & 0xFF) | |
1536 | #define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); | |
1537 | ||
1538 | ||
1539 | /* 2 SIFS_OFDM */ | |
1540 | #define _SIFS_OFDM_CTX(x) ((x) & 0xFF) | |
1541 | #define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); | |
1542 | ||
1543 | ||
1544 | /* 2 TBTT PROHIBIT */ | |
1545 | #define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) | |
1546 | ||
1547 | ||
1548 | /* 2 REG_RD_CTRL */ | |
1549 | #define DIS_EDCA_CNT_DWN BIT(11) | |
1550 | ||
1551 | ||
1552 | /* 2 BCN_CTRL */ | |
1553 | #define EN_MBSSID BIT(1) | |
1554 | #define EN_TXBCN_RPT BIT(2) | |
1555 | #define EN_BCN_FUNCTION BIT(3) | |
1556 | #define DIS_TSF_UPDATE BIT(3) | |
1557 | ||
1558 | /* The same function but different bit field. */ | |
1559 | #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) | |
1560 | #define DIS_TSF_UDT0_TEST_CHIP BIT(5) | |
1561 | ||
1562 | /* 2 ACMHWCTRL */ | |
1563 | #define AcmHw_HwEn BIT(0) | |
1564 | #define AcmHw_BeqEn BIT(1) | |
1565 | #define AcmHw_ViqEn BIT(2) | |
1566 | #define AcmHw_VoqEn BIT(3) | |
1567 | #define AcmHw_BeqStatus BIT(4) | |
1568 | #define AcmHw_ViqStatus BIT(5) | |
1569 | #define AcmHw_VoqStatus BIT(6) | |
1570 | ||
1571 | ||
1572 | ||
1573 | /* */ | |
1574 | /* */ | |
1575 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ | |
1576 | /* */ | |
1577 | /* */ | |
1578 | ||
1579 | /* 2 APSD_CTRL */ | |
1580 | #define APSDOFF BIT(6) | |
1581 | #define APSDOFF_STATUS BIT(7) | |
1582 | ||
1583 | ||
1584 | /* 2 BWOPMODE */ | |
1585 | #define BW_20MHZ BIT(2) | |
1586 | ||
1587 | ||
1588 | #define RATE_BITMAP_ALL 0xFFFFF | |
1589 | ||
1590 | /* Only use CCK 1M rate for ACK */ | |
1591 | #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 | |
1592 | ||
1593 | /* 2 TCR */ | |
1594 | #define TSFRST BIT(0) | |
1595 | #define DIS_GCLK BIT(1) | |
1596 | #define PAD_SEL BIT(2) | |
1597 | #define PWR_ST BIT(6) | |
1598 | #define PWRBIT_OW_EN BIT(7) | |
1599 | #define ACRC BIT(8) | |
1600 | #define CFENDFORM BIT(9) | |
1601 | #define ICV BIT(10) | |
1602 | ||
1603 | ||
1604 | ||
1605 | /* 2 RCR */ | |
1606 | #define AAP BIT(0) | |
1607 | #define APM BIT(1) | |
1608 | #define AM BIT(2) | |
1609 | #define AB BIT(3) | |
1610 | #define ADD3 BIT(4) | |
1611 | #define APWRMGT BIT(5) | |
1612 | #define CBSSID BIT(6) | |
1613 | #define CBSSID_BCN BIT(7) | |
1614 | #define ACRC32 BIT(8) | |
1615 | #define AICV BIT(9) | |
1616 | #define ADF BIT(11) | |
1617 | #define ACF BIT(12) | |
1618 | #define AMF BIT(13) | |
1619 | #define HTC_LOC_CTRL BIT(14) | |
1620 | #define UC_DATA_EN BIT(16) | |
1621 | #define BM_DATA_EN BIT(17) | |
1622 | #define MFBEN BIT(22) | |
1623 | #define LSIGEN BIT(23) | |
1624 | #define EnMBID BIT(24) | |
1625 | #define APP_BASSN BIT(27) | |
1626 | #define APP_PHYSTS BIT(28) | |
1627 | #define APP_ICV BIT(29) | |
1628 | #define APP_MIC BIT(30) | |
1629 | #define APP_FCS BIT(31) | |
1630 | ||
1631 | /* 2 RX_PKT_LIMIT */ | |
1632 | ||
1633 | /* 2 RX_DLK_TIME */ | |
1634 | ||
1635 | /* 2 MBIDCAMCFG */ | |
1636 | ||
1637 | ||
1638 | ||
1639 | /* 2 AMPDU_MIN_SPACE */ | |
1640 | #define _MIN_SPACE(x) ((x) & 0x7) | |
1641 | #define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) | |
1642 | ||
1643 | ||
1644 | /* 2 RXERR_RPT */ | |
1645 | #define RXERR_TYPE_OFDM_PPDU 0 | |
1646 | #define RXERR_TYPE_OFDMfalse_ALARM 1 | |
1647 | #define RXERR_TYPE_OFDM_MPDU_OK 2 | |
1648 | #define RXERR_TYPE_OFDM_MPDU_FAIL 3 | |
1649 | #define RXERR_TYPE_CCK_PPDU 4 | |
1650 | #define RXERR_TYPE_CCKfalse_ALARM 5 | |
1651 | #define RXERR_TYPE_CCK_MPDU_OK 6 | |
1652 | #define RXERR_TYPE_CCK_MPDU_FAIL 7 | |
1653 | #define RXERR_TYPE_HT_PPDU 8 | |
1654 | #define RXERR_TYPE_HTfalse_ALARM 9 | |
1655 | #define RXERR_TYPE_HT_MPDU_TOTAL 10 | |
1656 | #define RXERR_TYPE_HT_MPDU_OK 11 | |
1657 | #define RXERR_TYPE_HT_MPDU_FAIL 12 | |
1658 | #define RXERR_TYPE_RX_FULL_DROP 15 | |
1659 | ||
1660 | #define RXERR_COUNTER_MASK 0xFFFFF | |
1661 | #define RXERR_RPT_RST BIT(27) | |
1662 | #define _RXERR_RPT_SEL(type) ((type) << 28) | |
1663 | ||
1664 | ||
1665 | /* 2 SECCFG */ | |
1666 | #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ | |
1667 | #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ | |
1668 | #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ | |
1669 | #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ | |
1670 | #define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ | |
1671 | #define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ | |
1672 | ||
1673 | ||
1674 | ||
1675 | /* */ | |
1676 | /* */ | |
1677 | /* 0xFE00h ~ 0xFE55h USB Configuration */ | |
1678 | /* */ | |
1679 | /* */ | |
1680 | ||
1681 | /* 2 USB Information (0xFE17) */ | |
1682 | #define USB_IS_HIGH_SPEED 0 | |
1683 | #define USB_IS_FULL_SPEED 1 | |
1684 | #define USB_SPEED_MASK BIT(5) | |
1685 | ||
1686 | #define USB_NORMAL_SIE_EP_MASK 0xF | |
1687 | #define USB_NORMAL_SIE_EP_SHIFT 4 | |
1688 | ||
1689 | #define USB_TEST_EP_MASK 0x30 | |
1690 | #define USB_TEST_EP_SHIFT 4 | |
1691 | ||
1692 | /* 2 Special Option */ | |
1693 | #define USB_AGG_EN BIT(3) | |
1694 | ||
1695 | ||
1696 | /* 2REG_C2HEVT_CLEAR */ | |
1697 | /* Set by driver and notify FW that the driver has read the | |
1698 | C2H command message */ | |
1699 | #define C2H_EVT_HOST_CLOSE 0x00 | |
1700 | /* Set by FW indicating that FW had set the C2H command message | |
1701 | and it's not yet read by driver. */ | |
1702 | #define C2H_EVT_FW_CLOSE 0xFF | |
1703 | ||
1704 | ||
1705 | /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ | |
1706 | /* Enable GPIO[9] as WiFi HW PDn source */ | |
9c45c20d | 1707 | #define WL_HWPDN_EN BIT(0) |
364e30eb | 1708 | /* WiFi HW PDn polarity control */ |
9c45c20d | 1709 | #define WL_HWPDN_SL BIT(1) |
364e30eb | 1710 | /* WiFi function enable */ |
9c45c20d | 1711 | #define WL_FUNC_EN BIT(2) |
364e30eb | 1712 | /* Enable GPIO[9] as WiFi RF HW PDn source */ |
9c45c20d | 1713 | #define WL_HWROF_EN BIT(3) |
364e30eb | 1714 | /* Enable GPIO[11] as BT HW PDn source */ |
9c45c20d | 1715 | #define BT_HWPDN_EN BIT(16) |
364e30eb | 1716 | /* BT HW PDn polarity control */ |
9c45c20d | 1717 | #define BT_HWPDN_SL BIT(17) |
364e30eb | 1718 | /* BT function enable */ |
9c45c20d | 1719 | #define BT_FUNC_EN BIT(18) |
364e30eb | 1720 | /* Enable GPIO[11] as BT/GPS RF HW PDn source */ |
9c45c20d | 1721 | #define BT_HWROF_EN BIT(19) |
364e30eb | 1722 | /* Enable GPIO[10] as GPS HW PDn source */ |
9c45c20d | 1723 | #define GPS_HWPDN_EN BIT(20) |
364e30eb | 1724 | /* GPS HW PDn polarity control */ |
9c45c20d | 1725 | #define GPS_HWPDN_SL BIT(21) |
364e30eb | 1726 | /* GPS function enable */ |
9c45c20d | 1727 | #define GPS_FUNC_EN BIT(22) |
364e30eb LF |
1728 | |
1729 | /* 3 REG_LIFECTRL_CTRL */ | |
9c45c20d JS |
1730 | #define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3) |
1731 | #define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2) | |
1732 | #define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1) | |
1733 | #define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0) | |
364e30eb LF |
1734 | |
1735 | #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */ | |
1736 | ||
1737 | /* */ | |
1738 | /* General definitions */ | |
1739 | /* */ | |
1740 | ||
1741 | #define LAST_ENTRY_OF_TX_PKT_BUFFER 255 | |
1742 | ||
1743 | #define POLLING_LLT_THRESHOLD 20 | |
1744 | #define POLLING_READY_TIMEOUT_COUNT 1000 | |
1745 | ||
1746 | /* Min Spacing related settings. */ | |
1747 | #define MAX_MSS_DENSITY_2T 0x13 | |
1748 | #define MAX_MSS_DENSITY_1T 0x0A | |
1749 | ||
1750 | /* */ | |
1751 | /* 8723A Regsiter offset definition */ | |
1752 | /* */ | |
1753 | #define HAL_8723A_NAV_UPPER_UNIT 128 /* micro-second */ | |
1754 | ||
1755 | /* */ | |
1756 | /* */ | |
1757 | /* 0x0000h ~ 0x00FFh System Configuration */ | |
1758 | /* */ | |
1759 | /* */ | |
1760 | #define REG_SYSON_REG_LOCK 0x001C | |
1761 | ||
1762 | ||
1763 | /* */ | |
1764 | /* */ | |
1765 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ | |
1766 | /* */ | |
1767 | /* */ | |
1768 | #define REG_FTIMR 0x0138 | |
1769 | ||
1770 | ||
1771 | /* */ | |
1772 | /* */ | |
1773 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ | |
1774 | /* */ | |
1775 | /* */ | |
1776 | ||
1777 | ||
1778 | /* */ | |
1779 | /* */ | |
1780 | /* 0x0280h ~ 0x02FFh RXDMA Configuration */ | |
1781 | /* */ | |
1782 | /* */ | |
1783 | ||
1784 | ||
1785 | /* */ | |
1786 | /* */ | |
1787 | /* 0x0300h ~ 0x03FFh PCIe */ | |
1788 | /* */ | |
1789 | /* */ | |
1790 | ||
1791 | ||
1792 | /* */ | |
1793 | /* */ | |
1794 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ | |
1795 | /* */ | |
1796 | /* */ | |
1797 | #define REG_EARLY_MODE_CONTROL 0x4D0 | |
1798 | ||
1799 | ||
1800 | /* */ | |
1801 | /* */ | |
1802 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ | |
1803 | /* */ | |
1804 | /* */ | |
1805 | ||
1806 | /* 2 BCN_CTRL */ | |
1807 | #define DIS_ATIM BIT(0) | |
1808 | #define DIS_BCNQ_SUB BIT(1) | |
1809 | #define DIS_TSF_UDT BIT(4) | |
1810 | ||
1811 | ||
1812 | /* */ | |
1813 | /* */ | |
1814 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ | |
1815 | /* */ | |
1816 | /* */ | |
1817 | /* */ | |
1818 | /* Note: */ | |
1819 | /* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. | |
1820 | * The default value is always too small, but the WiFi TestPlan test | |
1821 | * by 25,000 microseconds of NAV through sending CTS in the air. We | |
1822 | * must update this value greater than 25,000 microseconds to pass the | |
1823 | * item. | |
1824 | * The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset | |
1825 | * should be 0x0652. Commented by SD1 Scott. */ | |
1826 | /* By Bruce, 2011-07-18. */ | |
1827 | /* */ | |
1828 | #define REG_NAV_UPPER 0x0652 /* unit of 128 */ | |
1829 | ||
1830 | ||
1831 | /* */ | |
1832 | /* 8723 Regsiter Bit and Content definition */ | |
1833 | /* */ | |
1834 | ||
1835 | /* */ | |
1836 | /* */ | |
1837 | /* 0x0000h ~ 0x00FFh System Configuration */ | |
1838 | /* */ | |
1839 | /* */ | |
1840 | ||
1841 | /* 2 SPS0_CTRL */ | |
1842 | ||
1843 | /* 2 SYS_ISO_CTRL */ | |
1844 | ||
1845 | /* 2 SYS_FUNC_EN */ | |
1846 | ||
1847 | /* 2 APS_FSMCO */ | |
1848 | #define EN_WLON BIT(16) | |
1849 | ||
1850 | /* 2 SYS_CLKR */ | |
1851 | ||
1852 | /* 2 9346CR */ | |
1853 | ||
1854 | /* 2 AFE_MISC */ | |
1855 | ||
1856 | /* 2 SPS0_CTRL */ | |
1857 | ||
1858 | /* 2 SPS_OCP_CFG */ | |
1859 | ||
1860 | /* 2 SYSON_REG_LOCK */ | |
1861 | #define WLOCK_ALL BIT(0) | |
1862 | #define WLOCK_00 BIT(1) | |
1863 | #define WLOCK_04 BIT(2) | |
1864 | #define WLOCK_08 BIT(3) | |
1865 | #define WLOCK_40 BIT(4) | |
1866 | #define WLOCK_1C_B6 BIT(5) | |
1867 | #define R_DIS_PRST_1 BIT(6) | |
1868 | #define LOCK_ALL_EN BIT(7) | |
1869 | ||
1870 | /* 2 RF_CTRL */ | |
1871 | ||
1872 | /* 2 LDOA15_CTRL */ | |
1873 | ||
1874 | /* 2 LDOV12D_CTRL */ | |
1875 | ||
1876 | /* 2 AFE_XTAL_CTRL */ | |
1877 | ||
1878 | /* 2 AFE_PLL_CTRL */ | |
1879 | ||
1880 | /* 2 EFUSE_CTRL */ | |
1881 | ||
1882 | /* 2 EFUSE_TEST (For RTL8723 partially) */ | |
1883 | ||
1884 | /* 2 PWR_DATA */ | |
1885 | ||
1886 | /* 2 CAL_TIMER */ | |
1887 | ||
1888 | /* 2 ACLK_MON */ | |
1889 | ||
1890 | /* 2 GPIO_MUXCFG */ | |
1891 | ||
1892 | /* 2 GPIO_PIN_CTRL */ | |
1893 | ||
1894 | /* 2 GPIO_INTM */ | |
1895 | ||
1896 | /* 2 LEDCFG */ | |
1897 | ||
1898 | /* 2 FSIMR */ | |
1899 | ||
1900 | /* 2 FSISR */ | |
1901 | ||
1902 | /* 2 HSIMR */ | |
1903 | /* 8723 Host System Interrupt Mask Register (offset 0x58, 32 byte) */ | |
1904 | #define HSIMR_GPIO12_0_INT_EN BIT(0) | |
1905 | #define HSIMR_SPS_OCP_INT_EN BIT(5) | |
1906 | #define HSIMR_RON_INT_EN BIT(6) | |
1907 | #define HSIMR_PDNINT_EN BIT(7) | |
1908 | #define HSIMR_GPIO9_INT_EN BIT(25) | |
1909 | ||
1910 | /* 2 HSISR */ | |
1911 | /* 8723 Host System Interrupt Status Register (offset 0x5C, 32 byte) */ | |
1912 | #define HSISR_GPIO12_0_INT BIT(0) | |
1913 | #define HSISR_SPS_OCP_INT BIT(5) | |
1914 | #define HSISR_RON_INT BIT(6) | |
1915 | #define HSISR_PDNINT BIT(7) | |
1916 | #define HSISR_GPIO9_INT BIT(25) | |
1917 | ||
1918 | /* interrupt mask which needs to clear */ | |
1919 | #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT | \ | |
1920 | HSISR_SPS_OCP_INT | \ | |
1921 | HSISR_RON_INT | \ | |
1922 | HSISR_PDNINT | \ | |
1923 | HSISR_GPIO9_INT) | |
1924 | ||
1925 | /* 2 MCUFWDL */ | |
9c45c20d | 1926 | #define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */ |
364e30eb LF |
1927 | |
1928 | /* 2 HPON_FSM */ | |
1929 | ||
1930 | /* 2 SYS_CFG */ | |
1931 | #define RTL_ID BIT(23) /* TestChip ID, | |
1932 | 1:Test(RLE); 0:MP(RL) */ | |
1933 | #define SPS_SEL BIT(24) /* 1:LDO regulator mode; | |
1934 | 0:Switching regulator mode*/ | |
1935 | ||
1936 | ||
1937 | /* */ | |
1938 | /* */ | |
1939 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ | |
1940 | /* */ | |
1941 | /* */ | |
1942 | ||
1943 | /* 2 Function Enable Registers */ | |
1944 | ||
1945 | /* 2 CR */ | |
1946 | #define CALTMR_EN BIT(10) | |
1947 | ||
1948 | /* 2 PBP - Page Size Register */ | |
1949 | ||
1950 | /* 2 TX/RXDMA */ | |
1951 | ||
1952 | /* 2 TRXFF_BNDY */ | |
1953 | ||
1954 | /* 2 LLT_INIT */ | |
1955 | ||
1956 | /* 2 BB_ACCESS_CTRL */ | |
1957 | ||
1958 | ||
1959 | /* */ | |
1960 | /* */ | |
1961 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ | |
1962 | /* */ | |
1963 | /* */ | |
1964 | ||
1965 | /* 2 RQPN */ | |
1966 | ||
1967 | /* 2 TDECTRL */ | |
1968 | ||
1969 | /* 2 TDECTL */ | |
1970 | ||
1971 | /* 2 TXDMA_OFFSET_CHK */ | |
1972 | ||
1973 | ||
1974 | /* */ | |
1975 | /* */ | |
1976 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ | |
1977 | /* */ | |
1978 | /* */ | |
1979 | ||
1980 | /* 2 FWHW_TXQ_CTRL */ | |
1981 | ||
1982 | /* 2 INIRTSMCS_SEL */ | |
1983 | ||
1984 | /* 2 SPEC SIFS */ | |
1985 | ||
1986 | /* 2 RRSR */ | |
1987 | ||
1988 | /* 2 ARFR */ | |
1989 | ||
1990 | /* 2 AGGLEN_LMT_L */ | |
1991 | ||
1992 | /* 2 RL */ | |
1993 | ||
1994 | /* 2 DARFRC */ | |
1995 | ||
1996 | /* 2 RARFRC */ | |
1997 | ||
1998 | ||
1999 | /* */ | |
2000 | /* */ | |
2001 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ | |
2002 | /* */ | |
2003 | /* */ | |
2004 | ||
2005 | /* 2 EDCA setting */ | |
2006 | ||
2007 | /* 2 EDCA_VO_PARAM */ | |
2008 | ||
2009 | /* 2 SIFS_CCK */ | |
2010 | ||
2011 | /* 2 SIFS_OFDM */ | |
2012 | ||
2013 | /* 2 TBTT PROHIBIT */ | |
2014 | ||
2015 | /* 2 REG_RD_CTRL */ | |
2016 | ||
2017 | /* 2 BCN_CTRL */ | |
2018 | ||
2019 | /* 2 ACMHWCTRL */ | |
2020 | ||
2021 | ||
2022 | /* */ | |
2023 | /* */ | |
2024 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ | |
2025 | /* */ | |
2026 | /* */ | |
2027 | ||
2028 | /* 2 APSD_CTRL */ | |
2029 | ||
2030 | /* 2 BWOPMODE */ | |
2031 | ||
2032 | /* 2 TCR */ | |
2033 | ||
2034 | /* 2 RCR */ | |
2035 | ||
2036 | /* 2 RX_PKT_LIMIT */ | |
2037 | ||
2038 | /* 2 RX_DLK_TIME */ | |
2039 | ||
2040 | /* 2 MBIDCAMCFG */ | |
2041 | ||
2042 | /* 2 AMPDU_MIN_SPACE */ | |
2043 | ||
2044 | /* 2 RXERR_RPT */ | |
2045 | ||
2046 | /* 2 SECCFG */ | |
2047 | ||
2048 | ||
2049 | /* */ | |
2050 | /* */ | |
2051 | /* 0xFE00h ~ 0xFE55h RTL8723 SDIO Configuration */ | |
2052 | /* */ | |
2053 | /* */ | |
2054 | ||
2055 | /* I/O bus domain address mapping */ | |
2056 | #define WLAN_IOREG_BASE 0x10260000 | |
2057 | #define FIRMWARE_FIFO_BASE 0x10270000 | |
2058 | #define TX_HIQ_BASE 0x10310000 | |
2059 | #define TX_MIQ_BASE 0x10320000 | |
2060 | #define TX_LOQ_BASE 0x10330000 | |
2061 | #define RX_RX0FF_BASE 0x10340000 | |
2062 | ||
2063 | /* SDIO host local register space mapping. */ | |
2064 | #define WLAN_IOREG_MSK 0x7FFF | |
2065 | #define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ | |
2066 | #define WLAN_RX0FF_MSK 0x0003 | |
2067 | ||
2068 | #define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ | |
2069 | #define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ | |
2070 | ||
2071 | /* 8723 EFUSE */ | |
2072 | #define HWSET_MAX_SIZE 256 | |
2073 | ||
2074 | ||
2075 | /* USB interrupt */ | |
9c45c20d JS |
2076 | #define UHIMR_TIMEOUT2 BIT(31) |
2077 | #define UHIMR_TIMEOUT1 BIT(30) | |
2078 | #define UHIMR_PSTIMEOUT BIT(29) | |
2079 | #define UHIMR_GTINT4 BIT(28) | |
2080 | #define UHIMR_GTINT3 BIT(27) | |
2081 | #define UHIMR_TXBCNERR BIT(26) | |
2082 | #define UHIMR_TXBCNOK BIT(25) | |
2083 | #define UHIMR_TSF_BIT32_TOGGLE BIT(24) | |
2084 | #define UHIMR_BCNDMAINT3 BIT(23) | |
2085 | #define UHIMR_BCNDMAINT2 BIT(22) | |
2086 | #define UHIMR_BCNDMAINT1 BIT(21) | |
2087 | #define UHIMR_BCNDMAINT0 BIT(20) | |
2088 | #define UHIMR_BCNDOK3 BIT(19) | |
2089 | #define UHIMR_BCNDOK2 BIT(18) | |
2090 | #define UHIMR_BCNDOK1 BIT(17) | |
2091 | #define UHIMR_BCNDOK0 BIT(16) | |
2092 | #define UHIMR_HSISR_IND BIT(15) | |
2093 | #define UHIMR_BCNDMAINT_E BIT(14) | |
2094 | /* RSVD BIT(13) */ | |
2095 | #define UHIMR_CTW_END BIT(12) | |
2096 | /* RSVD BIT(11) */ | |
2097 | #define UHIMR_C2HCMD BIT(10) | |
2098 | #define UHIMR_CPWM2 BIT(9) | |
2099 | #define UHIMR_CPWM BIT(8) | |
2100 | #define UHIMR_HIGHDOK BIT(7) /* High Queue DMA OK | |
364e30eb | 2101 | Interrupt */ |
9c45c20d | 2102 | #define UHIMR_MGNTDOK BIT(6) /* Management Queue DMA OK |
364e30eb | 2103 | Interrupt */ |
9c45c20d JS |
2104 | #define UHIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ |
2105 | #define UHIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ | |
2106 | #define UHIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ | |
2107 | #define UHIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ | |
2108 | #define UHIMR_RDU BIT(1) /* Receive Descriptor | |
364e30eb | 2109 | Unavailable */ |
9c45c20d | 2110 | #define UHIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ |
364e30eb LF |
2111 | |
2112 | /* USB Host Interrupt Status Extension bit */ | |
9c45c20d JS |
2113 | #define UHIMR_BCNDMAINT7 BIT(23) |
2114 | #define UHIMR_BCNDMAINT6 BIT(22) | |
2115 | #define UHIMR_BCNDMAINT5 BIT(21) | |
2116 | #define UHIMR_BCNDMAINT4 BIT(20) | |
2117 | #define UHIMR_BCNDOK7 BIT(19) | |
2118 | #define UHIMR_BCNDOK6 BIT(18) | |
2119 | #define UHIMR_BCNDOK5 BIT(17) | |
2120 | #define UHIMR_BCNDOK4 BIT(16) | |
364e30eb | 2121 | /* bit14-15: RSVD */ |
9c45c20d JS |
2122 | #define UHIMR_ATIMEND_E BIT(13) |
2123 | #define UHIMR_ATIMEND BIT(12) | |
2124 | #define UHIMR_TXERR BIT(11) | |
2125 | #define UHIMR_RXERR BIT(10) | |
2126 | #define UHIMR_TXFOVW BIT(9) | |
2127 | #define UHIMR_RXFOVW BIT(8) | |
364e30eb | 2128 | /* bit2-7: RSVD */ |
9c45c20d | 2129 | #define UHIMR_OCPINT BIT(1) |
364e30eb LF |
2130 | /* bit0: RSVD */ |
2131 | ||
2132 | #define REG_USB_HIMR 0xFE38 | |
2133 | #define REG_USB_HIMRE 0xFE3C | |
2134 | #define REG_USB_HISR 0xFE78 | |
2135 | #define REG_USB_HISRE 0xFE7C | |
2136 | ||
2137 | #define USB_INTR_CPWM_OFFSET 16 | |
2138 | #define USB_INTR_CONTENT_HISR_OFFSET 48 | |
2139 | #define USB_INTR_CONTENT_HISRE_OFFSET 52 | |
2140 | #define USB_INTR_CONTENT_LENGTH 56 | |
2141 | #define USB_C2H_CMDID_OFFSET 0 | |
2142 | #define USB_C2H_SEQ_OFFSET 1 | |
2143 | #define USB_C2H_EVENT_OFFSET 2 | |
2144 | /* */ | |
2145 | /* General definitions */ | |
2146 | /* */ | |
2147 | ||
2148 | #endif |