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1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | ******************************************************************************/ | |
15 | #ifndef __RTL8723A_XMIT_H__ | |
16 | #define __RTL8723A_XMIT_H__ | |
17 | ||
18 | /* */ | |
19 | /* Queue Select Value in TxDesc */ | |
20 | /* */ | |
21 | #define QSLT_BK 0x2/* 0x01 */ | |
22 | #define QSLT_BE 0x0 | |
23 | #define QSLT_VI 0x5/* 0x4 */ | |
24 | #define QSLT_VO 0x7/* 0x6 */ | |
25 | #define QSLT_BEACON 0x10 | |
26 | #define QSLT_HIGH 0x11 | |
27 | #define QSLT_MGNT 0x12 | |
28 | #define QSLT_CMD 0x13 | |
29 | ||
30 | /* */ | |
31 | /* defined for TX DESC Operation */ | |
32 | /* */ | |
33 | ||
34 | #define MAX_TID (15) | |
35 | ||
36 | /* OFFSET 0 */ | |
37 | #define OFFSET_SZ 0 | |
38 | #define OFFSET_SHT 16 | |
39 | #define BMC BIT(24) | |
40 | #define LSG BIT(26) | |
41 | #define FSG BIT(27) | |
42 | #define OWN BIT(31) | |
43 | ||
44 | ||
45 | /* OFFSET 4 */ | |
46 | #define PKT_OFFSET_SZ 0 | |
47 | #define BK BIT(6) | |
48 | #define QSEL_SHT 8 | |
49 | #define Rate_ID_SHT 16 | |
50 | #define NAVUSEHDR BIT(20) | |
51 | #define PKT_OFFSET_SHT 26 | |
52 | #define HWPC BIT(31) | |
53 | ||
54 | /* OFFSET 8 */ | |
55 | #define AGG_EN BIT(29) | |
56 | ||
57 | /* OFFSET 12 */ | |
58 | #define SEQ_SHT 16 | |
59 | ||
60 | /* OFFSET 16 */ | |
61 | #define QoS BIT(6) | |
62 | #define HW_SEQ_EN BIT(7) | |
63 | #define USERATE BIT(8) | |
64 | #define DISDATAFB BIT(10) | |
65 | #define DATA_SHORT BIT(24) | |
66 | #define DATA_BW BIT(25) | |
67 | ||
68 | /* OFFSET 20 */ | |
69 | #define SGI BIT(6) | |
70 | ||
71 | struct txdesc_8723a { | |
72 | u32 pktlen:16; | |
73 | u32 offset:8; | |
74 | u32 bmc:1; | |
75 | u32 htc:1; | |
76 | u32 ls:1; | |
77 | u32 fs:1; | |
78 | u32 linip:1; | |
79 | u32 noacm:1; | |
80 | u32 gf:1; | |
81 | u32 own:1; | |
82 | ||
83 | u32 macid:5; | |
84 | u32 agg_en:1; | |
85 | u32 bk:1; | |
86 | u32 rd_en:1; | |
87 | u32 qsel:5; | |
88 | u32 rd_nav_ext:1; | |
89 | u32 lsig_txop_en:1; | |
90 | u32 pifs:1; | |
91 | u32 rate_id:4; | |
92 | u32 navusehdr:1; | |
93 | u32 en_desc_id:1; | |
94 | u32 sectype:2; | |
95 | u32 rsvd0424:2; | |
96 | u32 pkt_offset:5; /* unit: 8 bytes */ | |
97 | u32 rsvd0431:1; | |
98 | ||
99 | u32 rts_rc:6; | |
100 | u32 data_rc:6; | |
101 | u32 rsvd0812:2; | |
102 | u32 bar_rty_th:2; | |
103 | u32 rsvd0816:1; | |
104 | u32 morefrag:1; | |
105 | u32 raw:1; | |
106 | u32 ccx:1; | |
107 | u32 ampdu_density:3; | |
108 | u32 bt_null:1; | |
109 | u32 ant_sel_a:1; | |
110 | u32 ant_sel_b:1; | |
111 | u32 tx_ant_cck:2; | |
112 | u32 tx_antl:2; | |
113 | u32 tx_ant_ht:2; | |
114 | ||
115 | u32 nextheadpage:8; | |
116 | u32 tailpage:8; | |
117 | u32 seq:12; | |
118 | u32 cpu_handle:1; | |
119 | u32 tag1:1; | |
120 | u32 trigger_int:1; | |
121 | u32 hwseq_en:1; | |
122 | ||
123 | u32 rtsrate:5; | |
124 | u32 ap_dcfe:1; | |
125 | u32 hwseq_sel:2; | |
126 | u32 userate:1; | |
127 | u32 disrtsfb:1; | |
128 | u32 disdatafb:1; | |
129 | u32 cts2self:1; | |
130 | u32 rtsen:1; | |
131 | u32 hw_rts_en:1; | |
132 | u32 port_id:1; | |
133 | u32 rsvd1615:3; | |
134 | u32 wait_dcts:1; | |
135 | u32 cts2ap_en:1; | |
136 | u32 data_sc:2; | |
137 | u32 data_stbc:2; | |
138 | u32 data_short:1; | |
139 | u32 data_bw:1; | |
140 | u32 rts_short:1; | |
141 | u32 rts_bw:1; | |
142 | u32 rts_sc:2; | |
143 | u32 vcs_stbc:2; | |
144 | ||
145 | u32 datarate:6; | |
146 | u32 sgi:1; | |
147 | u32 try_rate:1; | |
148 | u32 data_ratefb_lmt:5; | |
149 | u32 rts_ratefb_lmt:4; | |
150 | u32 rty_lmt_en:1; | |
151 | u32 data_rt_lmt:6; | |
152 | u32 usb_txagg_num:8; | |
153 | ||
154 | u32 txagg_a:5; | |
155 | u32 txagg_b:5; | |
156 | u32 use_max_len:1; | |
157 | u32 max_agg_num:5; | |
158 | u32 mcsg1_max_len:4; | |
159 | u32 mcsg2_max_len:4; | |
160 | u32 mcsg3_max_len:4; | |
161 | u32 mcs7_sgi_max_len:4; | |
162 | ||
163 | u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */ | |
164 | u32 mcsg4_max_len:4; | |
165 | u32 mcsg5_max_len:4; | |
166 | u32 mcsg6_max_len:4; | |
167 | u32 mcs15_sgi_max_len:4; | |
168 | }; | |
169 | ||
170 | #define txdesc_set_ccx_sw_8723a(txdesc, value) \ | |
171 | do { \ | |
172 | ((struct txdesc_8723a *)(txdesc))->mcsg4_max_len = (((value)>>8) & 0x0f); \ | |
173 | ((struct txdesc_8723a *)(txdesc))->mcs15_sgi_max_len= (((value)>>4) & 0x0f); \ | |
174 | ((struct txdesc_8723a *)(txdesc))->mcsg6_max_len = ((value) & 0x0f); \ | |
175 | } while (0) | |
176 | ||
177 | struct txrpt_ccx_8723a { | |
178 | /* offset 0 */ | |
179 | u8 tag1:1; | |
180 | u8 rsvd:4; | |
181 | u8 int_bt:1; | |
182 | u8 int_tri:1; | |
183 | u8 int_ccx:1; | |
184 | ||
185 | /* offset 1 */ | |
186 | u8 mac_id:5; | |
187 | u8 pkt_drop:1; | |
188 | u8 pkt_ok:1; | |
189 | u8 bmc:1; | |
190 | ||
191 | /* offset 2 */ | |
192 | u8 retry_cnt:6; | |
193 | u8 lifetime_over:1; | |
194 | u8 retry_over:1; | |
195 | ||
196 | /* offset 3 */ | |
197 | u8 ccx_qtime0; | |
198 | u8 ccx_qtime1; | |
199 | ||
200 | /* offset 5 */ | |
201 | u8 final_data_rate; | |
202 | ||
203 | /* offset 6 */ | |
204 | u8 sw1:4; | |
205 | u8 qsel:4; | |
206 | ||
207 | /* offset 7 */ | |
208 | u8 sw0; | |
209 | }; | |
210 | ||
211 | #define txrpt_ccx_sw_8723a(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8)) | |
212 | #define txrpt_ccx_qtime_8723a(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) | |
213 | ||
364e30eb | 214 | void handle_txrpt_ccx_8723a(struct rtw_adapter *adapter, void *buf); |
364e30eb LF |
215 | void rtl8723a_fill_fake_txdesc(struct rtw_adapter *padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull); |
216 | ||
638443dc | 217 | int rtl8723au_hal_xmitframe_enqueue(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe); |
364e30eb LF |
218 | s32 rtl8723au_xmit_buf_handler(struct rtw_adapter *padapter); |
219 | #define hal_xmit_handler rtl8723au_xmit_buf_handler | |
638443dc | 220 | bool rtl8723au_hal_xmit(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe); |
5c195cc2 JS |
221 | int rtl8723au_mgnt_xmit(struct rtw_adapter *padapter, struct xmit_frame *pmgntframe); |
222 | bool rtl8723au_xmitframe_complete(struct rtw_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); | |
364e30eb LF |
223 | |
224 | ||
225 | #endif |