[deliverable/linux.git] / drivers / staging / rtl8723au / include / rtw_io.h

/******************************************************************************
 *
 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 ******************************************************************************/

#ifndef _RTW_IO_H_
#define _RTW_IO_H_

#include <osdep_service.h>
#include <osdep_intf.h>

#include <asm/byteorder.h>
#include <linux/semaphore.h>
#include <linux/list.h>
/* include <linux/smp_lock.h> */
#include <linux/spinlock.h>
#include <asm/atomic.h>

#include <linux/usb.h>
#include <linux/usb/ch9.h>

#define rtw_usb_buffer_alloc(dev, size, dma) usb_alloc_coherent((dev), (size), (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), (dma))
#define rtw_usb_buffer_free(dev, size, addr, dma) usb_free_coherent((dev), (size), (addr), (dma))

#define NUM_IOREQ		8

#define MAX_PROT_SZ	(64-16)

#define _IOREADY			0
#define _IO_WAIT_COMPLETE   1
#define _IO_WAIT_RSP        2

/*  IO COMMAND TYPE */
#define _IOSZ_MASK_		(0x7F)
#define _IO_WRITE_		BIT(7)
#define _IO_FIXED_		BIT(8)
#define _IO_BURST_		BIT(9)
#define _IO_BYTE_		BIT(10)
#define _IO_HW_			BIT(11)
#define _IO_WORD_		BIT(12)
#define _IO_SYNC_		BIT(13)
#define _IO_CMDMASK_	(0x1F80)


/*
	For prompt mode accessing, caller shall free io_req
	Otherwise, io_handler will free io_req
*/


/*  IO STATUS TYPE */
#define _IO_ERR_		BIT(2)
#define _IO_SUCCESS_	BIT(1)
#define _IO_DONE_		BIT(0)


#define IO_RD32			(_IO_SYNC_ | _IO_WORD_)
#define IO_RD16			(_IO_SYNC_ | _IO_HW_)
#define IO_RD8			(_IO_SYNC_ | _IO_BYTE_)

#define IO_RD32_ASYNC	(_IO_WORD_)
#define IO_RD16_ASYNC	(_IO_HW_)
#define IO_RD8_ASYNC	(_IO_BYTE_)

#define IO_WR32			(_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)
#define IO_WR16			(_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)
#define IO_WR8			(_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)

#define IO_WR32_ASYNC	(_IO_WRITE_ | _IO_WORD_)
#define IO_WR16_ASYNC	(_IO_WRITE_ | _IO_HW_)
#define IO_WR8_ASYNC	(_IO_WRITE_ | _IO_BYTE_)

/*

	Only Sync. burst accessing is provided.

*/

#define IO_WR_BURST(x)		(_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_))
#define IO_RD_BURST(x)		(_IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_))


/* below is for the intf_option bit defition... */

#define _INTF_ASYNC_	BIT(0)	/* support async io */

struct intf_priv;

struct io_req {
	struct list_head	list;
	u32	addr;
	volatile u32	val;
	u32	command;
	u32	status;
	u8	*pbuf;
	struct semaphore	sema;

	void (*_async_io_callback)(struct rtw_adapter *padater, struct io_req *pio_req, u8 *cnxt);
	u8 *cnxt;
};

struct reg_protocol_rd {

#ifdef __LITTLE_ENDIAN

	/* DW1 */
	u32		NumOfTrans:4;
	u32		Reserved1:4;
	u32		Reserved2:24;
	/* DW2 */
	u32		ByteCount:7;
	u32		WriteEnable:1;		/* 0:read, 1:write */
	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
	u32		BurstMode:1;
	u32		Byte1Access:1;
	u32		Byte2Access:1;
	u32		Byte4Access:1;
	u32		Reserved3:3;
	u32		Reserved4:16;
	/* DW3 */
	u32		BusAddress;
	/* DW4 */
	/* u32		Value; */
#else


/* DW1 */
	u32 Reserved1  :4;
	u32 NumOfTrans :4;

	u32 Reserved2  :24;

	/* DW2 */
	u32 WriteEnable : 1;
	u32 ByteCount :7;


	u32 Reserved3 : 3;
	u32 Byte4Access : 1;

	u32 Byte2Access : 1;
	u32 Byte1Access : 1;
	u32 BurstMode :1 ;
	u32 FixOrContinuous : 1;

	u32 Reserved4 : 16;

	/* DW3 */
	u32		BusAddress;

	/* DW4 */
	/* u32		Value; */

#endif

};


struct reg_protocol_wt {


#ifdef __LITTLE_ENDIAN

	/* DW1 */
	u32		NumOfTrans:4;
	u32		Reserved1:4;
	u32		Reserved2:24;
	/* DW2 */
	u32		ByteCount:7;
	u32		WriteEnable:1;		/* 0:read, 1:write */
	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
	u32		BurstMode:1;
	u32		Byte1Access:1;
	u32		Byte2Access:1;
	u32		Byte4Access:1;
	u32		Reserved3:3;
	u32		Reserved4:16;
	/* DW3 */
	u32		BusAddress;
	/* DW4 */
	u32		Value;

#else
	/* DW1 */
	u32 Reserved1  :4;
	u32 NumOfTrans :4;

	u32 Reserved2  :24;

	/* DW2 */
	u32 WriteEnable : 1;
	u32 ByteCount :7;

	u32 Reserved3 : 3;
	u32 Byte4Access : 1;

	u32 Byte2Access : 1;
	u32 Byte1Access : 1;
	u32 BurstMode :1 ;
	u32 FixOrContinuous : 1;

	u32 Reserved4 : 16;

	/* DW3 */
	u32		BusAddress;

	/* DW4 */
	u32		Value;

#endif

};

#define PlatformEFIOWrite1Byte(_a, _b, _c)		\
	rtl8723au_write8(_a, _b, _c)
#define PlatformEFIOWrite2Byte(_a, _b, _c)		\
	rtl8723au_write16(_a, _b, _c)
#define PlatformEFIOWrite4Byte(_a, _b, _c)		\
	rtl8723au_write32(_a, _b, _c)

#define PlatformEFIORead1Byte(_a, _b)		rtl8723au_read8(_a, _b)
#define PlatformEFIORead2Byte(_a, _b)		rtl8723au_read16(_a, _b)
#define PlatformEFIORead4Byte(_a, _b)		rtl8723au_read32(_a, _b)

#endif	/* _RTL8711_IO_H_ */
Commit	Line	Data
364e30eb LF	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	******************************************************************************/
	15
	16	#ifndef _RTW_IO_H_
	17	#define _RTW_IO_H_
	18
	19	#include <osdep_service.h>
	20	#include <osdep_intf.h>
	21
	22	#include <asm/byteorder.h>
	23	#include <linux/semaphore.h>
	24	#include <linux/list.h>
	25	/* include <linux/smp_lock.h> */
	26	#include <linux/spinlock.h>
	27	#include <asm/atomic.h>
	28
	29	#include <linux/usb.h>
	30	#include <linux/usb/ch9.h>
	31
	32	#define rtw_usb_buffer_alloc(dev, size, dma) usb_alloc_coherent((dev), (size), (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), (dma))
	33	#define rtw_usb_buffer_free(dev, size, addr, dma) usb_free_coherent((dev), (size), (addr), (dma))
	34
	35	#define NUM_IOREQ 8
	36
	37	#define MAX_PROT_SZ (64-16)
	38
	39	#define _IOREADY 0
	40	#define _IO_WAIT_COMPLETE 1
	41	#define _IO_WAIT_RSP 2
	42
	43	/* IO COMMAND TYPE */
	44	#define _IOSZ_MASK_ (0x7F)
	45	#define _IO_WRITE_ BIT(7)
	46	#define _IO_FIXED_ BIT(8)
	47	#define _IO_BURST_ BIT(9)
	48	#define _IO_BYTE_ BIT(10)
	49	#define _IO_HW_ BIT(11)
	50	#define _IO_WORD_ BIT(12)
	51	#define _IO_SYNC_ BIT(13)
	52	#define _IO_CMDMASK_ (0x1F80)
	53
	54
	55	/*
	56	For prompt mode accessing, caller shall free io_req
	57	Otherwise, io_handler will free io_req
	58	*/
	59
	60
	61
	62	/* IO STATUS TYPE */
	63	#define _IO_ERR_ BIT(2)
	64	#define _IO_SUCCESS_ BIT(1)
65	#define _IO_DONE_ BIT(0)
66
67
68	#define IO_RD32 (_IO_SYNC_ \| _IO_WORD_)
69	#define IO_RD16 (_IO_SYNC_ \| _IO_HW_)
70	#define IO_RD8 (_IO_SYNC_ \| _IO_BYTE_)
71
72	#define IO_RD32_ASYNC (_IO_WORD_)
73	#define IO_RD16_ASYNC (_IO_HW_)
74	#define IO_RD8_ASYNC (_IO_BYTE_)
75
76	#define IO_WR32 (_IO_WRITE_ \| _IO_SYNC_ \| _IO_WORD_)
77	#define IO_WR16 (_IO_WRITE_ \| _IO_SYNC_ \| _IO_HW_)
78	#define IO_WR8 (_IO_WRITE_ \| _IO_SYNC_ \| _IO_BYTE_)
79
80	#define IO_WR32_ASYNC (_IO_WRITE_ \| _IO_WORD_)
81	#define IO_WR16_ASYNC (_IO_WRITE_ \| _IO_HW_)
82	#define IO_WR8_ASYNC (_IO_WRITE_ \| _IO_BYTE_)
83
84	/*
85
86	Only Sync. burst accessing is provided.
87
88	*/
89
90	#define IO_WR_BURST(x) (_IO_WRITE_ \| _IO_SYNC_ \| _IO_BURST_ \| ( (x) & _IOSZ_MASK_))
91	#define IO_RD_BURST(x) (_IO_SYNC_ \| _IO_BURST_ \| ( (x) & _IOSZ_MASK_))
92
93
94
95	/* below is for the intf_option bit defition... */
96
97	#define _INTF_ASYNC_ BIT(0) /* support async io */
98
99	struct intf_priv;
364e30eb	100
364e30eb LF	101	struct io_req {
	102	struct list_head list;
	103	u32 addr;
	104	volatile u32 val;
	105	u32 command;
	106	u32 status;
	107	u8 *pbuf;
	108	struct semaphore sema;
	109
	110	void (_async_io_callback)(struct rtw_adapter padater, struct io_req pio_req, u8 cnxt);
	111	u8 *cnxt;
	112	};
	113
364e30eb LF	114	struct reg_protocol_rd {
	115
	116	#ifdef __LITTLE_ENDIAN
	117
	118	/* DW1 */
	119	u32 NumOfTrans:4;
	120	u32 Reserved1:4;
	121	u32 Reserved2:24;
	122	/* DW2 */
	123	u32 ByteCount:7;
	124	u32 WriteEnable:1; /* 0:read, 1:write */
	125	u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */
	126	u32 BurstMode:1;
	127	u32 Byte1Access:1;
	128	u32 Byte2Access:1;
	129	u32 Byte4Access:1;
	130	u32 Reserved3:3;
	131	u32 Reserved4:16;
	132	/* DW3 */
	133	u32 BusAddress;
	134	/* DW4 */
	135	/* u32 Value; */
	136	#else
	137
	138
	139	/* DW1 */
	140	u32 Reserved1 :4;
	141	u32 NumOfTrans :4;
	142
	143	u32 Reserved2 :24;
	144
	145	/* DW2 */
	146	u32 WriteEnable : 1;
	147	u32 ByteCount :7;
	148
	149
	150	u32 Reserved3 : 3;
	151	u32 Byte4Access : 1;
	152
	153	u32 Byte2Access : 1;
	154	u32 Byte1Access : 1;
	155	u32 BurstMode :1 ;
	156	u32 FixOrContinuous : 1;
	157
	158	u32 Reserved4 : 16;
	159
	160	/* DW3 */
	161	u32 BusAddress;
	162
	163	/* DW4 */
	164	/* u32 Value; */
	165
	166	#endif
	167
	168	};
	169
	170
	171	struct reg_protocol_wt {
	172
	173
	174	#ifdef __LITTLE_ENDIAN
	175
	176	/* DW1 */
	177	u32 NumOfTrans:4;
178	u32 Reserved1:4;
179	u32 Reserved2:24;
180	/* DW2 */
181	u32 ByteCount:7;
182	u32 WriteEnable:1; /* 0:read, 1:write */
183	u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */
184	u32 BurstMode:1;
185	u32 Byte1Access:1;
186	u32 Byte2Access:1;
187	u32 Byte4Access:1;
188	u32 Reserved3:3;
189	u32 Reserved4:16;
190	/* DW3 */
191	u32 BusAddress;
192	/* DW4 */
193	u32 Value;
194
195	#else
196	/* DW1 */
197	u32 Reserved1 :4;
198	u32 NumOfTrans :4;
199
200	u32 Reserved2 :24;
201
202	/* DW2 */
203	u32 WriteEnable : 1;
204	u32 ByteCount :7;
205
206	u32 Reserved3 : 3;
207	u32 Byte4Access : 1;
208
209	u32 Byte2Access : 1;
210	u32 Byte1Access : 1;
211	u32 BurstMode :1 ;
212	u32 FixOrContinuous : 1;
213
214	u32 Reserved4 : 16;
215
216	/* DW3 */
217	u32 BusAddress;
218
219	/* DW4 */
220	u32 Value;
221
222	#endif
223
224	};
225
c895a5df GD	226	#define PlatformEFIOWrite1Byte(_a, _b, _c) \
	227	rtl8723au_write8(_a, _b, _c)
	228	#define PlatformEFIOWrite2Byte(_a, _b, _c) \
	229	rtl8723au_write16(_a, _b, _c)
	230	#define PlatformEFIOWrite4Byte(_a, _b, _c) \
	231	rtl8723au_write32(_a, _b, _c)
	232
	233	#define PlatformEFIORead1Byte(_a, _b) rtl8723au_read8(_a, _b)
	234	#define PlatformEFIORead2Byte(_a, _b) rtl8723au_read16(_a, _b)
	235	#define PlatformEFIORead4Byte(_a, _b) rtl8723au_read32(_a, _b)
364e30eb LF	236
364e30eb LF	237	#endif /* _RTL8711_IO_H_ */