projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4856ab33 MA |
1 | /* |
| 2 | * | |
| 3 | * sep_driver_hw_defs.h - Security Processor Driver hardware definitions | |
| 4 | * | |
| ff3d9c3c MA |
5 | * Copyright(c) 2009-2011 Intel Corporation. All rights reserved. |
| 6 | * Contributions(c) 2009-2011 Discretix. All rights reserved. | |
| 4856ab33 MA |
7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it | |
| 9 | * under the terms of the GNU General Public License as published by the Free | |
| 10 | * Software Foundation; version 2 of the License. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 15 | * more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License along with | |
| 18 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
| 19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 20 | * | |
| 21 | * CONTACTS: | |
| 22 | * | |
| 23 | * Mark Allyn mark.a.allyn@intel.com | |
| 24 | * Jayant Mangalampalli jayant.mangalampalli@intel.com | |
| 25 | * | |
| 26 | * CHANGES: | |
| 27 | * | |
| 28 | * 2010.09.20 Upgrade to Medfield | |
| ff3d9c3c | 29 | * 2011.02.22 Enable kernel crypto |
| 4856ab33 MA |
30 | * |
| 31 | */ | |
| 32 | ||
| 33 | #ifndef SEP_DRIVER_HW_DEFS__H | |
| 34 | #define SEP_DRIVER_HW_DEFS__H | |
| 35 | ||
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36 | /*----------------------- */ |
| 37 | /* HW Registers Defines. */ | |
| 38 | /* */ | |
| 39 | /*---------------------- -*/ | |
| 40 | ||
| 41 | ||
| 42 | /* cf registers */ | |
| 4856ab33 MA |
43 | #define HW_HOST_IRR_REG_ADDR 0x0A00UL |
| 44 | #define HW_HOST_IMR_REG_ADDR 0x0A04UL | |
| 45 | #define HW_HOST_ICR_REG_ADDR 0x0A08UL | |
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46 | #define HW_HOST_SEP_HOST_GPR0_REG_ADDR 0x0B00UL |
| 47 | #define HW_HOST_SEP_HOST_GPR1_REG_ADDR 0x0B04UL | |
| 48 | #define HW_HOST_SEP_HOST_GPR2_REG_ADDR 0x0B08UL | |
| 49 | #define HW_HOST_SEP_HOST_GPR3_REG_ADDR 0x0B0CUL | |
| 50 | #define HW_HOST_HOST_SEP_GPR0_REG_ADDR 0x0B80UL | |
| 51 | #define HW_HOST_HOST_SEP_GPR1_REG_ADDR 0x0B84UL | |
| 52 | #define HW_HOST_HOST_SEP_GPR2_REG_ADDR 0x0B88UL | |
| 53 | #define HW_HOST_HOST_SEP_GPR3_REG_ADDR 0x0B8CUL | |
| ff3d9c3c | 54 | #define HW_SRAM_DATA_READY_REG_ADDR 0x0F08UL |
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55 | |
| 56 | #endif /* ifndef HW_DEFS */ |