Merge remote-tracking branch 'staging/staging-next'
[deliverable/linux.git] / drivers / staging / slicoss / slicoss.c
CommitLineData
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1/**************************************************************************
2 *
3 * Copyright 2000-2006 Alacritech, Inc. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above
12 * copyright notice, this list of conditions and the following
13 * disclaimer in the documentation and/or other materials provided
14 * with the distribution.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") version 2 as published by the Free
18 * Software Foundation.
19 *
20 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * The views and conclusions contained in the software and documentation
34 * are those of the authors and should not be interpreted as representing
35 * official policies, either expressed or implied, of Alacritech, Inc.
36 *
37 **************************************************************************/
38
39/*
40 * FILENAME: slicoss.c
41 *
42 * The SLICOSS driver for Alacritech's IS-NIC products.
43 *
44 * This driver is supposed to support:
45 *
46 * Mojave cards (single port PCI Gigabit) both copper and fiber
47 * Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
48 * Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
49 *
493b67b7 50 * The driver was actually tested on Oasis and Kalahari cards.
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51 *
52 *
53 * NOTE: This is the standard, non-accelerated version of Alacritech's
54 * IS-NIC driver.
55 */
56
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57#define KLUDGE_FOR_4GB_BOUNDARY 1
58#define DEBUG_MICROCODE 1
4d6f6af8 59#define DBG 1
4d6f6af8 60#define SLIC_INTERRUPT_PROCESS_LIMIT 1
210ba93a
JR
61#define SLIC_OFFLOAD_IP_CHECKSUM 1
62#define STATS_TIMER_INTERVAL 2
63#define PING_TIMER_INTERVAL 1
1f6876cf 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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65
66#include <linux/kernel.h>
67#include <linux/string.h>
68#include <linux/errno.h>
69#include <linux/ioport.h>
70#include <linux/slab.h>
71#include <linux/interrupt.h>
72#include <linux/timer.h>
73#include <linux/pci.h>
74#include <linux/spinlock.h>
75#include <linux/init.h>
76#include <linux/bitops.h>
77#include <linux/io.h>
78#include <linux/netdevice.h>
97b3e0ed 79#include <linux/crc32.h>
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80#include <linux/etherdevice.h>
81#include <linux/skbuff.h>
82#include <linux/delay.h>
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83#include <linux/seq_file.h>
84#include <linux/kthread.h>
85#include <linux/module.h>
4d6f6af8 86
470c5736 87#include <linux/firmware.h>
4d6f6af8 88#include <linux/types.h>
4d6f6af8 89#include <linux/dma-mapping.h>
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90#include <linux/mii.h>
91#include <linux/if_vlan.h>
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92#include <asm/unaligned.h>
93
94#include <linux/ethtool.h>
4d6f6af8 95#include <linux/uaccess.h>
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96#include "slichw.h"
97#include "slic.h"
98
4d6f6af8 99static uint slic_first_init = 1;
1cd0989e 100static char *slic_banner = "Alacritech SLIC Technology(tm) Server and Storage Accelerator (Non-Accelerated)";
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101
102static char *slic_proc_version = "2.0.351 2006/07/14 12:26:00";
4d6f6af8 103
e9eff9d6 104static struct base_driver slic_global = { {}, 0, 0, 0, 1, NULL, NULL };
c8e9b92d 105#define DEFAULT_INTAGG_DELAY 100
4d6f6af8 106static unsigned int rcv_count;
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107
108#define DRV_NAME "slicoss"
109#define DRV_VERSION "2.0.1"
110#define DRV_AUTHOR "Alacritech, Inc. Engineering"
111#define DRV_DESCRIPTION "Alacritech SLIC Techonology(tm) "\
112 "Non-Accelerated Driver"
113#define DRV_COPYRIGHT "Copyright 2000-2006 Alacritech, Inc. "\
114 "All rights reserved."
115#define PFX DRV_NAME " "
116
117MODULE_AUTHOR(DRV_AUTHOR);
118MODULE_DESCRIPTION(DRV_DESCRIPTION);
119MODULE_LICENSE("Dual BSD/GPL");
120
41e043fc 121static const struct pci_device_id slic_pci_tbl[] = {
5d372900 122 { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_1GB_DEVICE_ID) },
123 { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_2GB_DEVICE_ID) },
124 { 0 }
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125};
126
dda3e265 127static const struct ethtool_ops slic_ethtool_ops;
c8e9b92d 128
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129MODULE_DEVICE_TABLE(pci, slic_pci_tbl);
130
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131static void slic_mcast_set_bit(struct adapter *adapter, char *address)
132{
133 unsigned char crcpoly;
4d6f6af8 134
4d6ea9c3 135 /* Get the CRC polynomial for the mac address */
f773a834
AG
136 /*
137 * we use bits 1-8 (lsb), bitwise reversed,
138 * msb (= lsb bit 0 before bitrev) is automatically discarded
139 */
0d45ffcd 140 crcpoly = ether_crc(ETH_ALEN, address) >> 23;
4d6f6af8 141
f773a834
AG
142 /*
143 * We only have space on the SLIC for 64 entries. Lop
4d6ea9c3
DK
144 * off the top two bits. (2^6 = 64)
145 */
146 crcpoly &= 0x3F;
4d6f6af8 147
4d6ea9c3 148 /* OR in the new bit into our 64 bit mask. */
8610cbc5 149 adapter->mcastmask |= (u64)1 << crcpoly;
4d6ea9c3 150}
4d6f6af8 151
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DK
152static void slic_mcast_set_mask(struct adapter *adapter)
153{
4d6ea9c3 154 if (adapter->macopts & (MAC_ALLMCAST | MAC_PROMISC)) {
f773a834
AG
155 /*
156 * Turn on all multicast addresses. We have to do this for
4d6ea9c3
DK
157 * promiscuous mode as well as ALLMCAST mode. It saves the
158 * Microcode from having to keep state about the MAC
159 * configuration.
160 */
c6d6a9a0
LS
161 slic_write32(adapter, SLIC_REG_MCASTLOW, 0xFFFFFFFF);
162 slic_write32(adapter, SLIC_REG_MCASTHIGH, 0xFFFFFFFF);
4d6ea9c3 163 } else {
f773a834
AG
164 /*
165 * Commit our multicast mast to the SLIC by writing to the
4d6ea9c3
DK
166 * multicast address mask registers
167 */
c6d6a9a0
LS
168 slic_write32(adapter, SLIC_REG_MCASTLOW,
169 (u32)(adapter->mcastmask & 0xFFFFFFFF));
170 slic_write32(adapter, SLIC_REG_MCASTHIGH,
171 (u32)((adapter->mcastmask >> 32) & 0xFFFFFFFF));
4d6f6af8 172 }
4d6ea9c3 173}
4d6f6af8 174
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DK
175static void slic_timer_ping(ulong dev)
176{
177 struct adapter *adapter;
178 struct sliccard *card;
4d6f6af8 179
4d6ea9c3 180 adapter = netdev_priv((struct net_device *)dev);
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181 card = adapter->card;
182
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DK
183 adapter->pingtimer.expires = jiffies + (PING_TIMER_INTERVAL * HZ);
184 add_timer(&adapter->pingtimer);
185}
4d6f6af8 186
4d6ea9c3
DK
187/*
188 * slic_link_config
189 *
190 * Write phy control to configure link duplex/speed
191 *
192 */
193static void slic_link_config(struct adapter *adapter,
194 u32 linkspeed, u32 linkduplex)
195{
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DK
196 u32 speed;
197 u32 duplex;
198 u32 phy_config;
199 u32 phy_advreg;
200 u32 phy_gctlreg;
4d6f6af8 201
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DK
202 if (adapter->state != ADAPT_UP)
203 return;
4d6f6af8 204
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DK
205 if (linkspeed > LINK_1000MB)
206 linkspeed = LINK_AUTOSPEED;
207 if (linkduplex > LINK_AUTOD)
208 linkduplex = LINK_AUTOD;
4d6f6af8 209
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DK
210 if ((linkspeed == LINK_AUTOSPEED) || (linkspeed == LINK_1000MB)) {
211 if (adapter->flags & ADAPT_FLAGS_FIBERMEDIA) {
f773a834
AG
212 /*
213 * We've got a fiber gigabit interface, and register
4d6ea9c3
DK
214 * 4 is different in fiber mode than in copper mode
215 */
4d6f6af8 216
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217 /* advertise FD only @1000 Mb */
218 phy_advreg = (MIICR_REG_4 | (PAR_ADV1000XFD));
219 /* enable PAUSE frames */
220 phy_advreg |= PAR_ASYMPAUSE_FIBER;
c6d6a9a0 221 slic_write32(adapter, SLIC_REG_WPHY, phy_advreg);
4d6f6af8 222
4d6ea9c3
DK
223 if (linkspeed == LINK_AUTOSPEED) {
224 /* reset phy, enable auto-neg */
225 phy_config =
226 (MIICR_REG_PCR |
227 (PCR_RESET | PCR_AUTONEG |
228 PCR_AUTONEG_RST));
c6d6a9a0
LS
229 slic_write32(adapter, SLIC_REG_WPHY,
230 phy_config);
4d6ea9c3 231 } else { /* forced 1000 Mb FD*/
f773a834
AG
232 /*
233 * power down phy to break link
234 * this may not work)
235 */
4d6ea9c3 236 phy_config = (MIICR_REG_PCR | PCR_POWERDOWN);
c6d6a9a0
LS
237 slic_write32(adapter, SLIC_REG_WPHY,
238 phy_config);
bc894318 239 slic_flush_write(adapter);
f773a834
AG
240 /*
241 * wait, Marvell says 1 sec,
242 * try to get away with 10 ms
243 */
4d6ea9c3 244 mdelay(10);
4d6f6af8 245
f773a834
AG
246 /*
247 * disable auto-neg, set speed/duplex,
248 * soft reset phy, powerup
249 */
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DK
250 phy_config =
251 (MIICR_REG_PCR |
252 (PCR_RESET | PCR_SPEED_1000 |
253 PCR_DUPLEX_FULL));
c6d6a9a0
LS
254 slic_write32(adapter, SLIC_REG_WPHY,
255 phy_config);
4d6ea9c3
DK
256 }
257 } else { /* copper gigabit */
4d6f6af8 258
f773a834
AG
259 /*
260 * Auto-Negotiate or 1000 Mb must be auto negotiated
4d6ea9c3
DK
261 * We've got a copper gigabit interface, and
262 * register 4 is different in copper mode than
263 * in fiber mode
264 */
265 if (linkspeed == LINK_AUTOSPEED) {
266 /* advertise 10/100 Mb modes */
267 phy_advreg =
268 (MIICR_REG_4 |
269 (PAR_ADV100FD | PAR_ADV100HD | PAR_ADV10FD
270 | PAR_ADV10HD));
271 } else {
f773a834
AG
272 /*
273 * linkspeed == LINK_1000MB -
274 * don't advertise 10/100 Mb modes
275 */
4d6ea9c3
DK
276 phy_advreg = MIICR_REG_4;
277 }
278 /* enable PAUSE frames */
279 phy_advreg |= PAR_ASYMPAUSE;
280 /* required by the Cicada PHY */
281 phy_advreg |= PAR_802_3;
c6d6a9a0 282 slic_write32(adapter, SLIC_REG_WPHY, phy_advreg);
4d6ea9c3
DK
283 /* advertise FD only @1000 Mb */
284 phy_gctlreg = (MIICR_REG_9 | (PGC_ADV1000FD));
c6d6a9a0 285 slic_write32(adapter, SLIC_REG_WPHY, phy_gctlreg);
4d6f6af8 286
4d6ea9c3 287 if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
f773a834
AG
288 /*
289 * if a Marvell PHY
290 * enable auto crossover
291 */
4d6ea9c3
DK
292 phy_config =
293 (MIICR_REG_16 | (MRV_REG16_XOVERON));
c6d6a9a0
LS
294 slic_write32(adapter, SLIC_REG_WPHY,
295 phy_config);
4d6f6af8 296
4d6ea9c3
DK
297 /* reset phy, enable auto-neg */
298 phy_config =
299 (MIICR_REG_PCR |
300 (PCR_RESET | PCR_AUTONEG |
301 PCR_AUTONEG_RST));
c6d6a9a0
LS
302 slic_write32(adapter, SLIC_REG_WPHY,
303 phy_config);
4d6ea9c3
DK
304 } else { /* it's a Cicada PHY */
305 /* enable and restart auto-neg (don't reset) */
306 phy_config =
307 (MIICR_REG_PCR |
308 (PCR_AUTONEG | PCR_AUTONEG_RST));
c6d6a9a0
LS
309 slic_write32(adapter, SLIC_REG_WPHY,
310 phy_config);
4d6ea9c3 311 }
4d6f6af8 312 }
4d6ea9c3
DK
313 } else {
314 /* Forced 10/100 */
315 if (linkspeed == LINK_10MB)
316 speed = 0;
317 else
318 speed = PCR_SPEED_100;
319 if (linkduplex == LINK_HALFD)
320 duplex = 0;
321 else
322 duplex = PCR_DUPLEX_FULL;
323
324 if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
f773a834
AG
325 /*
326 * if a Marvell PHY
327 * disable auto crossover
328 */
4d6ea9c3 329 phy_config = (MIICR_REG_16 | (MRV_REG16_XOVEROFF));
c6d6a9a0 330 slic_write32(adapter, SLIC_REG_WPHY, phy_config);
4d6f6af8 331 }
4d6f6af8 332
4d6ea9c3
DK
333 /* power down phy to break link (this may not work) */
334 phy_config = (MIICR_REG_PCR | (PCR_POWERDOWN | speed | duplex));
c6d6a9a0 335 slic_write32(adapter, SLIC_REG_WPHY, phy_config);
bc894318 336 slic_flush_write(adapter);
4d6ea9c3
DK
337 /* wait, Marvell says 1 sec, try to get away with 10 ms */
338 mdelay(10);
339
340 if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
f773a834
AG
341 /*
342 * if a Marvell PHY
343 * disable auto-neg, set speed,
344 * soft reset phy, powerup
345 */
4d6ea9c3
DK
346 phy_config =
347 (MIICR_REG_PCR | (PCR_RESET | speed | duplex));
c6d6a9a0 348 slic_write32(adapter, SLIC_REG_WPHY, phy_config);
4d6ea9c3
DK
349 } else { /* it's a Cicada PHY */
350 /* disable auto-neg, set speed, powerup */
351 phy_config = (MIICR_REG_PCR | (speed | duplex));
c6d6a9a0 352 slic_write32(adapter, SLIC_REG_WPHY, phy_config);
4d6ea9c3
DK
353 }
354 }
4d6f6af8
GKH
355}
356
4d6ea9c3 357static int slic_card_download_gbrcv(struct adapter *adapter)
4d6f6af8 358{
4d6ea9c3
DK
359 const struct firmware *fw;
360 const char *file = "";
361 int ret;
4d6ea9c3
DK
362 u32 codeaddr;
363 u32 instruction;
364 int index = 0;
365 u32 rcvucodelen = 0;
4d6f6af8 366
4d6ea9c3
DK
367 switch (adapter->devid) {
368 case SLIC_2GB_DEVICE_ID:
369 file = "slicoss/oasisrcvucode.sys";
370 break;
371 case SLIC_1GB_DEVICE_ID:
372 file = "slicoss/gbrcvucode.sys";
373 break;
374 default:
651d4bc7 375 return -ENOENT;
4d6ea9c3 376 }
4d6f6af8 377
4d6ea9c3
DK
378 ret = request_firmware(&fw, file, &adapter->pcidev->dev);
379 if (ret) {
380 dev_err(&adapter->pcidev->dev,
811e843d 381 "Failed to load firmware %s\n", file);
4d6ea9c3 382 return ret;
786ed801 383 }
4d6ea9c3
DK
384
385 rcvucodelen = *(u32 *)(fw->data + index);
386 index += 4;
387 switch (adapter->devid) {
388 case SLIC_2GB_DEVICE_ID:
7ee34ab2
DN
389 if (rcvucodelen != OasisRcvUCodeLen) {
390 release_firmware(fw);
4d6ea9c3 391 return -EINVAL;
7ee34ab2 392 }
4d6ea9c3
DK
393 break;
394 case SLIC_1GB_DEVICE_ID:
7ee34ab2
DN
395 if (rcvucodelen != GBRcvUCodeLen) {
396 release_firmware(fw);
4d6ea9c3 397 return -EINVAL;
7ee34ab2 398 }
4d6ea9c3 399 break;
4d6f6af8 400 }
4d6ea9c3 401 /* start download */
c6d6a9a0 402 slic_write32(adapter, SLIC_REG_RCV_WCS, SLIC_RCVWCS_BEGIN);
4d6ea9c3
DK
403 /* download the rcv sequencer ucode */
404 for (codeaddr = 0; codeaddr < rcvucodelen; codeaddr++) {
405 /* write out instruction address */
c6d6a9a0 406 slic_write32(adapter, SLIC_REG_RCV_WCS, codeaddr);
4d6ea9c3
DK
407
408 instruction = *(u32 *)(fw->data + index);
409 index += 4;
410 /* write out the instruction data low addr */
c6d6a9a0 411 slic_write32(adapter, SLIC_REG_RCV_WCS, instruction);
4d6ea9c3
DK
412
413 instruction = *(u8 *)(fw->data + index);
414 index++;
415 /* write out the instruction data high addr */
c6d6a9a0 416 slic_write32(adapter, SLIC_REG_RCV_WCS, instruction);
4d6ea9c3
DK
417 }
418
419 /* download finished */
420 release_firmware(fw);
c6d6a9a0 421 slic_write32(adapter, SLIC_REG_RCV_WCS, SLIC_RCVWCS_FINISH);
bc894318
LS
422 slic_flush_write(adapter);
423
4d6ea9c3 424 return 0;
4d6f6af8
GKH
425}
426
4d6ea9c3
DK
427MODULE_FIRMWARE("slicoss/oasisrcvucode.sys");
428MODULE_FIRMWARE("slicoss/gbrcvucode.sys");
429
430static int slic_card_download(struct adapter *adapter)
4d6f6af8 431{
4d6ea9c3
DK
432 const struct firmware *fw;
433 const char *file = "";
434 int ret;
435 u32 section;
436 int thissectionsize;
437 int codeaddr;
4d6ea9c3
DK
438 u32 instruction;
439 u32 baseaddress;
440 u32 i;
441 u32 numsects = 0;
442 u32 sectsize[3];
443 u32 sectstart[3];
444 int ucode_start, index = 0;
4d6f6af8 445
4d6ea9c3
DK
446 switch (adapter->devid) {
447 case SLIC_2GB_DEVICE_ID:
448 file = "slicoss/oasisdownload.sys";
449 break;
450 case SLIC_1GB_DEVICE_ID:
451 file = "slicoss/gbdownload.sys";
452 break;
453 default:
670d145a 454 return -ENOENT;
4d6f6af8 455 }
4d6ea9c3
DK
456 ret = request_firmware(&fw, file, &adapter->pcidev->dev);
457 if (ret) {
458 dev_err(&adapter->pcidev->dev,
811e843d 459 "Failed to load firmware %s\n", file);
4d6ea9c3
DK
460 return ret;
461 }
462 numsects = *(u32 *)(fw->data + index);
463 index += 4;
4d6ea9c3
DK
464 for (i = 0; i < numsects; i++) {
465 sectsize[i] = *(u32 *)(fw->data + index);
466 index += 4;
467 }
468 for (i = 0; i < numsects; i++) {
469 sectstart[i] = *(u32 *)(fw->data + index);
470 index += 4;
471 }
472 ucode_start = index;
473 instruction = *(u32 *)(fw->data + index);
474 index += 4;
475 for (section = 0; section < numsects; section++) {
476 baseaddress = sectstart[section];
477 thissectionsize = sectsize[section] >> 3;
4d6f6af8 478
4d6ea9c3
DK
479 for (codeaddr = 0; codeaddr < thissectionsize; codeaddr++) {
480 /* Write out instruction address */
c6d6a9a0
LS
481 slic_write32(adapter, SLIC_REG_WCS,
482 baseaddress + codeaddr);
4d6ea9c3 483 /* Write out instruction to low addr */
c6d6a9a0
LS
484 slic_write32(adapter, SLIC_REG_WCS,
485 instruction);
4d6ea9c3
DK
486 instruction = *(u32 *)(fw->data + index);
487 index += 4;
488
489 /* Write out instruction to high addr */
c6d6a9a0
LS
490 slic_write32(adapter, SLIC_REG_WCS,
491 instruction);
4d6ea9c3
DK
492 instruction = *(u32 *)(fw->data + index);
493 index += 4;
494 }
495 }
496 index = ucode_start;
497 for (section = 0; section < numsects; section++) {
498 instruction = *(u32 *)(fw->data + index);
499 baseaddress = sectstart[section];
500 if (baseaddress < 0x8000)
501 continue;
502 thissectionsize = sectsize[section] >> 3;
503
504 for (codeaddr = 0; codeaddr < thissectionsize; codeaddr++) {
505 /* Write out instruction address */
c6d6a9a0
LS
506 slic_write32(adapter, SLIC_REG_WCS,
507 SLIC_WCS_COMPARE | (baseaddress +
508 codeaddr));
4d6ea9c3 509 /* Write out instruction to low addr */
c6d6a9a0 510 slic_write32(adapter, SLIC_REG_WCS, instruction);
4d6ea9c3
DK
511 instruction = *(u32 *)(fw->data + index);
512 index += 4;
513 /* Write out instruction to high addr */
c6d6a9a0 514 slic_write32(adapter, SLIC_REG_WCS, instruction);
4d6ea9c3
DK
515 instruction = *(u32 *)(fw->data + index);
516 index += 4;
517
4d6ea9c3
DK
518 }
519 }
520 release_firmware(fw);
521 /* Everything OK, kick off the card */
522 mdelay(10);
4d6ea9c3 523
c6d6a9a0
LS
524 slic_write32(adapter, SLIC_REG_WCS, SLIC_WCS_START);
525 slic_flush_write(adapter);
f773a834
AG
526 /*
527 * stall for 20 ms, long enough for ucode to init card
528 * and reach mainloop
529 */
4d6ea9c3 530 mdelay(20);
4d6f6af8 531
d1939786 532 return 0;
4d6f6af8
GKH
533}
534
4d6ea9c3
DK
535MODULE_FIRMWARE("slicoss/oasisdownload.sys");
536MODULE_FIRMWARE("slicoss/gbdownload.sys");
537
538static void slic_adapter_set_hwaddr(struct adapter *adapter)
4d6f6af8 539{
4d6ea9c3 540 struct sliccard *card = adapter->card;
e52011e4 541
4d6ea9c3
DK
542 if ((adapter->card) && (card->config_set)) {
543 memcpy(adapter->macaddr,
544 card->config.MacInfo[adapter->functionnumber].macaddrA,
545 sizeof(struct slic_config_mac));
ae7d27c0
JP
546 if (is_zero_ether_addr(adapter->currmacaddr))
547 memcpy(adapter->currmacaddr, adapter->macaddr,
548 ETH_ALEN);
549 if (adapter->netdev)
4d6ea9c3 550 memcpy(adapter->netdev->dev_addr, adapter->currmacaddr,
ae7d27c0 551 ETH_ALEN);
4d6ea9c3
DK
552 }
553}
4d6f6af8 554
4d6ea9c3
DK
555static void slic_intagg_set(struct adapter *adapter, u32 value)
556{
c6d6a9a0 557 slic_write32(adapter, SLIC_REG_INTAGG, value);
4d6ea9c3
DK
558 adapter->card->loadlevel_current = value;
559}
4d6f6af8 560
4d6ea9c3
DK
561static void slic_soft_reset(struct adapter *adapter)
562{
563 if (adapter->card->state == CARD_UP) {
c6d6a9a0 564 slic_write32(adapter, SLIC_REG_QUIESCE, 0);
bc894318 565 slic_flush_write(adapter);
4d6ea9c3
DK
566 mdelay(1);
567 }
4d6f6af8 568
c6d6a9a0 569 slic_write32(adapter, SLIC_REG_RESET, SLIC_RESET_MAGIC);
bc894318 570 slic_flush_write(adapter);
c6d6a9a0 571
4d6ea9c3
DK
572 mdelay(1);
573}
e52011e4 574
4d6ea9c3
DK
575static void slic_mac_address_config(struct adapter *adapter)
576{
577 u32 value;
578 u32 value2;
e52011e4 579
8610cbc5 580 value = ntohl(*(__be32 *)&adapter->currmacaddr[2]);
c6d6a9a0
LS
581 slic_write32(adapter, SLIC_REG_WRADDRAL, value);
582 slic_write32(adapter, SLIC_REG_WRADDRBL, value);
e52011e4 583
8610cbc5 584 value2 = (u32)((adapter->currmacaddr[0] << 8 |
4d6ea9c3 585 adapter->currmacaddr[1]) & 0xFFFF);
4d6f6af8 586
c6d6a9a0
LS
587 slic_write32(adapter, SLIC_REG_WRADDRAH, value2);
588 slic_write32(adapter, SLIC_REG_WRADDRBH, value2);
e52011e4 589
f773a834
AG
590 /*
591 * Write our multicast mask out to the card. This is done
592 * here in addition to the slic_mcast_addr_set routine
593 * because ALL_MCAST may have been enabled or disabled
594 */
4d6ea9c3
DK
595 slic_mcast_set_mask(adapter);
596}
e52011e4 597
4d6ea9c3
DK
598static void slic_mac_config(struct adapter *adapter)
599{
600 u32 value;
e52011e4 601
4d6ea9c3
DK
602 /* Setup GMAC gaps */
603 if (adapter->linkspeed == LINK_1000MB) {
604 value = ((GMCR_GAPBB_1000 << GMCR_GAPBB_SHIFT) |
605 (GMCR_GAPR1_1000 << GMCR_GAPR1_SHIFT) |
606 (GMCR_GAPR2_1000 << GMCR_GAPR2_SHIFT));
607 } else {
608 value = ((GMCR_GAPBB_100 << GMCR_GAPBB_SHIFT) |
609 (GMCR_GAPR1_100 << GMCR_GAPR1_SHIFT) |
610 (GMCR_GAPR2_100 << GMCR_GAPR2_SHIFT));
611 }
e52011e4 612
4d6ea9c3
DK
613 /* enable GMII */
614 if (adapter->linkspeed == LINK_1000MB)
615 value |= GMCR_GBIT;
616
617 /* enable fullduplex */
618 if ((adapter->linkduplex == LINK_FULLD)
619 || (adapter->macopts & MAC_LOOPBACK)) {
620 value |= GMCR_FULLD;
4d6f6af8 621 }
4d6f6af8 622
4d6ea9c3 623 /* write mac config */
c6d6a9a0 624 slic_write32(adapter, SLIC_REG_WMCFG, value);
4d6f6af8 625
4d6ea9c3
DK
626 /* setup mac addresses */
627 slic_mac_address_config(adapter);
628}
629
630static void slic_config_set(struct adapter *adapter, bool linkchange)
4d6f6af8 631{
4d6ea9c3
DK
632 u32 value;
633 u32 RcrReset;
4d6f6af8 634
4d6ea9c3
DK
635 if (linkchange) {
636 /* Setup MAC */
637 slic_mac_config(adapter);
638 RcrReset = GRCR_RESET;
639 } else {
640 slic_mac_address_config(adapter);
641 RcrReset = 0;
642 }
4d6f6af8 643
4d6ea9c3
DK
644 if (adapter->linkduplex == LINK_FULLD) {
645 /* setup xmtcfg */
646 value = (GXCR_RESET | /* Always reset */
647 GXCR_XMTEN | /* Enable transmit */
648 GXCR_PAUSEEN); /* Enable pause */
4d6f6af8 649
c6d6a9a0 650 slic_write32(adapter, SLIC_REG_WXCFG, value);
4d6f6af8 651
4d6ea9c3
DK
652 /* Setup rcvcfg last */
653 value = (RcrReset | /* Reset, if linkchange */
654 GRCR_CTLEN | /* Enable CTL frames */
655 GRCR_ADDRAEN | /* Address A enable */
656 GRCR_RCVBAD | /* Rcv bad frames */
657 (GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
658 } else {
659 /* setup xmtcfg */
660 value = (GXCR_RESET | /* Always reset */
661 GXCR_XMTEN); /* Enable transmit */
4d6f6af8 662
c6d6a9a0 663 slic_write32(adapter, SLIC_REG_WXCFG, value);
4d6f6af8 664
4d6ea9c3
DK
665 /* Setup rcvcfg last */
666 value = (RcrReset | /* Reset, if linkchange */
667 GRCR_ADDRAEN | /* Address A enable */
668 GRCR_RCVBAD | /* Rcv bad frames */
669 (GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
4d6f6af8
GKH
670 }
671
4d6ea9c3
DK
672 if (adapter->state != ADAPT_DOWN) {
673 /* Only enable receive if we are restarting or running */
674 value |= GRCR_RCVEN;
4d6f6af8 675 }
4d6f6af8 676
4d6ea9c3
DK
677 if (adapter->macopts & MAC_PROMISC)
678 value |= GRCR_RCVALL;
4d6f6af8 679
c6d6a9a0 680 slic_write32(adapter, SLIC_REG_WRCFG, value);
4d6ea9c3 681}
4d6f6af8 682
4d6ea9c3
DK
683/*
684 * Turn off RCV and XMT, power down PHY
685 */
686static void slic_config_clear(struct adapter *adapter)
4d6f6af8 687{
4d6ea9c3
DK
688 u32 value;
689 u32 phy_config;
4d6ea9c3
DK
690
691 /* Setup xmtcfg */
692 value = (GXCR_RESET | /* Always reset */
693 GXCR_PAUSEEN); /* Enable pause */
694
c6d6a9a0 695 slic_write32(adapter, SLIC_REG_WXCFG, value);
4d6ea9c3
DK
696
697 value = (GRCR_RESET | /* Always reset */
698 GRCR_CTLEN | /* Enable CTL frames */
699 GRCR_ADDRAEN | /* Address A enable */
700 (GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
701
c6d6a9a0 702 slic_write32(adapter, SLIC_REG_WRCFG, value);
4d6ea9c3
DK
703
704 /* power down phy */
705 phy_config = (MIICR_REG_PCR | (PCR_POWERDOWN));
c6d6a9a0 706 slic_write32(adapter, SLIC_REG_WPHY, phy_config);
4d6f6af8
GKH
707}
708
4d6ea9c3
DK
709static bool slic_mac_filter(struct adapter *adapter,
710 struct ether_header *ether_frame)
4d6f6af8 711{
9092de6d 712 struct net_device *netdev = adapter->netdev;
4d6ea9c3 713 u32 opts = adapter->macopts;
4d6f6af8 714
4d6ea9c3
DK
715 if (opts & MAC_PROMISC)
716 return true;
4d6f6af8 717
ae7d27c0 718 if (is_broadcast_ether_addr(ether_frame->ether_dhost)) {
4d6ea9c3
DK
719 if (opts & MAC_BCAST) {
720 adapter->rcv_broadcasts++;
721 return true;
4d6f6af8 722 }
351e836f
VH
723
724 return false;
4d6ea9c3
DK
725 }
726
ae7d27c0 727 if (is_multicast_ether_addr(ether_frame->ether_dhost)) {
4d6ea9c3
DK
728 if (opts & MAC_ALLMCAST) {
729 adapter->rcv_multicasts++;
9092de6d 730 netdev->stats.multicast++;
4d6ea9c3 731 return true;
4d6f6af8 732 }
4d6ea9c3
DK
733 if (opts & MAC_MCAST) {
734 struct mcast_address *mcaddr = adapter->mcastaddrs;
4d6f6af8 735
4d6ea9c3 736 while (mcaddr) {
8329419a
JP
737 if (ether_addr_equal(mcaddr->address,
738 ether_frame->ether_dhost)) {
4d6ea9c3 739 adapter->rcv_multicasts++;
9092de6d 740 netdev->stats.multicast++;
4d6ea9c3
DK
741 return true;
742 }
743 mcaddr = mcaddr->next;
744 }
351e836f 745
4d6ea9c3 746 return false;
4d6f6af8 747 }
351e836f
VH
748
749 return false;
4d6f6af8 750 }
4d6ea9c3
DK
751 if (opts & MAC_DIRECTED) {
752 adapter->rcv_unicasts++;
753 return true;
754 }
755 return false;
4d6ea9c3 756}
4d6f6af8 757
4d6ea9c3 758static int slic_mac_set_address(struct net_device *dev, void *ptr)
4d6f6af8 759{
4d6ea9c3
DK
760 struct adapter *adapter = netdev_priv(dev);
761 struct sockaddr *addr = ptr;
4d6f6af8 762
4d6ea9c3
DK
763 if (netif_running(dev))
764 return -EBUSY;
765 if (!adapter)
766 return -EBUSY;
4d6f6af8 767
4d6ea9c3
DK
768 if (!is_valid_ether_addr(addr->sa_data))
769 return -EINVAL;
4d6f6af8 770
4d6ea9c3
DK
771 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
772 memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len);
4d6f6af8 773
4d6ea9c3
DK
774 slic_config_set(adapter, true);
775 return 0;
4d6f6af8
GKH
776}
777
4d6ea9c3 778static void slic_timer_load_check(ulong cardaddr)
4d6f6af8 779{
4d6ea9c3
DK
780 struct sliccard *card = (struct sliccard *)cardaddr;
781 struct adapter *adapter = card->master;
4d6ea9c3
DK
782 u32 load = card->events;
783 u32 level = 0;
4d6f6af8 784
4d6ea9c3
DK
785 if ((adapter) && (adapter->state == ADAPT_UP) &&
786 (card->state == CARD_UP) && (slic_global.dynamic_intagg)) {
787 if (adapter->devid == SLIC_1GB_DEVICE_ID) {
788 if (adapter->linkspeed == LINK_1000MB)
789 level = 100;
790 else {
791 if (load > SLIC_LOAD_5)
792 level = SLIC_INTAGG_5;
793 else if (load > SLIC_LOAD_4)
794 level = SLIC_INTAGG_4;
795 else if (load > SLIC_LOAD_3)
796 level = SLIC_INTAGG_3;
797 else if (load > SLIC_LOAD_2)
798 level = SLIC_INTAGG_2;
799 else if (load > SLIC_LOAD_1)
800 level = SLIC_INTAGG_1;
801 else
802 level = SLIC_INTAGG_0;
4d6f6af8 803 }
4d6ea9c3
DK
804 if (card->loadlevel_current != level) {
805 card->loadlevel_current = level;
c6d6a9a0 806 slic_write32(adapter, SLIC_REG_INTAGG, level);
4d6f6af8 807 }
4d6ea9c3
DK
808 } else {
809 if (load > SLIC_LOAD_5)
810 level = SLIC_INTAGG_5;
811 else if (load > SLIC_LOAD_4)
812 level = SLIC_INTAGG_4;
813 else if (load > SLIC_LOAD_3)
814 level = SLIC_INTAGG_3;
815 else if (load > SLIC_LOAD_2)
816 level = SLIC_INTAGG_2;
817 else if (load > SLIC_LOAD_1)
818 level = SLIC_INTAGG_1;
819 else
820 level = SLIC_INTAGG_0;
821 if (card->loadlevel_current != level) {
822 card->loadlevel_current = level;
c6d6a9a0 823 slic_write32(adapter, SLIC_REG_INTAGG, level);
4d6f6af8 824 }
4d6f6af8 825 }
4d6f6af8 826 }
4d6ea9c3
DK
827 card->events = 0;
828 card->loadtimer.expires = jiffies + (SLIC_LOADTIMER_PERIOD * HZ);
829 add_timer(&card->loadtimer);
4d6f6af8
GKH
830}
831
4d6ea9c3
DK
832static int slic_upr_queue_request(struct adapter *adapter,
833 u32 upr_request,
834 u32 upr_data,
835 u32 upr_data_h,
836 u32 upr_buffer, u32 upr_buffer_h)
4d6f6af8 837{
4d6ea9c3
DK
838 struct slic_upr *upr;
839 struct slic_upr *uprqueue;
4d6f6af8 840
82554c2f 841 upr = kmalloc(sizeof(*upr), GFP_ATOMIC);
4d6ea9c3
DK
842 if (!upr)
843 return -ENOMEM;
4d6f6af8 844
4d6ea9c3
DK
845 upr->adapter = adapter->port;
846 upr->upr_request = upr_request;
847 upr->upr_data = upr_data;
848 upr->upr_buffer = upr_buffer;
849 upr->upr_data_h = upr_data_h;
850 upr->upr_buffer_h = upr_buffer_h;
851 upr->next = NULL;
852 if (adapter->upr_list) {
853 uprqueue = adapter->upr_list;
a0a1cbef 854
4d6ea9c3
DK
855 while (uprqueue->next)
856 uprqueue = uprqueue->next;
857 uprqueue->next = upr;
858 } else {
859 adapter->upr_list = upr;
4d6f6af8 860 }
4d6ea9c3 861 return 0;
4d6f6af8
GKH
862}
863
4d6ea9c3 864static void slic_upr_start(struct adapter *adapter)
4d6f6af8 865{
4d6ea9c3 866 struct slic_upr *upr;
d37912dd 867
4d6ea9c3
DK
868 upr = adapter->upr_list;
869 if (!upr)
870 return;
871 if (adapter->upr_busy)
872 return;
873 adapter->upr_busy = 1;
4d6f6af8 874
4d6ea9c3
DK
875 switch (upr->upr_request) {
876 case SLIC_UPR_STATS:
877 if (upr->upr_data_h == 0) {
c6d6a9a0 878 slic_write32(adapter, SLIC_REG_RSTAT, upr->upr_data);
4d6ea9c3 879 } else {
c6d6a9a0
LS
880 slic_write64(adapter, SLIC_REG_RSTAT64, upr->upr_data,
881 upr->upr_data_h);
4d6ea9c3
DK
882 }
883 break;
4d6f6af8 884
4d6ea9c3 885 case SLIC_UPR_RLSR:
c6d6a9a0
LS
886 slic_write64(adapter, SLIC_REG_LSTAT, upr->upr_data,
887 upr->upr_data_h);
4d6ea9c3 888 break;
4d6f6af8 889
4d6ea9c3 890 case SLIC_UPR_RCONFIG:
c6d6a9a0
LS
891 slic_write64(adapter, SLIC_REG_RCONFIG, upr->upr_data,
892 upr->upr_data_h);
4d6ea9c3
DK
893 break;
894 case SLIC_UPR_PING:
c6d6a9a0 895 slic_write32(adapter, SLIC_REG_PING, 1);
4d6ea9c3 896 break;
4d6ea9c3 897 }
bc894318 898 slic_flush_write(adapter);
4d6f6af8
GKH
899}
900
4d6ea9c3
DK
901static int slic_upr_request(struct adapter *adapter,
902 u32 upr_request,
903 u32 upr_data,
904 u32 upr_data_h,
905 u32 upr_buffer, u32 upr_buffer_h)
4d6f6af8 906{
eafe6002 907 unsigned long flags;
4d6ea9c3 908 int rc;
4d6f6af8 909
eafe6002 910 spin_lock_irqsave(&adapter->upr_lock, flags);
4d6ea9c3
DK
911 rc = slic_upr_queue_request(adapter,
912 upr_request,
913 upr_data,
914 upr_data_h, upr_buffer, upr_buffer_h);
915 if (rc)
916 goto err_unlock_irq;
4d6f6af8 917
4d6ea9c3
DK
918 slic_upr_start(adapter);
919err_unlock_irq:
eafe6002 920 spin_unlock_irqrestore(&adapter->upr_lock, flags);
4d6ea9c3 921 return rc;
4d6f6af8
GKH
922}
923
4d6ea9c3 924static void slic_link_upr_complete(struct adapter *adapter, u32 isr)
4d6f6af8 925{
fdb77775
LS
926 struct slic_shmemory *sm = &adapter->shmem;
927 struct slic_shmem_data *sm_data = sm->shmem_data;
928 u32 lst = sm_data->lnkstatus;
4d6ea9c3
DK
929 uint linkup;
930 unsigned char linkspeed;
931 unsigned char linkduplex;
4d6f6af8 932
4d6ea9c3 933 if ((isr & ISR_UPCERR) || (isr & ISR_UPCBSY)) {
fdb77775 934 dma_addr_t phaddr = sm->lnkstatus_phaddr;
4d6f6af8 935
fdb77775
LS
936 slic_upr_queue_request(adapter, SLIC_UPR_RLSR,
937 cpu_to_le32(lower_32_bits(phaddr)),
938 cpu_to_le32(upper_32_bits(phaddr)),
4d6ea9c3 939 0, 0);
4d6ea9c3
DK
940 return;
941 }
942 if (adapter->state != ADAPT_UP)
943 return;
4d6f6af8 944
fdb77775
LS
945 linkup = lst & GIG_LINKUP ? LINK_UP : LINK_DOWN;
946 if (lst & GIG_SPEED_1000)
4d6ea9c3 947 linkspeed = LINK_1000MB;
fdb77775 948 else if (lst & GIG_SPEED_100)
4d6ea9c3
DK
949 linkspeed = LINK_100MB;
950 else
951 linkspeed = LINK_10MB;
4d6f6af8 952
fdb77775 953 if (lst & GIG_FULLDUPLEX)
4d6ea9c3
DK
954 linkduplex = LINK_FULLD;
955 else
956 linkduplex = LINK_HALFD;
4d6f6af8 957
4d6ea9c3
DK
958 if ((adapter->linkstate == LINK_DOWN) && (linkup == LINK_DOWN))
959 return;
4d6f6af8 960
4d6ea9c3
DK
961 /* link up event, but nothing has changed */
962 if ((adapter->linkstate == LINK_UP) &&
963 (linkup == LINK_UP) &&
964 (adapter->linkspeed == linkspeed) &&
965 (adapter->linkduplex == linkduplex))
966 return;
4d6f6af8 967
4d6ea9c3 968 /* link has changed at this point */
4d6f6af8 969
4d6ea9c3
DK
970 /* link has gone from up to down */
971 if (linkup == LINK_DOWN) {
972 adapter->linkstate = LINK_DOWN;
da169754 973 netif_carrier_off(adapter->netdev);
4d6ea9c3 974 return;
4d6f6af8
GKH
975 }
976
4d6ea9c3
DK
977 /* link has gone from down to up */
978 adapter->linkspeed = linkspeed;
979 adapter->linkduplex = linkduplex;
980
981 if (adapter->linkstate != LINK_UP) {
982 /* setup the mac */
b574488e 983 slic_config_set(adapter, true);
4d6ea9c3 984 adapter->linkstate = LINK_UP;
da169754 985 netif_carrier_on(adapter->netdev);
4d6f6af8 986 }
4d6f6af8
GKH
987}
988
4d6ea9c3 989static void slic_upr_request_complete(struct adapter *adapter, u32 isr)
4d6f6af8 990{
4d6ea9c3
DK
991 struct sliccard *card = adapter->card;
992 struct slic_upr *upr;
eafe6002 993 unsigned long flags;
4d6f6af8 994
eafe6002 995 spin_lock_irqsave(&adapter->upr_lock, flags);
4d6ea9c3
DK
996 upr = adapter->upr_list;
997 if (!upr) {
eafe6002 998 spin_unlock_irqrestore(&adapter->upr_lock, flags);
4d6ea9c3 999 return;
4d6f6af8 1000 }
4d6ea9c3
DK
1001 adapter->upr_list = upr->next;
1002 upr->next = NULL;
1003 adapter->upr_busy = 0;
4d6ea9c3 1004 switch (upr->upr_request) {
fdb77775
LS
1005 case SLIC_UPR_STATS: {
1006 struct slic_shmemory *sm = &adapter->shmem;
1007 struct slic_shmem_data *sm_data = sm->shmem_data;
1008 struct slic_stats *stats = &sm_data->stats;
1009 struct slic_stats *old = &adapter->inicstats_prev;
1010 struct slicnet_stats *stst = &adapter->slic_stats;
1011
1012 if (isr & ISR_UPCERR) {
1013 dev_err(&adapter->netdev->dev,
1014 "SLIC_UPR_STATS command failed isr[%x]\n", isr);
4d6ea9c3
DK
1015 break;
1016 }
fdb77775 1017
473256b0
LS
1018 UPDATE_STATS_GB(stst->tcp.xmit_tcp_segs, stats->xmit_tcp_segs,
1019 old->xmit_tcp_segs);
fdb77775 1020
473256b0
LS
1021 UPDATE_STATS_GB(stst->tcp.xmit_tcp_bytes, stats->xmit_tcp_bytes,
1022 old->xmit_tcp_bytes);
fdb77775 1023
473256b0
LS
1024 UPDATE_STATS_GB(stst->tcp.rcv_tcp_segs, stats->rcv_tcp_segs,
1025 old->rcv_tcp_segs);
fdb77775 1026
473256b0
LS
1027 UPDATE_STATS_GB(stst->tcp.rcv_tcp_bytes, stats->rcv_tcp_bytes,
1028 old->rcv_tcp_bytes);
fdb77775 1029
473256b0
LS
1030 UPDATE_STATS_GB(stst->iface.xmt_bytes, stats->xmit_bytes,
1031 old->xmit_bytes);
fdb77775 1032
473256b0
LS
1033 UPDATE_STATS_GB(stst->iface.xmt_ucast, stats->xmit_unicasts,
1034 old->xmit_unicasts);
fdb77775 1035
473256b0
LS
1036 UPDATE_STATS_GB(stst->iface.rcv_bytes, stats->rcv_bytes,
1037 old->rcv_bytes);
fdb77775 1038
473256b0
LS
1039 UPDATE_STATS_GB(stst->iface.rcv_ucast, stats->rcv_unicasts,
1040 old->rcv_unicasts);
fdb77775 1041
473256b0
LS
1042 UPDATE_STATS_GB(stst->iface.xmt_errors, stats->xmit_collisions,
1043 old->xmit_collisions);
fdb77775
LS
1044
1045 UPDATE_STATS_GB(stst->iface.xmt_errors,
473256b0
LS
1046 stats->xmit_excess_collisions,
1047 old->xmit_excess_collisions);
fdb77775 1048
473256b0
LS
1049 UPDATE_STATS_GB(stst->iface.xmt_errors, stats->xmit_other_error,
1050 old->xmit_other_error);
fdb77775 1051
473256b0
LS
1052 UPDATE_STATS_GB(stst->iface.rcv_errors, stats->rcv_other_error,
1053 old->rcv_other_error);
fdb77775 1054
473256b0
LS
1055 UPDATE_STATS_GB(stst->iface.rcv_discards, stats->rcv_drops,
1056 old->rcv_drops);
fdb77775 1057
473256b0
LS
1058 if (stats->rcv_drops > old->rcv_drops)
1059 adapter->rcv_drops += (stats->rcv_drops -
1060 old->rcv_drops);
fdb77775
LS
1061 memcpy_fromio(old, stats, sizeof(*stats));
1062 break;
1063 }
4d6ea9c3
DK
1064 case SLIC_UPR_RLSR:
1065 slic_link_upr_complete(adapter, isr);
1066 break;
1067 case SLIC_UPR_RCONFIG:
1068 break;
4d6ea9c3
DK
1069 case SLIC_UPR_PING:
1070 card->pingstatus |= (isr & ISR_PINGDSMASK);
1071 break;
4d6f6af8 1072 }
4d6ea9c3
DK
1073 kfree(upr);
1074 slic_upr_start(adapter);
eafe6002 1075 spin_unlock_irqrestore(&adapter->upr_lock, flags);
4d6f6af8
GKH
1076}
1077
47a401a8 1078static int slic_config_get(struct adapter *adapter, u32 config, u32 config_h)
4d6f6af8 1079{
47a401a8
DM
1080 return slic_upr_request(adapter, SLIC_UPR_RCONFIG, config, config_h,
1081 0, 0);
4d6f6af8
GKH
1082}
1083
4d6ea9c3 1084/*
55b62cdf 1085 * Compute a checksum of the EEPROM according to RFC 1071.
4d6ea9c3 1086 */
f2fe1bc9 1087static u16 slic_eeprom_cksum(void *eeprom, unsigned int len)
4d6f6af8 1088{
55b62cdf
DM
1089 u16 *wp = eeprom;
1090 u32 checksum = 0;
4d6f6af8 1091
55b62cdf
DM
1092 while (len > 1) {
1093 checksum += *(wp++);
1094 len -= 2;
1095 }
4d6f6af8 1096
55b62cdf 1097 if (len > 0)
8610cbc5 1098 checksum += *(u8 *)wp;
4d6ea9c3 1099
55b62cdf
DM
1100 while (checksum >> 16)
1101 checksum = (checksum & 0xFFFF) + ((checksum >> 16) & 0xFFFF);
4d6ea9c3 1102
55b62cdf 1103 return ~checksum;
4d6f6af8
GKH
1104}
1105
4d6ea9c3 1106static void slic_rspqueue_free(struct adapter *adapter)
4d6f6af8 1107{
4d6ea9c3
DK
1108 int i;
1109 struct slic_rspqueue *rspq = &adapter->rspqueue;
4d6f6af8 1110
4d6ea9c3
DK
1111 for (i = 0; i < rspq->num_pages; i++) {
1112 if (rspq->vaddr[i]) {
1113 pci_free_consistent(adapter->pcidev, PAGE_SIZE,
1114 rspq->vaddr[i], rspq->paddr[i]);
1115 }
1116 rspq->vaddr[i] = NULL;
1117 rspq->paddr[i] = 0;
1118 }
1119 rspq->offset = 0;
1120 rspq->pageindex = 0;
1121 rspq->rspbuf = NULL;
4d6f6af8
GKH
1122}
1123
4d6ea9c3 1124static int slic_rspqueue_init(struct adapter *adapter)
4d6f6af8 1125{
4d6ea9c3
DK
1126 int i;
1127 struct slic_rspqueue *rspq = &adapter->rspqueue;
4d6ea9c3
DK
1128 u32 paddrh = 0;
1129
4d6ea9c3
DK
1130 memset(rspq, 0, sizeof(struct slic_rspqueue));
1131
1132 rspq->num_pages = SLIC_RSPQ_PAGES_GB;
1133
1134 for (i = 0; i < rspq->num_pages; i++) {
8b983be5
JP
1135 rspq->vaddr[i] = pci_zalloc_consistent(adapter->pcidev,
1136 PAGE_SIZE,
1137 &rspq->paddr[i]);
4d6ea9c3
DK
1138 if (!rspq->vaddr[i]) {
1139 dev_err(&adapter->pcidev->dev,
1140 "pci_alloc_consistent failed\n");
1141 slic_rspqueue_free(adapter);
1142 return -ENOMEM;
1143 }
4d6ea9c3
DK
1144
1145 if (paddrh == 0) {
c6d6a9a0
LS
1146 slic_write32(adapter, SLIC_REG_RBAR,
1147 rspq->paddr[i] | SLIC_RSPQ_BUFSINPAGE);
4d6ea9c3 1148 } else {
c6d6a9a0
LS
1149 slic_write64(adapter, SLIC_REG_RBAR64,
1150 rspq->paddr[i] | SLIC_RSPQ_BUFSINPAGE,
1151 paddrh);
4d6ea9c3
DK
1152 }
1153 }
1154 rspq->offset = 0;
1155 rspq->pageindex = 0;
1156 rspq->rspbuf = (struct slic_rspbuf *)rspq->vaddr[0];
1157 return 0;
4d6f6af8
GKH
1158}
1159
4d6ea9c3 1160static struct slic_rspbuf *slic_rspqueue_getnext(struct adapter *adapter)
4d6f6af8 1161{
4d6ea9c3
DK
1162 struct slic_rspqueue *rspq = &adapter->rspqueue;
1163 struct slic_rspbuf *buf;
4d6f6af8 1164
4d6ea9c3
DK
1165 if (!(rspq->rspbuf->status))
1166 return NULL;
4d6f6af8 1167
4d6ea9c3 1168 buf = rspq->rspbuf;
4d6ea9c3
DK
1169 if (++rspq->offset < SLIC_RSPQ_BUFSINPAGE) {
1170 rspq->rspbuf++;
4d6ea9c3 1171 } else {
c6d6a9a0
LS
1172 slic_write64(adapter, SLIC_REG_RBAR64,
1173 rspq->paddr[rspq->pageindex] |
1174 SLIC_RSPQ_BUFSINPAGE, 0);
6d1b80fd 1175 rspq->pageindex = (rspq->pageindex + 1) % rspq->num_pages;
4d6ea9c3
DK
1176 rspq->offset = 0;
1177 rspq->rspbuf = (struct slic_rspbuf *)
1178 rspq->vaddr[rspq->pageindex];
4d6ea9c3 1179 }
40991e4f 1180
4d6ea9c3
DK
1181 return buf;
1182}
4d6f6af8 1183
4d6ea9c3
DK
1184static void slic_cmdqmem_free(struct adapter *adapter)
1185{
1186 struct slic_cmdqmem *cmdqmem = &adapter->cmdqmem;
1187 int i;
4d6f6af8 1188
4d6ea9c3
DK
1189 for (i = 0; i < SLIC_CMDQ_MAXPAGES; i++) {
1190 if (cmdqmem->pages[i]) {
1191 pci_free_consistent(adapter->pcidev,
1192 PAGE_SIZE,
8610cbc5 1193 (void *)cmdqmem->pages[i],
4d6ea9c3
DK
1194 cmdqmem->dma_pages[i]);
1195 }
1196 }
1197 memset(cmdqmem, 0, sizeof(struct slic_cmdqmem));
1198}
4d6f6af8 1199
4d6ea9c3
DK
1200static u32 *slic_cmdqmem_addpage(struct adapter *adapter)
1201{
1202 struct slic_cmdqmem *cmdqmem = &adapter->cmdqmem;
1203 u32 *pageaddr;
4d6f6af8 1204
4d6ea9c3
DK
1205 if (cmdqmem->pagecnt >= SLIC_CMDQ_MAXPAGES)
1206 return NULL;
1207 pageaddr = pci_alloc_consistent(adapter->pcidev,
1208 PAGE_SIZE,
1209 &cmdqmem->dma_pages[cmdqmem->pagecnt]);
1210 if (!pageaddr)
1211 return NULL;
40991e4f 1212
4d6ea9c3
DK
1213 cmdqmem->pages[cmdqmem->pagecnt] = pageaddr;
1214 cmdqmem->pagecnt++;
1215 return pageaddr;
1216}
4d6f6af8 1217
4d6ea9c3
DK
1218static void slic_cmdq_free(struct adapter *adapter)
1219{
1220 struct slic_hostcmd *cmd;
4d6f6af8 1221
4d6ea9c3
DK
1222 cmd = adapter->cmdq_all.head;
1223 while (cmd) {
1224 if (cmd->busy) {
1225 struct sk_buff *tempskb;
4d6f6af8 1226
4d6ea9c3
DK
1227 tempskb = cmd->skb;
1228 if (tempskb) {
1229 cmd->skb = NULL;
1230 dev_kfree_skb_irq(tempskb);
4d6f6af8
GKH
1231 }
1232 }
4d6ea9c3
DK
1233 cmd = cmd->next_all;
1234 }
1235 memset(&adapter->cmdq_all, 0, sizeof(struct slic_cmdqueue));
1236 memset(&adapter->cmdq_free, 0, sizeof(struct slic_cmdqueue));
1237 memset(&adapter->cmdq_done, 0, sizeof(struct slic_cmdqueue));
1238 slic_cmdqmem_free(adapter);
1239}
4d6f6af8 1240
4d6ea9c3
DK
1241static void slic_cmdq_addcmdpage(struct adapter *adapter, u32 *page)
1242{
1243 struct slic_hostcmd *cmd;
1244 struct slic_hostcmd *prev;
1245 struct slic_hostcmd *tail;
1246 struct slic_cmdqueue *cmdq;
1247 int cmdcnt;
1248 void *cmdaddr;
1249 ulong phys_addr;
1250 u32 phys_addrl;
1251 u32 phys_addrh;
1252 struct slic_handle *pslic_handle;
eafe6002 1253 unsigned long flags;
4d6f6af8 1254
4d6ea9c3 1255 cmdaddr = page;
dd146d21 1256 cmd = cmdaddr;
4d6ea9c3 1257 cmdcnt = 0;
4d6f6af8 1258
4d6ea9c3
DK
1259 phys_addr = virt_to_bus((void *)page);
1260 phys_addrl = SLIC_GET_ADDR_LOW(phys_addr);
1261 phys_addrh = SLIC_GET_ADDR_HIGH(phys_addr);
4d6f6af8 1262
4d6ea9c3
DK
1263 prev = NULL;
1264 tail = cmd;
1265 while ((cmdcnt < SLIC_CMDQ_CMDSINPAGE) &&
1266 (adapter->slic_handle_ix < 256)) {
1267 /* Allocate and initialize a SLIC_HANDLE for this command */
eafe6002 1268 spin_lock_irqsave(&adapter->handle_lock, flags);
b0a0fb1e 1269 pslic_handle = adapter->pfree_slic_handles;
bcadb1dc 1270 adapter->pfree_slic_handles = pslic_handle->next;
eafe6002 1271 spin_unlock_irqrestore(&adapter->handle_lock, flags);
4d6ea9c3 1272 pslic_handle->type = SLIC_HANDLE_CMD;
8610cbc5
AG
1273 pslic_handle->address = (void *)cmd;
1274 pslic_handle->offset = (ushort)adapter->slic_handle_ix++;
4d6ea9c3
DK
1275 pslic_handle->other_handle = NULL;
1276 pslic_handle->next = NULL;
1277
1278 cmd->pslic_handle = pslic_handle;
1279 cmd->cmd64.hosthandle = pslic_handle->token.handle_token;
1280 cmd->busy = false;
1281 cmd->paddrl = phys_addrl;
1282 cmd->paddrh = phys_addrh;
1283 cmd->next_all = prev;
1284 cmd->next = prev;
1285 prev = cmd;
1286 phys_addrl += SLIC_HOSTCMD_SIZE;
1287 cmdaddr += SLIC_HOSTCMD_SIZE;
1288
dd146d21 1289 cmd = cmdaddr;
4d6ea9c3 1290 cmdcnt++;
4d6f6af8 1291 }
4d6ea9c3
DK
1292
1293 cmdq = &adapter->cmdq_all;
1294 cmdq->count += cmdcnt; /* SLIC_CMDQ_CMDSINPAGE; mooktodo */
1295 tail->next_all = cmdq->head;
1296 cmdq->head = prev;
1297 cmdq = &adapter->cmdq_free;
eafe6002 1298 spin_lock_irqsave(&cmdq->lock, flags);
4d6ea9c3
DK
1299 cmdq->count += cmdcnt; /* SLIC_CMDQ_CMDSINPAGE; mooktodo */
1300 tail->next = cmdq->head;
1301 cmdq->head = prev;
eafe6002 1302 spin_unlock_irqrestore(&cmdq->lock, flags);
4d6f6af8
GKH
1303}
1304
4d6ea9c3 1305static int slic_cmdq_init(struct adapter *adapter)
4d6f6af8 1306{
4d6ea9c3
DK
1307 int i;
1308 u32 *pageaddr;
4d6f6af8 1309
4d6ea9c3
DK
1310 memset(&adapter->cmdq_all, 0, sizeof(struct slic_cmdqueue));
1311 memset(&adapter->cmdq_free, 0, sizeof(struct slic_cmdqueue));
1312 memset(&adapter->cmdq_done, 0, sizeof(struct slic_cmdqueue));
eafe6002
DM
1313 spin_lock_init(&adapter->cmdq_all.lock);
1314 spin_lock_init(&adapter->cmdq_free.lock);
1315 spin_lock_init(&adapter->cmdq_done.lock);
bae5c3d1 1316 memset(&adapter->cmdqmem, 0, sizeof(struct slic_cmdqmem));
4d6ea9c3
DK
1317 adapter->slic_handle_ix = 1;
1318 for (i = 0; i < SLIC_CMDQ_INITPAGES; i++) {
1319 pageaddr = slic_cmdqmem_addpage(adapter);
4d6ea9c3
DK
1320 if (!pageaddr) {
1321 slic_cmdq_free(adapter);
1322 return -ENOMEM;
1323 }
1324 slic_cmdq_addcmdpage(adapter, pageaddr);
1325 }
1326 adapter->slic_handle_ix = 1;
4d6f6af8 1327
4d6ea9c3 1328 return 0;
4d6f6af8
GKH
1329}
1330
4d6ea9c3 1331static void slic_cmdq_reset(struct adapter *adapter)
4d6f6af8 1332{
4d6ea9c3
DK
1333 struct slic_hostcmd *hcmd;
1334 struct sk_buff *skb;
1335 u32 outstanding;
eafe6002 1336 unsigned long flags;
4d6f6af8 1337
eafe6002 1338 spin_lock_irqsave(&adapter->cmdq_free.lock, flags);
46d74c38 1339 spin_lock(&adapter->cmdq_done.lock);
4d6ea9c3
DK
1340 outstanding = adapter->cmdq_all.count - adapter->cmdq_done.count;
1341 outstanding -= adapter->cmdq_free.count;
1342 hcmd = adapter->cmdq_all.head;
1343 while (hcmd) {
1344 if (hcmd->busy) {
1345 skb = hcmd->skb;
4d6ea9c3
DK
1346 hcmd->busy = 0;
1347 hcmd->skb = NULL;
1348 dev_kfree_skb_irq(skb);
1349 }
1350 hcmd = hcmd->next_all;
470c5736 1351 }
4d6ea9c3
DK
1352 adapter->cmdq_free.count = 0;
1353 adapter->cmdq_free.head = NULL;
1354 adapter->cmdq_free.tail = NULL;
1355 adapter->cmdq_done.count = 0;
1356 adapter->cmdq_done.head = NULL;
1357 adapter->cmdq_done.tail = NULL;
1358 adapter->cmdq_free.head = adapter->cmdq_all.head;
1359 hcmd = adapter->cmdq_all.head;
1360 while (hcmd) {
1361 adapter->cmdq_free.count++;
1362 hcmd->next = hcmd->next_all;
1363 hcmd = hcmd->next_all;
4d6f6af8 1364 }
4d6ea9c3
DK
1365 if (adapter->cmdq_free.count != adapter->cmdq_all.count) {
1366 dev_err(&adapter->netdev->dev,
1367 "free_count %d != all count %d\n",
1368 adapter->cmdq_free.count, adapter->cmdq_all.count);
4d6f6af8 1369 }
46d74c38 1370 spin_unlock(&adapter->cmdq_done.lock);
eafe6002 1371 spin_unlock_irqrestore(&adapter->cmdq_free.lock, flags);
4d6f6af8
GKH
1372}
1373
4d6ea9c3 1374static void slic_cmdq_getdone(struct adapter *adapter)
4d6f6af8 1375{
4d6ea9c3
DK
1376 struct slic_cmdqueue *done_cmdq = &adapter->cmdq_done;
1377 struct slic_cmdqueue *free_cmdq = &adapter->cmdq_free;
eafe6002 1378 unsigned long flags;
4d6f6af8 1379
eafe6002 1380 spin_lock_irqsave(&done_cmdq->lock, flags);
4d6f6af8 1381
4d6ea9c3
DK
1382 free_cmdq->head = done_cmdq->head;
1383 free_cmdq->count = done_cmdq->count;
1384 done_cmdq->head = NULL;
1385 done_cmdq->tail = NULL;
1386 done_cmdq->count = 0;
eafe6002 1387 spin_unlock_irqrestore(&done_cmdq->lock, flags);
4d6ea9c3 1388}
874073ea 1389
4d6ea9c3
DK
1390static struct slic_hostcmd *slic_cmdq_getfree(struct adapter *adapter)
1391{
1392 struct slic_cmdqueue *cmdq = &adapter->cmdq_free;
1393 struct slic_hostcmd *cmd = NULL;
eafe6002 1394 unsigned long flags;
4d6f6af8 1395
4d6ea9c3 1396lock_and_retry:
eafe6002 1397 spin_lock_irqsave(&cmdq->lock, flags);
4d6ea9c3
DK
1398retry:
1399 cmd = cmdq->head;
1400 if (cmd) {
1401 cmdq->head = cmd->next;
1402 cmdq->count--;
eafe6002 1403 spin_unlock_irqrestore(&cmdq->lock, flags);
4d6ea9c3
DK
1404 } else {
1405 slic_cmdq_getdone(adapter);
1406 cmd = cmdq->head;
1407 if (cmd) {
1408 goto retry;
1409 } else {
1410 u32 *pageaddr;
874073ea 1411
eafe6002 1412 spin_unlock_irqrestore(&cmdq->lock, flags);
4d6ea9c3
DK
1413 pageaddr = slic_cmdqmem_addpage(adapter);
1414 if (pageaddr) {
1415 slic_cmdq_addcmdpage(adapter, pageaddr);
1416 goto lock_and_retry;
1417 }
4d6f6af8
GKH
1418 }
1419 }
4d6ea9c3 1420 return cmd;
4d6f6af8
GKH
1421}
1422
4d6ea9c3
DK
1423static void slic_cmdq_putdone_irq(struct adapter *adapter,
1424 struct slic_hostcmd *cmd)
4d6f6af8 1425{
4d6ea9c3 1426 struct slic_cmdqueue *cmdq = &adapter->cmdq_done;
4d6f6af8 1427
eafe6002 1428 spin_lock(&cmdq->lock);
4d6ea9c3
DK
1429 cmd->busy = 0;
1430 cmd->next = cmdq->head;
1431 cmdq->head = cmd;
1432 cmdq->count++;
1433 if ((adapter->xmitq_full) && (cmdq->count > 10))
1434 netif_wake_queue(adapter->netdev);
eafe6002 1435 spin_unlock(&cmdq->lock);
4d6f6af8
GKH
1436}
1437
4d6ea9c3 1438static int slic_rcvqueue_fill(struct adapter *adapter)
4d6f6af8 1439{
4d6ea9c3
DK
1440 void *paddr;
1441 u32 paddrl;
1442 u32 paddrh;
1443 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
1444 int i = 0;
1445 struct device *dev = &adapter->netdev->dev;
1446
1447 while (i < SLIC_RCVQ_FILLENTRIES) {
1448 struct slic_rcvbuf *rcvbuf;
1449 struct sk_buff *skb;
1450#ifdef KLUDGE_FOR_4GB_BOUNDARY
1451retry_rcvqfill:
1452#endif
1453 skb = alloc_skb(SLIC_RCVQ_RCVBUFSIZE, GFP_ATOMIC);
1454 if (skb) {
01d0a9b4
JP
1455 paddr = (void *)(unsigned long)
1456 pci_map_single(adapter->pcidev,
1457 skb->data,
1458 SLIC_RCVQ_RCVBUFSIZE,
1459 PCI_DMA_FROMDEVICE);
4d6ea9c3
DK
1460 paddrl = SLIC_GET_ADDR_LOW(paddr);
1461 paddrh = SLIC_GET_ADDR_HIGH(paddr);
1462
1463 skb->len = SLIC_RCVBUF_HEADSIZE;
1464 rcvbuf = (struct slic_rcvbuf *)skb->head;
1465 rcvbuf->status = 0;
1466 skb->next = NULL;
1467#ifdef KLUDGE_FOR_4GB_BOUNDARY
1468 if (paddrl == 0) {
1469 dev_err(dev, "%s: LOW 32bits PHYSICAL ADDRESS == 0\n",
1470 __func__);
1471 dev_err(dev, "skb[%p] PROBLEM\n", skb);
17d2c643
SC
1472 dev_err(dev, " skbdata[%p]\n",
1473 skb->data);
4d6ea9c3
DK
1474 dev_err(dev, " skblen[%x]\n", skb->len);
1475 dev_err(dev, " paddr[%p]\n", paddr);
1476 dev_err(dev, " paddrl[%x]\n", paddrl);
1477 dev_err(dev, " paddrh[%x]\n", paddrh);
17d2c643
SC
1478 dev_err(dev, " rcvq->head[%p]\n",
1479 rcvq->head);
1480 dev_err(dev, " rcvq->tail[%p]\n",
1481 rcvq->tail);
1482 dev_err(dev, " rcvq->count[%x]\n",
1483 rcvq->count);
4d6ea9c3
DK
1484 dev_err(dev, "SKIP THIS SKB!!!!!!!!\n");
1485 goto retry_rcvqfill;
1486 }
1487#else
1488 if (paddrl == 0) {
1489 dev_err(dev, "%s: LOW 32bits PHYSICAL ADDRESS == 0\n",
1490 __func__);
1491 dev_err(dev, "skb[%p] PROBLEM\n", skb);
17d2c643
SC
1492 dev_err(dev, " skbdata[%p]\n",
1493 skb->data);
4d6ea9c3
DK
1494 dev_err(dev, " skblen[%x]\n", skb->len);
1495 dev_err(dev, " paddr[%p]\n", paddr);
1496 dev_err(dev, " paddrl[%x]\n", paddrl);
1497 dev_err(dev, " paddrh[%x]\n", paddrh);
17d2c643
SC
1498 dev_err(dev, " rcvq->head[%p]\n",
1499 rcvq->head);
1500 dev_err(dev, " rcvq->tail[%p]\n",
1501 rcvq->tail);
1502 dev_err(dev, " rcvq->count[%x]\n",
1503 rcvq->count);
4d6ea9c3
DK
1504 dev_err(dev, "GIVE TO CARD ANYWAY\n");
1505 }
1506#endif
1507 if (paddrh == 0) {
c6d6a9a0
LS
1508 slic_write32(adapter, SLIC_REG_HBAR,
1509 (u32)paddrl);
4d6ea9c3 1510 } else {
c6d6a9a0
LS
1511 slic_write64(adapter, SLIC_REG_HBAR64, paddrl,
1512 paddrh);
4d6ea9c3
DK
1513 }
1514 if (rcvq->head)
1515 rcvq->tail->next = skb;
1516 else
1517 rcvq->head = skb;
1518 rcvq->tail = skb;
1519 rcvq->count++;
1520 i++;
1521 } else {
1522 dev_err(&adapter->netdev->dev,
1523 "slic_rcvqueue_fill could only get [%d] skbuffs\n",
1524 i);
1525 break;
1526 }
1527 }
1528 return i;
4d6f6af8
GKH
1529}
1530
4d6ea9c3 1531static void slic_rcvqueue_free(struct adapter *adapter)
4d6f6af8 1532{
4d6ea9c3
DK
1533 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
1534 struct sk_buff *skb;
4d6f6af8 1535
4d6ea9c3
DK
1536 while (rcvq->head) {
1537 skb = rcvq->head;
1538 rcvq->head = rcvq->head->next;
1539 dev_kfree_skb(skb);
1540 }
1541 rcvq->tail = NULL;
1542 rcvq->head = NULL;
1543 rcvq->count = 0;
1544}
4d6f6af8 1545
4d6ea9c3
DK
1546static int slic_rcvqueue_init(struct adapter *adapter)
1547{
1548 int i, count;
1549 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
4d6f6af8 1550
4d6ea9c3
DK
1551 rcvq->tail = NULL;
1552 rcvq->head = NULL;
1553 rcvq->size = SLIC_RCVQ_ENTRIES;
1554 rcvq->errors = 0;
1555 rcvq->count = 0;
db9c9305 1556 i = SLIC_RCVQ_ENTRIES / SLIC_RCVQ_FILLENTRIES;
4d6ea9c3
DK
1557 count = 0;
1558 while (i) {
1559 count += slic_rcvqueue_fill(adapter);
1560 i--;
1561 }
1562 if (rcvq->count < SLIC_RCVQ_MINENTRIES) {
1563 slic_rcvqueue_free(adapter);
1564 return -ENOMEM;
4d6f6af8 1565 }
4d6ea9c3
DK
1566 return 0;
1567}
4d6f6af8 1568
4d6ea9c3
DK
1569static struct sk_buff *slic_rcvqueue_getnext(struct adapter *adapter)
1570{
1571 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
1572 struct sk_buff *skb;
1573 struct slic_rcvbuf *rcvbuf;
1574 int count;
4d6f6af8 1575
4d6ea9c3
DK
1576 if (rcvq->count) {
1577 skb = rcvq->head;
1578 rcvbuf = (struct slic_rcvbuf *)skb->head;
4d6f6af8 1579
4d6ea9c3
DK
1580 if (rcvbuf->status & IRHDDR_SVALID) {
1581 rcvq->head = rcvq->head->next;
1582 skb->next = NULL;
1583 rcvq->count--;
4d6f6af8 1584 } else {
4d6ea9c3 1585 skb = NULL;
4d6f6af8 1586 }
4d6ea9c3
DK
1587 } else {
1588 dev_err(&adapter->netdev->dev,
1589 "RcvQ Empty!! rcvq[%p] count[%x]\n", rcvq, rcvq->count);
1590 skb = NULL;
1591 }
1592 while (rcvq->count < SLIC_RCVQ_FILLTHRESH) {
1593 count = slic_rcvqueue_fill(adapter);
1594 if (!count)
1595 break;
1596 }
1597 if (skb)
1598 rcvq->errors = 0;
1599 return skb;
1600}
4d6f6af8 1601
4d6ea9c3
DK
1602static u32 slic_rcvqueue_reinsert(struct adapter *adapter, struct sk_buff *skb)
1603{
1604 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
1605 void *paddr;
1606 u32 paddrl;
1607 u32 paddrh;
1608 struct slic_rcvbuf *rcvbuf = (struct slic_rcvbuf *)skb->head;
1609 struct device *dev;
4d6f6af8 1610
01d0a9b4
JP
1611 paddr = (void *)(unsigned long)
1612 pci_map_single(adapter->pcidev, skb->head,
1613 SLIC_RCVQ_RCVBUFSIZE, PCI_DMA_FROMDEVICE);
4d6ea9c3
DK
1614 rcvbuf->status = 0;
1615 skb->next = NULL;
4d6f6af8 1616
4d6ea9c3
DK
1617 paddrl = SLIC_GET_ADDR_LOW(paddr);
1618 paddrh = SLIC_GET_ADDR_HIGH(paddr);
4d6f6af8 1619
4d6ea9c3
DK
1620 if (paddrl == 0) {
1621 dev = &adapter->netdev->dev;
1622 dev_err(dev, "%s: LOW 32bits PHYSICAL ADDRESS == 0\n",
1623 __func__);
1624 dev_err(dev, "skb[%p] PROBLEM\n", skb);
1625 dev_err(dev, " skbdata[%p]\n", skb->data);
1626 dev_err(dev, " skblen[%x]\n", skb->len);
1627 dev_err(dev, " paddr[%p]\n", paddr);
1628 dev_err(dev, " paddrl[%x]\n", paddrl);
1629 dev_err(dev, " paddrh[%x]\n", paddrh);
1630 dev_err(dev, " rcvq->head[%p]\n", rcvq->head);
1631 dev_err(dev, " rcvq->tail[%p]\n", rcvq->tail);
1632 dev_err(dev, " rcvq->count[%x]\n", rcvq->count);
4d6f6af8 1633 }
4d6ea9c3 1634 if (paddrh == 0) {
c6d6a9a0 1635 slic_write32(adapter, SLIC_REG_HBAR, (u32)paddrl);
4d6ea9c3 1636 } else {
c6d6a9a0 1637 slic_write64(adapter, SLIC_REG_HBAR64, paddrl, paddrh);
4d6f6af8 1638 }
4d6ea9c3
DK
1639 if (rcvq->head)
1640 rcvq->tail->next = skb;
e8bc9b7a 1641 else
4d6ea9c3
DK
1642 rcvq->head = skb;
1643 rcvq->tail = skb;
1644 rcvq->count++;
1645 return rcvq->count;
4d6f6af8
GKH
1646}
1647
4d6ea9c3
DK
1648/*
1649 * slic_link_event_handler -
1650 *
1651 * Initiate a link configuration sequence. The link configuration begins
1652 * by issuing a READ_LINK_STATUS command to the Utility Processor on the
1653 * SLIC. Since the command finishes asynchronously, the slic_upr_comlete
1654 * routine will follow it up witha UP configuration write command, which
1655 * will also complete asynchronously.
1656 *
1657 */
78affe65 1658static int slic_link_event_handler(struct adapter *adapter)
4d6ea9c3
DK
1659{
1660 int status;
fdb77775
LS
1661 struct slic_shmemory *sm = &adapter->shmem;
1662 dma_addr_t phaddr = sm->lnkstatus_phaddr;
1663
4d6f6af8 1664
4d6ea9c3
DK
1665 if (adapter->state != ADAPT_UP) {
1666 /* Adapter is not operational. Ignore. */
78affe65 1667 return -ENODEV;
4d6f6af8 1668 }
fdb77775 1669 /* no 4GB wrap guaranteed */
4d6ea9c3 1670 status = slic_upr_request(adapter, SLIC_UPR_RLSR,
fdb77775
LS
1671 cpu_to_le32(lower_32_bits(phaddr)),
1672 cpu_to_le32(upper_32_bits(phaddr)), 0, 0);
78affe65 1673 return status;
4d6f6af8
GKH
1674}
1675
4d6ea9c3 1676static void slic_init_cleanup(struct adapter *adapter)
4d6f6af8 1677{
4d6ea9c3
DK
1678 if (adapter->intrregistered) {
1679 adapter->intrregistered = 0;
1680 free_irq(adapter->netdev->irq, adapter->netdev);
4d6f6af8 1681 }
fdb77775
LS
1682
1683 if (adapter->shmem.shmem_data) {
1684 struct slic_shmemory *sm = &adapter->shmem;
1685 struct slic_shmem_data *sm_data = sm->shmem_data;
1686
1687 pci_free_consistent(adapter->pcidev, sizeof(*sm_data), sm_data,
1688 sm->isr_phaddr);
4d6f6af8 1689 }
4d6ea9c3
DK
1690
1691 if (adapter->pingtimerset) {
1692 adapter->pingtimerset = 0;
1693 del_timer(&adapter->pingtimer);
4d6f6af8 1694 }
4d6f6af8 1695
4d6ea9c3
DK
1696 slic_rspqueue_free(adapter);
1697 slic_cmdq_free(adapter);
1698 slic_rcvqueue_free(adapter);
4d6f6af8
GKH
1699}
1700
4d6ea9c3
DK
1701/*
1702 * Allocate a mcast_address structure to hold the multicast address.
1703 * Link it in.
1704 */
1705static int slic_mcast_add_list(struct adapter *adapter, char *address)
4d6f6af8 1706{
4d6ea9c3 1707 struct mcast_address *mcaddr, *mlist;
4d6f6af8 1708
4d6ea9c3
DK
1709 /* Check to see if it already exists */
1710 mlist = adapter->mcastaddrs;
1711 while (mlist) {
8329419a 1712 if (ether_addr_equal(mlist->address, address))
4d6ea9c3
DK
1713 return 0;
1714 mlist = mlist->next;
1715 }
e8bc9b7a 1716
4d6ea9c3 1717 /* Doesn't already exist. Allocate a structure to hold it */
5d7a3876 1718 mcaddr = kmalloc(sizeof(*mcaddr), GFP_ATOMIC);
2d5f6fec 1719 if (!mcaddr)
4d6ea9c3 1720 return 1;
a71b9978 1721
f999ac00 1722 ether_addr_copy(mcaddr->address, address);
4d6ea9c3
DK
1723
1724 mcaddr->next = adapter->mcastaddrs;
1725 adapter->mcastaddrs = mcaddr;
4d6f6af8 1726
4d6f6af8
GKH
1727 return 0;
1728}
1729
4d6ea9c3 1730static void slic_mcast_set_list(struct net_device *dev)
4d6f6af8 1731{
4d6ea9c3
DK
1732 struct adapter *adapter = netdev_priv(dev);
1733 int status = 0;
1734 char *addresses;
1735 struct netdev_hw_addr *ha;
4d6f6af8 1736
4d6ea9c3 1737 netdev_for_each_mc_addr(ha, dev) {
8610cbc5 1738 addresses = (char *)&ha->addr;
4d6ea9c3
DK
1739 status = slic_mcast_add_list(adapter, addresses);
1740 if (status != 0)
1741 break;
1742 slic_mcast_set_bit(adapter, addresses);
1743 }
1744
1745 if (adapter->devflags_prev != dev->flags) {
1746 adapter->macopts = MAC_DIRECTED;
1747 if (dev->flags) {
1748 if (dev->flags & IFF_BROADCAST)
1749 adapter->macopts |= MAC_BCAST;
1750 if (dev->flags & IFF_PROMISC)
1751 adapter->macopts |= MAC_PROMISC;
1752 if (dev->flags & IFF_ALLMULTI)
1753 adapter->macopts |= MAC_ALLMCAST;
1754 if (dev->flags & IFF_MULTICAST)
1755 adapter->macopts |= MAC_MCAST;
4d6f6af8 1756 }
4d6ea9c3
DK
1757 adapter->devflags_prev = dev->flags;
1758 slic_config_set(adapter, true);
1759 } else {
1760 if (status == 0)
1761 slic_mcast_set_mask(adapter);
4d6f6af8 1762 }
4d6f6af8
GKH
1763}
1764
4d6ea9c3
DK
1765#define XMIT_FAIL_LINK_STATE 1
1766#define XMIT_FAIL_ZERO_LENGTH 2
1767#define XMIT_FAIL_HOSTCMD_FAIL 3
1768
1769static void slic_xmit_build_request(struct adapter *adapter,
1770 struct slic_hostcmd *hcmd, struct sk_buff *skb)
4d6f6af8 1771{
4d6ea9c3
DK
1772 struct slic_host64_cmd *ihcmd;
1773 ulong phys_addr;
4d6f6af8 1774
4d6ea9c3
DK
1775 ihcmd = &hcmd->cmd64;
1776
6e28c2a2 1777 ihcmd->flags = adapter->port << IHFLG_IFSHFT;
4d6ea9c3
DK
1778 ihcmd->command = IHCMD_XMT_REQ;
1779 ihcmd->u.slic_buffers.totlen = skb->len;
1780 phys_addr = pci_map_single(adapter->pcidev, skb->data, skb->len,
1781 PCI_DMA_TODEVICE);
514dd88d
AKC
1782 if (pci_dma_mapping_error(adapter->pcidev, phys_addr)) {
1783 kfree_skb(skb);
1784 dev_err(&adapter->pcidev->dev, "DMA mapping error\n");
1785 return;
1786 }
4d6ea9c3
DK
1787 ihcmd->u.slic_buffers.bufs[0].paddrl = SLIC_GET_ADDR_LOW(phys_addr);
1788 ihcmd->u.slic_buffers.bufs[0].paddrh = SLIC_GET_ADDR_HIGH(phys_addr);
1789 ihcmd->u.slic_buffers.bufs[0].length = skb->len;
1033f1f7 1790#if BITS_PER_LONG == 64
8610cbc5
AG
1791 hcmd->cmdsize = (u32)((((u64)&ihcmd->u.slic_buffers.bufs[1] -
1792 (u64)hcmd) + 31) >> 5);
1033f1f7 1793#else
a659b3e8
AM
1794 hcmd->cmdsize = (((u32)&ihcmd->u.slic_buffers.bufs[1] -
1795 (u32)hcmd) + 31) >> 5;
4d6ea9c3 1796#endif
4d6f6af8
GKH
1797}
1798
4d6ea9c3
DK
1799static void slic_xmit_fail(struct adapter *adapter,
1800 struct sk_buff *skb,
1801 void *cmd, u32 skbtype, u32 status)
4d6f6af8 1802{
4d6ea9c3
DK
1803 if (adapter->xmitq_full)
1804 netif_stop_queue(adapter->netdev);
2d5f6fec 1805 if ((!cmd) && (status <= XMIT_FAIL_HOSTCMD_FAIL)) {
4d6ea9c3
DK
1806 switch (status) {
1807 case XMIT_FAIL_LINK_STATE:
1808 dev_err(&adapter->netdev->dev,
5d5b44b5 1809 "reject xmit skb[%p: %x] linkstate[%s] adapter[%s:%d] card[%s:%d]\n",
4d6ea9c3
DK
1810 skb, skb->pkt_type,
1811 SLIC_LINKSTATE(adapter->linkstate),
1812 SLIC_ADAPTER_STATE(adapter->state),
1813 adapter->state,
1814 SLIC_CARD_STATE(adapter->card->state),
1815 adapter->card->state);
1816 break;
1817 case XMIT_FAIL_ZERO_LENGTH:
1818 dev_err(&adapter->netdev->dev,
1819 "xmit_start skb->len == 0 skb[%p] type[%x]\n",
1820 skb, skb->pkt_type);
1821 break;
1822 case XMIT_FAIL_HOSTCMD_FAIL:
1823 dev_err(&adapter->netdev->dev,
17d2c643
SC
1824 "xmit_start skb[%p] type[%x] No host commands available\n",
1825 skb, skb->pkt_type);
4d6ea9c3 1826 break;
4d6ea9c3
DK
1827 }
1828 }
1829 dev_kfree_skb(skb);
9092de6d 1830 adapter->netdev->stats.tx_dropped++;
4d6ea9c3 1831}
e8bc9b7a 1832
4d6ea9c3
DK
1833static void slic_rcv_handle_error(struct adapter *adapter,
1834 struct slic_rcvbuf *rcvbuf)
1835{
1836 struct slic_hddr_wds *hdr = (struct slic_hddr_wds *)rcvbuf->data;
9092de6d 1837 struct net_device *netdev = adapter->netdev;
4d6f6af8 1838
4d6ea9c3
DK
1839 if (adapter->devid != SLIC_1GB_DEVICE_ID) {
1840 if (hdr->frame_status14 & VRHSTAT_802OE)
1841 adapter->if_events.oflow802++;
1842 if (hdr->frame_status14 & VRHSTAT_TPOFLO)
1843 adapter->if_events.Tprtoflow++;
1844 if (hdr->frame_status_b14 & VRHSTATB_802UE)
1845 adapter->if_events.uflow802++;
1846 if (hdr->frame_status_b14 & VRHSTATB_RCVE) {
1847 adapter->if_events.rcvearly++;
9092de6d 1848 netdev->stats.rx_fifo_errors++;
4d6ea9c3
DK
1849 }
1850 if (hdr->frame_status_b14 & VRHSTATB_BUFF) {
1851 adapter->if_events.Bufov++;
9092de6d 1852 netdev->stats.rx_over_errors++;
4d6ea9c3
DK
1853 }
1854 if (hdr->frame_status_b14 & VRHSTATB_CARRE) {
1855 adapter->if_events.Carre++;
9092de6d 1856 netdev->stats.tx_carrier_errors++;
4d6ea9c3
DK
1857 }
1858 if (hdr->frame_status_b14 & VRHSTATB_LONGE)
1859 adapter->if_events.Longe++;
1860 if (hdr->frame_status_b14 & VRHSTATB_PREA)
1861 adapter->if_events.Invp++;
1862 if (hdr->frame_status_b14 & VRHSTATB_CRC) {
1863 adapter->if_events.Crc++;
9092de6d 1864 netdev->stats.rx_crc_errors++;
4d6ea9c3
DK
1865 }
1866 if (hdr->frame_status_b14 & VRHSTATB_DRBL)
1867 adapter->if_events.Drbl++;
1868 if (hdr->frame_status_b14 & VRHSTATB_CODE)
1869 adapter->if_events.Code++;
1870 if (hdr->frame_status_b14 & VRHSTATB_TPCSUM)
1871 adapter->if_events.TpCsum++;
1872 if (hdr->frame_status_b14 & VRHSTATB_TPHLEN)
1873 adapter->if_events.TpHlen++;
1874 if (hdr->frame_status_b14 & VRHSTATB_IPCSUM)
1875 adapter->if_events.IpCsum++;
1876 if (hdr->frame_status_b14 & VRHSTATB_IPLERR)
1877 adapter->if_events.IpLen++;
1878 if (hdr->frame_status_b14 & VRHSTATB_IPHERR)
1879 adapter->if_events.IpHlen++;
4d6f6af8 1880 } else {
4d6ea9c3
DK
1881 if (hdr->frame_statusGB & VGBSTAT_XPERR) {
1882 u32 xerr = hdr->frame_statusGB >> VGBSTAT_XERRSHFT;
1883
1884 if (xerr == VGBSTAT_XCSERR)
1885 adapter->if_events.TpCsum++;
1886 if (xerr == VGBSTAT_XUFLOW)
1887 adapter->if_events.Tprtoflow++;
1888 if (xerr == VGBSTAT_XHLEN)
1889 adapter->if_events.TpHlen++;
1890 }
1891 if (hdr->frame_statusGB & VGBSTAT_NETERR) {
1892 u32 nerr =
1893 (hdr->
1894 frame_statusGB >> VGBSTAT_NERRSHFT) &
1895 VGBSTAT_NERRMSK;
1896 if (nerr == VGBSTAT_NCSERR)
1897 adapter->if_events.IpCsum++;
1898 if (nerr == VGBSTAT_NUFLOW)
1899 adapter->if_events.IpLen++;
1900 if (nerr == VGBSTAT_NHLEN)
1901 adapter->if_events.IpHlen++;
1902 }
1903 if (hdr->frame_statusGB & VGBSTAT_LNKERR) {
1904 u32 lerr = hdr->frame_statusGB & VGBSTAT_LERRMSK;
1905
1906 if (lerr == VGBSTAT_LDEARLY)
1907 adapter->if_events.rcvearly++;
1908 if (lerr == VGBSTAT_LBOFLO)
1909 adapter->if_events.Bufov++;
1910 if (lerr == VGBSTAT_LCODERR)
1911 adapter->if_events.Code++;
1912 if (lerr == VGBSTAT_LDBLNBL)
1913 adapter->if_events.Drbl++;
1914 if (lerr == VGBSTAT_LCRCERR)
1915 adapter->if_events.Crc++;
1916 if (lerr == VGBSTAT_LOFLO)
1917 adapter->if_events.oflow802++;
1918 if (lerr == VGBSTAT_LUFLO)
1919 adapter->if_events.uflow802++;
1920 }
4d6f6af8 1921 }
4d6f6af8
GKH
1922}
1923
4d6ea9c3
DK
1924#define TCP_OFFLOAD_FRAME_PUSHFLAG 0x10000000
1925#define M_FAST_PATH 0x0040
4d6f6af8 1926
4d6ea9c3 1927static void slic_rcv_handler(struct adapter *adapter)
4d6f6af8 1928{
9092de6d 1929 struct net_device *netdev = adapter->netdev;
4d6ea9c3
DK
1930 struct sk_buff *skb;
1931 struct slic_rcvbuf *rcvbuf;
1932 u32 frames = 0;
4d6f6af8 1933
4d6ea9c3
DK
1934 while ((skb = slic_rcvqueue_getnext(adapter))) {
1935 u32 rx_bytes;
4d6f6af8 1936
4d6ea9c3
DK
1937 rcvbuf = (struct slic_rcvbuf *)skb->head;
1938 adapter->card->events++;
1939 if (rcvbuf->status & IRHDDR_ERR) {
1940 adapter->rx_errors++;
1941 slic_rcv_handle_error(adapter, rcvbuf);
1942 slic_rcvqueue_reinsert(adapter, skb);
1943 continue;
1944 }
4d6f6af8 1945
4d6ea9c3
DK
1946 if (!slic_mac_filter(adapter, (struct ether_header *)
1947 rcvbuf->data)) {
1948 slic_rcvqueue_reinsert(adapter, skb);
1949 continue;
1950 }
1951 skb_pull(skb, SLIC_RCVBUF_HEADSIZE);
1952 rx_bytes = (rcvbuf->length & IRHDDR_FLEN_MSK);
1953 skb_put(skb, rx_bytes);
9092de6d
DK
1954 netdev->stats.rx_packets++;
1955 netdev->stats.rx_bytes += rx_bytes;
4d6ea9c3
DK
1956#if SLIC_OFFLOAD_IP_CHECKSUM
1957 skb->ip_summed = CHECKSUM_UNNECESSARY;
1958#endif
4d6f6af8 1959
4d6ea9c3
DK
1960 skb->dev = adapter->netdev;
1961 skb->protocol = eth_type_trans(skb, skb->dev);
1962 netif_rx(skb);
4d6f6af8 1963
4d6ea9c3
DK
1964 ++frames;
1965#if SLIC_INTERRUPT_PROCESS_LIMIT
1966 if (frames >= SLIC_RCVQ_MAX_PROCESS_ISR) {
1967 adapter->rcv_interrupt_yields++;
4d6f6af8
GKH
1968 break;
1969 }
4d6ea9c3 1970#endif
4d6f6af8 1971 }
4d6ea9c3 1972 adapter->max_isr_rcvs = max(adapter->max_isr_rcvs, frames);
4d6f6af8
GKH
1973}
1974
4d6ea9c3 1975static void slic_xmit_complete(struct adapter *adapter)
4d6f6af8 1976{
4d6ea9c3
DK
1977 struct slic_hostcmd *hcmd;
1978 struct slic_rspbuf *rspbuf;
1979 u32 frames = 0;
1980 struct slic_handle_word slic_handle_word;
4d6f6af8 1981
4d6ea9c3
DK
1982 do {
1983 rspbuf = slic_rspqueue_getnext(adapter);
1984 if (!rspbuf)
1985 break;
1986 adapter->xmit_completes++;
1987 adapter->card->events++;
1988 /*
f773a834
AG
1989 * Get the complete host command buffer
1990 */
4d6ea9c3 1991 slic_handle_word.handle_token = rspbuf->hosthandle;
4d6ea9c3 1992 hcmd =
4d6ea9c3
DK
1993 adapter->slic_handles[slic_handle_word.handle_index].
1994 address;
1995/* hcmd = (struct slic_hostcmd *) rspbuf->hosthandle; */
4d6ea9c3
DK
1996 if (hcmd->type == SLIC_CMD_DUMB) {
1997 if (hcmd->skb)
1998 dev_kfree_skb_irq(hcmd->skb);
1999 slic_cmdq_putdone_irq(adapter, hcmd);
4d6f6af8 2000 }
4d6ea9c3
DK
2001 rspbuf->status = 0;
2002 rspbuf->hosthandle = 0;
2003 frames++;
2004 } while (1);
2005 adapter->max_isr_xmits = max(adapter->max_isr_xmits, frames);
4d6f6af8
GKH
2006}
2007
f66626e4
RK
2008static void slic_interrupt_card_up(u32 isr, struct adapter *adapter,
2009 struct net_device *dev)
2010{
2011 if (isr & ~ISR_IO) {
2012 if (isr & ISR_ERR) {
2013 adapter->error_interrupts++;
2014 if (isr & ISR_RMISS) {
2015 int count;
2016 int pre_count;
2017 int errors;
2018
2019 struct slic_rcvqueue *rcvq =
2020 &adapter->rcvqueue;
2021
2022 adapter->error_rmiss_interrupts++;
2023
2024 if (!rcvq->errors)
2025 rcv_count = rcvq->count;
2026 pre_count = rcvq->count;
2027 errors = rcvq->errors;
2028
2029 while (rcvq->count < SLIC_RCVQ_FILLTHRESH) {
2030 count = slic_rcvqueue_fill(adapter);
2031 if (!count)
2032 break;
2033 }
2034 } else if (isr & ISR_XDROP) {
2035 dev_err(&dev->dev,
17d2c643
SC
2036 "isr & ISR_ERR [%x] ISR_XDROP\n",
2037 isr);
f66626e4
RK
2038 } else {
2039 dev_err(&dev->dev,
2040 "isr & ISR_ERR [%x]\n",
2041 isr);
2042 }
2043 }
2044
2045 if (isr & ISR_LEVENT) {
2046 adapter->linkevent_interrupts++;
cbdc251d
SM
2047 if (slic_link_event_handler(adapter))
2048 adapter->linkevent_interrupts--;
f66626e4
RK
2049 }
2050
2051 if ((isr & ISR_UPC) || (isr & ISR_UPCERR) ||
2052 (isr & ISR_UPCBSY)) {
2053 adapter->upr_interrupts++;
2054 slic_upr_request_complete(adapter, isr);
2055 }
2056 }
2057
2058 if (isr & ISR_RCV) {
2059 adapter->rcv_interrupts++;
2060 slic_rcv_handler(adapter);
2061 }
2062
2063 if (isr & ISR_CMD) {
2064 adapter->xmit_interrupts++;
2065 slic_xmit_complete(adapter);
2066 }
2067}
2068
4d6ea9c3 2069static irqreturn_t slic_interrupt(int irq, void *dev_id)
4d6f6af8 2070{
dd146d21 2071 struct net_device *dev = dev_id;
4d6ea9c3 2072 struct adapter *adapter = netdev_priv(dev);
fdb77775
LS
2073 struct slic_shmemory *sm = &adapter->shmem;
2074 struct slic_shmem_data *sm_data = sm->shmem_data;
4d6ea9c3 2075 u32 isr;
4d6f6af8 2076
fdb77775 2077 if (sm_data->isr) {
c6d6a9a0 2078 slic_write32(adapter, SLIC_REG_ICR, ICR_INT_MASK);
bc894318 2079 slic_flush_write(adapter);
c6d6a9a0 2080
fdb77775
LS
2081 isr = sm_data->isr;
2082 sm_data->isr = 0;
4d6ea9c3
DK
2083 adapter->num_isrs++;
2084 switch (adapter->card->state) {
2085 case CARD_UP:
f66626e4 2086 slic_interrupt_card_up(isr, adapter, dev);
4d6ea9c3 2087 break;
4d6f6af8 2088
4d6ea9c3
DK
2089 case CARD_DOWN:
2090 if ((isr & ISR_UPC) ||
2091 (isr & ISR_UPCERR) || (isr & ISR_UPCBSY)) {
2092 adapter->upr_interrupts++;
2093 slic_upr_request_complete(adapter, isr);
2094 }
2095 break;
4d6ea9c3 2096 }
4d6f6af8 2097
4d6ea9c3
DK
2098 adapter->all_reg_writes += 2;
2099 adapter->isr_reg_writes++;
c6d6a9a0 2100 slic_write32(adapter, SLIC_REG_ISR, 0);
4d6ea9c3
DK
2101 } else {
2102 adapter->false_interrupts++;
4d6f6af8 2103 }
4d6ea9c3 2104 return IRQ_HANDLED;
4d6f6af8
GKH
2105}
2106
4d6ea9c3 2107#define NORMAL_ETHFRAME 0
4d6f6af8 2108
4d6ea9c3
DK
2109static netdev_tx_t slic_xmit_start(struct sk_buff *skb, struct net_device *dev)
2110{
2111 struct sliccard *card;
2112 struct adapter *adapter = netdev_priv(dev);
2113 struct slic_hostcmd *hcmd = NULL;
2114 u32 status = 0;
4d6ea9c3 2115 void *offloadcmd = NULL;
4d6f6af8 2116
4d6ea9c3 2117 card = adapter->card;
4d6ea9c3
DK
2118 if ((adapter->linkstate != LINK_UP) ||
2119 (adapter->state != ADAPT_UP) || (card->state != CARD_UP)) {
2120 status = XMIT_FAIL_LINK_STATE;
2121 goto xmit_fail;
4d6f6af8 2122
4d6ea9c3
DK
2123 } else if (skb->len == 0) {
2124 status = XMIT_FAIL_ZERO_LENGTH;
2125 goto xmit_fail;
4d6f6af8
GKH
2126 }
2127
cbb0920b
PH
2128 hcmd = slic_cmdq_getfree(adapter);
2129 if (!hcmd) {
2130 adapter->xmitq_full = 1;
2131 status = XMIT_FAIL_HOSTCMD_FAIL;
2132 goto xmit_fail;
4d6ea9c3 2133 }
cbb0920b
PH
2134 hcmd->skb = skb;
2135 hcmd->busy = 1;
2136 hcmd->type = SLIC_CMD_DUMB;
2137 slic_xmit_build_request(adapter, hcmd, skb);
9092de6d
DK
2138 dev->stats.tx_packets++;
2139 dev->stats.tx_bytes += skb->len;
4d6f6af8 2140
4d6ea9c3
DK
2141#ifdef DEBUG_DUMP
2142 if (adapter->kill_card) {
2143 struct slic_host64_cmd ihcmd;
4d6f6af8 2144
4d6ea9c3
DK
2145 ihcmd = &hcmd->cmd64;
2146
2147 ihcmd->flags |= 0x40;
2148 adapter->kill_card = 0; /* only do this once */
4d6f6af8 2149 }
4d6ea9c3
DK
2150#endif
2151 if (hcmd->paddrh == 0) {
c6d6a9a0
LS
2152 slic_write32(adapter, SLIC_REG_CBAR, (hcmd->paddrl |
2153 hcmd->cmdsize));
4d6ea9c3 2154 } else {
c6d6a9a0
LS
2155 slic_write64(adapter, SLIC_REG_CBAR64,
2156 hcmd->paddrl | hcmd->cmdsize, hcmd->paddrh);
4d6ea9c3
DK
2157 }
2158xmit_done:
2159 return NETDEV_TX_OK;
2160xmit_fail:
cbb0920b 2161 slic_xmit_fail(adapter, skb, offloadcmd, NORMAL_ETHFRAME, status);
4d6ea9c3 2162 goto xmit_done;
4d6f6af8
GKH
2163}
2164
4d6ea9c3 2165static void slic_adapter_freeresources(struct adapter *adapter)
4d6f6af8 2166{
4d6ea9c3 2167 slic_init_cleanup(adapter);
4d6ea9c3
DK
2168 adapter->error_interrupts = 0;
2169 adapter->rcv_interrupts = 0;
2170 adapter->xmit_interrupts = 0;
2171 adapter->linkevent_interrupts = 0;
2172 adapter->upr_interrupts = 0;
2173 adapter->num_isrs = 0;
2174 adapter->xmit_completes = 0;
2175 adapter->rcv_broadcasts = 0;
2176 adapter->rcv_multicasts = 0;
2177 adapter->rcv_unicasts = 0;
2178}
4d6f6af8 2179
eafe6002
DM
2180static int slic_adapter_allocresources(struct adapter *adapter,
2181 unsigned long *flags)
4d6ea9c3
DK
2182{
2183 if (!adapter->intrregistered) {
2184 int retval;
4d6f6af8 2185
eafe6002 2186 spin_unlock_irqrestore(&slic_global.driver_lock, *flags);
4d6f6af8 2187
4d6ea9c3
DK
2188 retval = request_irq(adapter->netdev->irq,
2189 &slic_interrupt,
2190 IRQF_SHARED,
2191 adapter->netdev->name, adapter->netdev);
4d6f6af8 2192
eafe6002 2193 spin_lock_irqsave(&slic_global.driver_lock, *flags);
4d6ea9c3
DK
2194
2195 if (retval) {
2196 dev_err(&adapter->netdev->dev,
2197 "request_irq (%s) FAILED [%x]\n",
2198 adapter->netdev->name, retval);
2199 return retval;
4d6f6af8 2200 }
4d6ea9c3 2201 adapter->intrregistered = 1;
4d6f6af8 2202 }
d1939786 2203 return 0;
4d6f6af8
GKH
2204}
2205
4d6ea9c3
DK
2206/*
2207 * slic_if_init
2208 *
2209 * Perform initialization of our slic interface.
2210 *
2211 */
eafe6002 2212static int slic_if_init(struct adapter *adapter, unsigned long *flags)
4d6f6af8 2213{
4d6ea9c3
DK
2214 struct sliccard *card = adapter->card;
2215 struct net_device *dev = adapter->netdev;
fdb77775
LS
2216 struct slic_shmemory *sm = &adapter->shmem;
2217 struct slic_shmem_data *sm_data = sm->shmem_data;
4d6ea9c3 2218 int rc;
4d6f6af8 2219
4d6ea9c3
DK
2220 /* adapter should be down at this point */
2221 if (adapter->state != ADAPT_DOWN) {
2222 dev_err(&dev->dev, "%s: adapter->state != ADAPT_DOWN\n",
2223 __func__);
2224 rc = -EIO;
2225 goto err;
4d6f6af8 2226 }
4d6f6af8 2227
4d6ea9c3
DK
2228 adapter->devflags_prev = dev->flags;
2229 adapter->macopts = MAC_DIRECTED;
2230 if (dev->flags) {
2231 if (dev->flags & IFF_BROADCAST)
2232 adapter->macopts |= MAC_BCAST;
2233 if (dev->flags & IFF_PROMISC)
2234 adapter->macopts |= MAC_PROMISC;
2235 if (dev->flags & IFF_ALLMULTI)
2236 adapter->macopts |= MAC_ALLMCAST;
2237 if (dev->flags & IFF_MULTICAST)
2238 adapter->macopts |= MAC_MCAST;
2239 }
eafe6002 2240 rc = slic_adapter_allocresources(adapter, flags);
4d6ea9c3 2241 if (rc) {
eb856202
HM
2242 dev_err(&dev->dev, "slic_adapter_allocresources FAILED %x\n",
2243 rc);
4d6ea9c3
DK
2244 slic_adapter_freeresources(adapter);
2245 goto err;
2246 }
4d6f6af8 2247
4d6ea9c3 2248 if (!adapter->queues_initialized) {
83682cd2
CJB
2249 rc = slic_rspqueue_init(adapter);
2250 if (rc)
4d6ea9c3 2251 goto err;
83682cd2
CJB
2252 rc = slic_cmdq_init(adapter);
2253 if (rc)
4d6ea9c3 2254 goto err;
83682cd2
CJB
2255 rc = slic_rcvqueue_init(adapter);
2256 if (rc)
4d6ea9c3
DK
2257 goto err;
2258 adapter->queues_initialized = 1;
2259 }
4d6f6af8 2260
c6d6a9a0 2261 slic_write32(adapter, SLIC_REG_ICR, ICR_INT_OFF);
bc894318 2262 slic_flush_write(adapter);
4d6ea9c3
DK
2263 mdelay(1);
2264
2265 if (!adapter->isp_initialized) {
eafe6002 2266 unsigned long flags;
740d6c17 2267
eafe6002 2268 spin_lock_irqsave(&adapter->bit64reglock, flags);
c6d6a9a0 2269 slic_write32(adapter, SLIC_REG_ADDR_UPPER,
fdb77775 2270 cpu_to_le32(upper_32_bits(sm->isr_phaddr)));
c6d6a9a0 2271 slic_write32(adapter, SLIC_REG_ISP,
fdb77775 2272 cpu_to_le32(lower_32_bits(sm->isr_phaddr)));
eafe6002 2273 spin_unlock_irqrestore(&adapter->bit64reglock, flags);
fdb77775 2274
4d6ea9c3 2275 adapter->isp_initialized = 1;
4d6f6af8 2276 }
4d6f6af8 2277
4d6ea9c3
DK
2278 adapter->state = ADAPT_UP;
2279 if (!card->loadtimerset) {
7d2b3cf7
AM
2280 setup_timer(&card->loadtimer, &slic_timer_load_check,
2281 (ulong)card);
4d6ea9c3
DK
2282 card->loadtimer.expires =
2283 jiffies + (SLIC_LOADTIMER_PERIOD * HZ);
4d6ea9c3
DK
2284 add_timer(&card->loadtimer);
2285
2286 card->loadtimerset = 1;
2287 }
2288
2289 if (!adapter->pingtimerset) {
7d2b3cf7 2290 setup_timer(&adapter->pingtimer, &slic_timer_ping, (ulong)dev);
4d6ea9c3
DK
2291 adapter->pingtimer.expires =
2292 jiffies + (PING_TIMER_INTERVAL * HZ);
4d6ea9c3
DK
2293 add_timer(&adapter->pingtimer);
2294 adapter->pingtimerset = 1;
2295 adapter->card->pingstatus = ISR_PINGMASK;
2296 }
2297
2298 /*
2299 * clear any pending events, then enable interrupts
2300 */
fdb77775 2301 sm_data->isr = 0;
c6d6a9a0
LS
2302 slic_write32(adapter, SLIC_REG_ISR, 0);
2303 slic_write32(adapter, SLIC_REG_ICR, ICR_INT_ON);
4d6ea9c3
DK
2304
2305 slic_link_config(adapter, LINK_AUTOSPEED, LINK_AUTOD);
bc894318 2306 slic_flush_write(adapter);
c6d6a9a0 2307
de4772ae
SM
2308 rc = slic_link_event_handler(adapter);
2309 if (rc) {
2310 /* disable interrupts then clear pending events */
c6d6a9a0
LS
2311 slic_write32(adapter, SLIC_REG_ICR, ICR_INT_OFF);
2312 slic_write32(adapter, SLIC_REG_ISR, 0);
bc894318 2313 slic_flush_write(adapter);
c6d6a9a0 2314
de4772ae
SM
2315 if (adapter->pingtimerset) {
2316 del_timer(&adapter->pingtimer);
2317 adapter->pingtimerset = 0;
2318 }
2319 if (card->loadtimerset) {
2320 del_timer(&card->loadtimer);
2321 card->loadtimerset = 0;
2322 }
2323 adapter->state = ADAPT_DOWN;
2324 slic_adapter_freeresources(adapter);
2325 }
4d6f6af8 2326
4d6ea9c3
DK
2327err:
2328 return rc;
4d6f6af8
GKH
2329}
2330
4d6ea9c3 2331static int slic_entry_open(struct net_device *dev)
4d6f6af8 2332{
4d6ea9c3
DK
2333 struct adapter *adapter = netdev_priv(dev);
2334 struct sliccard *card = adapter->card;
eafe6002 2335 unsigned long flags;
4d6ea9c3 2336 int status;
4d6f6af8 2337
da169754 2338 netif_carrier_off(dev);
4d6f6af8 2339
eafe6002 2340 spin_lock_irqsave(&slic_global.driver_lock, flags);
4d6ea9c3
DK
2341 if (!adapter->activated) {
2342 card->adapters_activated++;
2343 slic_global.num_slic_ports_active++;
2344 adapter->activated = 1;
2345 }
eafe6002 2346 status = slic_if_init(adapter, &flags);
4d6f6af8 2347
4d6ea9c3
DK
2348 if (status != 0) {
2349 if (adapter->activated) {
2350 card->adapters_activated--;
2351 slic_global.num_slic_ports_active--;
2352 adapter->activated = 0;
4d6f6af8 2353 }
71329965 2354 goto spin_unlock;
4d6ea9c3
DK
2355 }
2356 if (!card->master)
2357 card->master = adapter;
2358
71329965 2359spin_unlock:
eafe6002 2360 spin_unlock_irqrestore(&slic_global.driver_lock, flags);
a5e32e74
LS
2361
2362 netif_start_queue(adapter->netdev);
2363
71329965 2364 return status;
4d6f6af8
GKH
2365}
2366
4d6ea9c3 2367static void slic_card_cleanup(struct sliccard *card)
4d6f6af8 2368{
4d6ea9c3
DK
2369 if (card->loadtimerset) {
2370 card->loadtimerset = 0;
161737a6 2371 del_timer_sync(&card->loadtimer);
4d6ea9c3 2372 }
4d6f6af8 2373
4d6ea9c3 2374 kfree(card);
4d6f6af8
GKH
2375}
2376
ecb4f387 2377static void slic_entry_remove(struct pci_dev *pcidev)
4d6f6af8 2378{
4d6ea9c3 2379 struct net_device *dev = pci_get_drvdata(pcidev);
4d6ea9c3
DK
2380 struct adapter *adapter = netdev_priv(dev);
2381 struct sliccard *card;
2382 struct mcast_address *mcaddr, *mlist;
4d6f6af8 2383
dedabbbc
DM
2384 unregister_netdev(dev);
2385
4d6ea9c3 2386 slic_adapter_freeresources(adapter);
c6d6a9a0 2387 iounmap(adapter->regs);
4d6ea9c3 2388
4d6ea9c3
DK
2389 /* free multicast addresses */
2390 mlist = adapter->mcastaddrs;
2391 while (mlist) {
2392 mcaddr = mlist;
2393 mlist = mlist->next;
2394 kfree(mcaddr);
4d6f6af8 2395 }
4d6ea9c3 2396 card = adapter->card;
4d6ea9c3
DK
2397 card->adapters_allocated--;
2398 adapter->allocated = 0;
2399 if (!card->adapters_allocated) {
2400 struct sliccard *curr_card = slic_global.slic_card;
0d0e9d9e 2401
4d6ea9c3
DK
2402 if (curr_card == card) {
2403 slic_global.slic_card = card->next;
2404 } else {
2405 while (curr_card->next != card)
2406 curr_card = curr_card->next;
4d6ea9c3
DK
2407 curr_card->next = card->next;
2408 }
4d6ea9c3
DK
2409 slic_global.num_slic_cards--;
2410 slic_card_cleanup(card);
4d6f6af8 2411 }
20caa14c 2412 free_netdev(dev);
4d6ea9c3 2413 pci_release_regions(pcidev);
d99b5ac6 2414 pci_disable_device(pcidev);
4d6f6af8
GKH
2415}
2416
4d6ea9c3 2417static int slic_entry_halt(struct net_device *dev)
4d6f6af8 2418{
4d6ea9c3
DK
2419 struct adapter *adapter = netdev_priv(dev);
2420 struct sliccard *card = adapter->card;
eafe6002 2421 unsigned long flags;
4d6f6af8 2422
eafe6002 2423 spin_lock_irqsave(&slic_global.driver_lock, flags);
4d6ea9c3
DK
2424 netif_stop_queue(adapter->netdev);
2425 adapter->state = ADAPT_DOWN;
2426 adapter->linkstate = LINK_DOWN;
2427 adapter->upr_list = NULL;
2428 adapter->upr_busy = 0;
2429 adapter->devflags_prev = 0;
c6d6a9a0 2430 slic_write32(adapter, SLIC_REG_ICR, ICR_INT_OFF);
4d6ea9c3
DK
2431 adapter->all_reg_writes++;
2432 adapter->icr_reg_writes++;
2433 slic_config_clear(adapter);
2434 if (adapter->activated) {
2435 card->adapters_activated--;
2436 slic_global.num_slic_ports_active--;
2437 adapter->activated = 0;
2438 }
2439#ifdef AUTOMATIC_RESET
c6d6a9a0 2440 slic_write32(adapter, SLIC_REG_RESET_IFACE, 0);
4d6ea9c3 2441#endif
bc894318 2442 slic_flush_write(adapter);
c6d6a9a0 2443
4d6ea9c3
DK
2444 /*
2445 * Reset the adapter's cmd queues
2446 */
2447 slic_cmdq_reset(adapter);
4d6f6af8 2448
4d6ea9c3
DK
2449#ifdef AUTOMATIC_RESET
2450 if (!card->adapters_activated)
2451 slic_card_init(card, adapter);
2452#endif
4d6f6af8 2453
eafe6002 2454 spin_unlock_irqrestore(&slic_global.driver_lock, flags);
da169754
LS
2455
2456 netif_carrier_off(dev);
2457
4d6ea9c3
DK
2458 return 0;
2459}
4d6f6af8 2460
4d6ea9c3
DK
2461static struct net_device_stats *slic_get_stats(struct net_device *dev)
2462{
2463 struct adapter *adapter = netdev_priv(dev);
4d6f6af8 2464
4d6ea9c3
DK
2465 dev->stats.collisions = adapter->slic_stats.iface.xmit_collisions;
2466 dev->stats.rx_errors = adapter->slic_stats.iface.rcv_errors;
2467 dev->stats.tx_errors = adapter->slic_stats.iface.xmt_errors;
2468 dev->stats.rx_missed_errors = adapter->slic_stats.iface.rcv_discards;
2469 dev->stats.tx_heartbeat_errors = 0;
2470 dev->stats.tx_aborted_errors = 0;
2471 dev->stats.tx_window_errors = 0;
2472 dev->stats.tx_fifo_errors = 0;
2473 dev->stats.rx_frame_errors = 0;
2474 dev->stats.rx_length_errors = 0;
2475
2476 return &dev->stats;
4d6f6af8
GKH
2477}
2478
4d6ea9c3 2479static int slic_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4d6f6af8 2480{
4d6ea9c3
DK
2481 struct adapter *adapter = netdev_priv(dev);
2482 struct ethtool_cmd edata;
2483 struct ethtool_cmd ecmd;
2484 u32 data[7];
2485 u32 intagg;
4d6f6af8 2486
4d6ea9c3
DK
2487 switch (cmd) {
2488 case SIOCSLICSETINTAGG:
2489 if (copy_from_user(data, rq->ifr_data, 28))
2490 return -EFAULT;
2491 intagg = data[0];
eb856202
HM
2492 dev_err(&dev->dev, "set interrupt aggregation to %d\n",
2493 intagg);
4d6ea9c3
DK
2494 slic_intagg_set(adapter, intagg);
2495 return 0;
4d6f6af8 2496
4d6ea9c3 2497 case SIOCETHTOOL:
4d6ea9c3
DK
2498 if (copy_from_user(&ecmd, rq->ifr_data, sizeof(ecmd)))
2499 return -EFAULT;
4d6f6af8 2500
4d6ea9c3 2501 if (ecmd.cmd == ETHTOOL_GSET) {
986d7584 2502 memset(&edata, 0, sizeof(edata));
4d6ea9c3
DK
2503 edata.supported = (SUPPORTED_10baseT_Half |
2504 SUPPORTED_10baseT_Full |
2505 SUPPORTED_100baseT_Half |
2506 SUPPORTED_100baseT_Full |
2507 SUPPORTED_Autoneg | SUPPORTED_MII);
2508 edata.port = PORT_MII;
2509 edata.transceiver = XCVR_INTERNAL;
2510 edata.phy_address = 0;
2511 if (adapter->linkspeed == LINK_100MB)
2512 edata.speed = SPEED_100;
2513 else if (adapter->linkspeed == LINK_10MB)
2514 edata.speed = SPEED_10;
2515 else
2516 edata.speed = 0;
4d6f6af8 2517
4d6ea9c3
DK
2518 if (adapter->linkduplex == LINK_FULLD)
2519 edata.duplex = DUPLEX_FULL;
2520 else
2521 edata.duplex = DUPLEX_HALF;
4d6f6af8 2522
4d6ea9c3
DK
2523 edata.autoneg = AUTONEG_ENABLE;
2524 edata.maxtxpkt = 1;
2525 edata.maxrxpkt = 1;
2526 if (copy_to_user(rq->ifr_data, &edata, sizeof(edata)))
2527 return -EFAULT;
4d6f6af8 2528
4d6ea9c3
DK
2529 } else if (ecmd.cmd == ETHTOOL_SSET) {
2530 if (!capable(CAP_NET_ADMIN))
2531 return -EPERM;
4d6f6af8 2532
4d6ea9c3
DK
2533 if (adapter->linkspeed == LINK_100MB)
2534 edata.speed = SPEED_100;
2535 else if (adapter->linkspeed == LINK_10MB)
2536 edata.speed = SPEED_10;
2537 else
2538 edata.speed = 0;
2539
2540 if (adapter->linkduplex == LINK_FULLD)
2541 edata.duplex = DUPLEX_FULL;
2542 else
2543 edata.duplex = DUPLEX_HALF;
2544
2545 edata.autoneg = AUTONEG_ENABLE;
2546 edata.maxtxpkt = 1;
2547 edata.maxrxpkt = 1;
2548 if ((ecmd.speed != edata.speed) ||
2549 (ecmd.duplex != edata.duplex)) {
2550 u32 speed;
2551 u32 duplex;
2552
2553 if (ecmd.speed == SPEED_10)
2554 speed = 0;
2555 else
2556 speed = PCR_SPEED_100;
2557 if (ecmd.duplex == DUPLEX_FULL)
2558 duplex = PCR_DUPLEX_FULL;
2559 else
2560 duplex = 0;
2561 slic_link_config(adapter, speed, duplex);
4b8645d6
SM
2562 if (slic_link_event_handler(adapter))
2563 return -EFAULT;
4d6ea9c3
DK
2564 }
2565 }
2566 return 0;
2567 default:
2568 return -EOPNOTSUPP;
2569 }
4d6f6af8
GKH
2570}
2571
4d6ea9c3 2572static void slic_config_pci(struct pci_dev *pcidev)
4d6f6af8 2573{
4d6ea9c3
DK
2574 u16 pci_command;
2575 u16 new_command;
4d6f6af8 2576
4d6ea9c3
DK
2577 pci_read_config_word(pcidev, PCI_COMMAND, &pci_command);
2578
2579 new_command = pci_command | PCI_COMMAND_MASTER
2580 | PCI_COMMAND_MEMORY
2581 | PCI_COMMAND_INVALIDATE
2582 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
2583 if (pci_command != new_command)
2584 pci_write_config_word(pcidev, PCI_COMMAND, new_command);
4d6f6af8
GKH
2585}
2586
4d6ea9c3 2587static int slic_card_init(struct sliccard *card, struct adapter *adapter)
4d6f6af8 2588{
fdb77775
LS
2589 struct slic_shmemory *sm = &adapter->shmem;
2590 struct slic_shmem_data *sm_data = sm->shmem_data;
4d6ea9c3
DK
2591 struct slic_eeprom *peeprom;
2592 struct oslic_eeprom *pOeeprom;
2593 dma_addr_t phys_config;
2594 u32 phys_configh;
2595 u32 phys_configl;
2596 u32 i = 0;
4d6ea9c3
DK
2597 int status;
2598 uint macaddrs = card->card_size;
2599 ushort eecodesize;
2600 ushort dramsize;
2601 ushort ee_chksum;
2602 ushort calc_chksum;
2603 struct slic_config_mac *pmac;
2604 unsigned char fruformat;
2605 unsigned char oemfruformat;
2606 struct atk_fru *patkfru;
2607 union oemfru *poemfru;
eafe6002 2608 unsigned long flags;
4d6f6af8 2609
4d6ea9c3
DK
2610 /* Reset everything except PCI configuration space */
2611 slic_soft_reset(adapter);
2612
2613 /* Download the microcode */
2614 status = slic_card_download(adapter);
811e843d 2615 if (status)
4d6ea9c3 2616 return status;
4d6f6af8 2617
4d6ea9c3
DK
2618 if (!card->config_set) {
2619 peeprom = pci_alloc_consistent(adapter->pcidev,
2620 sizeof(struct slic_eeprom),
2621 &phys_config);
4d6f6af8 2622
4d6ea9c3
DK
2623 phys_configl = SLIC_GET_ADDR_LOW(phys_config);
2624 phys_configh = SLIC_GET_ADDR_HIGH(phys_config);
4d6f6af8 2625
4d6ea9c3
DK
2626 if (!peeprom) {
2627 dev_err(&adapter->pcidev->dev,
811e843d 2628 "Failed to allocate DMA memory for EEPROM.\n");
4d6ea9c3 2629 return -ENOMEM;
4d6f6af8 2630 }
351e836f
VH
2631
2632 memset(peeprom, 0, sizeof(struct slic_eeprom));
2633
c6d6a9a0 2634 slic_write32(adapter, SLIC_REG_ICR, ICR_INT_OFF);
bc894318 2635 slic_flush_write(adapter);
4d6ea9c3 2636 mdelay(1);
4d6f6af8 2637
eafe6002 2638 spin_lock_irqsave(&adapter->bit64reglock, flags);
c6d6a9a0 2639 slic_write32(adapter, SLIC_REG_ADDR_UPPER,
fdb77775 2640 cpu_to_le32(upper_32_bits(sm->isr_phaddr)));
c6d6a9a0 2641 slic_write32(adapter, SLIC_REG_ISP,
fdb77775 2642 cpu_to_le32(lower_32_bits(sm->isr_phaddr)));
eafe6002 2643 spin_unlock_irqrestore(&adapter->bit64reglock, flags);
4d6f6af8 2644
47a401a8
DM
2645 status = slic_config_get(adapter, phys_configl, phys_configh);
2646 if (status) {
2647 dev_err(&adapter->pcidev->dev,
2648 "Failed to fetch config data from device.\n");
2649 goto card_init_err;
2650 }
4d6f6af8 2651
4d6ea9c3 2652 for (;;) {
fdb77775
LS
2653 if (sm_data->isr) {
2654 if (sm_data->isr & ISR_UPC) {
2655 sm_data->isr = 0;
c6d6a9a0
LS
2656 slic_write64(adapter, SLIC_REG_ISP, 0,
2657 0);
2658 slic_write32(adapter, SLIC_REG_ISR, 0);
bc894318 2659 slic_flush_write(adapter);
4d6ea9c3
DK
2660
2661 slic_upr_request_complete(adapter, 0);
2662 break;
4d6ea9c3 2663 }
351e836f 2664
fdb77775 2665 sm_data->isr = 0;
c6d6a9a0 2666 slic_write32(adapter, SLIC_REG_ISR, 0);
bc894318 2667 slic_flush_write(adapter);
4d6f6af8 2668 } else {
4d6ea9c3
DK
2669 mdelay(1);
2670 i++;
2671 if (i > 5000) {
2672 dev_err(&adapter->pcidev->dev,
811e843d 2673 "Fetch of config data timed out.\n");
c6d6a9a0
LS
2674 slic_write64(adapter, SLIC_REG_ISP,
2675 0, 0);
bc894318 2676 slic_flush_write(adapter);
c6d6a9a0 2677
47a401a8
DM
2678 status = -EINVAL;
2679 goto card_init_err;
4d6ea9c3 2680 }
4d6f6af8 2681 }
4d6ea9c3
DK
2682 }
2683
2684 switch (adapter->devid) {
2685 /* Oasis card */
2686 case SLIC_2GB_DEVICE_ID:
2687 /* extract EEPROM data and pointers to EEPROM data */
8610cbc5 2688 pOeeprom = (struct oslic_eeprom *)peeprom;
4d6ea9c3
DK
2689 eecodesize = pOeeprom->EecodeSize;
2690 dramsize = pOeeprom->DramSize;
2691 pmac = pOeeprom->MacInfo;
2692 fruformat = pOeeprom->FruFormat;
2693 patkfru = &pOeeprom->AtkFru;
2694 oemfruformat = pOeeprom->OemFruFormat;
2695 poemfru = &pOeeprom->OemFru;
2696 macaddrs = 2;
f773a834
AG
2697 /*
2698 * Minor kludge for Oasis card
2699 * get 2 MAC addresses from the
2700 * EEPROM to ensure that function 1
2701 * gets the Port 1 MAC address
2702 */
4d6ea9c3
DK
2703 break;
2704 default:
2705 /* extract EEPROM data and pointers to EEPROM data */
2706 eecodesize = peeprom->EecodeSize;
2707 dramsize = peeprom->DramSize;
2708 pmac = peeprom->u2.mac.MacInfo;
2709 fruformat = peeprom->FruFormat;
2710 patkfru = &peeprom->AtkFru;
2711 oemfruformat = peeprom->OemFruFormat;
2712 poemfru = &peeprom->OemFru;
4d6f6af8
GKH
2713 break;
2714 }
4d6f6af8 2715
4d6ea9c3
DK
2716 card->config.EepromValid = false;
2717
2718 /* see if the EEPROM is valid by checking it's checksum */
2719 if ((eecodesize <= MAX_EECODE_SIZE) &&
2720 (eecodesize >= MIN_EECODE_SIZE)) {
2721
2722 ee_chksum =
8610cbc5 2723 *(u16 *)((char *)peeprom + (eecodesize - 2));
4d6ea9c3 2724 /*
f773a834
AG
2725 * calculate the EEPROM checksum
2726 */
55b62cdf
DM
2727 calc_chksum = slic_eeprom_cksum(peeprom,
2728 eecodesize - 2);
4d6ea9c3 2729 /*
f773a834
AG
2730 * if the ucdoe chksum flag bit worked,
2731 * we wouldn't need this
2732 */
4d6ea9c3
DK
2733 if (ee_chksum == calc_chksum)
2734 card->config.EepromValid = true;
2735 }
2736 /* copy in the DRAM size */
2737 card->config.DramSize = dramsize;
2738
2739 /* copy in the MAC address(es) */
2740 for (i = 0; i < macaddrs; i++) {
2741 memcpy(&card->config.MacInfo[i],
2742 &pmac[i], sizeof(struct slic_config_mac));
2743 }
4d6f6af8 2744
4d6ea9c3
DK
2745 /* copy the Alacritech FRU information */
2746 card->config.FruFormat = fruformat;
2747 memcpy(&card->config.AtkFru, patkfru,
2748 sizeof(struct atk_fru));
e9eff9d6 2749
4d6ea9c3
DK
2750 pci_free_consistent(adapter->pcidev,
2751 sizeof(struct slic_eeprom),
2752 peeprom, phys_config);
4d6f6af8 2753
28277a55 2754 if (!card->config.EepromValid) {
c6d6a9a0 2755 slic_write64(adapter, SLIC_REG_ISP, 0, 0);
bc894318 2756 slic_flush_write(adapter);
811e843d 2757 dev_err(&adapter->pcidev->dev, "EEPROM invalid.\n");
4d6ea9c3
DK
2758 return -EINVAL;
2759 }
4d6f6af8 2760
4d6ea9c3 2761 card->config_set = 1;
4d6f6af8 2762 }
4d6ea9c3 2763
811e843d
DM
2764 status = slic_card_download_gbrcv(adapter);
2765 if (status)
2766 return status;
4d6ea9c3
DK
2767
2768 if (slic_global.dynamic_intagg)
2769 slic_intagg_set(adapter, 0);
4d6f6af8 2770 else
c8e9b92d 2771 slic_intagg_set(adapter, adapter->intagg_delay);
4d6f6af8 2772
4d6ea9c3
DK
2773 /*
2774 * Initialize ping status to "ok"
2775 */
2776 card->pingstatus = ISR_PINGMASK;
4d6f6af8 2777
4d6ea9c3
DK
2778 /*
2779 * Lastly, mark our card state as up and return success
2780 */
2781 card->state = CARD_UP;
2782 card->reset_in_progress = 0;
4d6f6af8 2783
4d6ea9c3 2784 return 0;
47a401a8
DM
2785
2786card_init_err:
2787 pci_free_consistent(adapter->pcidev, sizeof(struct slic_eeprom),
2788 peeprom, phys_config);
2789 return status;
4d6ea9c3
DK
2790}
2791
c8e9b92d
KW
2792static int slic_get_coalesce(struct net_device *dev,
2793 struct ethtool_coalesce *coalesce)
2794{
2795 struct adapter *adapter = netdev_priv(dev);
2796
2797 adapter->intagg_delay = coalesce->rx_coalesce_usecs;
2798 adapter->dynamic_intagg = coalesce->use_adaptive_rx_coalesce;
2799 return 0;
2800}
2801
2802static int slic_set_coalesce(struct net_device *dev,
2803 struct ethtool_coalesce *coalesce)
2804{
2805 struct adapter *adapter = netdev_priv(dev);
2806
2807 coalesce->rx_coalesce_usecs = adapter->intagg_delay;
2808 coalesce->use_adaptive_rx_coalesce = adapter->dynamic_intagg;
2809 return 0;
2810}
2811
4d6ea9c3
DK
2812static void slic_init_driver(void)
2813{
2814 if (slic_first_init) {
2815 slic_first_init = 0;
eafe6002 2816 spin_lock_init(&slic_global.driver_lock);
4d6f6af8 2817 }
4d6ea9c3 2818}
4d6f6af8 2819
7ed4eb51
LS
2820static int slic_init_adapter(struct net_device *netdev,
2821 struct pci_dev *pcidev,
2822 const struct pci_device_id *pci_tbl_entry,
2823 void __iomem *memaddr, int chip_idx)
4d6ea9c3
DK
2824{
2825 ushort index;
2826 struct slic_handle *pslic_handle;
2827 struct adapter *adapter = netdev_priv(netdev);
fdb77775
LS
2828 struct slic_shmemory *sm = &adapter->shmem;
2829 struct slic_shmem_data *sm_data;
2830 dma_addr_t phaddr;
4d6f6af8 2831
4d6ea9c3
DK
2832/* adapter->pcidev = pcidev;*/
2833 adapter->vendid = pci_tbl_entry->vendor;
2834 adapter->devid = pci_tbl_entry->device;
2835 adapter->subsysid = pci_tbl_entry->subdevice;
2836 adapter->busnumber = pcidev->bus->number;
2837 adapter->slotnumber = ((pcidev->devfn >> 3) & 0x1F);
2838 adapter->functionnumber = (pcidev->devfn & 0x7);
b200da67 2839 adapter->regs = memaddr;
4d6ea9c3 2840 adapter->irq = pcidev->irq;
4d6ea9c3 2841 adapter->chipid = chip_idx;
3e0a66d0 2842 adapter->port = 0;
4d6ea9c3 2843 adapter->cardindex = adapter->port;
eafe6002
DM
2844 spin_lock_init(&adapter->upr_lock);
2845 spin_lock_init(&adapter->bit64reglock);
2846 spin_lock_init(&adapter->adapter_lock);
2847 spin_lock_init(&adapter->reset_lock);
2848 spin_lock_init(&adapter->handle_lock);
4d6f6af8 2849
4d6ea9c3
DK
2850 adapter->card_size = 1;
2851 /*
f773a834
AG
2852 * Initialize slic_handle array
2853 */
4d6ea9c3 2854 /*
f773a834
AG
2855 * Start with 1. 0 is an invalid host handle.
2856 */
4d6ea9c3
DK
2857 for (index = 1, pslic_handle = &adapter->slic_handles[1];
2858 index < SLIC_CMDQ_MAXCMDS; index++, pslic_handle++) {
2859
2860 pslic_handle->token.handle_index = index;
2861 pslic_handle->type = SLIC_HANDLE_FREE;
2862 pslic_handle->next = adapter->pfree_slic_handles;
2863 adapter->pfree_slic_handles = pslic_handle;
4d6f6af8 2864 }
fdb77775
LS
2865 sm_data = pci_zalloc_consistent(adapter->pcidev, sizeof(*sm_data),
2866 &phaddr);
2867 if (!sm_data)
7ed4eb51
LS
2868 return -ENOMEM;
2869
fdb77775
LS
2870 sm->shmem_data = sm_data;
2871 sm->isr_phaddr = phaddr;
2872 sm->lnkstatus_phaddr = phaddr + offsetof(struct slic_shmem_data,
2873 lnkstatus);
2874 sm->stats_phaddr = phaddr + offsetof(struct slic_shmem_data, stats);
2875
7ed4eb51 2876 return 0;
4d6ea9c3 2877}
4d6f6af8 2878
4d6ea9c3
DK
2879static const struct net_device_ops slic_netdev_ops = {
2880 .ndo_open = slic_entry_open,
2881 .ndo_stop = slic_entry_halt,
2882 .ndo_start_xmit = slic_xmit_start,
2883 .ndo_do_ioctl = slic_ioctl,
2884 .ndo_set_mac_address = slic_mac_set_address,
2885 .ndo_get_stats = slic_get_stats,
afc4b13d 2886 .ndo_set_rx_mode = slic_mcast_set_list,
4d6ea9c3
DK
2887 .ndo_validate_addr = eth_validate_addr,
2888 .ndo_change_mtu = eth_change_mtu,
2889};
4d6f6af8 2890
4d6ea9c3
DK
2891static u32 slic_card_locate(struct adapter *adapter)
2892{
2893 struct sliccard *card = slic_global.slic_card;
2894 struct physcard *physcard = slic_global.phys_card;
2895 ushort card_hostid;
4d6ea9c3 2896 uint i;
4d6f6af8 2897
c6d6a9a0 2898 card_hostid = slic_read32(adapter, SLIC_REG_HOSTID);
4d6f6af8 2899
4d6ea9c3
DK
2900 /* Initialize a new card structure if need be */
2901 if (card_hostid == SLIC_HOSTID_DEFAULT) {
e4a34826 2902 card = kzalloc(sizeof(*card), GFP_KERNEL);
2d5f6fec 2903 if (!card)
4d6ea9c3
DK
2904 return -ENOMEM;
2905
2906 card->next = slic_global.slic_card;
2907 slic_global.slic_card = card;
2908 card->busnumber = adapter->busnumber;
2909 card->slotnumber = adapter->slotnumber;
2910
2911 /* Find an available cardnum */
2912 for (i = 0; i < SLIC_MAX_CARDS; i++) {
2913 if (slic_global.cardnuminuse[i] == 0) {
2914 slic_global.cardnuminuse[i] = 1;
2915 card->cardnum = i;
2916 break;
2917 }
2918 }
2919 slic_global.num_slic_cards++;
4d6ea9c3
DK
2920 } else {
2921 /* Card exists, find the card this adapter belongs to */
2922 while (card) {
2923 if (card->cardnum == card_hostid)
2924 break;
2925 card = card->next;
2926 }
2927 }
2928
4d6ea9c3
DK
2929 if (!card)
2930 return -ENXIO;
2931 /* Put the adapter in the card's adapter list */
4d6ea9c3
DK
2932 if (!card->adapter[adapter->port]) {
2933 card->adapter[adapter->port] = adapter;
2934 adapter->card = card;
2935 }
2936
2937 card->card_size = 1; /* one port per *logical* card */
2938
2939 while (physcard) {
2940 for (i = 0; i < SLIC_MAX_PORTS; i++) {
20d403e8 2941 if (physcard->adapter[i])
4d6ea9c3
DK
2942 break;
2943 }
20d403e8
PH
2944 if (i == SLIC_MAX_PORTS)
2945 break;
2946
4d6ea9c3
DK
2947 if (physcard->adapter[i]->slotnumber == adapter->slotnumber)
2948 break;
2949 physcard = physcard->next;
2950 }
2951 if (!physcard) {
2952 /* no structure allocated for this physical card yet */
4374849e 2953 physcard = kzalloc(sizeof(*physcard), GFP_ATOMIC);
34ec83f4
DN
2954 if (!physcard) {
2955 if (card_hostid == SLIC_HOSTID_DEFAULT)
2956 kfree(card);
0608882d 2957 return -ENOMEM;
34ec83f4 2958 }
4d6ea9c3
DK
2959
2960 physcard->next = slic_global.phys_card;
2961 slic_global.phys_card = physcard;
2962 physcard->adapters_allocd = 1;
2963 } else {
2964 physcard->adapters_allocd++;
2965 }
2966 /* Note - this is ZERO relative */
2967 adapter->physport = physcard->adapters_allocd - 1;
2968
4d6ea9c3
DK
2969 physcard->adapter[adapter->physport] = adapter;
2970 adapter->physcard = physcard;
4d6f6af8
GKH
2971
2972 return 0;
2973}
4d6f6af8 2974
a0c2feb1 2975static int slic_entry_probe(struct pci_dev *pcidev,
4d6ea9c3 2976 const struct pci_device_id *pci_tbl_entry)
4d6f6af8 2977{
4d6ea9c3
DK
2978 static int cards_found;
2979 static int did_version;
2980 int err = -ENODEV;
2981 struct net_device *netdev;
2982 struct adapter *adapter;
2983 void __iomem *memmapped_ioaddr = NULL;
4d6ea9c3
DK
2984 ulong mmio_start = 0;
2985 ulong mmio_len = 0;
2986 struct sliccard *card = NULL;
2987 int pci_using_dac = 0;
4d6f6af8 2988
4d6ea9c3 2989 err = pci_enable_device(pcidev);
4d6f6af8 2990
4d6ea9c3
DK
2991 if (err)
2992 return err;
4d6f6af8 2993
04cc3c8a
DM
2994 if (did_version++ == 0) {
2995 dev_info(&pcidev->dev, "%s\n", slic_banner);
2996 dev_info(&pcidev->dev, "%s\n", slic_proc_version);
4d6ea9c3 2997 }
4d6f6af8 2998
4d6ea9c3
DK
2999 if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
3000 pci_using_dac = 1;
1154eb51
WY
3001 err = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
3002 if (err) {
79b0ae8d 3003 dev_err(&pcidev->dev, "unable to obtain 64-bit DMA for consistent allocations\n");
4d6ea9c3
DK
3004 goto err_out_disable_pci;
3005 }
1154eb51
WY
3006 } else {
3007 err = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
3008 if (err) {
3009 dev_err(&pcidev->dev, "no usable DMA configuration\n");
3010 goto err_out_disable_pci;
3011 }
4d6ea9c3
DK
3012 pci_using_dac = 0;
3013 pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
4d6ea9c3 3014 }
4d6f6af8 3015
4d6ea9c3
DK
3016 err = pci_request_regions(pcidev, DRV_NAME);
3017 if (err) {
3018 dev_err(&pcidev->dev, "can't obtain PCI resources\n");
3019 goto err_out_disable_pci;
3020 }
4d6f6af8 3021
4d6ea9c3 3022 pci_set_master(pcidev);
4d6f6af8 3023
4d6ea9c3
DK
3024 netdev = alloc_etherdev(sizeof(struct adapter));
3025 if (!netdev) {
3026 err = -ENOMEM;
3027 goto err_out_exit_slic_probe;
4d6f6af8 3028 }
4d6f6af8 3029
c8e9b92d 3030 netdev->ethtool_ops = &slic_ethtool_ops;
4d6ea9c3 3031 SET_NETDEV_DEV(netdev, &pcidev->dev);
4d6f6af8 3032
4d6ea9c3
DK
3033 pci_set_drvdata(pcidev, netdev);
3034 adapter = netdev_priv(netdev);
3035 adapter->netdev = netdev;
3036 adapter->pcidev = pcidev;
c8e9b92d 3037 slic_global.dynamic_intagg = adapter->dynamic_intagg;
4d6ea9c3
DK
3038 if (pci_using_dac)
3039 netdev->features |= NETIF_F_HIGHDMA;
4d6f6af8 3040
4d6ea9c3
DK
3041 mmio_start = pci_resource_start(pcidev, 0);
3042 mmio_len = pci_resource_len(pcidev, 0);
3043
6d5f2ea7 3044 memmapped_ioaddr = ioremap_nocache(mmio_start, mmio_len);
4d6ea9c3
DK
3045 if (!memmapped_ioaddr) {
3046 dev_err(&pcidev->dev, "cannot remap MMIO region %lx @ %lx\n",
3047 mmio_len, mmio_start);
1154eb51 3048 err = -ENOMEM;
4d6ea9c3 3049 goto err_out_free_netdev;
4d6f6af8 3050 }
4d6ea9c3
DK
3051
3052 slic_config_pci(pcidev);
3053
3054 slic_init_driver();
3055
7ed4eb51
LS
3056 err = slic_init_adapter(netdev, pcidev, pci_tbl_entry, memmapped_ioaddr,
3057 cards_found);
3058 if (err) {
3059 dev_err(&pcidev->dev, "failed to init adapter: %i\n", err);
3060 goto err_out_unmap;
3061 }
4d6ea9c3 3062
1154eb51
WY
3063 err = slic_card_locate(adapter);
3064 if (err) {
4d6ea9c3 3065 dev_err(&pcidev->dev, "cannot locate card\n");
7ed4eb51 3066 goto err_clean_init;
4d6f6af8 3067 }
4d6ea9c3
DK
3068
3069 card = adapter->card;
3070
3071 if (!adapter->allocated) {
3072 card->adapters_allocated++;
3073 adapter->allocated = 1;
4d6f6af8 3074 }
4d6f6af8 3075
65bc0aaa
DM
3076 err = slic_card_init(card, adapter);
3077 if (err)
7ed4eb51 3078 goto err_clean_init;
4d6f6af8 3079
65bc0aaa 3080 slic_adapter_set_hwaddr(adapter);
4d6f6af8 3081
8610cbc5 3082 netdev->base_addr = (unsigned long)memmapped_ioaddr;
4d6ea9c3
DK
3083 netdev->irq = adapter->irq;
3084 netdev->netdev_ops = &slic_netdev_ops;
4d6f6af8 3085
da169754
LS
3086 netif_carrier_off(netdev);
3087
4d6ea9c3
DK
3088 strcpy(netdev->name, "eth%d");
3089 err = register_netdev(netdev);
3090 if (err) {
3091 dev_err(&pcidev->dev, "Cannot register net device, aborting.\n");
7ed4eb51 3092 goto err_clean_init;
4d6f6af8 3093 }
4d6f6af8 3094
4d6ea9c3
DK
3095 cards_found++;
3096
65bc0aaa 3097 return 0;
4d6ea9c3 3098
7ed4eb51
LS
3099err_clean_init:
3100 slic_init_cleanup(adapter);
4d6ea9c3
DK
3101err_out_unmap:
3102 iounmap(memmapped_ioaddr);
4d6ea9c3
DK
3103err_out_free_netdev:
3104 free_netdev(netdev);
3105err_out_exit_slic_probe:
3106 pci_release_regions(pcidev);
3107err_out_disable_pci:
3108 pci_disable_device(pcidev);
3109 return err;
3110}
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3111
3112static struct pci_driver slic_driver = {
3113 .name = DRV_NAME,
3114 .id_table = slic_pci_tbl,
3115 .probe = slic_entry_probe,
2e0d79c5 3116 .remove = slic_entry_remove,
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3117};
3118
3119static int __init slic_module_init(void)
3120{
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3121 slic_init_driver();
3122
e8bc9b7a 3123 return pci_register_driver(&slic_driver);
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3124}
3125
3126static void __exit slic_module_cleanup(void)
3127{
4d6f6af8 3128 pci_unregister_driver(&slic_driver);
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3129}
3130
dda3e265 3131static const struct ethtool_ops slic_ethtool_ops = {
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3132 .get_coalesce = slic_get_coalesce,
3133 .set_coalesce = slic_set_coalesce
3134};
3135
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3136module_init(slic_module_init);
3137module_exit(slic_module_cleanup);
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