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Staging: vme: fix compiler warnings in vme_ca91cx42.c
[deliverable/linux.git] / drivers / staging / vme / bridges / vme_tsi148.c
CommitLineData
d22b8ed9
MW		 1/*
2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
3 *
4 * Author: Martyn Welch <martyn.welch@gefanuc.com>
5 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
d22b8ed9
MW		 16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/mm.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/proc_fs.h>
22#include <linux/pci.h>
23#include <linux/poll.h>
24#include <linux/dma-mapping.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
6af783c8 27#include <linux/sched.h>
d22b8ed9
MW		 28#include <asm/time.h>
29#include <asm/io.h>
30#include <asm/uaccess.h>
31
32#include "../vme.h"
33#include "../vme_bridge.h"
34#include "vme_tsi148.h"
35
36static int __init tsi148_init(void);
37static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
38static void tsi148_remove(struct pci_dev *);
39static void __exit tsi148_exit(void);
40
41
42int tsi148_slave_set(struct vme_slave_resource *, int, unsigned long long,
43 unsigned long long, dma_addr_t, vme_address_t, vme_cycle_t);
44int tsi148_slave_get(struct vme_slave_resource *, int *, unsigned long long *,
45 unsigned long long *, dma_addr_t *, vme_address_t *, vme_cycle_t *);
46
47int tsi148_master_get(struct vme_master_resource *, int *, unsigned long long *,
48 unsigned long long *, vme_address_t *, vme_cycle_t *, vme_width_t *);
49int tsi148_master_set(struct vme_master_resource *, int, unsigned long long,
50 unsigned long long, vme_address_t, vme_cycle_t, vme_width_t);
51ssize_t tsi148_master_read(struct vme_master_resource *, void *, size_t,
52 loff_t);
53ssize_t tsi148_master_write(struct vme_master_resource *, void *, size_t,
54 loff_t);
55unsigned int tsi148_master_rmw(struct vme_master_resource *, unsigned int,
56 unsigned int, unsigned int, loff_t);
57int tsi148_dma_list_add (struct vme_dma_list *, struct vme_dma_attr *,
58 struct vme_dma_attr *, size_t);
59int tsi148_dma_list_exec(struct vme_dma_list *);
60int tsi148_dma_list_empty(struct vme_dma_list *);
61int tsi148_generate_irq(int, int);
d22b8ed9
MW		 62int tsi148_slot_get(void);
63
64/* Modue parameter */
65int err_chk = 0;
66
67/* XXX These should all be in a per device structure */
68struct vme_bridge *tsi148_bridge;
69wait_queue_head_t dma_queue[2];
70wait_queue_head_t iack_queue;
71void (*lm_callback[4])(int); /* Called in interrupt handler, be careful! */
72void *crcsr_kernel;
73dma_addr_t crcsr_bus;
74struct vme_master_resource *flush_image;
400822fe
MW		 75struct mutex vme_rmw; /* Only one RMW cycle at a time */
76struct mutex vme_int; /*
d22b8ed9
MW		 77 * Only one VME interrupt can be
78 * generated at a time, provide locking
79 */
d22b8ed9
MW		 80
81static char driver_name[] = "vme_tsi148";
82
83static struct pci_device_id tsi148_ids[] = {
84 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
85 { },
86};
87
88static struct pci_driver tsi148_driver = {
89 .name = driver_name,
90 .id_table = tsi148_ids,
91 .probe = tsi148_probe,
92 .remove = tsi148_remove,
93};
94
95static void reg_join(unsigned int high, unsigned int low,
96 unsigned long long *variable)
97{
98 *variable = (unsigned long long)high << 32;
99 *variable |= (unsigned long long)low;
100}
101
102static void reg_split(unsigned long long variable, unsigned int *high,
103 unsigned int *low)
104{
105 *low = (unsigned int)variable & 0xFFFFFFFF;
106 *high = (unsigned int)(variable >> 32);
107}
108
109/*
110 * Wakes up DMA queue.
111 */
112static u32 tsi148_DMA_irqhandler(int channel_mask)
113{
114 u32 serviced = 0;
115
116 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
117 wake_up(&dma_queue[0]);
118 serviced |= TSI148_LCSR_INTC_DMA0C;
119 }
120 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
121 wake_up(&dma_queue[1]);
122 serviced |= TSI148_LCSR_INTC_DMA1C;
123 }
124
125 return serviced;
126}
127
128/*
129 * Wake up location monitor queue
130 */
131static u32 tsi148_LM_irqhandler(u32 stat)
132{
133 int i;
134 u32 serviced = 0;
135
136 for (i = 0; i < 4; i++) {
137 if(stat & TSI148_LCSR_INTS_LMS[i]) {
138 /* We only enable interrupts if the callback is set */
139 lm_callback[i](i);
140 serviced |= TSI148_LCSR_INTC_LMC[i];
141 }
142 }
143
144 return serviced;
145}
146
147/*
148 * Wake up mail box queue.
149 *
150 * XXX This functionality is not exposed up though API.
151 */
152static u32 tsi148_MB_irqhandler(u32 stat)
153{
154 int i;
155 u32 val;
156 u32 serviced = 0;
157
158 for (i = 0; i < 4; i++) {
159 if(stat & TSI148_LCSR_INTS_MBS[i]) {
160 val = ioread32be(tsi148_bridge->base +
161 TSI148_GCSR_MBOX[i]);
162 printk("VME Mailbox %d received: 0x%x\n", i, val);
163 serviced |= TSI148_LCSR_INTC_MBC[i];
164 }
165 }
166
167 return serviced;
168}
169
170/*
171 * Display error & status message when PERR (PCI) exception interrupt occurs.
172 */
173static u32 tsi148_PERR_irqhandler(void)
174{
175 printk(KERN_ERR
176 "PCI Exception at address: 0x%08x:%08x, attributes: %08x\n",
177 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAU),
178 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAL),
179 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAT)
180 );
181 printk(KERN_ERR
182 "PCI-X attribute reg: %08x, PCI-X split completion reg: %08x\n",
183 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXA),
184 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXS)
185 );
186
187 iowrite32be(TSI148_LCSR_EDPAT_EDPCL,
188 tsi148_bridge->base + TSI148_LCSR_EDPAT);
189
190 return TSI148_LCSR_INTC_PERRC;
191}
192
193/*
194 * Save address and status when VME error interrupt occurs.
195 */
196static u32 tsi148_VERR_irqhandler(void)
197{
198 unsigned int error_addr_high, error_addr_low;
199 unsigned long long error_addr;
200 u32 error_attrib;
201 struct vme_bus_error *error;
202
203 error_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAU);
204 error_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAL);
205 error_attrib = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAT);
206
207 reg_join(error_addr_high, error_addr_low, &error_addr);
208
209 /* Check for exception register overflow (we have lost error data) */
210 if(error_attrib & TSI148_LCSR_VEAT_VEOF) {
211 printk(KERN_ERR "VME Bus Exception Overflow Occurred\n");
212 }
213
214 error = (struct vme_bus_error *)kmalloc(sizeof (struct vme_bus_error),
215 GFP_ATOMIC);
216 if (error) {
217 error->address = error_addr;
218 error->attributes = error_attrib;
219 list_add_tail(&(error->list), &(tsi148_bridge->vme_errors));
220 } else {
221 printk(KERN_ERR
222 "Unable to alloc memory for VMEbus Error reporting\n");
223 printk(KERN_ERR
224 "VME Bus Error at address: 0x%llx, attributes: %08x\n",
225 error_addr, error_attrib);
226 }
227
228 /* Clear Status */
229 iowrite32be(TSI148_LCSR_VEAT_VESCL,
230 tsi148_bridge->base + TSI148_LCSR_VEAT);
231
232 return TSI148_LCSR_INTC_VERRC;
233}
234
235/*
236 * Wake up IACK queue.
237 */
238static u32 tsi148_IACK_irqhandler(void)
239{
240 printk("tsi148_IACK_irqhandler\n");
241 wake_up(&iack_queue);
242
243 return TSI148_LCSR_INTC_IACKC;
244}
245
246/*
247 * Calling VME bus interrupt callback if provided.
248 */
249static u32 tsi148_VIRQ_irqhandler(u32 stat)
250{
251 int vec, i, serviced = 0;
d22b8ed9
MW		 252
253 for (i = 7; i > 0; i--) {
254 if (stat & (1 << i)) {
255 /*
256 * Note: Even though the registers are defined
257 * as 32-bits in the spec, we only want to issue
258 * 8-bit IACK cycles on the bus, read from offset
259 * 3.
260 */
261 vec = ioread8(tsi148_bridge->base +
262 TSI148_LCSR_VIACK[i] + 3);
263
c813f592 264 vme_irq_handler(tsi148_bridge, i, vec);
d22b8ed9
MW		 265
266 serviced |= (1 << i);
267 }
268 }
269
270 return serviced;
271}
272
273/*
274 * Top level interrupt handler. Clears appropriate interrupt status bits and
275 * then calls appropriate sub handler(s).
276 */
277static irqreturn_t tsi148_irqhandler(int irq, void *dev_id)
278{
279 u32 stat, enable, serviced = 0;
280
281 /* Determine which interrupts are unmasked and set */
282 enable = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
283 stat = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTS);
284
285 /* Only look at unmasked interrupts */
286 stat &= enable;
287
288 if (unlikely(!stat)) {
289 return IRQ_NONE;
290 }
291
292 /* Call subhandlers as appropriate */
293 /* DMA irqs */
294 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
295 serviced |= tsi148_DMA_irqhandler(stat);
296
297 /* Location monitor irqs */
298 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
299 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
300 serviced |= tsi148_LM_irqhandler(stat);
301
302 /* Mail box irqs */
303 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
304 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
305 serviced |= tsi148_MB_irqhandler(stat);
306
307 /* PCI bus error */
308 if (stat & TSI148_LCSR_INTS_PERRS)
309 serviced |= tsi148_PERR_irqhandler();
310
311 /* VME bus error */
312 if (stat & TSI148_LCSR_INTS_VERRS)
313 serviced |= tsi148_VERR_irqhandler();
314
315 /* IACK irq */
316 if (stat & TSI148_LCSR_INTS_IACKS)
317 serviced |= tsi148_IACK_irqhandler();
318
319 /* VME bus irqs */
320 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
321 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
322 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
323 TSI148_LCSR_INTS_IRQ1S))
324 serviced |= tsi148_VIRQ_irqhandler(stat);
325
326 /* Clear serviced interrupts */
327 iowrite32be(serviced, tsi148_bridge->base + TSI148_LCSR_INTC);
328
329 return IRQ_HANDLED;
330}
331
332static int tsi148_irq_init(struct vme_bridge *bridge)
333{
334 int result;
335 unsigned int tmp;
336 struct pci_dev *pdev;
337
338 /* Need pdev */
339 pdev = container_of(bridge->parent, struct pci_dev, dev);
340
341 /* Initialise list for VME bus errors */
342 INIT_LIST_HEAD(&(bridge->vme_errors));
343
c813f592
MW		 344 mutex_init(&(bridge->irq_mtx));
345
d22b8ed9
MW		 346 result = request_irq(pdev->irq,
347 tsi148_irqhandler,
348 IRQF_SHARED,
349 driver_name, pdev);
350 if (result) {
351 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
352 pdev->irq);
353 return result;
354 }
355
356 /* Enable and unmask interrupts */
357 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
358 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
359 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
360 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
361 TSI148_LCSR_INTEO_IACKEO;
362
363 /* XXX This leaves the following interrupts masked.
364 * TSI148_LCSR_INTEO_VIEEO
365 * TSI148_LCSR_INTEO_SYSFLEO
366 * TSI148_LCSR_INTEO_ACFLEO
367 */
368
369 /* Don't enable Location Monitor interrupts here - they will be
370 * enabled when the location monitors are properly configured and
371 * a callback has been attached.
372 * TSI148_LCSR_INTEO_LM0EO
373 * TSI148_LCSR_INTEO_LM1EO
374 * TSI148_LCSR_INTEO_LM2EO
375 * TSI148_LCSR_INTEO_LM3EO
376 */
377
378 /* Don't enable VME interrupts until we add a handler, else the board
379 * will respond to it and we don't want that unless it knows how to
380 * properly deal with it.
381 * TSI148_LCSR_INTEO_IRQ7EO
382 * TSI148_LCSR_INTEO_IRQ6EO
383 * TSI148_LCSR_INTEO_IRQ5EO
384 * TSI148_LCSR_INTEO_IRQ4EO
385 * TSI148_LCSR_INTEO_IRQ3EO
386 * TSI148_LCSR_INTEO_IRQ2EO
387 * TSI148_LCSR_INTEO_IRQ1EO
388 */
389
390 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
391 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
392
393 return 0;
394}
395
396static void tsi148_irq_exit(struct pci_dev *pdev)
397{
398 /* Turn off interrupts */
399 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEO);
400 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEN);
401
402 /* Clear all interrupts */
403 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTC);
404
405 /* Detach interrupt handler */
406 free_irq(pdev->irq, pdev);
407}
408
409/*
410 * Check to see if an IACk has been received, return true (1) or false (0).
411 */
412int tsi148_iack_received(void)
413{
414 u32 tmp;
415
416 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR);
417
418 if (tmp & TSI148_LCSR_VICR_IRQS)
419 return 0;
420 else
421 return 1;
422}
423
424/*
c813f592 425 * Configure VME interrupt
d22b8ed9 426 */
c813f592 427void tsi148_irq_set(int level, int state, int sync)
d22b8ed9 428{
75155020 429 struct pci_dev *pdev;
c813f592 430 u32 tmp;
d22b8ed9 431
c813f592
MW		 432 /* We need to do the ordering differently for enabling and disabling */
433 if (state == 0) {
d22b8ed9
MW		 434 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
435 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
436 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
df455175
MW		 437
438 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
439 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
440 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
75155020 441
c813f592
MW		 442 if (sync != 0) {
443 pdev = container_of(tsi148_bridge->parent,
444 struct pci_dev, dev);
75155020 445
c813f592
MW		 446 synchronize_irq(pdev->irq);
447 }
448 } else {
449 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
450 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
451 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
df455175 452
c813f592
MW		 453 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
454 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
455 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
456 }
d22b8ed9
MW		 457}
458
459/*
460 * Generate a VME bus interrupt at the requested level & vector. Wait for
461 * interrupt to be acked.
d22b8ed9 462 */
c813f592 463int tsi148_irq_generate(int level, int statid)
d22b8ed9
MW		 464{
465 u32 tmp;
466
400822fe 467 mutex_lock(&(vme_int));
d22b8ed9
MW		 468
469 /* Read VICR register */
470 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR);
471
472 /* Set Status/ID */
473 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
474 (statid & TSI148_LCSR_VICR_STID_M);
475 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR);
476
477 /* Assert VMEbus IRQ */
478 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
479 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR);
480
481 /* XXX Consider implementing a timeout? */
482 wait_event_interruptible(iack_queue, tsi148_iack_received());
483
400822fe 484 mutex_unlock(&(vme_int));
d22b8ed9
MW		 485
486 return 0;
487}
488
489/*
490 * Find the first error in this address range
491 */
492static struct vme_bus_error *tsi148_find_error(vme_address_t aspace,
493 unsigned long long address, size_t count)
494{
495 struct list_head *err_pos;
496 struct vme_bus_error *vme_err, *valid = NULL;
497 unsigned long long bound;
498
499 bound = address + count;
500
501 /*
502 * XXX We are currently not looking at the address space when parsing
503 * for errors. This is because parsing the Address Modifier Codes
504 * is going to be quite resource intensive to do properly. We
505 * should be OK just looking at the addresses and this is certainly
506 * much better than what we had before.
507 */
508 err_pos = NULL;
509 /* Iterate through errors */
510 list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {
511 vme_err = list_entry(err_pos, struct vme_bus_error, list);
512 if((vme_err->address >= address) && (vme_err->address < bound)){
513 valid = vme_err;
514 break;
515 }
516 }
517
518 return valid;
519}
520
521/*
522 * Clear errors in the provided address range.
523 */
524static void tsi148_clear_errors(vme_address_t aspace,
525 unsigned long long address, size_t count)
526{
527 struct list_head *err_pos, *temp;
528 struct vme_bus_error *vme_err;
529 unsigned long long bound;
530
531 bound = address + count;
532
533 /*
534 * XXX We are currently not looking at the address space when parsing
535 * for errors. This is because parsing the Address Modifier Codes
536 * is going to be quite resource intensive to do properly. We
537 * should be OK just looking at the addresses and this is certainly
538 * much better than what we had before.
539 */
540 err_pos = NULL;
541 /* Iterate through errors */
542 list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {
543 vme_err = list_entry(err_pos, struct vme_bus_error, list);
544
545 if((vme_err->address >= address) && (vme_err->address < bound)){
546 list_del(err_pos);
547 kfree(vme_err);
548 }
549 }
550}
551
552/*
553 * Initialize a slave window with the requested attributes.
554 */
555int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
556 unsigned long long vme_base, unsigned long long size,
557 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
558{
559 unsigned int i, addr = 0, granularity = 0;
560 unsigned int temp_ctl = 0;
561 unsigned int vme_base_low, vme_base_high;
562 unsigned int vme_bound_low, vme_bound_high;
563 unsigned int pci_offset_low, pci_offset_high;
564 unsigned long long vme_bound, pci_offset;
565
566#if 0
567 printk("Set slave image %d to:\n", image->number);
568 printk("\tEnabled: %s\n", (enabled == 1)? "yes" : "no");
569 printk("\tVME Base:0x%llx\n", vme_base);
570 printk("\tWindow Size:0x%llx\n", size);
571 printk("\tPCI Base:0x%lx\n", (unsigned long)pci_base);
572 printk("\tAddress Space:0x%x\n", aspace);
573 printk("\tTransfer Cycle Properties:0x%x\n", cycle);
574#endif
575
576 i = image->number;
577
578 switch (aspace) {
579 case VME_A16:
580 granularity = 0x10;
581 addr |= TSI148_LCSR_ITAT_AS_A16;
582 break;
583 case VME_A24:
584 granularity = 0x1000;
585 addr |= TSI148_LCSR_ITAT_AS_A24;
586 break;
587 case VME_A32:
588 granularity = 0x10000;
589 addr |= TSI148_LCSR_ITAT_AS_A32;
590 break;
591 case VME_A64:
592 granularity = 0x10000;
593 addr |= TSI148_LCSR_ITAT_AS_A64;
594 break;
595 case VME_CRCSR:
596 case VME_USER1:
597 case VME_USER2:
598 case VME_USER3:
599 case VME_USER4:
600 default:
601 printk("Invalid address space\n");
602 return -EINVAL;
603 break;
604 }
605
606 /* Convert 64-bit variables to 2x 32-bit variables */
607 reg_split(vme_base, &vme_base_high, &vme_base_low);
608
609 /*
610 * Bound address is a valid address for the window, adjust
611 * accordingly
612 */
613 vme_bound = vme_base + size - granularity;
614 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
615 pci_offset = (unsigned long long)pci_base - vme_base;
616 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
617
618 if (vme_base_low & (granularity - 1)) {
619 printk("Invalid VME base alignment\n");
620 return -EINVAL;
621 }
622 if (vme_bound_low & (granularity - 1)) {
623 printk("Invalid VME bound alignment\n");
624 return -EINVAL;
625 }
626 if (pci_offset_low & (granularity - 1)) {
627 printk("Invalid PCI Offset alignment\n");
628 return -EINVAL;
629 }
630
631#if 0
632 printk("\tVME Bound:0x%llx\n", vme_bound);
633 printk("\tPCI Offset:0x%llx\n", pci_offset);
634#endif
635
636 /* Disable while we are mucking around */
637 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
638 TSI148_LCSR_OFFSET_ITAT);
639 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
640 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
641 TSI148_LCSR_OFFSET_ITAT);
642
643 /* Setup mapping */
644 iowrite32be(vme_base_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
645 TSI148_LCSR_OFFSET_ITSAU);
646 iowrite32be(vme_base_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
647 TSI148_LCSR_OFFSET_ITSAL);
648 iowrite32be(vme_bound_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
649 TSI148_LCSR_OFFSET_ITEAU);
650 iowrite32be(vme_bound_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
651 TSI148_LCSR_OFFSET_ITEAL);
652 iowrite32be(pci_offset_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
653 TSI148_LCSR_OFFSET_ITOFU);
654 iowrite32be(pci_offset_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
655 TSI148_LCSR_OFFSET_ITOFL);
656
657/* XXX Prefetch stuff currently unsupported */
658#if 0
659
660 for (x = 0; x < 4; x++) {
661 if ((64 << x) >= vmeIn->prefetchSize) {
662 break;
663 }
664 }
665 if (x == 4)
666 x--;
667 temp_ctl |= (x << 16);
668
669 if (vmeIn->prefetchThreshold)
670 if (vmeIn->prefetchThreshold)
671 temp_ctl |= 0x40000;
672#endif
673
674 /* Setup 2eSST speeds */
675 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
676 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
677 case VME_2eSST160:
678 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
679 break;
680 case VME_2eSST267:
681 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
682 break;
683 case VME_2eSST320:
684 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
685 break;
686 }
687
688 /* Setup cycle types */
689 temp_ctl &= ~(0x1F << 7);
690 if (cycle & VME_BLT)
691 temp_ctl |= TSI148_LCSR_ITAT_BLT;
692 if (cycle & VME_MBLT)
693 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
694 if (cycle & VME_2eVME)
695 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
696 if (cycle & VME_2eSST)
697 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
698 if (cycle & VME_2eSSTB)
699 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
700
701 /* Setup address space */
702 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
703 temp_ctl |= addr;
704
705 temp_ctl &= ~0xF;
706 if (cycle & VME_SUPER)
707 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
708 if (cycle & VME_USER)
709 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
710 if (cycle & VME_PROG)
711 temp_ctl |= TSI148_LCSR_ITAT_PGM;
712 if (cycle & VME_DATA)
713 temp_ctl |= TSI148_LCSR_ITAT_DATA;
714
715 /* Write ctl reg without enable */
716 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
717 TSI148_LCSR_OFFSET_ITAT);
718
719 if (enabled)
720 temp_ctl |= TSI148_LCSR_ITAT_EN;
721
722 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
723 TSI148_LCSR_OFFSET_ITAT);
724
725 return 0;
726}
727
728/*
729 * Get slave window configuration.
730 *
731 * XXX Prefetch currently unsupported.
732 */
733int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
734 unsigned long long *vme_base, unsigned long long *size,
735 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
736{
737 unsigned int i, granularity = 0, ctl = 0;
738 unsigned int vme_base_low, vme_base_high;
739 unsigned int vme_bound_low, vme_bound_high;
740 unsigned int pci_offset_low, pci_offset_high;
741 unsigned long long vme_bound, pci_offset;
742
743
744 i = image->number;
745
746 /* Read registers */
747 ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
748 TSI148_LCSR_OFFSET_ITAT);
749
750 vme_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
751 TSI148_LCSR_OFFSET_ITSAU);
752 vme_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
753 TSI148_LCSR_OFFSET_ITSAL);
754 vme_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
755 TSI148_LCSR_OFFSET_ITEAU);
756 vme_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
757 TSI148_LCSR_OFFSET_ITEAL);
758 pci_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
759 TSI148_LCSR_OFFSET_ITOFU);
760 pci_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
761 TSI148_LCSR_OFFSET_ITOFL);
762
763 /* Convert 64-bit variables to 2x 32-bit variables */
764 reg_join(vme_base_high, vme_base_low, vme_base);
765 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
766 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
767
768 *pci_base = (dma_addr_t)vme_base + pci_offset;
769
770 *enabled = 0;
771 *aspace = 0;
772 *cycle = 0;
773
774 if (ctl & TSI148_LCSR_ITAT_EN)
775 *enabled = 1;
776
777 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
778 granularity = 0x10;
779 *aspace |= VME_A16;
780 }
781 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
782 granularity = 0x1000;
783 *aspace |= VME_A24;
784 }
785 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
786 granularity = 0x10000;
787 *aspace |= VME_A32;
788 }
789 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
790 granularity = 0x10000;
791 *aspace |= VME_A64;
792 }
793
794 /* Need granularity before we set the size */
795 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
796
797
798 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
799 *cycle |= VME_2eSST160;
800 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
801 *cycle |= VME_2eSST267;
802 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
803 *cycle |= VME_2eSST320;
804
805 if (ctl & TSI148_LCSR_ITAT_BLT)
806 *cycle |= VME_BLT;
807 if (ctl & TSI148_LCSR_ITAT_MBLT)
808 *cycle |= VME_MBLT;
809 if (ctl & TSI148_LCSR_ITAT_2eVME)
810 *cycle |= VME_2eVME;
811 if (ctl & TSI148_LCSR_ITAT_2eSST)
812 *cycle |= VME_2eSST;
813 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
814 *cycle |= VME_2eSSTB;
815
816 if (ctl & TSI148_LCSR_ITAT_SUPR)
817 *cycle |= VME_SUPER;
818 if (ctl & TSI148_LCSR_ITAT_NPRIV)
819 *cycle |= VME_USER;
820 if (ctl & TSI148_LCSR_ITAT_PGM)
821 *cycle |= VME_PROG;
822 if (ctl & TSI148_LCSR_ITAT_DATA)
823 *cycle |= VME_DATA;
824
825 return 0;
826}
827
828/*
829 * Allocate and map PCI Resource
830 */
831static int tsi148_alloc_resource(struct vme_master_resource *image,
832 unsigned long long size)
833{
834 unsigned long long existing_size;
835 int retval = 0;
836 struct pci_dev *pdev;
837
838 /* Find pci_dev container of dev */
839 if (tsi148_bridge->parent == NULL) {
840 printk("Dev entry NULL\n");
841 return -EINVAL;
842 }
843 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
844
845 existing_size = (unsigned long long)(image->pci_resource.end -
846 image->pci_resource.start);
847
848 /* If the existing size is OK, return */
849 if (existing_size == (size - 1))
850 return 0;
851
852 if (existing_size != 0) {
853 iounmap(image->kern_base);
854 image->kern_base = NULL;
855 if (image->pci_resource.name != NULL)
856 kfree(image->pci_resource.name);
857 release_resource(&(image->pci_resource));
858 memset(&(image->pci_resource), 0, sizeof(struct resource));
859 }
860
861 if (image->pci_resource.name == NULL) {
862 image->pci_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
863 if (image->pci_resource.name == NULL) {
864 printk(KERN_ERR "Unable to allocate memory for resource"
865 " name\n");
866 retval = -ENOMEM;
867 goto err_name;
868 }
869 }
870
871 sprintf((char *)image->pci_resource.name, "%s.%d", tsi148_bridge->name,
872 image->number);
873
874 image->pci_resource.start = 0;
875 image->pci_resource.end = (unsigned long)size;
876 image->pci_resource.flags = IORESOURCE_MEM;
877
878 retval = pci_bus_alloc_resource(pdev->bus,
879 &(image->pci_resource), size, size, PCIBIOS_MIN_MEM,
880 0, NULL, NULL);
881 if (retval) {
882 printk(KERN_ERR "Failed to allocate mem resource for "
883 "window %d size 0x%lx start 0x%lx\n",
884 image->number, (unsigned long)size,
885 (unsigned long)image->pci_resource.start);
886 goto err_resource;
887 }
888
889 image->kern_base = ioremap_nocache(
890 image->pci_resource.start, size);
891 if (image->kern_base == NULL) {
892 printk(KERN_ERR "Failed to remap resource\n");
893 retval = -ENOMEM;
894 goto err_remap;
895 }
896
897 return 0;
898
899 iounmap(image->kern_base);
900 image->kern_base = NULL;
901err_remap:
902 release_resource(&(image->pci_resource));
903err_resource:
904 kfree(image->pci_resource.name);
905 memset(&(image->pci_resource), 0, sizeof(struct resource));
906err_name:
907 return retval;
908}
909
910/*
911 * Free and unmap PCI Resource
912 */
913static void tsi148_free_resource(struct vme_master_resource *image)
914{
915 iounmap(image->kern_base);
916 image->kern_base = NULL;
917 release_resource(&(image->pci_resource));
918 kfree(image->pci_resource.name);
919 memset(&(image->pci_resource), 0, sizeof(struct resource));
920}
921
922/*
923 * Set the attributes of an outbound window.
924 */
925int tsi148_master_set( struct vme_master_resource *image, int enabled,
926 unsigned long long vme_base, unsigned long long size,
927 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
928{
929 int retval = 0;
930 unsigned int i;
931 unsigned int temp_ctl = 0;
932 unsigned int pci_base_low, pci_base_high;
933 unsigned int pci_bound_low, pci_bound_high;
934 unsigned int vme_offset_low, vme_offset_high;
935 unsigned long long pci_bound, vme_offset, pci_base;
936
937 /* Verify input data */
938 if (vme_base & 0xFFFF) {
939 printk("Invalid VME Window alignment\n");
940 retval = -EINVAL;
941 goto err_window;
942 }
943 if (size < 0x10000) {
944 printk("Invalid VME Window size\n");
945 retval = -EINVAL;
946 goto err_window;
947 }
948
949 spin_lock(&(image->lock));
950
951 /* Let's allocate the resource here rather than further up the stack as
952 * it avoids pushing loads of bus dependant stuff up the stack
953 */
954 retval = tsi148_alloc_resource(image, size);
955 if (retval) {
956 spin_unlock(&(image->lock));
957 printk(KERN_ERR "Unable to allocate memory for resource "
958 "name\n");
959 retval = -ENOMEM;
960 goto err_res;
961 }
962
963 pci_base = (unsigned long long)image->pci_resource.start;
964
965
966 /*
967 * Bound address is a valid address for the window, adjust
968 * according to window granularity.
969 */
970 pci_bound = pci_base + (size - 0x10000);
971 vme_offset = vme_base - pci_base;
972
973 /* Convert 64-bit variables to 2x 32-bit variables */
974 reg_split(pci_base, &pci_base_high, &pci_base_low);
975 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
976 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
977
978 if (pci_base_low & 0xFFFF) {
979 spin_unlock(&(image->lock));
980 printk("Invalid PCI base alignment\n");
981 retval = -EINVAL;
982 goto err_gran;
983 }
984 if (pci_bound_low & 0xFFFF) {
985 spin_unlock(&(image->lock));
986 printk("Invalid PCI bound alignment\n");
987 retval = -EINVAL;
988 goto err_gran;
989 }
990 if (vme_offset_low & 0xFFFF) {
991 spin_unlock(&(image->lock));
992 printk("Invalid VME Offset alignment\n");
993 retval = -EINVAL;
994 goto err_gran;
995 }
996
997 i = image->number;
998
999 /* Disable while we are mucking around */
1000 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1001 TSI148_LCSR_OFFSET_OTAT);
1002 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
1003 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1004 TSI148_LCSR_OFFSET_OTAT);
1005
1006/* XXX Prefetch stuff currently unsupported */
1007#if 0
1008 if (vmeOut->prefetchEnable) {
1009 temp_ctl |= 0x40000;
1010 for (x = 0; x < 4; x++) {
1011 if ((2 << x) >= vmeOut->prefetchSize)
1012 break;
1013 }
1014 if (x == 4)
1015 x = 3;
1016 temp_ctl |= (x << 16);
1017 }
1018#endif
1019
1020 /* Setup 2eSST speeds */
1021 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
1022 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1023 case VME_2eSST160:
1024 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
1025 break;
1026 case VME_2eSST267:
1027 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
1028 break;
1029 case VME_2eSST320:
1030 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1031 break;
1032 }
1033
1034 /* Setup cycle types */
1035 if (cycle & VME_BLT) {
1036 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1037 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1038 }
1039 if (cycle & VME_MBLT) {
1040 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1041 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1042 }
1043 if (cycle & VME_2eVME) {
1044 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1045 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1046 }
1047 if (cycle & VME_2eSST) {
1048 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1049 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1050 }
1051 if (cycle & VME_2eSSTB) {
1052 printk("Currently not setting Broadcast Select Registers\n");
1053 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1054 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1055 }
1056
1057 /* Setup data width */
1058 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1059 switch (dwidth) {
1060 case VME_D16:
1061 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1062 break;
1063 case VME_D32:
1064 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1065 break;
1066 default:
1067 spin_unlock(&(image->lock));
1068 printk("Invalid data width\n");
1069 retval = -EINVAL;
1070 goto err_dwidth;
1071 }
1072
1073 /* Setup address space */
1074 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1075 switch (aspace) {
1076 case VME_A16:
1077 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1078 break;
1079 case VME_A24:
1080 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1081 break;
1082 case VME_A32:
1083 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1084 break;
1085 case VME_A64:
1086 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1087 break;
1088 case VME_CRCSR:
1089 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1090 break;
1091 case VME_USER1:
1092 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1093 break;
1094 case VME_USER2:
1095 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1096 break;
1097 case VME_USER3:
1098 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1099 break;
1100 case VME_USER4:
1101 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1102 break;
1103 default:
1104 spin_unlock(&(image->lock));
1105 printk("Invalid address space\n");
1106 retval = -EINVAL;
1107 goto err_aspace;
1108 break;
1109 }
1110
1111 temp_ctl &= ~(3<<4);
1112 if (cycle & VME_SUPER)
1113 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1114 if (cycle & VME_PROG)
1115 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1116
1117 /* Setup mapping */
1118 iowrite32be(pci_base_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1119 TSI148_LCSR_OFFSET_OTSAU);
1120 iowrite32be(pci_base_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1121 TSI148_LCSR_OFFSET_OTSAL);
1122 iowrite32be(pci_bound_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1123 TSI148_LCSR_OFFSET_OTEAU);
1124 iowrite32be(pci_bound_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1125 TSI148_LCSR_OFFSET_OTEAL);
1126 iowrite32be(vme_offset_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1127 TSI148_LCSR_OFFSET_OTOFU);
1128 iowrite32be(vme_offset_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1129 TSI148_LCSR_OFFSET_OTOFL);
1130
1131/* XXX We need to deal with OTBS */
1132#if 0
1133 iowrite32be(vmeOut->bcastSelect2esst, tsi148_bridge->base +
1134 TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTBS);
1135#endif
1136
1137 /* Write ctl reg without enable */
1138 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1139 TSI148_LCSR_OFFSET_OTAT);
1140
1141 if (enabled)
1142 temp_ctl |= TSI148_LCSR_OTAT_EN;
1143
1144 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1145 TSI148_LCSR_OFFSET_OTAT);
1146
1147 spin_unlock(&(image->lock));
1148 return 0;
1149
1150err_aspace:
1151err_dwidth:
1152err_gran:
1153 tsi148_free_resource(image);
1154err_res:
1155err_window:
1156 return retval;
1157
1158}
1159
1160/*
1161 * Set the attributes of an outbound window.
1162 *
1163 * XXX Not parsing prefetch information.
1164 */
1165int __tsi148_master_get( struct vme_master_resource *image, int *enabled,
1166 unsigned long long *vme_base, unsigned long long *size,
1167 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1168{
1169 unsigned int i, ctl;
1170 unsigned int pci_base_low, pci_base_high;
1171 unsigned int pci_bound_low, pci_bound_high;
1172 unsigned int vme_offset_low, vme_offset_high;
1173
1174 unsigned long long pci_base, pci_bound, vme_offset;
1175
1176 i = image->number;
1177
1178 ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1179 TSI148_LCSR_OFFSET_OTAT);
1180
1181 pci_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1182 TSI148_LCSR_OFFSET_OTSAU);
1183 pci_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1184 TSI148_LCSR_OFFSET_OTSAL);
1185 pci_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1186 TSI148_LCSR_OFFSET_OTEAU);
1187 pci_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1188 TSI148_LCSR_OFFSET_OTEAL);
1189 vme_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1190 TSI148_LCSR_OFFSET_OTOFU);
1191 vme_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1192 TSI148_LCSR_OFFSET_OTOFL);
1193
1194 /* Convert 64-bit variables to 2x 32-bit variables */
1195 reg_join(pci_base_high, pci_base_low, &pci_base);
1196 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1197 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1198
1199 *vme_base = pci_base + vme_offset;
1200 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1201
1202 *enabled = 0;
1203 *aspace = 0;
1204 *cycle = 0;
1205 *dwidth = 0;
1206
1207 if (ctl & TSI148_LCSR_OTAT_EN)
1208 *enabled = 1;
1209
1210 /* Setup address space */
1211 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1212 *aspace |= VME_A16;
1213 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1214 *aspace |= VME_A24;
1215 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1216 *aspace |= VME_A32;
1217 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1218 *aspace |= VME_A64;
1219 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1220 *aspace |= VME_CRCSR;
1221 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1222 *aspace |= VME_USER1;
1223 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1224 *aspace |= VME_USER2;
1225 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1226 *aspace |= VME_USER3;
1227 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1228 *aspace |= VME_USER4;
1229
1230 /* Setup 2eSST speeds */
1231 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1232 *cycle |= VME_2eSST160;
1233 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1234 *cycle |= VME_2eSST267;
1235 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1236 *cycle |= VME_2eSST320;
1237
1238 /* Setup cycle types */
1239 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_SCT)
1240 *cycle |= VME_SCT;
1241 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_BLT)
1242 *cycle |= VME_BLT;
1243 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_MBLT)
1244 *cycle |= VME_MBLT;
1245 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eVME)
1246 *cycle |= VME_2eVME;
1247 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSST)
1248 *cycle |= VME_2eSST;
1249 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSSTB)
1250 *cycle |= VME_2eSSTB;
1251
1252 if (ctl & TSI148_LCSR_OTAT_SUP)
1253 *cycle |= VME_SUPER;
1254 else
1255 *cycle |= VME_USER;
1256
1257 if (ctl & TSI148_LCSR_OTAT_PGM)
1258 *cycle |= VME_PROG;
1259 else
1260 *cycle |= VME_DATA;
1261
1262 /* Setup data width */
1263 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1264 *dwidth = VME_D16;
1265 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1266 *dwidth = VME_D32;
1267
1268 return 0;
1269}
1270
1271
1272int tsi148_master_get( struct vme_master_resource *image, int *enabled,
1273 unsigned long long *vme_base, unsigned long long *size,
1274 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1275{
1276 int retval;
1277
1278 spin_lock(&(image->lock));
1279
1280 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1281 cycle, dwidth);
1282
1283 spin_unlock(&(image->lock));
1284
1285 return retval;
1286}
1287
1288ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1289 size_t count, loff_t offset)
1290{
1291 int retval, enabled;
1292 unsigned long long vme_base, size;
1293 vme_address_t aspace;
1294 vme_cycle_t cycle;
1295 vme_width_t dwidth;
1296 struct vme_bus_error *vme_err = NULL;
1297
1298 spin_lock(&(image->lock));
1299
1300 memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1301 retval = count;
1302
1303 if (!err_chk)
1304 goto skip_chk;
1305
1306 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1307 &dwidth);
1308
1309 vme_err = tsi148_find_error(aspace, vme_base + offset, count);
1310 if(vme_err != NULL) {
1311 dev_err(image->parent->parent, "First VME read error detected "
1312 "an at address 0x%llx\n", vme_err->address);
1313 retval = vme_err->address - (vme_base + offset);
1314 /* Clear down save errors in this address range */
1315 tsi148_clear_errors(aspace, vme_base + offset, count);
1316 }
1317
1318skip_chk:
1319 spin_unlock(&(image->lock));
1320
1321 return retval;
1322}
1323
1324
400822fe 1325/* XXX We need to change vme_master_resource->mtx to a spinlock so that read
d22b8ed9
MW		 1326 * and write functions can be used in an interrupt context
1327 */
1328ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1329 size_t count, loff_t offset)
1330{
1331 int retval = 0, enabled;
1332 unsigned long long vme_base, size;
1333 vme_address_t aspace;
1334 vme_cycle_t cycle;
1335 vme_width_t dwidth;
1336
1337 struct vme_bus_error *vme_err = NULL;
1338
1339 spin_lock(&(image->lock));
1340
1341 memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1342 retval = count;
1343
1344 /*
1345 * Writes are posted. We need to do a read on the VME bus to flush out
1346 * all of the writes before we check for errors. We can't guarentee
1347 * that reading the data we have just written is safe. It is believed
1348 * that there isn't any read, write re-ordering, so we can read any
1349 * location in VME space, so lets read the Device ID from the tsi148's
1350 * own registers as mapped into CR/CSR space.
1351 *
1352 * We check for saved errors in the written address range/space.
1353 */
1354
1355 if (!err_chk)
1356 goto skip_chk;
1357
1358 /*
1359 * Get window info first, to maximise the time that the buffers may
1360 * fluch on their own
1361 */
1362 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1363 &dwidth);
1364
1365 ioread16(flush_image->kern_base + 0x7F000);
1366
1367 vme_err = tsi148_find_error(aspace, vme_base + offset, count);
1368 if(vme_err != NULL) {
1369 printk("First VME write error detected an at address 0x%llx\n",
1370 vme_err->address);
1371 retval = vme_err->address - (vme_base + offset);
1372 /* Clear down save errors in this address range */
1373 tsi148_clear_errors(aspace, vme_base + offset, count);
1374 }
1375
1376skip_chk:
1377 spin_unlock(&(image->lock));
1378
1379 return retval;
1380}
1381
1382/*
1383 * Perform an RMW cycle on the VME bus.
1384 *
1385 * Requires a previously configured master window, returns final value.
1386 */
1387unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1388 unsigned int mask, unsigned int compare, unsigned int swap,
1389 loff_t offset)
1390{
1391 unsigned long long pci_addr;
1392 unsigned int pci_addr_high, pci_addr_low;
1393 u32 tmp, result;
1394 int i;
1395
1396
1397 /* Find the PCI address that maps to the desired VME address */
1398 i = image->number;
1399
1400 /* Locking as we can only do one of these at a time */
400822fe 1401 mutex_lock(&(vme_rmw));
d22b8ed9
MW		 1402
1403 /* Lock image */
1404 spin_lock(&(image->lock));
1405
1406 pci_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1407 TSI148_LCSR_OFFSET_OTSAU);
1408 pci_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1409 TSI148_LCSR_OFFSET_OTSAL);
1410
1411 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1412 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1413
1414 /* Configure registers */
1415 iowrite32be(mask, tsi148_bridge->base + TSI148_LCSR_RMWEN);
1416 iowrite32be(compare, tsi148_bridge->base + TSI148_LCSR_RMWC);
1417 iowrite32be(swap, tsi148_bridge->base + TSI148_LCSR_RMWS);
1418 iowrite32be(pci_addr_high, tsi148_bridge->base + TSI148_LCSR_RMWAU);
1419 iowrite32be(pci_addr_low, tsi148_bridge->base + TSI148_LCSR_RMWAL);
1420
1421 /* Enable RMW */
1422 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1423 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1424 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1425
1426 /* Kick process off with a read to the required address. */
1427 result = ioread32be(image->kern_base + offset);
1428
1429 /* Disable RMW */
1430 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1431 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1432 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1433
1434 spin_unlock(&(image->lock));
1435
400822fe 1436 mutex_unlock(&(vme_rmw));
d22b8ed9
MW		 1437
1438 return result;
1439}
1440
1441static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace,
1442 vme_cycle_t cycle, vme_width_t dwidth)
1443{
1444 /* Setup 2eSST speeds */
1445 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1446 case VME_2eSST160:
1447 *attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1448 break;
1449 case VME_2eSST267:
1450 *attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1451 break;
1452 case VME_2eSST320:
1453 *attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1454 break;
1455 }
1456
1457 /* Setup cycle types */
1458 if (cycle & VME_SCT) {
1459 *attr |= TSI148_LCSR_DSAT_TM_SCT;
1460 }
1461 if (cycle & VME_BLT) {
1462 *attr |= TSI148_LCSR_DSAT_TM_BLT;
1463 }
1464 if (cycle & VME_MBLT) {
1465 *attr |= TSI148_LCSR_DSAT_TM_MBLT;
1466 }
1467 if (cycle & VME_2eVME) {
1468 *attr |= TSI148_LCSR_DSAT_TM_2eVME;
1469 }
1470 if (cycle & VME_2eSST) {
1471 *attr |= TSI148_LCSR_DSAT_TM_2eSST;
1472 }
1473 if (cycle & VME_2eSSTB) {
1474 printk("Currently not setting Broadcast Select Registers\n");
1475 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1476 }
1477
1478 /* Setup data width */
1479 switch (dwidth) {
1480 case VME_D16:
1481 *attr |= TSI148_LCSR_DSAT_DBW_16;
1482 break;
1483 case VME_D32:
1484 *attr |= TSI148_LCSR_DSAT_DBW_32;
1485 break;
1486 default:
1487 printk("Invalid data width\n");
1488 return -EINVAL;
1489 }
1490
1491 /* Setup address space */
1492 switch (aspace) {
1493 case VME_A16:
1494 *attr |= TSI148_LCSR_DSAT_AMODE_A16;
1495 break;
1496 case VME_A24:
1497 *attr |= TSI148_LCSR_DSAT_AMODE_A24;
1498 break;
1499 case VME_A32:
1500 *attr |= TSI148_LCSR_DSAT_AMODE_A32;
1501 break;
1502 case VME_A64:
1503 *attr |= TSI148_LCSR_DSAT_AMODE_A64;
1504 break;
1505 case VME_CRCSR:
1506 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1507 break;
1508 case VME_USER1:
1509 *attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1510 break;
1511 case VME_USER2:
1512 *attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1513 break;
1514 case VME_USER3:
1515 *attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1516 break;
1517 case VME_USER4:
1518 *attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1519 break;
1520 default:
1521 printk("Invalid address space\n");
1522 return -EINVAL;
1523 break;
1524 }
1525
1526 if (cycle & VME_SUPER)
1527 *attr |= TSI148_LCSR_DSAT_SUP;
1528 if (cycle & VME_PROG)
1529 *attr |= TSI148_LCSR_DSAT_PGM;
1530
1531 return 0;
1532}
1533
1534static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace,
1535 vme_cycle_t cycle, vme_width_t dwidth)
1536{
1537 /* Setup 2eSST speeds */
1538 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1539 case VME_2eSST160:
1540 *attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1541 break;
1542 case VME_2eSST267:
1543 *attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1544 break;
1545 case VME_2eSST320:
1546 *attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1547 break;
1548 }
1549
1550 /* Setup cycle types */
1551 if (cycle & VME_SCT) {
1552 *attr |= TSI148_LCSR_DDAT_TM_SCT;
1553 }
1554 if (cycle & VME_BLT) {
1555 *attr |= TSI148_LCSR_DDAT_TM_BLT;
1556 }
1557 if (cycle & VME_MBLT) {
1558 *attr |= TSI148_LCSR_DDAT_TM_MBLT;
1559 }
1560 if (cycle & VME_2eVME) {
1561 *attr |= TSI148_LCSR_DDAT_TM_2eVME;
1562 }
1563 if (cycle & VME_2eSST) {
1564 *attr |= TSI148_LCSR_DDAT_TM_2eSST;
1565 }
1566 if (cycle & VME_2eSSTB) {
1567 printk("Currently not setting Broadcast Select Registers\n");
1568 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1569 }
1570
1571 /* Setup data width */
1572 switch (dwidth) {
1573 case VME_D16:
1574 *attr |= TSI148_LCSR_DDAT_DBW_16;
1575 break;
1576 case VME_D32:
1577 *attr |= TSI148_LCSR_DDAT_DBW_32;
1578 break;
1579 default:
1580 printk("Invalid data width\n");
1581 return -EINVAL;
1582 }
1583
1584 /* Setup address space */
1585 switch (aspace) {
1586 case VME_A16:
1587 *attr |= TSI148_LCSR_DDAT_AMODE_A16;
1588 break;
1589 case VME_A24:
1590 *attr |= TSI148_LCSR_DDAT_AMODE_A24;
1591 break;
1592 case VME_A32:
1593 *attr |= TSI148_LCSR_DDAT_AMODE_A32;
1594 break;
1595 case VME_A64:
1596 *attr |= TSI148_LCSR_DDAT_AMODE_A64;
1597 break;
1598 case VME_CRCSR:
1599 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1600 break;
1601 case VME_USER1:
1602 *attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1603 break;
1604 case VME_USER2:
1605 *attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1606 break;
1607 case VME_USER3:
1608 *attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1609 break;
1610 case VME_USER4:
1611 *attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1612 break;
1613 default:
1614 printk("Invalid address space\n");
1615 return -EINVAL;
1616 break;
1617 }
1618
1619 if (cycle & VME_SUPER)
1620 *attr |= TSI148_LCSR_DDAT_SUP;
1621 if (cycle & VME_PROG)
1622 *attr |= TSI148_LCSR_DDAT_PGM;
1623
1624 return 0;
1625}
1626
1627/*
1628 * Add a link list descriptor to the list
1629 *
1630 * XXX Need to handle 2eSST Broadcast select bits
1631 */
1632int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
1633 struct vme_dma_attr *dest, size_t count)
1634{
1635 struct tsi148_dma_entry *entry, *prev;
1636 u32 address_high, address_low;
1637 struct vme_dma_pattern *pattern_attr;
1638 struct vme_dma_pci *pci_attr;
1639 struct vme_dma_vme *vme_attr;
1640 dma_addr_t desc_ptr;
1641 int retval = 0;
1642
1643 /* XXX descriptor must be aligned on 64-bit boundaries */
1644 entry = (struct tsi148_dma_entry *)kmalloc(
1645 sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1646 if (entry == NULL) {
1647 printk("Failed to allocate memory for dma resource "
1648 "structure\n");
1649 retval = -ENOMEM;
1650 goto err_mem;
1651 }
1652
1653 /* Test descriptor alignment */
1654 if ((unsigned long)&(entry->descriptor) & 0x7) {
1655 printk("Descriptor not aligned to 8 byte boundary as "
1656 "required: %p\n", &(entry->descriptor));
1657 retval = -EINVAL;
1658 goto err_align;
1659 }
1660
1661 /* Given we are going to fill out the structure, we probably don't
1662 * need to zero it, but better safe than sorry for now.
1663 */
1664 memset(&(entry->descriptor), 0, sizeof(struct tsi148_dma_descriptor));
1665
1666 /* Fill out source part */
1667 switch (src->type) {
1668 case VME_DMA_PATTERN:
1669 pattern_attr = (struct vme_dma_pattern *)src->private;
1670
1671 entry->descriptor.dsal = pattern_attr->pattern;
1672 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1673 /* Default behaviour is 32 bit pattern */
1674 if (pattern_attr->type & VME_DMA_PATTERN_BYTE) {
1675 entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
1676 }
1677 /* It seems that the default behaviour is to increment */
1678 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) {
1679 entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
1680 }
1681 break;
1682 case VME_DMA_PCI:
1683 pci_attr = (struct vme_dma_pci *)src->private;
1684
1685 reg_split((unsigned long long)pci_attr->address, &address_high,
1686 &address_low);
1687 entry->descriptor.dsau = address_high;
1688 entry->descriptor.dsal = address_low;
1689 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1690 break;
1691 case VME_DMA_VME:
1692 vme_attr = (struct vme_dma_vme *)src->private;
1693
1694 reg_split((unsigned long long)vme_attr->address, &address_high,
1695 &address_low);
1696 entry->descriptor.dsau = address_high;
1697 entry->descriptor.dsal = address_low;
1698 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1699
1700 retval = tsi148_dma_set_vme_src_attributes(
1701 &(entry->descriptor.dsat), vme_attr->aspace,
1702 vme_attr->cycle, vme_attr->dwidth);
1703 if(retval < 0 )
1704 goto err_source;
1705 break;
1706 default:
1707 printk("Invalid source type\n");
1708 retval = -EINVAL;
1709 goto err_source;
1710 break;
1711 }
1712
1713 /* Assume last link - this will be over-written by adding another */
1714 entry->descriptor.dnlau = 0;
1715 entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1716
1717
1718 /* Fill out destination part */
1719 switch (dest->type) {
1720 case VME_DMA_PCI:
1721 pci_attr = (struct vme_dma_pci *)dest->private;
1722
1723 reg_split((unsigned long long)pci_attr->address, &address_high,
1724 &address_low);
1725 entry->descriptor.ddau = address_high;
1726 entry->descriptor.ddal = address_low;
1727 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1728 break;
1729 case VME_DMA_VME:
1730 vme_attr = (struct vme_dma_vme *)dest->private;
1731
1732 reg_split((unsigned long long)vme_attr->address, &address_high,
1733 &address_low);
1734 entry->descriptor.ddau = address_high;
1735 entry->descriptor.ddal = address_low;
1736 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1737
1738 retval = tsi148_dma_set_vme_dest_attributes(
1739 &(entry->descriptor.ddat), vme_attr->aspace,
1740 vme_attr->cycle, vme_attr->dwidth);
1741 if(retval < 0 )
1742 goto err_dest;
1743 break;
1744 default:
1745 printk("Invalid destination type\n");
1746 retval = -EINVAL;
1747 goto err_dest;
1748 break;
1749 }
1750
1751 /* Fill out count */
1752 entry->descriptor.dcnt = (u32)count;
1753
1754 /* Add to list */
1755 list_add_tail(&(entry->list), &(list->entries));
1756
1757 /* Fill out previous descriptors "Next Address" */
1758 if(entry->list.prev != &(list->entries)){
1759 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1760 list);
1761 /* We need the bus address for the pointer */
1762 desc_ptr = virt_to_bus(&(entry->descriptor));
1763 reg_split(desc_ptr, &(prev->descriptor.dnlau),
1764 &(prev->descriptor.dnlal));
1765 }
1766
1767 return 0;
1768
1769err_dest:
1770err_source:
1771err_align:
1772 kfree(entry);
1773err_mem:
1774 return retval;
1775}
1776
1777/*
1778 * Check to see if the provided DMA channel is busy.
1779 */
1780static int tsi148_dma_busy(int channel)
1781{
1782 u32 tmp;
1783
1784 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
1785 TSI148_LCSR_OFFSET_DSTA);
1786
1787 if (tmp & TSI148_LCSR_DSTA_BSY)
1788 return 0;
1789 else
1790 return 1;
1791
1792}
1793
1794/*
1795 * Execute a previously generated link list
1796 *
1797 * XXX Need to provide control register configuration.
1798 */
1799int tsi148_dma_list_exec(struct vme_dma_list *list)
1800{
1801 struct vme_dma_resource *ctrlr;
1802 int channel, retval = 0;
1803 struct tsi148_dma_entry *entry;
1804 dma_addr_t bus_addr;
1805 u32 bus_addr_high, bus_addr_low;
1806 u32 val, dctlreg = 0;
1807#if 0
1808 int x;
1809#endif
1810
1811 ctrlr = list->parent;
1812
400822fe 1813 mutex_lock(&(ctrlr->mtx));
d22b8ed9
MW		 1814
1815 channel = ctrlr->number;
1816
1817 if (! list_empty(&(ctrlr->running))) {
1818 /*
1819 * XXX We have an active DMA transfer and currently haven't
1820 * sorted out the mechanism for "pending" DMA transfers.
1821 * Return busy.
1822 */
1823 /* Need to add to pending here */
400822fe 1824 mutex_unlock(&(ctrlr->mtx));
d22b8ed9
MW		 1825 return -EBUSY;
1826 } else {
1827 list_add(&(list->list), &(ctrlr->running));
1828 }
1829#if 0
1830 /* XXX Still todo */
1831 for (x = 0; x < 8; x++) { /* vme block size */
1832 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
1833 break;
1834 }
1835 }
1836 if (x == 8)
1837 x = 7;
1838 dctlreg |= (x << 12);
1839
1840 for (x = 0; x < 8; x++) { /* pci block size */
1841 if ((32 << x) >= vmeDma->maxPciBlockSize) {
1842 break;
1843 }
1844 }
1845 if (x == 8)
1846 x = 7;
1847 dctlreg |= (x << 4);
1848
1849 if (vmeDma->vmeBackOffTimer) {
1850 for (x = 1; x < 8; x++) { /* vme timer */
1851 if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
1852 break;
1853 }
1854 }
1855 if (x == 8)
1856 x = 7;
1857 dctlreg |= (x << 8);
1858 }
1859
1860 if (vmeDma->pciBackOffTimer) {
1861 for (x = 1; x < 8; x++) { /* pci timer */
1862 if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
1863 break;
1864 }
1865 }
1866 if (x == 8)
1867 x = 7;
1868 dctlreg |= (x << 0);
1869 }
1870#endif
1871
1872 /* Get first bus address and write into registers */
1873 entry = list_first_entry(&(list->entries), struct tsi148_dma_entry,
1874 list);
1875
1876 bus_addr = virt_to_bus(&(entry->descriptor));
1877
400822fe 1878 mutex_unlock(&(ctrlr->mtx));
d22b8ed9
MW		 1879
1880 reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1881
1882 iowrite32be(bus_addr_high, tsi148_bridge->base +
1883 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1884 iowrite32be(bus_addr_low, tsi148_bridge->base +
1885 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1886
1887 /* Start the operation */
1888 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, tsi148_bridge->base +
1889 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1890
1891 wait_event_interruptible(dma_queue[channel], tsi148_dma_busy(channel));
1892 /*
1893 * Read status register, this register is valid until we kick off a
1894 * new transfer.
1895 */
1896 val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
1897 TSI148_LCSR_OFFSET_DSTA);
1898
1899 if (val & TSI148_LCSR_DSTA_VBE) {
1900 printk(KERN_ERR "tsi148: DMA Error. DSTA=%08X\n", val);
1901 retval = -EIO;
1902 }
1903
1904 /* Remove list from running list */
400822fe 1905 mutex_lock(&(ctrlr->mtx));
d22b8ed9 1906 list_del(&(list->list));
400822fe 1907 mutex_unlock(&(ctrlr->mtx));
d22b8ed9
MW		 1908
1909 return retval;
1910}
1911
1912/*
1913 * Clean up a previously generated link list
1914 *
1915 * We have a separate function, don't assume that the chain can't be reused.
1916 */
1917int tsi148_dma_list_empty(struct vme_dma_list *list)
1918{
1919 struct list_head *pos, *temp;
1920 struct tsi148_dma_entry *entry;
1921
1922 /* detach and free each entry */
1923 list_for_each_safe(pos, temp, &(list->entries)) {
1924 list_del(pos);
1925 entry = list_entry(pos, struct tsi148_dma_entry, list);
1926 kfree(entry);
1927 }
1928
1929 return (0);
1930}
1931
1932/*
1933 * All 4 location monitors reside at the same base - this is therefore a
1934 * system wide configuration.
1935 *
1936 * This does not enable the LM monitor - that should be done when the first
1937 * callback is attached and disabled when the last callback is removed.
1938 */
42fb5031
MW		 1939int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1940 vme_address_t aspace, vme_cycle_t cycle)
d22b8ed9
MW		 1941{
1942 u32 lm_base_high, lm_base_low, lm_ctl = 0;
1943 int i;
1944
42fb5031 1945 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 1946
1947 /* If we already have a callback attached, we can't move it! */
42fb5031 1948 for (i = 0; i < lm->monitors; i++) {
d22b8ed9 1949 if(lm_callback[i] != NULL) {
42fb5031 1950 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 1951 printk("Location monitor callback attached, can't "
1952 "reset\n");
1953 return -EBUSY;
1954 }
1955 }
1956
1957 switch (aspace) {
1958 case VME_A16:
1959 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
1960 break;
1961 case VME_A24:
1962 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
1963 break;
1964 case VME_A32:
1965 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
1966 break;
1967 case VME_A64:
1968 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
1969 break;
1970 default:
42fb5031 1971 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 1972 printk("Invalid address space\n");
1973 return -EINVAL;
1974 break;
1975 }
1976
1977 if (cycle & VME_SUPER)
1978 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
1979 if (cycle & VME_USER)
1980 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
1981 if (cycle & VME_PROG)
1982 lm_ctl |= TSI148_LCSR_LMAT_PGM;
1983 if (cycle & VME_DATA)
1984 lm_ctl |= TSI148_LCSR_LMAT_DATA;
1985
1986 reg_split(lm_base, &lm_base_high, &lm_base_low);
1987
1988 iowrite32be(lm_base_high, tsi148_bridge->base + TSI148_LCSR_LMBAU);
1989 iowrite32be(lm_base_low, tsi148_bridge->base + TSI148_LCSR_LMBAL);
1990 iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT);
1991
42fb5031 1992 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 1993
1994 return 0;
1995}
1996
1997/* Get configuration of the callback monitor and return whether it is enabled
1998 * or disabled.
1999 */
42fb5031
MW		 2000int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
2001 vme_address_t *aspace, vme_cycle_t *cycle)
d22b8ed9
MW		 2002{
2003 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
2004
42fb5031 2005 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 2006
2007 lm_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAU);
2008 lm_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAL);
2009 lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2010
2011 reg_join(lm_base_high, lm_base_low, lm_base);
2012
2013 if (lm_ctl & TSI148_LCSR_LMAT_EN)
2014 enabled = 1;
2015
2016 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) {
2017 *aspace |= VME_A16;
2018 }
2019 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) {
2020 *aspace |= VME_A24;
2021 }
2022 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) {
2023 *aspace |= VME_A32;
2024 }
2025 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) {
2026 *aspace |= VME_A64;
2027 }
2028
2029 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2030 *cycle |= VME_SUPER;
2031 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2032 *cycle |= VME_USER;
2033 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2034 *cycle |= VME_PROG;
2035 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2036 *cycle |= VME_DATA;
2037
42fb5031 2038 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2039
2040 return enabled;
2041}
2042
2043/*
2044 * Attach a callback to a specific location monitor.
2045 *
2046 * Callback will be passed the monitor triggered.
2047 */
42fb5031
MW		 2048int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2049 void (*callback)(int))
d22b8ed9
MW		 2050{
2051 u32 lm_ctl, tmp;
2052
42fb5031 2053 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 2054
2055 /* Ensure that the location monitor is configured - need PGM or DATA */
2056 lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2057 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
42fb5031 2058 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2059 printk("Location monitor not properly configured\n");
2060 return -EINVAL;
2061 }
2062
2063 /* Check that a callback isn't already attached */
2064 if (lm_callback[monitor] != NULL) {
42fb5031 2065 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2066 printk("Existing callback attached\n");
2067 return -EBUSY;
2068 }
2069
2070 /* Attach callback */
2071 lm_callback[monitor] = callback;
2072
2073 /* Enable Location Monitor interrupt */
2074 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
2075 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2076 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
2077
2078 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
2079 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2080 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
2081
2082 /* Ensure that global Location Monitor Enable set */
2083 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2084 lm_ctl |= TSI148_LCSR_LMAT_EN;
2085 iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT);
2086 }
2087
42fb5031 2088 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2089
2090 return 0;
2091}
2092
2093/*
2094 * Detach a callback function forn a specific location monitor.
2095 */
42fb5031 2096int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
d22b8ed9
MW		 2097{
2098 u32 lm_en, tmp;
2099
42fb5031 2100 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 2101
2102 /* Disable Location Monitor and ensure previous interrupts are clear */
2103 lm_en = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
2104 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2105 iowrite32be(lm_en, tsi148_bridge->base + TSI148_LCSR_INTEN);
2106
2107 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
2108 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2109 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
2110
2111 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2112 tsi148_bridge->base + TSI148_LCSR_INTEO);
2113
2114 /* Detach callback */
2115 lm_callback[monitor] = NULL;
2116
2117 /* If all location monitors disabled, disable global Location Monitor */
2118 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2119 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2120 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2121 tmp &= ~TSI148_LCSR_LMAT_EN;
2122 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_LMAT);
2123 }
2124
42fb5031 2125 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2126
2127 return 0;
2128}
2129
2130/*
2131 * Determine Geographical Addressing
2132 */
2133int tsi148_slot_get(void)
2134{
2135 u32 slot = 0;
2136
2137 slot = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2138 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2139 return (int)slot;
2140}
2141
2142static int __init tsi148_init(void)
2143{
2144 return pci_register_driver(&tsi148_driver);
2145}
2146
2147/*
2148 * Configure CR/CSR space
2149 *
2150 * Access to the CR/CSR can be configured at power-up. The location of the
2151 * CR/CSR registers in the CR/CSR address space is determined by the boards
2152 * Auto-ID or Geographic address. This function ensures that the window is
2153 * enabled at an offset consistent with the boards geopgraphic address.
2154 *
2155 * Each board has a 512kB window, with the highest 4kB being used for the
2156 * boards registers, this means there is a fix length 508kB window which must
2157 * be mapped onto PCI memory.
2158 */
2159static int tsi148_crcsr_init(struct pci_dev *pdev)
2160{
2161 u32 cbar, crat, vstat;
2162 u32 crcsr_bus_high, crcsr_bus_low;
2163 int retval;
2164
2165 /* Allocate mem for CR/CSR image */
2166 crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2167 &crcsr_bus);
2168 if (crcsr_kernel == NULL) {
2169 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
2170 "image\n");
2171 return -ENOMEM;
2172 }
2173
2174 memset(crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2175
2176 reg_split(crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2177
2178 iowrite32be(crcsr_bus_high, tsi148_bridge->base + TSI148_LCSR_CROU);
2179 iowrite32be(crcsr_bus_low, tsi148_bridge->base + TSI148_LCSR_CROL);
2180
2181 /* Ensure that the CR/CSR is configured at the correct offset */
2182 cbar = ioread32be(tsi148_bridge->base + TSI148_CBAR);
2183 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2184
2185 vstat = tsi148_slot_get();
2186
2187 if (cbar != vstat) {
2188 dev_info(&pdev->dev, "Setting CR/CSR offset\n");
2189 iowrite32be(cbar<<3, tsi148_bridge->base + TSI148_CBAR);
2190 }
2191 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", cbar);
2192
2193 crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT);
2194 if (crat & TSI148_LCSR_CRAT_EN) {
2195 dev_info(&pdev->dev, "Enabling CR/CSR space\n");
2196 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2197 tsi148_bridge->base + TSI148_LCSR_CRAT);
2198 } else
2199 dev_info(&pdev->dev, "CR/CSR already enabled\n");
2200
2201 /* If we want flushed, error-checked writes, set up a window
2202 * over the CR/CSR registers. We read from here to safely flush
2203 * through VME writes.
2204 */
2205 if(err_chk) {
2206 retval = tsi148_master_set(flush_image, 1, (vstat * 0x80000),
2207 0x80000, VME_CRCSR, VME_SCT, VME_D16);
2208 if (retval)
2209 dev_err(&pdev->dev, "Configuring flush image failed\n");
2210 }
2211
2212 return 0;
2213
2214}
2215
2216static void tsi148_crcsr_exit(struct pci_dev *pdev)
2217{
2218 u32 crat;
2219
2220 /* Turn off CR/CSR space */
2221 crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT);
2222 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2223 tsi148_bridge->base + TSI148_LCSR_CRAT);
2224
2225 /* Free image */
2226 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROU);
2227 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROL);
2228
2229 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, crcsr_kernel, crcsr_bus);
2230}
2231
2232static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2233{
2234 int retval, i, master_num;
2235 u32 data;
2236 struct list_head *pos = NULL;
2237 struct vme_master_resource *master_image;
2238 struct vme_slave_resource *slave_image;
2239 struct vme_dma_resource *dma_ctrlr;
42fb5031 2240 struct vme_lm_resource *lm;
d22b8ed9
MW		 2241
2242 /* If we want to support more than one of each bridge, we need to
2243 * dynamically generate this so we get one per device
2244 */
2245 tsi148_bridge = (struct vme_bridge *)kmalloc(sizeof(struct vme_bridge),
2246 GFP_KERNEL);
2247 if (tsi148_bridge == NULL) {
2248 dev_err(&pdev->dev, "Failed to allocate memory for device "
2249 "structure\n");
2250 retval = -ENOMEM;
2251 goto err_struct;
2252 }
2253
2254 memset(tsi148_bridge, 0, sizeof(struct vme_bridge));
2255
2256 /* Enable the device */
2257 retval = pci_enable_device(pdev);
2258 if (retval) {
2259 dev_err(&pdev->dev, "Unable to enable device\n");
2260 goto err_enable;
2261 }
2262
2263 /* Map Registers */
2264 retval = pci_request_regions(pdev, driver_name);
2265 if (retval) {
2266 dev_err(&pdev->dev, "Unable to reserve resources\n");
2267 goto err_resource;
2268 }
2269
2270 /* map registers in BAR 0 */
2271 tsi148_bridge->base = ioremap_nocache(pci_resource_start(pdev, 0), 4096);
2272 if (!tsi148_bridge->base) {
2273 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2274 retval = -EIO;
2275 goto err_remap;
2276 }
2277
2278 /* Check to see if the mapping worked out */
2279 data = ioread32(tsi148_bridge->base + TSI148_PCFS_ID) & 0x0000FFFF;
2280 if (data != PCI_VENDOR_ID_TUNDRA) {
2281 dev_err(&pdev->dev, "CRG region check failed\n");
2282 retval = -EIO;
2283 goto err_test;
2284 }
2285
2286 /* Initialize wait queues & mutual exclusion flags */
2287 /* XXX These need to be moved to the vme_bridge structure */
2288 init_waitqueue_head(&dma_queue[0]);
2289 init_waitqueue_head(&dma_queue[1]);
2290 init_waitqueue_head(&iack_queue);
400822fe 2291 mutex_init(&(vme_int));
400822fe 2292 mutex_init(&(vme_rmw));
d22b8ed9
MW		 2293
2294 tsi148_bridge->parent = &(pdev->dev);
2295 strcpy(tsi148_bridge->name, driver_name);
2296
2297 /* Setup IRQ */
2298 retval = tsi148_irq_init(tsi148_bridge);
2299 if (retval != 0) {
2300 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2301 goto err_irq;
2302 }
2303
2304 /* If we are going to flush writes, we need to read from the VME bus.
2305 * We need to do this safely, thus we read the devices own CR/CSR
2306 * register. To do this we must set up a window in CR/CSR space and
2307 * hence have one less master window resource available.
2308 */
2309 master_num = TSI148_MAX_MASTER;
2310 if(err_chk){
2311 master_num--;
2312 /* XXX */
2313 flush_image = (struct vme_master_resource *)kmalloc(
2314 sizeof(struct vme_master_resource), GFP_KERNEL);
2315 if (flush_image == NULL) {
2316 dev_err(&pdev->dev, "Failed to allocate memory for "
2317 "flush resource structure\n");
2318 retval = -ENOMEM;
2319 goto err_master;
2320 }
2321 flush_image->parent = tsi148_bridge;
2322 spin_lock_init(&(flush_image->lock));
2323 flush_image->locked = 1;
2324 flush_image->number = master_num;
2325 flush_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2326 VME_A64;
2327 flush_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2328 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2329 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2330 VME_PROG | VME_DATA;
2331 flush_image->width_attr = VME_D16 | VME_D32;
2332 memset(&(flush_image->pci_resource), 0,
2333 sizeof(struct resource));
2334 flush_image->kern_base = NULL;
2335 }
2336
2337 /* Add master windows to list */
2338 INIT_LIST_HEAD(&(tsi148_bridge->master_resources));
2339 for (i = 0; i < master_num; i++) {
2340 master_image = (struct vme_master_resource *)kmalloc(
2341 sizeof(struct vme_master_resource), GFP_KERNEL);
2342 if (master_image == NULL) {
2343 dev_err(&pdev->dev, "Failed to allocate memory for "
2344 "master resource structure\n");
2345 retval = -ENOMEM;
2346 goto err_master;
2347 }
2348 master_image->parent = tsi148_bridge;
2349 spin_lock_init(&(master_image->lock));
2350 master_image->locked = 0;
2351 master_image->number = i;
2352 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2353 VME_A64;
2354 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2355 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2356 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2357 VME_PROG | VME_DATA;
2358 master_image->width_attr = VME_D16 | VME_D32;
2359 memset(&(master_image->pci_resource), 0,
2360 sizeof(struct resource));
2361 master_image->kern_base = NULL;
2362 list_add_tail(&(master_image->list),
2363 &(tsi148_bridge->master_resources));
2364 }
2365
2366 /* Add slave windows to list */
2367 INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));
2368 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2369 slave_image = (struct vme_slave_resource *)kmalloc(
2370 sizeof(struct vme_slave_resource), GFP_KERNEL);
2371 if (slave_image == NULL) {
2372 dev_err(&pdev->dev, "Failed to allocate memory for "
2373 "slave resource structure\n");
2374 retval = -ENOMEM;
2375 goto err_slave;
2376 }
2377 slave_image->parent = tsi148_bridge;
400822fe 2378 mutex_init(&(slave_image->mtx));
d22b8ed9
MW		 2379 slave_image->locked = 0;
2380 slave_image->number = i;
2381 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2382 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2383 VME_USER3 | VME_USER4;
2384 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2385 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2386 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2387 VME_PROG | VME_DATA;
2388 list_add_tail(&(slave_image->list),
2389 &(tsi148_bridge->slave_resources));
2390 }
2391
2392 /* Add dma engines to list */
2393 INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));
2394 for (i = 0; i < TSI148_MAX_DMA; i++) {
2395 dma_ctrlr = (struct vme_dma_resource *)kmalloc(
2396 sizeof(struct vme_dma_resource), GFP_KERNEL);
2397 if (dma_ctrlr == NULL) {
2398 dev_err(&pdev->dev, "Failed to allocate memory for "
2399 "dma resource structure\n");
2400 retval = -ENOMEM;
2401 goto err_dma;
2402 }
2403 dma_ctrlr->parent = tsi148_bridge;
400822fe 2404 mutex_init(&(dma_ctrlr->mtx));
d22b8ed9
MW		 2405 dma_ctrlr->locked = 0;
2406 dma_ctrlr->number = i;
2407 INIT_LIST_HEAD(&(dma_ctrlr->pending));
2408 INIT_LIST_HEAD(&(dma_ctrlr->running));
2409 list_add_tail(&(dma_ctrlr->list),
2410 &(tsi148_bridge->dma_resources));
2411 }
2412
42fb5031
MW		 2413 /* Add location monitor to list */
2414 INIT_LIST_HEAD(&(tsi148_bridge->lm_resources));
2415 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2416 if (lm == NULL) {
2417 dev_err(&pdev->dev, "Failed to allocate memory for "
2418 "location monitor resource structure\n");
2419 retval = -ENOMEM;
2420 goto err_lm;
2421 }
2422 lm->parent = tsi148_bridge;
2423 mutex_init(&(lm->mtx));
2424 lm->locked = 0;
2425 lm->number = 1;
2426 lm->monitors = 4;
2427 list_add_tail(&(lm->list), &(tsi148_bridge->lm_resources));
2428
d22b8ed9
MW		 2429 tsi148_bridge->slave_get = tsi148_slave_get;
2430 tsi148_bridge->slave_set = tsi148_slave_set;
2431 tsi148_bridge->master_get = tsi148_master_get;
2432 tsi148_bridge->master_set = tsi148_master_set;
2433 tsi148_bridge->master_read = tsi148_master_read;
2434 tsi148_bridge->master_write = tsi148_master_write;
2435 tsi148_bridge->master_rmw = tsi148_master_rmw;
2436 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2437 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2438 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
c813f592
MW		 2439 tsi148_bridge->irq_set = tsi148_irq_set;
2440 tsi148_bridge->irq_generate = tsi148_irq_generate;
d22b8ed9
MW		 2441 tsi148_bridge->lm_set = tsi148_lm_set;
2442 tsi148_bridge->lm_get = tsi148_lm_get;
2443 tsi148_bridge->lm_attach = tsi148_lm_attach;
2444 tsi148_bridge->lm_detach = tsi148_lm_detach;
2445 tsi148_bridge->slot_get = tsi148_slot_get;
2446
2447 data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2448 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2449 (data & TSI148_LCSR_VSTAT_SCONS)? "" : " not");
2450 dev_info(&pdev->dev, "VME geographical address is %d\n",
2451 data & TSI148_LCSR_VSTAT_GA_M);
2452 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2453 err_chk ? "enabled" : "disabled");
2454
2455 if(tsi148_crcsr_init(pdev)) {
2456 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2457 goto err_crcsr;
2458
2459 }
2460
2461 /* Need to save tsi148_bridge pointer locally in link list for use in
2462 * tsi148_remove()
2463 */
2464 retval = vme_register_bridge(tsi148_bridge);
2465 if (retval != 0) {
2466 dev_err(&pdev->dev, "Chip Registration failed.\n");
2467 goto err_reg;
2468 }
2469
2470 /* Clear VME bus "board fail", and "power-up reset" lines */
2471 data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2472 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2473 data |= TSI148_LCSR_VSTAT_CPURST;
2474 iowrite32be(data, tsi148_bridge->base + TSI148_LCSR_VSTAT);
2475
2476 return 0;
2477
2478 vme_unregister_bridge(tsi148_bridge);
2479err_reg:
2480 tsi148_crcsr_exit(pdev);
2481err_crcsr:
42fb5031
MW		 2482err_lm:
2483 /* resources are stored in link list */
2484 list_for_each(pos, &(tsi148_bridge->lm_resources)) {
2485 lm = list_entry(pos, struct vme_lm_resource, list);
2486 list_del(pos);
2487 kfree(lm);
2488 }
d22b8ed9
MW		 2489err_dma:
2490 /* resources are stored in link list */
2491 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2492 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2493 list_del(pos);
2494 kfree(dma_ctrlr);
2495 }
2496err_slave:
2497 /* resources are stored in link list */
2498 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2499 slave_image = list_entry(pos, struct vme_slave_resource, list);
2500 list_del(pos);
2501 kfree(slave_image);
2502 }
2503err_master:
2504 /* resources are stored in link list */
2505 list_for_each(pos, &(tsi148_bridge->master_resources)) {
2506 master_image = list_entry(pos, struct vme_master_resource, list);
2507 list_del(pos);
2508 kfree(master_image);
2509 }
2510
2511 tsi148_irq_exit(pdev);
2512err_irq:
2513err_test:
2514 iounmap(tsi148_bridge->base);
2515err_remap:
2516 pci_release_regions(pdev);
2517err_resource:
2518 pci_disable_device(pdev);
2519err_enable:
2520 kfree(tsi148_bridge);
2521err_struct:
2522 return retval;
2523
2524}
2525
2526static void tsi148_remove(struct pci_dev *pdev)
2527{
2528 struct list_head *pos = NULL;
2529 struct vme_master_resource *master_image;
2530 struct vme_slave_resource *slave_image;
2531 struct vme_dma_resource *dma_ctrlr;
2532 int i;
2533
2534 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2535
2536 /* XXX We need to find the pdev->dev in the list of vme_bridge->dev's */
2537
2538 /*
2539 * Shutdown all inbound and outbound windows.
2540 */
2541 for (i = 0; i < 8; i++) {
2542 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_IT[i] +
2543 TSI148_LCSR_OFFSET_ITAT);
2544 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_OT[i] +
2545 TSI148_LCSR_OFFSET_OTAT);
2546 }
2547
2548 /*
2549 * Shutdown Location monitor.
2550 */
2551 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_LMAT);
2552
2553 /*
2554 * Shutdown CRG map.
2555 */
2556 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CSRAT);
2557
2558 /*
2559 * Clear error status.
2560 */
2561 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_EDPAT);
2562 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_VEAT);
2563 iowrite32be(0x07000700, tsi148_bridge->base + TSI148_LCSR_PSTAT);
2564
2565 /*
2566 * Remove VIRQ interrupt (if any)
2567 */
2568 if (ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR) & 0x800) {
2569 iowrite32be(0x8000, tsi148_bridge->base + TSI148_LCSR_VICR);
2570 }
2571
2572 /*
2573 * Disable and clear all interrupts.
2574 */
2575 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEO);
2576 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTC);
2577 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTEN);
2578
2579 /*
2580 * Map all Interrupts to PCI INTA
2581 */
2582 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM1);
2583 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM2);
2584
2585 tsi148_irq_exit(pdev);
2586
2587 vme_unregister_bridge(tsi148_bridge);
2588
2589 tsi148_crcsr_exit(pdev);
2590
2591 /* resources are stored in link list */
2592 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2593 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2594 list_del(pos);
2595 kfree(dma_ctrlr);
2596 }
2597
2598 /* resources are stored in link list */
2599 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2600 slave_image = list_entry(pos, struct vme_slave_resource, list);
2601 list_del(pos);
2602 kfree(slave_image);
2603 }
2604
2605 /* resources are stored in link list */
2606 list_for_each(pos, &(tsi148_bridge->master_resources)) {
2607 master_image = list_entry(pos, struct vme_master_resource, list);
2608 list_del(pos);
2609 kfree(master_image);
2610 }
2611
2612 tsi148_irq_exit(pdev);
2613
2614 iounmap(tsi148_bridge->base);
2615
2616 pci_release_regions(pdev);
2617
2618 pci_disable_device(pdev);
2619
2620 kfree(tsi148_bridge);
2621}
2622
2623static void __exit tsi148_exit(void)
2624{
2625 pci_unregister_driver(&tsi148_driver);
2626
2627 printk(KERN_DEBUG "Driver removed.\n");
2628}
2629
2630MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2631module_param(err_chk, bool, 0);
2632
2633MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2634MODULE_LICENSE("GPL");
2635
2636module_init(tsi148_init);
2637module_exit(tsi148_exit);
2638
2639/*----------------------------------------------------------------------------
2640 * STAGING
2641 *--------------------------------------------------------------------------*/
2642
2643#if 0
2644/*
2645 * Direct Mode DMA transfer
2646 *
2647 * XXX Not looking at direct mode for now, we can always use link list mode
2648 * with a single entry.
2649 */
2650int tsi148_dma_run(struct vme_dma_resource *resource, struct vme_dma_attr src,
2651 struct vme_dma_attr dest, size_t count)
2652{
2653 u32 dctlreg = 0;
2654 unsigned int tmp;
2655 int val;
2656 int channel, x;
2657 struct vmeDmaPacket *cur_dma;
2658 struct tsi148_dma_descriptor *dmaLL;
2659
2660 /* direct mode */
2661 dctlreg = 0x800000;
2662
2663 for (x = 0; x < 8; x++) { /* vme block size */
2664 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
2665 break;
2666 }
2667 }
2668 if (x == 8)
2669 x = 7;
2670 dctlreg |= (x << 12);
2671
2672 for (x = 0; x < 8; x++) { /* pci block size */
2673 if ((32 << x) >= vmeDma->maxPciBlockSize) {
2674 break;
2675 }
2676 }
2677 if (x == 8)
2678 x = 7;
2679 dctlreg |= (x << 4);
2680
2681 if (vmeDma->vmeBackOffTimer) {
2682 for (x = 1; x < 8; x++) { /* vme timer */
2683 if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
2684 break;
2685 }
2686 }
2687 if (x == 8)
2688 x = 7;
2689 dctlreg |= (x << 8);
2690 }
2691
2692 if (vmeDma->pciBackOffTimer) {
2693 for (x = 1; x < 8; x++) { /* pci timer */
2694 if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
2695 break;
2696 }
2697 }
2698 if (x == 8)
2699 x = 7;
2700 dctlreg |= (x << 0);
2701 }
2702
2703 /* Program registers for DMA transfer */
2704 iowrite32be(dmaLL->dsau, tsi148_bridge->base +
2705 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAU);
2706 iowrite32be(dmaLL->dsal, tsi148_bridge->base +
2707 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAL);
2708 iowrite32be(dmaLL->ddau, tsi148_bridge->base +
2709 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAU);
2710 iowrite32be(dmaLL->ddal, tsi148_bridge->base +
2711 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAL);
2712 iowrite32be(dmaLL->dsat, tsi148_bridge->base +
2713 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAT);
2714 iowrite32be(dmaLL->ddat, tsi148_bridge->base +
2715 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAT);
2716 iowrite32be(dmaLL->dcnt, tsi148_bridge->base +
2717 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCNT);
2718 iowrite32be(dmaLL->ddbs, tsi148_bridge->base +
2719 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDBS);
2720
2721 /* Start the operation */
2722 iowrite32be(dctlreg | 0x2000000, tsi148_bridge->base +
2723 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
2724
2725 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
2726 TSI148_LCSR_OFFSET_DSTA);
2727 wait_event_interruptible(dma_queue[channel], (tmp & 0x1000000) == 0);
2728
2729 /*
2730 * Read status register, we should probably do this in some error
2731 * handler rather than here so that we can be sure we haven't kicked off
2732 * another DMA transfer.
2733 */
2734 val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
2735 TSI148_LCSR_OFFSET_DSTA);
2736
2737 vmeDma->vmeDmaStatus = 0;
2738 if (val & 0x10000000) {
2739 printk(KERN_ERR
2740 "DMA Error in DMA_tempe_irqhandler DSTA=%08X\n",
2741 val);
2742 vmeDma->vmeDmaStatus = val;
2743
2744 }
2745 return (0);
2746}
2747#endif
2748
2749#if 0
2750
2751/* Global VME controller information */
2752struct pci_dev *vme_pci_dev;
2753
2754/*
2755 * Set the VME bus arbiter with the requested attributes
2756 */
2757int tempe_set_arbiter(vmeArbiterCfg_t * vmeArb)
2758{
2759 int temp_ctl = 0;
2760 int gto = 0;
2761
2762 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL);
2763 temp_ctl &= 0xFFEFFF00;
2764
2765 if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) {
2766 gto = 8;
2767 } else if (vmeArb->globalTimeoutTimer > 2048) {
2768 return (-EINVAL);
2769 } else if (vmeArb->globalTimeoutTimer == 0) {
2770 gto = 0;
2771 } else {
2772 gto = 1;
2773 while ((16 * (1 << (gto - 1))) < vmeArb->globalTimeoutTimer) {
2774 gto += 1;
2775 }
2776 }
2777 temp_ctl |= gto;
2778
2779 if (vmeArb->arbiterMode != VME_PRIORITY_MODE) {
2780 temp_ctl |= 1 << 6;
2781 }
2782
2783 if (vmeArb->arbiterTimeoutFlag) {
2784 temp_ctl |= 1 << 7;
2785 }
2786
2787 if (vmeArb->noEarlyReleaseFlag) {
2788 temp_ctl |= 1 << 20;
2789 }
2790 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VCTRL);
2791
2792 return (0);
2793}
2794
2795/*
2796 * Return the attributes of the VME bus arbiter.
2797 */
2798int tempe_get_arbiter(vmeArbiterCfg_t * vmeArb)
2799{
2800 int temp_ctl = 0;
2801 int gto = 0;
2802
2803
2804 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL);
2805
2806 gto = temp_ctl & 0xF;
2807 if (gto != 0) {
2808 vmeArb->globalTimeoutTimer = (16 * (1 << (gto - 1)));
2809 }
2810
2811 if (temp_ctl & (1 << 6)) {
2812 vmeArb->arbiterMode = VME_R_ROBIN_MODE;
2813 } else {
2814 vmeArb->arbiterMode = VME_PRIORITY_MODE;
2815 }
2816
2817 if (temp_ctl & (1 << 7)) {
2818 vmeArb->arbiterTimeoutFlag = 1;
2819 }
2820
2821 if (temp_ctl & (1 << 20)) {
2822 vmeArb->noEarlyReleaseFlag = 1;
2823 }
2824
2825 return (0);
2826}
2827
2828/*
2829 * Set the VME bus requestor with the requested attributes
2830 */
2831int tempe_set_requestor(vmeRequesterCfg_t * vmeReq)
2832{
2833 int temp_ctl = 0;
2834
2835 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2836 temp_ctl &= 0xFFFF0000;
2837
2838 if (vmeReq->releaseMode == 1) {
2839 temp_ctl |= (1 << 3);
2840 }
2841
2842 if (vmeReq->fairMode == 1) {
2843 temp_ctl |= (1 << 2);
2844 }
2845
2846 temp_ctl |= (vmeReq->timeonTimeoutTimer & 7) << 8;
2847 temp_ctl |= (vmeReq->timeoffTimeoutTimer & 7) << 12;
2848 temp_ctl |= vmeReq->requestLevel;
2849
2850 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2851 return (0);
2852}
2853
2854/*
2855 * Return the attributes of the VME bus requestor
2856 */
2857int tempe_get_requestor(vmeRequesterCfg_t * vmeReq)
2858{
2859 int temp_ctl = 0;
2860
2861 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2862
2863 if (temp_ctl & 0x18) {
2864 vmeReq->releaseMode = 1;
2865 }
2866
2867 if (temp_ctl & (1 << 2)) {
2868 vmeReq->fairMode = 1;
2869 }
2870
2871 vmeReq->requestLevel = temp_ctl & 3;
2872 vmeReq->timeonTimeoutTimer = (temp_ctl >> 8) & 7;
2873 vmeReq->timeoffTimeoutTimer = (temp_ctl >> 12) & 7;
2874
2875 return (0);
2876}
2877
2878
2879#endif
Linux kernel - Deliverables
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