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Merge remote-tracking branch 'asoc/topic/dapm' into asoc-next
[deliverable/linux.git] / drivers / staging / wlags49_h2 / hcfdef.h
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HG		 1#ifndef HCFDEFC_H
2#define HCFDEFC_H 1
3
4/*************************************************************************************************
fe4d2755
DK		 5 *
6 * FILE : HCFDEF.H
7 *
8 * DATE : $Date: 2004/08/05 11:47:10 $ $Revision: 1.8 $
9 * Original: 2004/05/28 14:05:35 Revision: 1.59 Tag: hcf7_t20040602_01
10 * Original: 2004/05/13 15:31:45 Revision: 1.53 Tag: hcf7_t7_20040513_01
11 * Original: 2004/04/15 09:24:42 Revision: 1.44 Tag: hcf7_t7_20040415_01
12 * Original: 2004/04/13 14:22:45 Revision: 1.43 Tag: t7_20040413_01
13 * Original: 2004/04/01 15:32:55 Revision: 1.40 Tag: t7_20040401_01
14 * Original: 2004/03/10 15:39:28 Revision: 1.36 Tag: t20040310_01
15 * Original: 2004/03/03 14:10:12 Revision: 1.34 Tag: t20040304_01
16 * Original: 2004/03/02 09:27:12 Revision: 1.32 Tag: t20040302_03
17 * Original: 2004/02/24 13:00:29 Revision: 1.29 Tag: t20040224_01
18 * Original: 2004/02/18 17:13:57 Revision: 1.26 Tag: t20040219_01
19 *
20 * AUTHOR : Nico Valster
21 *
22 * SPECIFICATION: ...........
23 *
24 * DESC : Definitions and Prototypes for HCF only
25 *
26 **************************************************************************************************
27 *
28 *
29 * SOFTWARE LICENSE
30 *
31 * This software is provided subject to the following terms and conditions,
32 * which you should read carefully before using the software. Using this
33 * software indicates your acceptance of these terms and conditions. If you do
34 * not agree with these terms and conditions, do not use the software.
35 *
d36b6910
AV		 36 * COPYRIGHT © 1994 - 1995 by AT&T. All Rights Reserved
37 * COPYRIGHT © 1996 - 2000 by Lucent Technologies. All Rights Reserved
38 * COPYRIGHT © 2001 - 2004 by Agere Systems Inc. All Rights Reserved
fe4d2755
DK		 39 * All rights reserved.
40 *
41 * Redistribution and use in source or binary forms, with or without
42 * modifications, are permitted provided that the following conditions are met:
43 *
44 * . Redistributions of source code must retain the above copyright notice, this
45 * list of conditions and the following Disclaimer as comments in the code as
46 * well as in the documentation and/or other materials provided with the
47 * distribution.
48 *
49 * . Redistributions in binary form must reproduce the above copyright notice,
50 * this list of conditions and the following Disclaimer in the documentation
51 * and/or other materials provided with the distribution.
52 *
53 * . Neither the name of Agere Systems Inc. nor the names of the contributors
54 * may be used to endorse or promote products derived from this software
55 * without specific prior written permission.
56 *
57 * Disclaimer
58 *
59 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
60 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
62 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
63 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
64 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
65 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
66 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
67 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
69 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
70 * DAMAGE.
71 *
72 *
73 *************************************************************************************************/
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HG		 74
75
76/************************************************************************************************/
77/********************************* P R E F I X E S ********************************************/
78/************************************************************************************************/
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DK		 79//IFB_ Interface Block
80//HCMD_ Hermes Command
81//HFS_ Hermes (Transmit/Receive) Frame Structure
82//HREG_ Hermes Register
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HG		 83
84/*************************************************************************************************/
85
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HG		 86/************************************************************************************************/
87/********************************* GENERAL EQUATES **********************************************/
88/************************************************************************************************/
89
90
fe4d2755 91#define HCF_MAGIC 0x7D37 // "}7" Handle validation
68c0bdff 92
fe4d2755 93#define PLUG_DATA_OFFSET 0x00000800 //needed by some test tool on top of H-II NDIS driver
68c0bdff 94
fe4d2755 95#define INI_TICK_INI 0x00040000L
68c0bdff 96
fe4d2755
DK		 97#define IO_IN 0 //hcfio_in_string
98#define IO_OUT 1 //hcfio_out_string
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HG		 99
100//DO_ASSERT, create an artificial FALSE to force an ASSERT without the nasty compiler warning
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DK		 101#define DO_ASSERT ( assert_ifbp->IFB_Magic != HCF_MAGIC && assert_ifbp->IFB_Magic == HCF_MAGIC )
102#define NT_ASSERT 0x0000 //, NEVER_TESTED
103#define NEVER_TESTED MERGE_2( 0xEFFE, 0xFEEF )
104#define SE_ASSERT 0x5EFF /* Side Effect, HCFASSERT invokation which are only called for the
105 * side effect and which should never trigger */
106#define DHF_FILE_NAME_OFFSET 10000 //to distinguish DHF from HCF asserts by means of line number
107#define MMD_FILE_NAME_OFFSET 20000 //to distinguish MMD from HCF asserts by means of line number
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HG		 108
109// trace codes used to
110// 1: profile execution times via HCF_TRACE and HCF_TRACE_VALUE
111// 2: hierarchical flow information via HCFLOGENTRY / HCFLOGEXIT
112
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DK		 113//#define HCF_TRACE_CONNECT useless
114//#define HCF_TRACE_DISCONNECT useless
115#define HCF_TRACE_ACTION 0x0000 // 0x0001
116#define HCF_TRACE_CNTL 0x0001 // 0x0002
117#define HCF_TRACE_DMA_RX_GET 0x0002 // 0x0004
118#define HCF_TRACE_DMA_RX_PUT 0x0003 // 0x0008
119#define HCF_TRACE_DMA_TX_GET 0x0004 // 0x0010
120#define HCF_TRACE_DMA_TX_PUT 0x0005 // 0x0020
121#define HCF_TRACE_GET_INFO 0x0006 // 0x0040
122#define HCF_TRACE_PUT_INFO 0x0007 // 0x0080
123#define HCF_TRACE_RCV_MSG 0x0008 // 0x0100
124#define HCF_TRACE_SEND_MSG 0x0009 // 0x0200
125#define HCF_TRACE_SERVICE_NIC 0x000A // 0x0400
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HG		 126// #define HCF_TRACE_ 0x000C // 0x1000
127// #define HCF_TRACE_ 0x000D // 0x2000
128// #define HCF_TRACE_ 0x000E // 0x4000
129// #define HCF_TRACE_ 0x000F // 0x8000
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DK		 130// ============================================ HCF_TRACE_... codes below 0x0010 are asserted on re-entry
131#define HCF_TRACE_ACTION_KLUDGE 0x0010 /* once you start introducing kludges there is no end to it
132 * this is an escape to do not assert on re-entrancy problem caused
133 * by HCF_ACT_INT_FORCE_ON used to get Microsofts NDIS drivers going
134 */
135#define HCF_TRACE_STRIO 0x0020
136#define HCF_TRACE_ALLOC 0X0021
137#define HCF_TRACE_DL 0X0023
138#define HCF_TRACE_ISR_INFO 0X0024
139#define HCF_TRACE_CALIBRATE 0x0026
140
141#define HCF_TRACE_CMD_CPL 0x0040
142#define HCF_TRACE_CMD_EXE 0x0041
143#define HCF_TRACE_GET_FID 0x0042
144#define HCF_TRACE_GET_FRAG 0x0043
145#define HCF_TRACE_INIT 0x0044
146#define HCF_TRACE_PUT_FRAG 0x0045
147#define HCF_TRACE_SETUP_BAP 0x0046
148
149#define HCF_TRACE_EXIT 0x8000 // Keil C warns "long constant truncated to int"
150
151//#define BAP_0 HREG_DATA_0 //Used by DMA controller to access NIC RAM
152#define BAP_1 HREG_DATA_1 //Used by HCF to access NIC RAM
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HG		 153
154
155//************************* Hermes Receive/Transmit Frame Structures
156//HFS_STAT
157//see MMD.H for HFS_STAT_ERR
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DK		 158#define HFS_STAT_MSG_TYPE 0xE000 //Hermes reported Message Type
159#define HFS_STAT_MIC_KEY_ID 0x1800 //MIC key used (if any)
160#define HFS_STAT_1042 0x2000 //RFC1042 Encoded
161#define HFS_STAT_TUNNEL 0x4000 //Bridge-Tunnel Encoded
162#define HFS_STAT_WMP_MSG 0x6000 //WaveLAN-II Management Protocol Frame
68c0bdff 163#if (HCF_TYPE) & HCF_TYPE_WPA
fe4d2755 164#define HFS_STAT_MIC 0x0010 //Frame contains MIC //;? re-instate when F/W ready
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HG		 165#endif
166
167//************************* Hermes Register Offsets and Command bits
fe4d2755 168#define HREG_IO_RANGE 0x80 //I/O Range used by Hermes
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HG		 169
170
171//************************* Command/Status
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DK		 172#define HREG_CMD 0x00 //
173#define HCMD_CMD_CODE 0x3F
174#define HREG_PARAM_0 0x02 //
175#define HREG_PARAM_1 0x04 //
176#define HREG_PARAM_2 0x06 //
177#define HREG_STAT 0x08 //
178#define HREG_STAT_CMD_CODE 0x003F //
179#define HREG_STAT_DIAG_ERR 0x0100
180#define HREG_STAT_INQUIRE_ERR 0x0500
181#define HREG_STAT_CMD_RESULT 0x7F00 //
182#define HREG_RESP_0 0x0A //
183#define HREG_RESP_1 0x0C //
184#define HREG_RESP_2 0x0E //
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HG		 185
186
187//************************* FID Management
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DK		 188#define HREG_INFO_FID 0x10 //
189#define HREG_RX_FID 0x20 //
190#define HREG_ALLOC_FID 0x22 //
191#define HREG_TX_COMPL_FID 0x24 //
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HG		 192
193
194//************************* BAP
195//20031030 HWi Inserted this again because the dongle code uses this (GPIF.C)
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DK		 196//#define HREG_SELECT_0 0x18 //
197//#define HREG_OFFSET_0 0x1C //
198//#define HREG_DATA_0 0x36 //
68c0bdff 199
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DK		 200//#define HREG_OFFSET_BUSY 0x8000 // use HCMD_BUSY
201#define HREG_OFFSET_ERR 0x4000 //
202//rsrvd #define HREG_OFFSET_DATA_OFFSET 0x0FFF //
68c0bdff 203
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DK		 204#define HREG_SELECT_1 0x1A //
205#define HREG_OFFSET_1 0x1E //
206#define HREG_DATA_1 0x38 //
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HG		 207
208
209//************************* Event
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DK		 210#define HREG_EV_STAT 0x30 //
211#define HREG_INT_EN 0x32 //
212#define HREG_EV_ACK 0x34 //
68c0bdff 213
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DK		 214#define HREG_EV_TICK 0x8000 //Auxiliary Timer Tick
215//#define HREG_EV_RES 0x4000 //H-I only: H/W error (Wait Time-out)
216#define HREG_EV_INFO_DROP 0x2000 //WMAC did not have sufficient RAM to build Unsollicited Frame
68c0bdff 217#if (HCF_TYPE) & HCF_TYPE_HII5
fe4d2755 218#define HREG_EV_ACK_REG_READY 0x0000
68c0bdff 219#else
fe4d2755 220#define HREG_EV_ACK_REG_READY 0x1000 //Workaround Kludge bit for H-II (not H-II.5)
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HG		 221#endif // HCF_TYPE_HII5
222#if (HCF_SLEEP) & ( HCF_CDS | HCF_DDS )
fe4d2755 223#define HREG_EV_SLEEP_REQ 0x0800
68c0bdff 224#else
fe4d2755 225#define HREG_EV_SLEEP_REQ 0x0000
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HG		 226#endif // HCF_CDS / HCF_DDS
227#if HCF_DMA
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DK		 228//#define HREG_EV_LPESC 0x0400 // firmware sets this bit and clears it, not for host usage.
229#define HREG_EV_RDMAD 0x0200 // rx frame in host memory
230#define HREG_EV_TDMAD 0x0100 // tx frame in host memory processed
231//#define HREG_EV_RXDMA 0x0040 // firmware kicks off DMA engine (bit is not for host usage)
232//#define HREG_EV_TXDMA 0x0020 // firmware kicks off DMA engine (bit is not for host usage)
233#define HREG_EV_FW_DMA 0x0460 // firmware / DMA engine I/F (bits are not for host usage)
68c0bdff 234#else
fe4d2755 235#define HREG_EV_FW_DMA 0x0000
68c0bdff 236#endif // HCF_DMA
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DK		 237#define HREG_EV_INFO 0x0080 // Asynchronous Information Frame
238#define HREG_EV_CMD 0x0010 // Command completed, Status and Response available
239#define HREG_EV_ALLOC 0x0008 // Asynchronous part of Allocation/Reclaim completed
240#define HREG_EV_TX_EXC 0x0004 // Asynchronous Transmission unsuccessful completed
241#define HREG_EV_TX 0x0002 // Asynchronous Transmission successful completed
242#define HREG_EV_RX 0x0001 // Asynchronous Receive Frame
243
244#define HREG_EV_TX_EXT ( (HCF_EXT) & (HCF_EXT_INT_TX_EX | HCF_EXT_INT_TICK ) )
245/* HREG_EV_TX_EXT := 0x0000 or HREG_EV_TX_EXC and/or HREG_EV_TICK
246 * could be extended with HREG_EV_TX */
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HG		 247#if HCF_EXT_INT_TX_EX != HREG_EV_TX_EXC
248err: these values should match;
249#endif // HCF_EXT_INT_TX_EX / HREG_EV_TX_EXC
250
251#if HCF_EXT_INT_TICK != HREG_EV_TICK
252err: these values should match;
253#endif // HCF_EXT_INT_TICK / HREG_EV_TICK
254
255//************************* Host Software
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DK		 256#define HREG_SW_0 0x28 //
257#define HREG_SW_1 0x2A //
258#define HREG_SW_2 0x2C //
259//rsrvd #define HREG_SW_3 0x2E //
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HG		 260//************************* Control and Auxiliary Port
261
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DK		 262#define HREG_IO 0x12
263#define HREG_IO_SRESET 0x0001
264#define HREG_IO_WAKEUP_ASYNC 0x0002
265#define HREG_IO_WOKEN_UP 0x0004
266#define HREG_CNTL 0x14 //
267//#define HREG_CNTL_WAKEUP_SYNC 0x0001
268#define HREG_CNTL_AUX_ENA_STAT 0xC000
269#define HREG_CNTL_AUX_DIS_STAT 0x0000
270#define HREG_CNTL_AUX_ENA_CNTL 0x8000
271#define HREG_CNTL_AUX_DIS_CNTL 0x4000
272#define HREG_CNTL_AUX_DSD 0x2000
273#define HREG_CNTL_AUX_ENA (HREG_CNTL_AUX_ENA_CNTL | HREG_CNTL_AUX_DIS_CNTL )
274#define HREG_SPARE 0x16 //
275#define HREG_AUX_PAGE 0x3A //
276#define HREG_AUX_OFFSET 0x3C //
277#define HREG_AUX_DATA 0x3E //
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HG		 278
279#if HCF_DMA
280//************************* DMA (bus mastering)
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DK		 281// Be careful to use these registers only at a genuine 32 bits NIC
282// On 16 bits NICs, these addresses are mapped into the range 0x00 through 0x3F with all consequences
283// thereof, e.g. HREG_DMA_CTRL register maps to HREG_CMD.
284#define HREG_DMA_CTRL 0x0040
285#define HREG_TXDMA_PTR32 0x0044
286#define HREG_TXDMA_PRIO_PTR32 0x0048
287#define HREG_TXDMA_HIPRIO_PTR32 0x004C
288#define HREG_RXDMA_PTR32 0x0050
289#define HREG_CARDDETECT_1 0x007C // contains 7D37
290#define HREG_CARDDETECT_2 0x007E // contains 7DE7
291#define HREG_FREETIMER 0x0058
292#define HREG_DMA_RX_CNT 0x0026
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HG		 293
294/******************************************************************************
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DK		 295 * Defines for the bits in the DmaControl register (@40h)
296 ******************************************************************************/
297#define HREG_DMA_CTRL_RXHWEN 0x80000000 // high word enable bit
298#define HREG_DMA_CTRL_RXRESET 0x40000000 // tx dma init bit
299#define HREG_DMA_CTRL_RXBAP1 BIT29
300#define HREG_DMA_CTRL_RX_STALLED BIT28
301#define HREG_DMA_CTRL_RXAUTOACK_DMADONE BIT27 // no host involvement req. for TDMADONE event
302#define HREG_DMA_CTRL_RXAUTOACK_INFO BIT26 // no host involvement req. for alloc event
303#define HREG_DMA_CTRL_RXAUTOACK_DMAEN 0x02000000 // no host involvement req. for TxDMAen event
304#define HREG_DMA_CTRL_RXAUTOACK_RX 0x01000000 // no host involvement req. for tx event
305#define HREG_DMA_CTRL_RX_BUSY BIT23 // read only bit
306//#define HREG_DMA_CTRL_RX_RBUFCONT_PLAIN 0 // bits 21..20
307//#define HREG_DMA_CTRL_RX_MODE_PLAIN_DMA 0 // mode 0
308#define HREG_DMA_CTRL_RX_MODE_SINGLE_PACKET 0x00010000 // mode 1
309#define HREG_DMA_CTRL_RX_MODE_MULTI_PACKET 0x00020000 // mode 2
310//#define HREG_DMA_CTRL_RX_MODE_DISABLE (0x00020000|0x00010000) // disable tx dma engine
311#define HREG_DMA_CTRL_TXHWEN 0x8000 // low word enable bit
312#define HREG_DMA_CTRL_TXRESET 0x4000 // rx dma init bit
313#define HREG_DMA_CTRL_TXBAP1 BIT13
314#define HREG_DMA_CTRL_TXAUTOACK_DMADONE BIT11 // no host involvement req. for RxDMADONE event
315#define HREG_DMA_CTRL_TXAUTOACK_DMAEN 0x00000400 // no host involvement req. for RxDMAen event
316#define HREG_DMA_CTRL_TXAUTOACK_DMAALLOC 0x00000200 // no host involvement req. for info event
317#define HREG_DMA_CTRL_TXAUTOACK_TX 0x00000100 // no host involvement req. for rx event
318#define HREG_DMA_CTRL_TX_BUSY BIT7 // read only bit
319//#define HREG_DMA_CTRL_TX_TBUFCONT_PLAIN 0 // bits 6..5
320//#define HREG_DMA_CTRL_TX_MODE_PLAIN_DMA 0 // mode 0
321#define HREG_DMA_CTRL_TX_MODE_SINGLE_PACKET BIT0 // mode 1
322#define HREG_DMA_CTRL_TX_MODE_MULTI_PACKET 0x00000002 // mode 2
323//#define HREG_DMA_CTRL_TX_MODE_DISABLE (0x00000001|0x00000002) // disable tx dma engine
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HG		 324
325//configuration DWORD to configure DMA for mode2 operation, using BAP0 as the DMA BAP.
326#define DMA_CTRLSTAT_GO (HREG_DMA_CTRL_RXHWEN | HREG_DMA_CTRL_RX_MODE_MULTI_PACKET | \
327 HREG_DMA_CTRL_RXAUTOACK_DMAEN | HREG_DMA_CTRL_RXAUTOACK_RX | \
328 HREG_DMA_CTRL_TXHWEN | /*;?HREG_DMA_CTRL_TX_TBUFCONT_PLAIN |*/ \
fe4d2755 329 HREG_DMA_CTRL_TX_MODE_MULTI_PACKET | HREG_DMA_CTRL_TXAUTOACK_DMAEN | \
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HG		 330 HREG_DMA_CTRL_TXAUTOACK_DMAALLOC)
331
332//configuration DWORD to reset both the Tx and Rx DMA engines
333#define DMA_CTRLSTAT_RESET (HREG_DMA_CTRL_RXHWEN | HREG_DMA_CTRL_RXRESET | HREG_DMA_CTRL_TXHWEN | HREG_DMA_CTRL_TXRESET)
334
fe4d2755
DK		 335//#define DESC_DMA_OWNED 0x80000000 // BIT31
336#define DESC_DMA_OWNED 0x8000 // BIT31
337#define DESC_SOP 0x8000 // BIT15
338#define DESC_EOP 0x4000 // BIT14
68c0bdff 339
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DK		 340#define DMA_RX 0
341#define DMA_TX 1
68c0bdff 342
fe4d2755
DK		 343// #define IFB_RxFirstDesc IFB_FirstDesc[DMA_RX]
344// #define IFB_TxFirstDesc IFB_FirstDesc[DMA_TX]
345// #define IFB_RxLastDesc IFB_LastDesc[DMA_RX]
346// #define IFB_TxLastDesc IFB_LastDesc[DMA_TX]
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HG		 347
348#endif // HCF_DMA
349//
350/************************************************************************************************/
351/********************************** EQUATES ***************************************************/
352/************************************************************************************************/
353
354
355// Hermes Command Codes and Qualifier bits
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DK		 356#define HCMD_BUSY 0x8000 // Busy bit, applicable for all commands
357#define HCMD_INI 0x0000 //
358#define HCMD_ENABLE HCF_CNTL_ENABLE // 0x0001
359#define HCMD_DISABLE HCF_CNTL_DISABLE // 0x0002
360#define HCMD_CONNECT HCF_CNTL_CONNECT // 0x0003
361#define HCMD_EXECUTE 0x0004 //
362#define HCMD_DISCONNECT HCF_CNTL_DISCONNECT // 0x0005
363#define HCMD_SLEEP 0x0006 //
364#define HCMD_CONTINUE HCF_CNTL_CONTINUE // 0x0007
365#define HCMD_RETRY 0x0100 // Retry bit
366#define HCMD_ALLOC 0x000A //
367#define HCMD_TX 0x000B //
368#define HCMD_RECL 0x0100 // Reclaim bit, applicable for Tx and Inquire
369#define HCMD_INQUIRE 0x0011 //
370#define HCMD_ACCESS 0x0021 //
371#define HCMD_ACCESS_WRITE 0x0100 // Write bit
372#define HCMD_PROGRAM 0x0022 //
373#define HCMD_READ_MIF 0x0030
374#define HCMD_WRITE_MIF 0x0031
375#define HCMD_THESEUS 0x0038
376#define HCMD_STARTPREAMBLE 0x0E00 // Start continuous preamble Tx
377#define HCMD_STOP 0x0F00 // Stop Theseus test mode
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HG		 378
379
380//Configuration Management
381//
382
fe4d2755
DK		 383#define CFG_DRV_ACT_RANGES_PRI_3_BOTTOM 1 // Default Bottom Compatibility for Primary Firmware - driver I/F
384#define CFG_DRV_ACT_RANGES_PRI_3_TOP 1 // Default Top Compatibility for Primary Firmware - driver I/F
68c0bdff 385
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DK		 386#define CFG_DRV_ACT_RANGES_HSI_4_BOTTOM 1 // Default Bottom Compatibility for H/W - driver I/F
387#define CFG_DRV_ACT_RANGES_HSI_4_TOP 1 // Default Top Compatibility for H/W - driver I/F
68c0bdff 388
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DK		 389#define CFG_DRV_ACT_RANGES_HSI_5_BOTTOM 1 // Default Bottom Compatibility for H/W - driver I/F
390#define CFG_DRV_ACT_RANGES_HSI_5_TOP 1 // Default Top Compatibility for H/W - driver I/F
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HG		 391
392#if (HCF_TYPE) & HCF_TYPE_WPA
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DK		 393#define CFG_DRV_ACT_RANGES_APF_1_BOTTOM 16 // Default Bottom Compatibility for AP Firmware - driver I/F
394#define CFG_DRV_ACT_RANGES_APF_1_TOP 16 // Default Top Compatibility for AP Firmware - driver I/F
68c0bdff 395#else //;? is this REALLY O.K.
fe4d2755
DK		 396#define CFG_DRV_ACT_RANGES_APF_1_BOTTOM 1 // Default Bottom Compatibility for AP Firmware - driver I/F
397#define CFG_DRV_ACT_RANGES_APF_1_TOP 1 // Default Top Compatibility for AP Firmware - driver I/F
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HG		 398#endif // HCF_TYPE_WPA
399
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DK		 400#define CFG_DRV_ACT_RANGES_APF_2_BOTTOM 2 // Default Bottom Compatibility for AP Firmware - driver I/F
401#define CFG_DRV_ACT_RANGES_APF_2_TOP 2 // Default Top Compatibility for AP Firmware - driver I/F
68c0bdff 402
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DK		 403#define CFG_DRV_ACT_RANGES_APF_3_BOTTOM 1 // Default Bottom Compatibility for AP Firmware - driver I/F
404#define CFG_DRV_ACT_RANGES_APF_3_TOP 1 // Default Top Compatibility for AP Firmware - driver I/F
68c0bdff 405
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DK		 406#define CFG_DRV_ACT_RANGES_APF_4_BOTTOM 1 // Default Bottom Compatibility for AP Firmware - driver I/F
407#define CFG_DRV_ACT_RANGES_APF_4_TOP 1 // Default Top Compatibility for AP Firmware - driver I/F
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HG		 408
409#if (HCF_TYPE) & HCF_TYPE_HII5
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DK		 410#define CFG_DRV_ACT_RANGES_STA_2_BOTTOM 6 // Default Bottom Compatibility for Station Firmware - driver I/F
411#define CFG_DRV_ACT_RANGES_STA_2_TOP 6 // Default Top Compatibility for Station Firmware - driver I/F
68c0bdff 412#else // (HCF_TYPE) & HCF_TYPE_HII5
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DK		 413#define CFG_DRV_ACT_RANGES_STA_2_BOTTOM 1 // Default Bottom Compatibility for Station Firmware - driver I/F
414#define CFG_DRV_ACT_RANGES_STA_2_TOP 2 // Default Top Compatibility for Station Firmware - driver I/F
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HG		 415#endif // (HCF_TYPE) & HCF_TYPE_HII5
416
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DK		 417#define CFG_DRV_ACT_RANGES_STA_3_BOTTOM 1 // Default Bottom Compatibility for Station Firmware - driver I/F
418#define CFG_DRV_ACT_RANGES_STA_3_TOP 1 // Default Top Compatibility for Station Firmware - driver I/F
68c0bdff 419
fe4d2755
DK		 420#define CFG_DRV_ACT_RANGES_STA_4_BOTTOM 1 // Default Bottom Compatibility for Station Firmware - driver I/F
421#define CFG_DRV_ACT_RANGES_STA_4_TOP 1 // Default Top Compatibility for Station Firmware - driver I/F
68c0bdff
HG		 422
423//---------------------------------------------------------------------------------------------------------------------
424#if defined HCF_CFG_PRI_1_TOP || defined HCF_CFG_PRI_1_BOTTOM
fe4d2755 425err: PRI_1 not supported for H-I; // Compatibility for Primary Firmware - driver I/F
68c0bdff
HG		 426#endif // HCF_CFG_PRI_1_TOP / HCF_CFG_PRI_1_BOTTOM
427
428#if defined HCF_CFG_PRI_2_TOP || defined HCF_CFG_PRI_2_BOTTOM
fe4d2755 429err: PRI_2 not supported for H-I; // Compatibility for Primary Firmware - driver I/F
68c0bdff
HG		 430#endif // HCF_CFG_PRI_2_TOP / HCF_CFG_PRI_2_BOTTOM
431
fe4d2755
DK		 432#ifdef HCF_CFG_PRI_3_TOP // Top Compatibility for Primary Firmware - driver I/F
433#if HCF_CFG_PRI_3_TOP == 0 || \
68c0bdff
HG		 434 CFG_DRV_ACT_RANGES_PRI_3_BOTTOM <= HCF_CFG_PRI_3_TOP && HCF_CFG_PRI_3_TOP <= CFG_DRV_ACT_RANGES_PRI_3_TOP
435#undef CFG_DRV_ACT_RANGES_PRI_3_TOP
fe4d2755 436#define CFG_DRV_ACT_RANGES_PRI_3_TOP HCF_CFG_PRI_3_TOP
68c0bdff
HG		 437#else
438err: ;
439#endif
440#endif // HCF_CFG_PRI_3_TOP
441
fe4d2755 442#ifdef HCF_CFG_PRI_3_BOTTOM // Bottom Compatibility for Primary Firmware - driver I/F
68c0bdff
HG		 443#if CFG_DRV_ACT_RANGES_PRI_3_BOTTOM <= HCF_CFG_PRI_3_BOTTOM && HCF_CFG_PRI_3_BOTTOM <= CFG_DRV_ACT_RANGES_PRI_3_TOP
444#undef CFG_DRV_ACT_RANGES_PRI_3_BOTTOM
fe4d2755 445#define CFG_DRV_ACT_RANGES_PRI_3_BOTTOM HCF_CFG_PRI_3_BOTTOM
68c0bdff
HG		 446#else
447err: ;
448#endif
449#endif // HCF_CFG_PRI_3_BOTTOM
450
451
452//---------------------------------------------------------------------------------------------------------------------
453#if defined HCF_CFG_HSI_0_TOP || defined HCF_CFG_HSI_0_BOTTOM
fe4d2755 454err: HSI_0 not supported for H-I; // Compatibility for HSI I/F
68c0bdff
HG		 455#endif // HCF_CFG_HSI_0_TOP / HCF_CFG_HSI_0_BOTTOM
456
457#if defined HCF_CFG_HSI_1_TOP || defined HCF_CFG_HSI_1_BOTTOM
fe4d2755 458err: HSI_1 not supported for H-I; // Compatibility for HSI I/F
68c0bdff
HG		 459#endif // HCF_CFG_HSI_1_TOP / HCF_CFG_HSI_1_BOTTOM
460
461#if defined HCF_CFG_HSI_2_TOP || defined HCF_CFG_HSI_2_BOTTOM
fe4d2755 462err: HSI_2 not supported for H-I; // Compatibility for HSI I/F
68c0bdff
HG		 463#endif // HCF_CFG_HSI_2_TOP / HCF_CFG_HSI_2_BOTTOM
464
465#if defined HCF_CFG_HSI_3_TOP || defined HCF_CFG_HSI_3_BOTTOM
fe4d2755 466err: HSI_3 not supported for H-I; // Compatibility for HSI I/F
68c0bdff
HG		 467#endif // HCF_CFG_HSI_3_TOP / HCF_CFG_HSI_3_BOTTOM
468
fe4d2755
DK		 469#ifdef HCF_CFG_HSI_4_TOP // Top Compatibility for HSI I/F
470#if HCF_CFG_HSI_4_TOP == 0 || \
68c0bdff
HG		 471 CFG_DRV_ACT_RANGES_HSI_4_BOTTOM <= CF_CFG_HSI_4_TOP && HCF_CFG_HSI_4_TOP <= CFG_DRV_ACT_RANGES_HSI_4_TOP
472#undef CFG_DRV_ACT_RANGES_HSI_4_TOP
fe4d2755 473#define CFG_DRV_ACT_RANGES_HSI_4_TOP HCF_CFG_HSI_4_TOP
68c0bdff
HG		 474#else
475err: ;
476#endif
477#endif // HCF_CFG_HSI_4_TOP
478
fe4d2755 479#ifdef HCF_CFG_HSI_4_BOTTOM // Bottom Compatibility for HSI I/F
68c0bdff
HG		 480#if CFG_DRV_ACT_RANGES_HSI_4_BOTTOM <= HCF_CFG_HSI_4_BOTTOM && HCF_CFG_HSI_4_BOTTOM <= CFG_DRV_ACT_RANGES_HSI_4_TOP
481#undef CFG_DRV_ACT_RANGES_HSI_4_BOTTOM
fe4d2755 482#define CFG_DRV_ACT_RANGES_HSI_4_BOTTOM HCF_CFG_HSI_4_BOTTOM
68c0bdff
HG		 483#else
484err: ;
485#endif
486#endif // HCF_CFG_HSI_4_BOTTOM
487
fe4d2755
DK		 488#ifdef HCF_CFG_HSI_5_TOP // Top Compatibility for HSI I/F
489#if HCF_CFG_HSI_5_TOP == 0 || \
68c0bdff
HG		 490 CFG_DRV_ACT_RANGES_HSI_5_BOTTOM <= CF_CFG_HSI_5_TOP && HCF_CFG_HSI_5_TOP <= CFG_DRV_ACT_RANGES_HSI_5_TOP
491#undef CFG_DRV_ACT_RANGES_HSI_5_TOP
fe4d2755 492#define CFG_DRV_ACT_RANGES_HSI_5_TOP HCF_CFG_HSI_5_TOP
68c0bdff
HG		 493#else
494err: ;
495#endif
496#endif // HCF_CFG_HSI_5_TOP
497
fe4d2755 498#ifdef HCF_CFG_HSI_5_BOTTOM // Bottom Compatibility for HSI I/F
68c0bdff
HG		 499#if CFG_DRV_ACT_RANGES_HSI_5_BOTTOM <= HCF_CFG_HSI_5_BOTTOM && HCF_CFG_HSI_5_BOTTOM <= CFG_DRV_ACT_RANGES_HSI_5_TOP
500#undef CFG_DRV_ACT_RANGES_HSI_5_BOTTOM
fe4d2755 501#define CFG_DRV_ACT_RANGES_HSI_5_BOTTOM HCF_CFG_HSI_5_BOTTOM
68c0bdff
HG		 502#else
503err: ;
504#endif
505#endif // HCF_CFG_HSI_5_BOTTOM
506//---------------------------------------------------------------------------------------------------------------------
507#if defined HCF_CFG_APF_1_TOP || defined HCF_CFG_APF_1_BOTTOM
fe4d2755 508err: APF_1 not supported for H-I; // Compatibility for AP Firmware - driver I/F
68c0bdff
HG		 509#endif // HCF_CFG_APF_1_TOP / HCF_CFG_APF_1_BOTTOM
510
fe4d2755
DK		 511#ifdef HCF_CFG_APF_2_TOP // Top Compatibility for AP Firmware - driver I/F
512#if HCF_CFG_APF_2_TOP == 0 || \
68c0bdff
HG		 513 CFG_DRV_ACT_RANGES_APF_2_BOTTOM <= HCF_CFG_APF_2_TOP && HCF_CFG_APF_2_TOP <= CFG_DRV_ACT_RANGES_APF_2_TOP
514#undef CFG_DRV_ACT_RANGES_APF_2_TOP
fe4d2755 515#define CFG_DRV_ACT_RANGES_APF_2_TOP HCF_CFG_APF_2_TOP
68c0bdff
HG		 516#else
517err: ;
518#endif
519#endif // HCF_CFG_APF_TOP
520
fe4d2755 521#ifdef HCF_CFG_APF_2_BOTTOM // Bottom Compatibility for AP Firmware - driver I/F
68c0bdff
HG		 522#if CFG_DRV_ACT_RANGES_APF_2_BOTTOM <= HCF_CFG_APF_2_BOTTOM && HCF_CFG_APF_2_BOTTOM <= CFG_DRV_ACT_RANGES_APF_2_TOP
523#undef CFG_DRV_ACT_RANGES_APF_2_BOTTOM
fe4d2755 524#define CFG_DRV_ACT_RANGES_APF_2_BOTTOM HCF_CFG_APF_2_BOTTOM
68c0bdff
HG		 525#else
526err: ;
527#endif
528#endif // HCF_CFG_APF_BOTTOM
529
530//---------------------------------------------------------------------------------------------------------------------
531#if defined HCF_CFG_STA_1_TOP || defined HCF_CFG_STA_1_BOTTOM
fe4d2755 532err: STA_1 not supported for H-I; // Compatibility for Station Firmware - driver I/F
68c0bdff
HG		 533#endif // HCF_CFG_STA_1_TOP / HCF_CFG_STA_1_BOTTOM
534
fe4d2755
DK		 535#ifdef HCF_CFG_STA_2_TOP // Top Compatibility for Station Firmware - driver I/F
536#if HCF_CFG_STA_2_TOP == 0 || \
68c0bdff
HG		 537 CFG_DRV_ACT_RANGES_STA_2_BOTTOM <= HCF_CFG_STA_2_TOP && HCF_CFG_STA_2_TOP <= CFG_DRV_ACT_RANGES_STA_2_TOP
538#undef CFG_DRV_ACT_RANGES_STA_2_TOP
fe4d2755 539#define CFG_DRV_ACT_RANGES_STA_2_TOP HCF_CFG_STA_2_TOP
68c0bdff
HG		 540#else
541err: ;
542#endif
543#endif // HCF_CFG_STA_TOP
544
fe4d2755 545#ifdef HCF_CFG_STA_2_BOTTOM // Bottom Compatibility for Station Firmware - driver I/F
68c0bdff
HG		 546#if CFG_DRV_ACT_RANGES_STA_2_BOTTOM <= HCF_CFG_STA_2_BOTTOM && HCF_CFG_STA_2_BOTTOM <= CFG_DRV_ACT_RANGES_STA_2_TOP
547#undef CFG_DRV_ACT_RANGES_STA_2_BOTTOM
fe4d2755 548#define CFG_DRV_ACT_RANGES_STA_2_BOTTOM HCF_CFG_STA_2_BOTTOM
68c0bdff
HG		 549#else
550err: ;
551#endif
552#endif // HCF_CFG_STA_BOTTOM
553
554
555/************************************************************************************************/
556/************************************** MACROS ************************************************/
557/************************************************************************************************/
558
68c0bdff 559#ifdef HCF_SLEEP
788c2bce
DK		 560#define MSF_WAIT(x) do { \
561 PROT_CNT_INI; \
562 HCF_WAIT_WHILE((IPW(HREG_IO) & HREG_IO_WOKEN_UP) == 0); \
563 HCFASSERT( prot_cnt, IPW( HREG_IO ) ); \
564 } while (0)
68c0bdff 565#else
788c2bce 566#define MSF_WAIT(x) do { } while (0)
68c0bdff
HG		 567#endif // HCF_SLEEP
568
fe4d2755 569#define LOF(x) (sizeof(x)/sizeof(hcf_16)-1)
68c0bdff 570
68c0bdff 571//resolve problems on for some 16 bits compilers to create 32 bit values
fe4d2755 572#define MERGE_2( hw, lw ) ( ( ((hcf_32)(hw)) << 16 ) | ((hcf_16)(lw)) )
68c0bdff
HG		 573
574#if ! defined HCF_STATIC
fe4d2755
DK		 575#define HCF_STATIC static
576#endif // HCF_STATIC
68c0bdff
HG		 577
578#if ( (HCF_TYPE) & HCF_TYPE_HII5 ) == 0
788c2bce 579#define DAWA_ACK( mask) do { \
fe4d2755 580 OPW( HREG_EV_ACK, mask | HREG_EV_ACK_REG_READY ); \
788c2bce
DK		 581 OPW( HREG_EV_ACK, (mask & ~HREG_EV_ALLOC) | HREG_EV_ACK_REG_READY ); \
582 } while (0)
583#define DAWA_ZERO_FID(reg) OPW( reg, 0 )
68c0bdff 584#else
788c2bce
DK		 585#define DAWA_ACK( mask) OPW( HREG_EV_ACK, mask )
586#define DAWA_ZERO_FID(reg) do { } while (0)
68c0bdff
HG		 587#endif // HCF_TYPE_HII5
588
589#if (HCF_TYPE) & HCF_TYPE_WPA
fe4d2755
DK		 590#define CALC_RX_MIC( p, len ) calc_mic_rx_frag( ifbp, p, len )
591#define CALC_TX_MIC( p, len ) calc_mic_tx_frag( ifbp, p, len )
68c0bdff 592#else
fe4d2755
DK		 593#define CALC_RX_MIC( p, len )
594#define CALC_TX_MIC( p, len )
68c0bdff
HG		 595#define MIC_RX_RTN( mic, dw )
596#define MIC_TX_RTN( mic, dw )
68c0bdff
HG		 597#endif // HCF_TYPE_WPA
598
fe4d2755 599#if HCF_TALLIES & HCF_TALLIES_HCF //HCF tally support
788c2bce 600#define IF_TALLY(x) do { x; } while (0)
68c0bdff 601#else
788c2bce 602#define IF_TALLY(x) do { } while (0)
68c0bdff
HG		 603#endif // HCF_TALLIES_HCF
604
605
606#if HCF_DMA
788c2bce
DK		 607#define IF_DMA(x) do { x; } while(0)
608#define IF_NOT_DMA(x) do { } while(0)
609#define IF_USE_DMA(x) if ( ifbp->IFB_CntlOpt & USE_DMA ) { x; }
610#define IF_NOT_USE_DMA(x) if ( !(ifbp->IFB_CntlOpt & USE_DMA) ) { x; }
68c0bdff 611#else
788c2bce
DK		 612#define IF_DMA(x) do { } while(0)
613#define IF_NOT_DMA(x) do { x; } while(0)
614#define IF_USE_DMA(x) do { } while(0)
615#define IF_NOT_USE_DMA(x) do { x; } while(0)
68c0bdff
HG		 616#endif // HCF_DMA
617
618
619#define IPW(x) ((hcf_16)IN_PORT_WORD( ifbp->IFB_IOBase + (x) ) )
620#define OPW(x, y) OUT_PORT_WORD( ifbp->IFB_IOBase + (x), y )
fe4d2755
DK		 621/* make sure the implementation of HCF_WAIT_WHILE is such that there may be multiple HCF_WAIT_WHILE calls
622 * in a row and that when one fails all subsequent fail immediately without reinitialization of prot_cnt
623 */
68c0bdff 624#if HCF_PROT_TIME == 0
788c2bce
DK		 625#define PROT_CNT_INI do { } while(0)
626#define IF_PROT_TIME(x) do { } while(0)
68c0bdff 627#if defined HCF_YIELD
788c2bce 628#define HCF_WAIT_WHILE( x ) do { } while( (x) && (HCF_YIELD) )
68c0bdff 629#else
788c2bce 630#define HCF_WAIT_WHILE( x ) do { } while ( x )
68c0bdff
HG		 631#endif // HCF_YIELD
632#else
788c2bce
DK		 633#define PROT_CNT_INI hcf_32 prot_cnt = ifbp->IFB_TickIni
634#define IF_PROT_TIME(x) do { x; } while(0)
68c0bdff
HG		 635#if defined HCF_YIELD
636#define HCF_WAIT_WHILE( x ) while ( prot_cnt && (x) && (HCF_YIELD) ) prot_cnt--;
637#else
638#include <linux/delay.h>
639#define HCF_WAIT_WHILE( x ) while ( prot_cnt && (x) ) { udelay(2); prot_cnt--; }
640#endif // HCF_YIELD
641#endif // HCF_PROT_TIME
642
643#if defined HCF_EX_INT
644//#if HCF_EX_INT & ~( HCF_EX_INT_TX_EX | HCF_EX_INT_TX_OK | HCF_EX_INT_TICK )
645;? out dated checking
646err: you used an invalid bitmask;
647// #endif // HCF_EX_INT validation
648// #else
649// #define HCF_EX_INT 0x000
650#endif // HCF_EX_INT
651
652#if 0 //get compiler going
fe4d2755 653#if HCF_EX_INT_TICK != HREG_EV_TICK
68c0bdff 654;? out dated checking
cb154c18 655err: someone redefined these macros while the implementation assumes they are equal;
68c0bdff
HG		 656#endif
657#if HCF_EX_INT_TX_OK != HFS_TX_CNTL_TX_OK || HFS_TX_CNTL_TX_OK != HREG_EV_TX_OK
658;? out dated checking
cb154c18 659err: someone redefined these macros while the implementation assumes they are equal;
68c0bdff
HG		 660#endif
661#if HCF_EX_INT_TX_EX != HFS_TX_CNTL_TX_EX || HFS_TX_CNTL_TX_EX != HREG_EV_TX_EX
662;? out dated checking
cb154c18 663err: someone redefined these macros while the implementation assumes they are equal;
68c0bdff
HG		 664#endif
665#endif // 0 get compiler going
666
667
668/* The assert in HCFLOGENTRY checks against re-entrancy. Re-entrancy could be caused by MSF logic at
669 * task-level calling hcf_functions without shielding with HCF_ACT_ON/_OFF. When an interrupt occurs,
670 * the ISR could (either directly or indirectly) cause re-entering of the interrupted HCF-routine.
671 *
672 * The "(ifbp->IFB_AssertWhere = where)" test in HCFLOGENTRY services ALSO as a statement to get around:
673 * #pragma warning: conditional expression is constant
674 * on the if-statement
675 */
676#if HCF_ASSERT
788c2bce 677#define HCFASSERT(x,q) do { if (!(x)) {mdd_assert(ifbp, __LINE__, q );} } while(0)
68c0bdff
HG		 678#define MMDASSERT(x,q) {if (!(x)) {mdd_assert( assert_ifbp, __LINE__ + FILE_NAME_OFFSET, q );}}
679
788c2bce
DK		 680#define HCFLOGENTRY( where, what ) do { \
681 if ( (ifbp->IFB_AssertWhere = where) <= 15 ) { \
fe4d2755
DK		 682 HCFASSERT( (ifbp->IFB_AssertTrace & 1<<((where)&0xF)) == 0, ifbp->IFB_AssertTrace ); \
683 ifbp->IFB_AssertTrace |= 1<<((where)&0xF); \
684 } \
788c2bce
DK		 685 HCFTRACE(ifbp, where ); \
686 HCFTRACEVALUE(ifbp, what ); \
687 } while (0)
fe4d2755 688
788c2bce
DK		 689#define HCFLOGEXIT( where ) do { \
690 if ( (ifbp->IFB_AssertWhere = where) <= 15 ) { \
fe4d2755
DK		 691 ifbp->IFB_AssertTrace &= ~(1<<((where)&0xF)); \
692 } \
788c2bce
DK		 693 HCFTRACE(ifbp, (where)|HCF_TRACE_EXIT ); \
694 } while (0)
68c0bdff
HG		 695
696#else // HCF_ASSERT
788c2bce 697#define HCFASSERT( x, q ) do { } while(0)
68c0bdff 698#define MMDASSERT( x, q )
7a9541c3
DK		 699#define HCFLOGENTRY( where, what ) do { } while(0)
700#define HCFLOGEXIT( where ) do { } while(0)
68c0bdff
HG		 701#endif // HCF_ASSERT
702
703#if HCF_INT_ON
704/* ;? HCFASSERT_INT
705 * #if (HCF_SLEEP) & HCF_DDS
706 * #define HCFASSERT_INT HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFF && ifbp->IFB_IntOffCnt != 0xFFFE, \
fe4d2755 707 * ifbp->IFB_IntOffCnt )
68c0bdff
HG		 708 * #else
709 */
710#define HCFASSERT_INT HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFF, ifbp->IFB_IntOffCnt )
711// #endif // HCF_DDS
712#else
713#define HCFASSERT_INT
714#endif // HCF_INT_ON
715
716
717#if defined HCF_TRACE
788c2bce 718#define HCFTRACE(ifbp, where ) do {OPW( HREG_SW_1, where );} while(0)
fe4d2755 719//#define HCFTRACE(ifbp, where ) {HCFASSERT( DO_ASSERT, where );}
788c2bce 720#define HCFTRACEVALUE(ifbp, what ) do {OPW( HREG_SW_2, what );} while (0)
68c0bdff
HG		 721//#define HCFTRACEVALUE(ifbp, what ) {HCFASSERT( DO_ASSERT, what );}
722#else
788c2bce
DK		 723#define HCFTRACE(ifbp, where ) do { } while(0)
724#define HCFTRACEVALUE(ifbp, what ) do { } while(0)
68c0bdff
HG		 725#endif // HCF_TRACE
726
727
728#if HCF_BIG_ENDIAN
fe4d2755 729#define BE_PAR(x) ,x
68c0bdff
HG		 730#else
731#define BE_PAR(x)
732#endif // HCF_BIG_ENDIAN
733
734/************************************************************************************************/
735/************************************** END OF MACROS *****************************************/
736/************************************************************************************************/
737
738/************************************************************************************************/
739/*************************************** PROTOTYPES *******************************************/
740/************************************************************************************************/
741
742#if HCF_ASSERT
fe4d2755
DK		 743extern IFBP BASED assert_ifbp; //to make asserts easily work under MMD and DHF
744EXTERN_C void mdd_assert (IFBP ifbp, unsigned int line_number, hcf_32 q );
68c0bdff
HG		 745#endif //HCF_ASSERT
746
fe4d2755 747#if ! ( (HCF_IO) & HCF_IO_32BITS ) // defined 16 bits only
68c0bdff
HG		 748#undef OUT_PORT_STRING_32
749#undef IN_PORT_STRING_32
750#endif // HCF_IO
fe4d2755 751#endif //HCFDEFC_H
68c0bdff 752
Linux kernel - Deliverables
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