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a92db1c8 SH |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> | |
4 | * Sascha Hauer <s.hauer@pengutronix.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/clk.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/nvmem-consumer.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/thermal.h> | |
28 | #include <linux/reset.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/nvmem-consumer.h> | |
31 | ||
32 | /* AUXADC Registers */ | |
33 | #define AUXADC_CON0_V 0x000 | |
34 | #define AUXADC_CON1_V 0x004 | |
35 | #define AUXADC_CON1_SET_V 0x008 | |
36 | #define AUXADC_CON1_CLR_V 0x00c | |
37 | #define AUXADC_CON2_V 0x010 | |
38 | #define AUXADC_DATA(channel) (0x14 + (channel) * 4) | |
39 | #define AUXADC_MISC_V 0x094 | |
40 | ||
41 | #define AUXADC_CON1_CHANNEL(x) BIT(x) | |
42 | ||
43 | #define APMIXED_SYS_TS_CON1 0x604 | |
44 | ||
45 | /* Thermal Controller Registers */ | |
46 | #define TEMP_MONCTL0 0x000 | |
47 | #define TEMP_MONCTL1 0x004 | |
48 | #define TEMP_MONCTL2 0x008 | |
49 | #define TEMP_MONIDET0 0x014 | |
50 | #define TEMP_MONIDET1 0x018 | |
51 | #define TEMP_MSRCTL0 0x038 | |
52 | #define TEMP_AHBPOLL 0x040 | |
53 | #define TEMP_AHBTO 0x044 | |
54 | #define TEMP_ADCPNP0 0x048 | |
55 | #define TEMP_ADCPNP1 0x04c | |
56 | #define TEMP_ADCPNP2 0x050 | |
57 | #define TEMP_ADCPNP3 0x0b4 | |
58 | ||
59 | #define TEMP_ADCMUX 0x054 | |
60 | #define TEMP_ADCEN 0x060 | |
61 | #define TEMP_PNPMUXADDR 0x064 | |
62 | #define TEMP_ADCMUXADDR 0x068 | |
63 | #define TEMP_ADCENADDR 0x074 | |
64 | #define TEMP_ADCVALIDADDR 0x078 | |
65 | #define TEMP_ADCVOLTADDR 0x07c | |
66 | #define TEMP_RDCTRL 0x080 | |
67 | #define TEMP_ADCVALIDMASK 0x084 | |
68 | #define TEMP_ADCVOLTAGESHIFT 0x088 | |
69 | #define TEMP_ADCWRITECTRL 0x08c | |
70 | #define TEMP_MSR0 0x090 | |
71 | #define TEMP_MSR1 0x094 | |
72 | #define TEMP_MSR2 0x098 | |
73 | #define TEMP_MSR3 0x0B8 | |
74 | ||
75 | #define TEMP_SPARE0 0x0f0 | |
76 | ||
77 | #define PTPCORESEL 0x400 | |
78 | ||
79 | #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) | |
80 | ||
eb4fc33e | 81 | #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) |
a92db1c8 SH |
82 | #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) |
83 | ||
84 | #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) | |
85 | ||
86 | #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) | |
87 | #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) | |
88 | ||
89 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) | |
90 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) | |
91 | ||
92 | #define MT8173_TS1 0 | |
93 | #define MT8173_TS2 1 | |
94 | #define MT8173_TS3 2 | |
95 | #define MT8173_TS4 3 | |
96 | #define MT8173_TSABB 4 | |
97 | ||
98 | /* AUXADC channel 11 is used for the temperature sensors */ | |
99 | #define MT8173_TEMP_AUXADC_CHANNEL 11 | |
100 | ||
101 | /* The total number of temperature sensors in the MT8173 */ | |
102 | #define MT8173_NUM_SENSORS 5 | |
103 | ||
104 | /* The number of banks in the MT8173 */ | |
105 | #define MT8173_NUM_ZONES 4 | |
106 | ||
107 | /* The number of sensing points per bank */ | |
108 | #define MT8173_NUM_SENSORS_PER_ZONE 4 | |
109 | ||
110 | /* Layout of the fuses providing the calibration data */ | |
eb4fc33e EV |
111 | #define MT8173_CALIB_BUF0_VALID BIT(0) |
112 | #define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff) | |
113 | #define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff) | |
114 | #define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff) | |
115 | #define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff) | |
116 | #define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff) | |
117 | #define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff) | |
118 | #define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f) | |
119 | #define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f) | |
a92db1c8 SH |
120 | |
121 | #define THERMAL_NAME "mtk-thermal" | |
122 | ||
123 | struct mtk_thermal; | |
124 | ||
125 | struct mtk_thermal_bank { | |
126 | struct mtk_thermal *mt; | |
127 | int id; | |
128 | }; | |
129 | ||
130 | struct mtk_thermal { | |
131 | struct device *dev; | |
132 | void __iomem *thermal_base; | |
133 | ||
134 | struct clk *clk_peri_therm; | |
135 | struct clk *clk_auxadc; | |
136 | ||
137 | struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; | |
138 | ||
eb4fc33e | 139 | /* lock: for getting and putting banks */ |
a92db1c8 SH |
140 | struct mutex lock; |
141 | ||
142 | /* Calibration values */ | |
143 | s32 adc_ge; | |
144 | s32 degc_cali; | |
145 | s32 o_slope; | |
146 | s32 vts[MT8173_NUM_SENSORS]; | |
147 | ||
148 | struct thermal_zone_device *tzd; | |
149 | }; | |
150 | ||
151 | struct mtk_thermal_bank_cfg { | |
152 | unsigned int num_sensors; | |
153 | unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; | |
154 | }; | |
155 | ||
156 | static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; | |
157 | ||
158 | /* | |
159 | * The MT8173 thermal controller has four banks. Each bank can read up to | |
160 | * four temperature sensors simultaneously. The MT8173 has a total of 5 | |
161 | * temperature sensors. We use each bank to measure a certain area of the | |
162 | * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple | |
163 | * areas, hence is used in different banks. | |
164 | * | |
165 | * The thermal core only gets the maximum temperature of all banks, so | |
166 | * the bank concept wouldn't be necessary here. However, the SVS (Smart | |
167 | * Voltage Scaling) unit makes its decisions based on the same bank | |
168 | * data, and this indeed needs the temperatures of the individual banks | |
169 | * for making better decisions. | |
170 | */ | |
171 | static const struct mtk_thermal_bank_cfg bank_data[] = { | |
172 | { | |
173 | .num_sensors = 2, | |
174 | .sensors = { MT8173_TS2, MT8173_TS3 }, | |
175 | }, { | |
176 | .num_sensors = 2, | |
177 | .sensors = { MT8173_TS2, MT8173_TS4 }, | |
178 | }, { | |
179 | .num_sensors = 3, | |
180 | .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, | |
181 | }, { | |
182 | .num_sensors = 1, | |
183 | .sensors = { MT8173_TS2 }, | |
184 | }, | |
185 | }; | |
186 | ||
187 | struct mtk_thermal_sense_point { | |
188 | int msr; | |
189 | int adcpnp; | |
190 | }; | |
191 | ||
192 | static const struct mtk_thermal_sense_point | |
193 | sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { | |
194 | { | |
195 | .msr = TEMP_MSR0, | |
196 | .adcpnp = TEMP_ADCPNP0, | |
197 | }, { | |
198 | .msr = TEMP_MSR1, | |
199 | .adcpnp = TEMP_ADCPNP1, | |
200 | }, { | |
201 | .msr = TEMP_MSR2, | |
202 | .adcpnp = TEMP_ADCPNP2, | |
203 | }, { | |
204 | .msr = TEMP_MSR3, | |
205 | .adcpnp = TEMP_ADCPNP3, | |
206 | }, | |
207 | }; | |
208 | ||
209 | /** | |
210 | * raw_to_mcelsius - convert a raw ADC value to mcelsius | |
211 | * @mt: The thermal controller | |
212 | * @raw: raw ADC value | |
213 | * | |
214 | * This converts the raw ADC value to mcelsius using the SoC specific | |
215 | * calibration constants | |
216 | */ | |
217 | static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) | |
218 | { | |
219 | s32 tmp; | |
220 | ||
221 | raw &= 0xfff; | |
222 | ||
223 | tmp = 203450520 << 3; | |
224 | tmp /= 165 + mt->o_slope; | |
225 | tmp /= 10000 + mt->adc_ge; | |
226 | tmp *= raw - mt->vts[sensno] - 3350; | |
227 | tmp >>= 3; | |
228 | ||
229 | return mt->degc_cali * 500 - tmp; | |
230 | } | |
231 | ||
232 | /** | |
233 | * mtk_thermal_get_bank - get bank | |
234 | * @bank: The bank | |
235 | * | |
236 | * The bank registers are banked, we have to select a bank in the | |
237 | * PTPCORESEL register to access it. | |
238 | */ | |
239 | static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) | |
240 | { | |
241 | struct mtk_thermal *mt = bank->mt; | |
242 | u32 val; | |
243 | ||
244 | mutex_lock(&mt->lock); | |
245 | ||
246 | val = readl(mt->thermal_base + PTPCORESEL); | |
247 | val &= ~0xf; | |
248 | val |= bank->id; | |
249 | writel(val, mt->thermal_base + PTPCORESEL); | |
250 | } | |
251 | ||
252 | /** | |
253 | * mtk_thermal_put_bank - release bank | |
254 | * @bank: The bank | |
255 | * | |
256 | * release a bank previously taken with mtk_thermal_get_bank, | |
257 | */ | |
258 | static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) | |
259 | { | |
260 | struct mtk_thermal *mt = bank->mt; | |
261 | ||
262 | mutex_unlock(&mt->lock); | |
263 | } | |
264 | ||
265 | /** | |
266 | * mtk_thermal_bank_temperature - get the temperature of a bank | |
267 | * @bank: The bank | |
268 | * | |
269 | * The temperature of a bank is considered the maximum temperature of | |
270 | * the sensors associated to the bank. | |
271 | */ | |
272 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) | |
273 | { | |
274 | struct mtk_thermal *mt = bank->mt; | |
eb4fc33e | 275 | int i, temp = INT_MIN, max = INT_MIN; |
a92db1c8 SH |
276 | u32 raw; |
277 | ||
a92db1c8 SH |
278 | for (i = 0; i < bank_data[bank->id].num_sensors; i++) { |
279 | raw = readl(mt->thermal_base + sensing_points[i].msr); | |
280 | ||
281 | temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); | |
282 | ||
283 | /* | |
284 | * The first read of a sensor often contains very high bogus | |
285 | * temperature value. Filter these out so that the system does | |
286 | * not immediately shut down. | |
287 | */ | |
288 | if (temp > 200000) | |
289 | temp = 0; | |
290 | ||
291 | if (temp > max) | |
292 | max = temp; | |
293 | } | |
294 | ||
295 | return max; | |
296 | } | |
297 | ||
298 | static int mtk_read_temp(void *data, int *temperature) | |
299 | { | |
300 | struct mtk_thermal *mt = data; | |
301 | int i; | |
302 | int tempmax = INT_MIN; | |
303 | ||
304 | for (i = 0; i < MT8173_NUM_ZONES; i++) { | |
305 | struct mtk_thermal_bank *bank = &mt->banks[i]; | |
306 | ||
307 | mtk_thermal_get_bank(bank); | |
308 | ||
309 | tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); | |
310 | ||
311 | mtk_thermal_put_bank(bank); | |
312 | } | |
313 | ||
314 | *temperature = tempmax; | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
319 | static const struct thermal_zone_of_device_ops mtk_thermal_ops = { | |
320 | .get_temp = mtk_read_temp, | |
321 | }; | |
322 | ||
323 | static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |
eb4fc33e | 324 | u32 apmixed_phys_base, u32 auxadc_phys_base) |
a92db1c8 SH |
325 | { |
326 | struct mtk_thermal_bank *bank = &mt->banks[num]; | |
327 | const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; | |
328 | int i; | |
329 | ||
330 | bank->id = num; | |
331 | bank->mt = mt; | |
332 | ||
333 | mtk_thermal_get_bank(bank); | |
334 | ||
335 | /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ | |
336 | writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); | |
337 | ||
338 | /* | |
339 | * filt interval is 1 * 46.540us = 46.54us, | |
340 | * sen interval is 429 * 46.540us = 19.96ms | |
341 | */ | |
342 | writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | | |
343 | TEMP_MONCTL2_SENSOR_INTERVAL(429), | |
344 | mt->thermal_base + TEMP_MONCTL2); | |
345 | ||
346 | /* poll is set to 10u */ | |
347 | writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), | |
eb4fc33e | 348 | mt->thermal_base + TEMP_AHBPOLL); |
a92db1c8 SH |
349 | |
350 | /* temperature sampling control, 1 sample */ | |
351 | writel(0x0, mt->thermal_base + TEMP_MSRCTL0); | |
352 | ||
353 | /* exceed this polling time, IRQ would be inserted */ | |
354 | writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); | |
355 | ||
356 | /* number of interrupts per event, 1 is enough */ | |
357 | writel(0x0, mt->thermal_base + TEMP_MONIDET0); | |
358 | writel(0x0, mt->thermal_base + TEMP_MONIDET1); | |
359 | ||
360 | /* | |
361 | * The MT8173 thermal controller does not have its own ADC. Instead it | |
362 | * uses AHB bus accesses to control the AUXADC. To do this the thermal | |
363 | * controller has to be programmed with the physical addresses of the | |
364 | * AUXADC registers and with the various bit positions in the AUXADC. | |
365 | * Also the thermal controller controls a mux in the APMIXEDSYS register | |
366 | * space. | |
367 | */ | |
368 | ||
369 | /* | |
370 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) | |
371 | * automatically by hw | |
372 | */ | |
373 | writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); | |
374 | ||
375 | /* AHB address for auxadc mux selection */ | |
376 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, | |
eb4fc33e | 377 | mt->thermal_base + TEMP_ADCMUXADDR); |
a92db1c8 SH |
378 | |
379 | /* AHB address for pnp sensor mux selection */ | |
380 | writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, | |
eb4fc33e | 381 | mt->thermal_base + TEMP_PNPMUXADDR); |
a92db1c8 SH |
382 | |
383 | /* AHB value for auxadc enable */ | |
384 | writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); | |
385 | ||
386 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ | |
387 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, | |
eb4fc33e | 388 | mt->thermal_base + TEMP_ADCENADDR); |
a92db1c8 SH |
389 | |
390 | /* AHB address for auxadc valid bit */ | |
391 | writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), | |
eb4fc33e | 392 | mt->thermal_base + TEMP_ADCVALIDADDR); |
a92db1c8 SH |
393 | |
394 | /* AHB address for auxadc voltage output */ | |
395 | writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), | |
eb4fc33e | 396 | mt->thermal_base + TEMP_ADCVOLTADDR); |
a92db1c8 SH |
397 | |
398 | /* read valid & voltage are at the same register */ | |
399 | writel(0x0, mt->thermal_base + TEMP_RDCTRL); | |
400 | ||
401 | /* indicate where the valid bit is */ | |
402 | writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), | |
eb4fc33e | 403 | mt->thermal_base + TEMP_ADCVALIDMASK); |
a92db1c8 SH |
404 | |
405 | /* no shift */ | |
406 | writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); | |
407 | ||
408 | /* enable auxadc mux write transaction */ | |
409 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
eb4fc33e | 410 | mt->thermal_base + TEMP_ADCWRITECTRL); |
a92db1c8 SH |
411 | |
412 | for (i = 0; i < cfg->num_sensors; i++) | |
413 | writel(sensor_mux_values[cfg->sensors[i]], | |
eb4fc33e | 414 | mt->thermal_base + sensing_points[i].adcpnp); |
a92db1c8 SH |
415 | |
416 | writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); | |
417 | ||
eb4fc33e EV |
418 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
419 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
420 | mt->thermal_base + TEMP_ADCWRITECTRL); | |
a92db1c8 SH |
421 | |
422 | mtk_thermal_put_bank(bank); | |
423 | } | |
424 | ||
425 | static u64 of_get_phys_base(struct device_node *np) | |
426 | { | |
427 | u64 size64; | |
428 | const __be32 *regaddr_p; | |
429 | ||
430 | regaddr_p = of_get_address(np, 0, &size64, NULL); | |
431 | if (!regaddr_p) | |
432 | return OF_BAD_ADDR; | |
433 | ||
434 | return of_translate_address(np, regaddr_p); | |
435 | } | |
436 | ||
eb4fc33e EV |
437 | static int mtk_thermal_get_calibration_data(struct device *dev, |
438 | struct mtk_thermal *mt) | |
a92db1c8 SH |
439 | { |
440 | struct nvmem_cell *cell; | |
441 | u32 *buf; | |
442 | size_t len; | |
443 | int i, ret = 0; | |
444 | ||
445 | /* Start with default values */ | |
446 | mt->adc_ge = 512; | |
447 | for (i = 0; i < MT8173_NUM_SENSORS; i++) | |
448 | mt->vts[i] = 260; | |
449 | mt->degc_cali = 40; | |
450 | mt->o_slope = 0; | |
451 | ||
452 | cell = nvmem_cell_get(dev, "calibration-data"); | |
453 | if (IS_ERR(cell)) { | |
454 | if (PTR_ERR(cell) == -EPROBE_DEFER) | |
455 | return PTR_ERR(cell); | |
456 | return 0; | |
457 | } | |
458 | ||
459 | buf = (u32 *)nvmem_cell_read(cell, &len); | |
460 | ||
461 | nvmem_cell_put(cell); | |
462 | ||
463 | if (IS_ERR(buf)) | |
464 | return PTR_ERR(buf); | |
465 | ||
466 | if (len < 3 * sizeof(u32)) { | |
467 | dev_warn(dev, "invalid calibration data\n"); | |
468 | ret = -EINVAL; | |
469 | goto out; | |
470 | } | |
471 | ||
472 | if (buf[0] & MT8173_CALIB_BUF0_VALID) { | |
473 | mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); | |
474 | mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); | |
475 | mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); | |
476 | mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); | |
477 | mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); | |
478 | mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); | |
479 | mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); | |
480 | mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); | |
481 | } else { | |
482 | dev_info(dev, "Device not calibrated, using default calibration values\n"); | |
483 | } | |
484 | ||
485 | out: | |
486 | kfree(buf); | |
487 | ||
488 | return ret; | |
489 | } | |
490 | ||
491 | static int mtk_thermal_probe(struct platform_device *pdev) | |
492 | { | |
493 | int ret, i; | |
494 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; | |
495 | struct mtk_thermal *mt; | |
496 | struct resource *res; | |
497 | u64 auxadc_phys_base, apmixed_phys_base; | |
498 | ||
499 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); | |
500 | if (!mt) | |
501 | return -ENOMEM; | |
502 | ||
503 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); | |
504 | if (IS_ERR(mt->clk_peri_therm)) | |
505 | return PTR_ERR(mt->clk_peri_therm); | |
506 | ||
507 | mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); | |
508 | if (IS_ERR(mt->clk_auxadc)) | |
509 | return PTR_ERR(mt->clk_auxadc); | |
510 | ||
511 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
512 | mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); | |
513 | if (IS_ERR(mt->thermal_base)) | |
514 | return PTR_ERR(mt->thermal_base); | |
515 | ||
516 | ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); | |
517 | if (ret) | |
518 | return ret; | |
519 | ||
520 | mutex_init(&mt->lock); | |
521 | ||
522 | mt->dev = &pdev->dev; | |
523 | ||
524 | auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); | |
525 | if (!auxadc) { | |
526 | dev_err(&pdev->dev, "missing auxadc node\n"); | |
527 | return -ENODEV; | |
528 | } | |
529 | ||
530 | auxadc_phys_base = of_get_phys_base(auxadc); | |
531 | ||
532 | of_node_put(auxadc); | |
533 | ||
534 | if (auxadc_phys_base == OF_BAD_ADDR) { | |
535 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
536 | return -EINVAL; | |
537 | } | |
538 | ||
539 | apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); | |
540 | if (!apmixedsys) { | |
541 | dev_err(&pdev->dev, "missing apmixedsys node\n"); | |
542 | return -ENODEV; | |
543 | } | |
544 | ||
545 | apmixed_phys_base = of_get_phys_base(apmixedsys); | |
546 | ||
547 | of_node_put(apmixedsys); | |
548 | ||
549 | if (apmixed_phys_base == OF_BAD_ADDR) { | |
550 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | ret = clk_prepare_enable(mt->clk_auxadc); | |
555 | if (ret) { | |
556 | dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); | |
557 | return ret; | |
558 | } | |
559 | ||
560 | ret = device_reset(&pdev->dev); | |
561 | if (ret) | |
562 | goto err_disable_clk_auxadc; | |
563 | ||
564 | ret = clk_prepare_enable(mt->clk_peri_therm); | |
565 | if (ret) { | |
566 | dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); | |
567 | goto err_disable_clk_auxadc; | |
568 | } | |
569 | ||
570 | for (i = 0; i < MT8173_NUM_ZONES; i++) | |
eb4fc33e EV |
571 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, |
572 | auxadc_phys_base); | |
a92db1c8 SH |
573 | |
574 | platform_set_drvdata(pdev, mt); | |
575 | ||
576 | mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, | |
577 | &mtk_thermal_ops); | |
578 | if (IS_ERR(mt->tzd)) | |
579 | goto err_register; | |
580 | ||
581 | return 0; | |
582 | ||
583 | err_register: | |
584 | clk_disable_unprepare(mt->clk_peri_therm); | |
585 | ||
586 | err_disable_clk_auxadc: | |
587 | clk_disable_unprepare(mt->clk_auxadc); | |
588 | ||
589 | return ret; | |
590 | } | |
591 | ||
592 | static int mtk_thermal_remove(struct platform_device *pdev) | |
593 | { | |
594 | struct mtk_thermal *mt = platform_get_drvdata(pdev); | |
595 | ||
596 | thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); | |
597 | ||
598 | clk_disable_unprepare(mt->clk_peri_therm); | |
599 | clk_disable_unprepare(mt->clk_auxadc); | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | static const struct of_device_id mtk_thermal_of_match[] = { | |
605 | { | |
606 | .compatible = "mediatek,mt8173-thermal", | |
607 | }, { | |
608 | }, | |
609 | }; | |
610 | ||
611 | static struct platform_driver mtk_thermal_driver = { | |
612 | .probe = mtk_thermal_probe, | |
613 | .remove = mtk_thermal_remove, | |
614 | .driver = { | |
615 | .name = THERMAL_NAME, | |
616 | .of_match_table = mtk_thermal_of_match, | |
617 | }, | |
618 | }; | |
619 | ||
620 | module_platform_driver(mtk_thermal_driver); | |
621 | ||
622 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); | |
623 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); | |
624 | MODULE_DESCRIPTION("Mediatek thermal driver"); | |
625 | MODULE_LICENSE("GPL v2"); |