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Merge branch 'akpm' (patches from Andrew)
[deliverable/linux.git] / drivers / thermal / rockchip_thermal.c
CommitLineData
cbac8f63 1/*
678065d5 2 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
20f0af75
CW		 3 * Caesar Wang <wxt@rock-chips.com>
4 *
cbac8f63
CW		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23#include <linux/platform_device.h>
b9484763 24#include <linux/regmap.h>
cbac8f63
CW		 25#include <linux/reset.h>
26#include <linux/thermal.h>
b9484763 27#include <linux/mfd/syscon.h>
c970872e 28#include <linux/pinctrl/consumer.h>
cbac8f63
CW		 29
30/**
31 * If the temperature over a period of time High,
32 * the resulting TSHUT gave CRU module,let it reset the entire chip,
33 * or via GPIO give PMIC.
34 */
35enum tshut_mode {
36 TSHUT_MODE_CRU = 0,
37 TSHUT_MODE_GPIO,
38};
39
40/**
13c1cfda 41 * The system Temperature Sensors tshut(tshut) polarity
cbac8f63
CW		 42 * the bit 8 is tshut polarity.
43 * 0: low active, 1: high active
44 */
45enum tshut_polarity {
46 TSHUT_LOW_ACTIVE = 0,
47 TSHUT_HIGH_ACTIVE,
48};
49
50/**
1d98b618
CW		 51 * The system has two Temperature Sensors.
52 * sensor0 is for CPU, and sensor1 is for GPU.
cbac8f63
CW		 53 */
54enum sensor_id {
1d98b618 55 SENSOR_CPU = 0,
cbac8f63
CW		 56 SENSOR_GPU,
57};
58
020ba95d 59/**
13c1cfda 60 * The conversion table has the adc value and temperature.
952418a3
CW		 61 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
62 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
13c1cfda 63 */
020ba95d
CW		 64enum adc_sort_mode {
65 ADC_DECREMENT = 0,
66 ADC_INCREMENT,
67};
68
1d98b618
CW		 69/**
70 * The max sensors is two in rockchip SoCs.
71 * Two sensors: CPU and GPU sensor.
72 */
73#define SOC_MAX_SENSORS 2
74
13c1cfda 75/**
678065d5 76 * struct chip_tsadc_table - hold information about chip-specific differences
13c1cfda
CW		 77 * @id: conversion table
78 * @length: size of conversion table
79 * @data_mask: mask to apply on data inputs
80 * @mode: sort mode of this adc variant (incrementing or decrementing)
81 */
ce74110d
CW		 82struct chip_tsadc_table {
83 const struct tsadc_table *id;
ce74110d 84 unsigned int length;
ce74110d 85 u32 data_mask;
020ba95d 86 enum adc_sort_mode mode;
ce74110d
CW		 87};
88
678065d5
CW		 89/**
90 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
91 * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel
92 * @chn_num: the channel number of tsadc chip
93 * @tshut_temp: the hardware-controlled shutdown temperature value
94 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
95 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
96 * @initialize: SoC special initialize tsadc controller method
97 * @irq_ack: clear the interrupt
98 * @get_temp: get the temperature
99 * @set_tshut_temp: set the hardware-controlled shutdown temperature
100 * @set_tshut_mode: set the hardware-controlled shutdown mode
101 * @table: the chip-specific conversion table
102 */
cbac8f63 103struct rockchip_tsadc_chip {
1d98b618
CW		 104 /* The sensor id of chip correspond to the ADC channel */
105 int chn_id[SOC_MAX_SENSORS];
106 int chn_num;
107
cbac8f63 108 /* The hardware-controlled tshut property */
437df217 109 int tshut_temp;
cbac8f63
CW		 110 enum tshut_mode tshut_mode;
111 enum tshut_polarity tshut_polarity;
112
113 /* Chip-wide methods */
b9484763
CW		 114 void (*initialize)(struct regmap *grf,
115 void __iomem *reg, enum tshut_polarity p);
cbac8f63
CW		 116 void (*irq_ack)(void __iomem *reg);
117 void (*control)(void __iomem *reg, bool on);
118
119 /* Per-sensor methods */
ce74110d
CW		 120 int (*get_temp)(struct chip_tsadc_table table,
121 int chn, void __iomem *reg, int *temp);
122 void (*set_tshut_temp)(struct chip_tsadc_table table,
437df217 123 int chn, void __iomem *reg, int temp);
cbac8f63 124 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
ce74110d
CW		 125
126 /* Per-table methods */
127 struct chip_tsadc_table table;
cbac8f63
CW		 128};
129
678065d5
CW		 130/**
131 * struct rockchip_thermal_sensor - hold the information of thermal sensor
132 * @thermal: pointer to the platform/configuration data
133 * @tzd: pointer to a thermal zone
134 * @id: identifier of the thermal sensor
135 */
cbac8f63
CW		 136struct rockchip_thermal_sensor {
137 struct rockchip_thermal_data *thermal;
138 struct thermal_zone_device *tzd;
1d98b618 139 int id;
cbac8f63
CW		 140};
141
678065d5
CW		 142/**
143 * struct rockchip_thermal_data - hold the private data of thermal driver
144 * @chip: pointer to the platform/configuration data
145 * @pdev: platform device of thermal
146 * @reset: the reset controller of tsadc
147 * @sensors[SOC_MAX_SENSORS]: the thermal sensor
148 * @clk: the controller clock is divided by the exteral 24MHz
149 * @pclk: the advanced peripherals bus clock
150 * @grf: the general register file will be used to do static set by software
151 * @regs: the base address of tsadc controller
152 * @tshut_temp: the hardware-controlled shutdown temperature value
153 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
154 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
155 */
cbac8f63
CW		 156struct rockchip_thermal_data {
157 const struct rockchip_tsadc_chip *chip;
158 struct platform_device *pdev;
159 struct reset_control *reset;
160
1d98b618 161 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
cbac8f63
CW		 162
163 struct clk *clk;
164 struct clk *pclk;
165
b9484763 166 struct regmap *grf;
cbac8f63
CW		 167 void __iomem *regs;
168
437df217 169 int tshut_temp;
cbac8f63
CW		 170 enum tshut_mode tshut_mode;
171 enum tshut_polarity tshut_polarity;
172};
173
952418a3
CW		 174/**
175 * TSADC Sensor Register description:
176 *
177 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
178 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
179 *
180 */
b9484763 181#define TSADCV2_USER_CON 0x00
cbac8f63
CW		 182#define TSADCV2_AUTO_CON 0x04
183#define TSADCV2_INT_EN 0x08
184#define TSADCV2_INT_PD 0x0c
185#define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
186#define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
187#define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
188#define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
189#define TSADCV2_AUTO_PERIOD 0x68
190#define TSADCV2_AUTO_PERIOD_HT 0x6c
191
192#define TSADCV2_AUTO_EN BIT(0)
cbac8f63
CW		 193#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
194#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
678065d5 195
7ea38c6c 196#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
cbac8f63
CW		 197
198#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
199#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
200#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
201
452e01b3 202#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
952418a3 203#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
cbac8f63
CW		 204
205#define TSADCV2_DATA_MASK 0xfff
20f0af75
CW		 206#define TSADCV3_DATA_MASK 0x3ff
207
cbac8f63
CW		 208#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
209#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
210#define TSADCV2_AUTO_PERIOD_TIME 250 /* msec */
211#define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* msec */
b9484763
CW		 212#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
213
214#define GRF_SARADC_TESTBIT 0x0e644
215#define GRF_TSADC_TESTBIT_L 0x0e648
216#define GRF_TSADC_TESTBIT_H 0x0e64c
217
218#define GRF_TSADC_TSEN_PD_ON (0x30003 << 0)
219#define GRF_TSADC_TSEN_PD_OFF (0x30000 << 0)
220#define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
221#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
cbac8f63 222
7b02a5e7 223/**
678065d5
CW		 224 * struct tsadc_table - code to temperature conversion table
225 * @code: the value of adc channel
226 * @temp: the temperature
7b02a5e7 227 * Note:
678065d5 228 * code to temperature mapping of the temperature sensor is a piece wise linear
7b02a5e7
CW		 229 * curve.Any temperature, code faling between to 2 give temperatures can be
230 * linearly interpolated.
678065d5 231 * Code to Temperature mapping should be updated based on manufacturer results.
7b02a5e7 232 */
678065d5
CW		 233struct tsadc_table {
234 u32 code;
235 int temp;
236};
237
952418a3 238static const struct tsadc_table rk3228_code_table[] = {
7ea38c6c
CW		 239 {0, -40000},
240 {588, -40000},
241 {593, -35000},
242 {598, -30000},
243 {603, -25000},
244 {608, -20000},
245 {613, -15000},
246 {618, -10000},
247 {623, -5000},
248 {629, 0},
249 {634, 5000},
250 {639, 10000},
251 {644, 15000},
252 {649, 20000},
253 {654, 25000},
254 {660, 30000},
255 {665, 35000},
256 {670, 40000},
257 {675, 45000},
258 {681, 50000},
259 {686, 55000},
260 {691, 60000},
261 {696, 65000},
262 {702, 70000},
263 {707, 75000},
264 {712, 80000},
265 {717, 85000},
266 {723, 90000},
267 {728, 95000},
268 {733, 100000},
269 {738, 105000},
270 {744, 110000},
271 {749, 115000},
272 {754, 120000},
273 {760, 125000},
274 {TSADCV2_DATA_MASK, 125000},
7b02a5e7
CW		 275};
276
952418a3 277static const struct tsadc_table rk3288_code_table[] = {
cbac8f63
CW		 278 {TSADCV2_DATA_MASK, -40000},
279 {3800, -40000},
280 {3792, -35000},
281 {3783, -30000},
282 {3774, -25000},
283 {3765, -20000},
284 {3756, -15000},
285 {3747, -10000},
286 {3737, -5000},
287 {3728, 0},
288 {3718, 5000},
289 {3708, 10000},
290 {3698, 15000},
291 {3688, 20000},
292 {3678, 25000},
293 {3667, 30000},
294 {3656, 35000},
295 {3645, 40000},
296 {3634, 45000},
297 {3623, 50000},
298 {3611, 55000},
299 {3600, 60000},
300 {3588, 65000},
301 {3575, 70000},
302 {3563, 75000},
303 {3550, 80000},
304 {3537, 85000},
305 {3524, 90000},
306 {3510, 95000},
307 {3496, 100000},
308 {3482, 105000},
309 {3467, 110000},
310 {3452, 115000},
311 {3437, 120000},
312 {3421, 125000},
cbac8f63
CW		 313};
314
952418a3 315static const struct tsadc_table rk3368_code_table[] = {
20f0af75
CW		 316 {0, -40000},
317 {106, -40000},
318 {108, -35000},
319 {110, -30000},
320 {112, -25000},
321 {114, -20000},
322 {116, -15000},
323 {118, -10000},
324 {120, -5000},
325 {122, 0},
326 {124, 5000},
327 {126, 10000},
328 {128, 15000},
329 {130, 20000},
330 {132, 25000},
331 {134, 30000},
332 {136, 35000},
333 {138, 40000},
334 {140, 45000},
335 {142, 50000},
336 {144, 55000},
337 {146, 60000},
338 {148, 65000},
339 {150, 70000},
340 {152, 75000},
341 {154, 80000},
342 {156, 85000},
343 {158, 90000},
344 {160, 95000},
345 {162, 100000},
346 {163, 105000},
347 {165, 110000},
348 {167, 115000},
349 {169, 120000},
350 {171, 125000},
351 {TSADCV3_DATA_MASK, 125000},
352};
353
952418a3 354static const struct tsadc_table rk3399_code_table[] = {
7ea38c6c 355 {0, -40000},
f762a35d
CW		 356 {402, -40000},
357 {410, -35000},
358 {419, -30000},
359 {427, -25000},
360 {436, -20000},
361 {444, -15000},
362 {453, -10000},
363 {461, -5000},
364 {470, 0},
365 {478, 5000},
366 {487, 10000},
367 {496, 15000},
368 {504, 20000},
369 {513, 25000},
370 {521, 30000},
371 {530, 35000},
372 {538, 40000},
373 {547, 45000},
374 {555, 50000},
375 {564, 55000},
376 {573, 60000},
377 {581, 65000},
378 {590, 70000},
379 {599, 75000},
380 {607, 80000},
381 {616, 85000},
382 {624, 90000},
383 {633, 95000},
384 {642, 100000},
385 {650, 105000},
386 {659, 110000},
387 {668, 115000},
388 {677, 120000},
389 {685, 125000},
7ea38c6c 390 {TSADCV3_DATA_MASK, 125000},
b0d70338
CW		 391};
392
ce74110d 393static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table,
437df217 394 int temp)
cbac8f63
CW		 395{
396 int high, low, mid;
397
398 low = 0;
ce74110d 399 high = table.length - 1;
cbac8f63
CW		 400 mid = (high + low) / 2;
401
ce74110d 402 if (temp < table.id[low].temp || temp > table.id[high].temp)
cbac8f63
CW		 403 return 0;
404
405 while (low <= high) {
ce74110d
CW		 406 if (temp == table.id[mid].temp)
407 return table.id[mid].code;
408 else if (temp < table.id[mid].temp)
cbac8f63
CW		 409 high = mid - 1;
410 else
411 low = mid + 1;
412 mid = (low + high) / 2;
413 }
414
415 return 0;
416}
417
ce74110d
CW		 418static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code,
419 int *temp)
cbac8f63 420{
d9a241cb 421 unsigned int low = 1;
ce74110d 422 unsigned int high = table.length - 1;
1e9a1aea
CW		 423 unsigned int mid = (low + high) / 2;
424 unsigned int num;
425 unsigned long denom;
426
ce74110d 427 WARN_ON(table.length < 2);
1e9a1aea 428
020ba95d
CW		 429 switch (table.mode) {
430 case ADC_DECREMENT:
431 code &= table.data_mask;
432 if (code < table.id[high].code)
433 return -EAGAIN; /* Incorrect reading */
434
435 while (low <= high) {
436 if (code >= table.id[mid].code &&
437 code < table.id[mid - 1].code)
438 break;
439 else if (code < table.id[mid].code)
440 low = mid + 1;
441 else
442 high = mid - 1;
443
444 mid = (low + high) / 2;
445 }
446 break;
447 case ADC_INCREMENT:
448 code &= table.data_mask;
449 if (code < table.id[low].code)
450 return -EAGAIN; /* Incorrect reading */
451
452 while (low <= high) {
a87dd797
CW		 453 if (code <= table.id[mid].code &&
454 code > table.id[mid - 1].code)
020ba95d
CW		 455 break;
456 else if (code > table.id[mid].code)
457 low = mid + 1;
458 else
459 high = mid - 1;
460
461 mid = (low + high) / 2;
462 }
463 break;
464 default:
465 pr_err("Invalid the conversion table\n");
cbac8f63
CW		 466 }
467
1e9a1aea
CW		 468 /*
469 * The 5C granularity provided by the table is too much. Let's
470 * assume that the relationship between sensor readings and
471 * temperature between 2 table entries is linear and interpolate
472 * to produce less granular result.
473 */
1d37a037 474 num = table.id[mid].temp - table.id[mid - 1].temp;
020ba95d
CW		 475 num *= abs(table.id[mid - 1].code - code);
476 denom = abs(table.id[mid - 1].code - table.id[mid].code);
ce74110d 477 *temp = table.id[mid - 1].temp + (num / denom);
d9a241cb
DT		 478
479 return 0;
cbac8f63
CW		 480}
481
482/**
144c5565
CW		 483 * rk_tsadcv2_initialize - initialize TASDC Controller.
484 *
485 * (1) Set TSADC_V2_AUTO_PERIOD:
486 * Configure the interleave between every two accessing of
487 * TSADC in normal operation.
488 *
489 * (2) Set TSADCV2_AUTO_PERIOD_HT:
490 * Configure the interleave between every two accessing of
491 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
492 *
493 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
494 * If the temperature is higher than COMP_INT or COMP_SHUT for
495 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
cbac8f63 496 */
b9484763 497static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
cbac8f63
CW		 498 enum tshut_polarity tshut_polarity)
499{
500 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
452e01b3 501 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
cbac8f63
CW		 502 regs + TSADCV2_AUTO_CON);
503 else
452e01b3 504 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
cbac8f63
CW		 505 regs + TSADCV2_AUTO_CON);
506
507 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
508 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
509 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
510 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
511 regs + TSADCV2_AUTO_PERIOD_HT);
512 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
513 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
b9484763
CW		 514
515 if (IS_ERR(grf)) {
516 pr_warn("%s: Missing rockchip,grf property\n", __func__);
517 return;
518 }
519}
520
521/**
522 * rk_tsadcv3_initialize - initialize TASDC Controller.
678065d5 523 *
b9484763
CW		 524 * (1) The tsadc control power sequence.
525 *
526 * (2) Set TSADC_V2_AUTO_PERIOD:
527 * Configure the interleave between every two accessing of
528 * TSADC in normal operation.
529 *
530 * (2) Set TSADCV2_AUTO_PERIOD_HT:
531 * Configure the interleave between every two accessing of
532 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
533 *
534 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
535 * If the temperature is higher than COMP_INT or COMP_SHUT for
536 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
537 */
538static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
539 enum tshut_polarity tshut_polarity)
540{
541 /* The tsadc control power sequence */
542 if (IS_ERR(grf)) {
543 /* Set interleave value to workround ic time sync issue */
544 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
545 TSADCV2_USER_CON);
546 } else {
547 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_TSEN_PD_ON);
548 mdelay(10);
549 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_TSEN_PD_OFF);
2fe5c1b0 550 usleep_range(15, 100); /* The spec note says at least 15 us */
b9484763
CW		 551 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
552 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
2fe5c1b0 553 usleep_range(90, 200); /* The spec note says at least 90 us */
b9484763
CW		 554 }
555
556 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
557 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
558 regs + TSADCV2_AUTO_CON);
559 else
560 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
561 regs + TSADCV2_AUTO_CON);
562
563 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
564 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
565 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
566 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
567 regs + TSADCV2_AUTO_PERIOD_HT);
568 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
569 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
cbac8f63
CW		 570}
571
952418a3 572static void rk_tsadcv2_irq_ack(void __iomem *regs)
7b02a5e7
CW		 573{
574 u32 val;
575
576 val = readl_relaxed(regs + TSADCV2_INT_PD);
952418a3 577 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
7b02a5e7
CW		 578}
579
952418a3 580static void rk_tsadcv3_irq_ack(void __iomem *regs)
cbac8f63
CW		 581{
582 u32 val;
583
584 val = readl_relaxed(regs + TSADCV2_INT_PD);
952418a3 585 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
cbac8f63
CW		 586}
587
588static void rk_tsadcv2_control(void __iomem *regs, bool enable)
589{
590 u32 val;
591
592 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
593 if (enable)
594 val |= TSADCV2_AUTO_EN;
595 else
596 val &= ~TSADCV2_AUTO_EN;
597
598 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
599}
600
7ea38c6c 601/**
678065d5
CW		 602 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
603 *
604 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
605 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
606 * adc value if setting this bit to enable.
7ea38c6c
CW		 607 */
608static void rk_tsadcv3_control(void __iomem *regs, bool enable)
609{
610 u32 val;
611
612 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
613 if (enable)
614 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
615 else
616 val &= ~TSADCV2_AUTO_EN;
617
618 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
619}
620
ce74110d
CW		 621static int rk_tsadcv2_get_temp(struct chip_tsadc_table table,
622 int chn, void __iomem *regs, int *temp)
cbac8f63
CW		 623{
624 u32 val;
625
cbac8f63 626 val = readl_relaxed(regs + TSADCV2_DATA(chn));
cbac8f63 627
ce74110d 628 return rk_tsadcv2_code_to_temp(table, val, temp);
cbac8f63
CW		 629}
630
ce74110d 631static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table,
437df217 632 int chn, void __iomem *regs, int temp)
cbac8f63
CW		 633{
634 u32 tshut_value, val;
635
ce74110d 636 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
cbac8f63
CW		 637 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
638
639 /* TSHUT will be valid */
640 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
641 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
642}
643
644static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
645 enum tshut_mode mode)
646{
647 u32 val;
648
649 val = readl_relaxed(regs + TSADCV2_INT_EN);
650 if (mode == TSHUT_MODE_GPIO) {
651 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
652 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
653 } else {
654 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
655 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
656 }
657
658 writel_relaxed(val, regs + TSADCV2_INT_EN);
659}
660
7b02a5e7
CW		 661static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
662 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
663 .chn_num = 1, /* one channel for tsadc */
664
665 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
666 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
667 .tshut_temp = 95000,
668
669 .initialize = rk_tsadcv2_initialize,
952418a3 670 .irq_ack = rk_tsadcv3_irq_ack,
7ea38c6c 671 .control = rk_tsadcv3_control,
7b02a5e7
CW		 672 .get_temp = rk_tsadcv2_get_temp,
673 .set_tshut_temp = rk_tsadcv2_tshut_temp,
674 .set_tshut_mode = rk_tsadcv2_tshut_mode,
675
676 .table = {
952418a3
CW		 677 .id = rk3228_code_table,
678 .length = ARRAY_SIZE(rk3228_code_table),
7b02a5e7 679 .data_mask = TSADCV3_DATA_MASK,
7ea38c6c 680 .mode = ADC_INCREMENT,
7b02a5e7
CW		 681 },
682};
683
cbac8f63 684static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
1d98b618
CW		 685 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
686 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
687 .chn_num = 2, /* two channels for tsadc */
688
cbac8f63
CW		 689 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
690 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
691 .tshut_temp = 95000,
692
693 .initialize = rk_tsadcv2_initialize,
694 .irq_ack = rk_tsadcv2_irq_ack,
695 .control = rk_tsadcv2_control,
696 .get_temp = rk_tsadcv2_get_temp,
697 .set_tshut_temp = rk_tsadcv2_tshut_temp,
698 .set_tshut_mode = rk_tsadcv2_tshut_mode,
ce74110d
CW		 699
700 .table = {
952418a3
CW		 701 .id = rk3288_code_table,
702 .length = ARRAY_SIZE(rk3288_code_table),
ce74110d 703 .data_mask = TSADCV2_DATA_MASK,
020ba95d 704 .mode = ADC_DECREMENT,
ce74110d 705 },
cbac8f63
CW		 706};
707
1cd60269
EZ		 708static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
709 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
710 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
711 .chn_num = 2, /* two channels for tsadc */
712
713 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
714 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
715 .tshut_temp = 95000,
716
717 .initialize = rk_tsadcv3_initialize,
718 .irq_ack = rk_tsadcv3_irq_ack,
719 .control = rk_tsadcv3_control,
720 .get_temp = rk_tsadcv2_get_temp,
721 .set_tshut_temp = rk_tsadcv2_tshut_temp,
722 .set_tshut_mode = rk_tsadcv2_tshut_mode,
723
724 .table = {
725 .id = rk3228_code_table,
726 .length = ARRAY_SIZE(rk3228_code_table),
727 .data_mask = TSADCV3_DATA_MASK,
728 .mode = ADC_INCREMENT,
729 },
730};
731
20f0af75
CW		 732static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
733 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
734 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
735 .chn_num = 2, /* two channels for tsadc */
736
737 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
738 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
739 .tshut_temp = 95000,
740
741 .initialize = rk_tsadcv2_initialize,
742 .irq_ack = rk_tsadcv2_irq_ack,
743 .control = rk_tsadcv2_control,
744 .get_temp = rk_tsadcv2_get_temp,
745 .set_tshut_temp = rk_tsadcv2_tshut_temp,
746 .set_tshut_mode = rk_tsadcv2_tshut_mode,
747
748 .table = {
952418a3
CW		 749 .id = rk3368_code_table,
750 .length = ARRAY_SIZE(rk3368_code_table),
20f0af75
CW		 751 .data_mask = TSADCV3_DATA_MASK,
752 .mode = ADC_INCREMENT,
753 },
754};
755
b0d70338
CW		 756static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
757 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
758 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
759 .chn_num = 2, /* two channels for tsadc */
760
761 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
762 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
763 .tshut_temp = 95000,
764
b9484763 765 .initialize = rk_tsadcv3_initialize,
952418a3 766 .irq_ack = rk_tsadcv3_irq_ack,
7ea38c6c 767 .control = rk_tsadcv3_control,
b0d70338
CW		 768 .get_temp = rk_tsadcv2_get_temp,
769 .set_tshut_temp = rk_tsadcv2_tshut_temp,
770 .set_tshut_mode = rk_tsadcv2_tshut_mode,
771
772 .table = {
952418a3
CW		 773 .id = rk3399_code_table,
774 .length = ARRAY_SIZE(rk3399_code_table),
b0d70338 775 .data_mask = TSADCV3_DATA_MASK,
7ea38c6c 776 .mode = ADC_INCREMENT,
b0d70338
CW		 777 },
778};
779
cbac8f63 780static const struct of_device_id of_rockchip_thermal_match[] = {
7b02a5e7
CW		 781 {
782 .compatible = "rockchip,rk3228-tsadc",
783 .data = (void *)&rk3228_tsadc_data,
784 },
cbac8f63
CW		 785 {
786 .compatible = "rockchip,rk3288-tsadc",
787 .data = (void *)&rk3288_tsadc_data,
788 },
1cd60269
EZ		 789 {
790 .compatible = "rockchip,rk3366-tsadc",
791 .data = (void *)&rk3366_tsadc_data,
792 },
20f0af75
CW		 793 {
794 .compatible = "rockchip,rk3368-tsadc",
795 .data = (void *)&rk3368_tsadc_data,
796 },
b0d70338
CW		 797 {
798 .compatible = "rockchip,rk3399-tsadc",
799 .data = (void *)&rk3399_tsadc_data,
800 },
cbac8f63
CW		 801 { /* end */ },
802};
803MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
804
805static void
806rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
807{
808 struct thermal_zone_device *tzd = sensor->tzd;
809
810 tzd->ops->set_mode(tzd,
811 on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
812}
813
814static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
815{
816 struct rockchip_thermal_data *thermal = dev;
817 int i;
818
819 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
820
821 thermal->chip->irq_ack(thermal->regs);
822
1d98b618 823 for (i = 0; i < thermal->chip->chn_num; i++)
cbac8f63
CW		 824 thermal_zone_device_update(thermal->sensors[i].tzd);
825
826 return IRQ_HANDLED;
827}
828
17e8351a 829static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
cbac8f63
CW		 830{
831 struct rockchip_thermal_sensor *sensor = _sensor;
832 struct rockchip_thermal_data *thermal = sensor->thermal;
833 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
834 int retval;
835
ce74110d
CW		 836 retval = tsadc->get_temp(tsadc->table,
837 sensor->id, thermal->regs, out_temp);
17e8351a 838 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
cbac8f63
CW		 839 sensor->id, *out_temp, retval);
840
841 return retval;
842}
843
844static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
845 .get_temp = rockchip_thermal_get_temp,
846};
847
848static int rockchip_configure_from_dt(struct device *dev,
849 struct device_node *np,
850 struct rockchip_thermal_data *thermal)
851{
852 u32 shut_temp, tshut_mode, tshut_polarity;
853
854 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
855 dev_warn(dev,
437df217 856 "Missing tshut temp property, using default %d\n",
cbac8f63
CW		 857 thermal->chip->tshut_temp);
858 thermal->tshut_temp = thermal->chip->tshut_temp;
859 } else {
43b4eb9f
CW		 860 if (shut_temp > INT_MAX) {
861 dev_err(dev, "Invalid tshut temperature specified: %d\n",
862 shut_temp);
863 return -ERANGE;
864 }
cbac8f63
CW		 865 thermal->tshut_temp = shut_temp;
866 }
867
cbac8f63
CW		 868 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
869 dev_warn(dev,
870 "Missing tshut mode property, using default (%s)\n",
871 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
872 "gpio" : "cru");
873 thermal->tshut_mode = thermal->chip->tshut_mode;
874 } else {
875 thermal->tshut_mode = tshut_mode;
876 }
877
878 if (thermal->tshut_mode > 1) {
879 dev_err(dev, "Invalid tshut mode specified: %d\n",
880 thermal->tshut_mode);
881 return -EINVAL;
882 }
883
884 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
885 &tshut_polarity)) {
886 dev_warn(dev,
887 "Missing tshut-polarity property, using default (%s)\n",
888 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
889 "low" : "high");
890 thermal->tshut_polarity = thermal->chip->tshut_polarity;
891 } else {
892 thermal->tshut_polarity = tshut_polarity;
893 }
894
895 if (thermal->tshut_polarity > 1) {
896 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
897 thermal->tshut_polarity);
898 return -EINVAL;
899 }
900
b9484763
CW		 901 /* The tsadc wont to handle the error in here since some SoCs didn't
902 * need this property.
903 */
904 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
905
cbac8f63
CW		 906 return 0;
907}
908
909static int
910rockchip_thermal_register_sensor(struct platform_device *pdev,
911 struct rockchip_thermal_data *thermal,
912 struct rockchip_thermal_sensor *sensor,
1d98b618 913 int id)
cbac8f63
CW		 914{
915 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
916 int error;
917
918 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
ce74110d
CW		 919 tsadc->set_tshut_temp(tsadc->table, id, thermal->regs,
920 thermal->tshut_temp);
cbac8f63
CW		 921
922 sensor->thermal = thermal;
923 sensor->id = id;
2633ad19
EV		 924 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
925 sensor, &rockchip_of_thermal_ops);
cbac8f63
CW		 926 if (IS_ERR(sensor->tzd)) {
927 error = PTR_ERR(sensor->tzd);
928 dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
929 id, error);
930 return error;
931 }
932
933 return 0;
934}
935
13c1cfda 936/**
cbac8f63
CW		 937 * Reset TSADC Controller, reset all tsadc registers.
938 */
939static void rockchip_thermal_reset_controller(struct reset_control *reset)
940{
941 reset_control_assert(reset);
942 usleep_range(10, 20);
943 reset_control_deassert(reset);
944}
945
946static int rockchip_thermal_probe(struct platform_device *pdev)
947{
948 struct device_node *np = pdev->dev.of_node;
949 struct rockchip_thermal_data *thermal;
950 const struct of_device_id *match;
951 struct resource *res;
952 int irq;
2633ad19 953 int i;
cbac8f63
CW		 954 int error;
955
956 match = of_match_node(of_rockchip_thermal_match, np);
957 if (!match)
958 return -ENXIO;
959
960 irq = platform_get_irq(pdev, 0);
961 if (irq < 0) {
962 dev_err(&pdev->dev, "no irq resource?\n");
963 return -EINVAL;
964 }
965
966 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
967 GFP_KERNEL);
968 if (!thermal)
969 return -ENOMEM;
970
971 thermal->pdev = pdev;
972
973 thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
974 if (!thermal->chip)
975 return -EINVAL;
976
977 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
978 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
979 if (IS_ERR(thermal->regs))
980 return PTR_ERR(thermal->regs);
981
982 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
983 if (IS_ERR(thermal->reset)) {
984 error = PTR_ERR(thermal->reset);
985 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
986 return error;
987 }
988
989 thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
990 if (IS_ERR(thermal->clk)) {
991 error = PTR_ERR(thermal->clk);
992 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
993 return error;
994 }
995
996 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
997 if (IS_ERR(thermal->pclk)) {
0d0a2bf6 998 error = PTR_ERR(thermal->pclk);
cbac8f63
CW		 999 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
1000 error);
1001 return error;
1002 }
1003
1004 error = clk_prepare_enable(thermal->clk);
1005 if (error) {
1006 dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
1007 error);
1008 return error;
1009 }
1010
1011 error = clk_prepare_enable(thermal->pclk);
1012 if (error) {
1013 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
1014 goto err_disable_clk;
1015 }
1016
1017 rockchip_thermal_reset_controller(thermal->reset);
1018
1019 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1020 if (error) {
1021 dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
1022 error);
1023 goto err_disable_pclk;
1024 }
1025
b9484763
CW		 1026 thermal->chip->initialize(thermal->grf, thermal->regs,
1027 thermal->tshut_polarity);
cbac8f63 1028
1d98b618
CW		 1029 for (i = 0; i < thermal->chip->chn_num; i++) {
1030 error = rockchip_thermal_register_sensor(pdev, thermal,
1031 &thermal->sensors[i],
1032 thermal->chip->chn_id[i]);
1033 if (error) {
1034 dev_err(&pdev->dev,
1035 "failed to register sensor[%d] : error = %d\n",
1036 i, error);
1d98b618
CW		 1037 goto err_disable_pclk;
1038 }
cbac8f63
CW		 1039 }
1040
1041 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1042 &rockchip_thermal_alarm_irq_thread,
1043 IRQF_ONESHOT,
1044 "rockchip_thermal", thermal);
1045 if (error) {
1046 dev_err(&pdev->dev,
1047 "failed to request tsadc irq: %d\n", error);
2633ad19 1048 goto err_disable_pclk;
cbac8f63
CW		 1049 }
1050
1051 thermal->chip->control(thermal->regs, true);
1052
1d98b618 1053 for (i = 0; i < thermal->chip->chn_num; i++)
cbac8f63
CW		 1054 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1055
1056 platform_set_drvdata(pdev, thermal);
1057
1058 return 0;
1059
cbac8f63
CW		 1060err_disable_pclk:
1061 clk_disable_unprepare(thermal->pclk);
1062err_disable_clk:
1063 clk_disable_unprepare(thermal->clk);
1064
1065 return error;
1066}
1067
1068static int rockchip_thermal_remove(struct platform_device *pdev)
1069{
1070 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1071 int i;
1072
1d98b618 1073 for (i = 0; i < thermal->chip->chn_num; i++) {
cbac8f63
CW		 1074 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1075
1076 rockchip_thermal_toggle_sensor(sensor, false);
cbac8f63
CW		 1077 }
1078
1079 thermal->chip->control(thermal->regs, false);
1080
1081 clk_disable_unprepare(thermal->pclk);
1082 clk_disable_unprepare(thermal->clk);
1083
1084 return 0;
1085}
1086
1087static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1088{
1089 struct platform_device *pdev = to_platform_device(dev);
1090 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1091 int i;
1092
1d98b618 1093 for (i = 0; i < thermal->chip->chn_num; i++)
cbac8f63
CW		 1094 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1095
1096 thermal->chip->control(thermal->regs, false);
1097
1098 clk_disable(thermal->pclk);
1099 clk_disable(thermal->clk);
1100
7e38a5b1
CW		 1101 pinctrl_pm_select_sleep_state(dev);
1102
cbac8f63
CW		 1103 return 0;
1104}
1105
1106static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1107{
1108 struct platform_device *pdev = to_platform_device(dev);
1109 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1110 int i;
1111 int error;
1112
1113 error = clk_enable(thermal->clk);
1114 if (error)
1115 return error;
1116
1117 error = clk_enable(thermal->pclk);
ab5b52f1
SL		 1118 if (error) {
1119 clk_disable(thermal->clk);
cbac8f63 1120 return error;
ab5b52f1 1121 }
cbac8f63
CW		 1122
1123 rockchip_thermal_reset_controller(thermal->reset);
1124
b9484763
CW		 1125 thermal->chip->initialize(thermal->grf, thermal->regs,
1126 thermal->tshut_polarity);
cbac8f63 1127
1d98b618
CW		 1128 for (i = 0; i < thermal->chip->chn_num; i++) {
1129 int id = thermal->sensors[i].id;
cbac8f63
CW		 1130
1131 thermal->chip->set_tshut_mode(id, thermal->regs,
1132 thermal->tshut_mode);
ce74110d
CW		 1133 thermal->chip->set_tshut_temp(thermal->chip->table,
1134 id, thermal->regs,
cbac8f63
CW		 1135 thermal->tshut_temp);
1136 }
1137
1138 thermal->chip->control(thermal->regs, true);
1139
1d98b618 1140 for (i = 0; i < thermal->chip->chn_num; i++)
cbac8f63
CW		 1141 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1142
7e38a5b1
CW		 1143 pinctrl_pm_select_default_state(dev);
1144
cbac8f63
CW		 1145 return 0;
1146}
1147
1148static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1149 rockchip_thermal_suspend, rockchip_thermal_resume);
1150
1151static struct platform_driver rockchip_thermal_driver = {
1152 .driver = {
1153 .name = "rockchip-thermal",
cbac8f63
CW		 1154 .pm = &rockchip_thermal_pm_ops,
1155 .of_match_table = of_rockchip_thermal_match,
1156 },
1157 .probe = rockchip_thermal_probe,
1158 .remove = rockchip_thermal_remove,
1159};
1160
1161module_platform_driver(rockchip_thermal_driver);
1162
1163MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1164MODULE_AUTHOR("Rockchip, Inc.");
1165MODULE_LICENSE("GPL v2");
1166MODULE_ALIAS("platform:rockchip-thermal");
Linux kernel - Deliverables
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