Commit | Line | Data |
---|---|---|
9d97e5c8 | 1 | /* |
59dfa54c | 2 | * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) |
9d97e5c8 DK |
3 | * |
4 | * Copyright (C) 2011 Samsung Electronics | |
5 | * Donggeun Kim <dg77.kim@samsung.com> | |
c48cbba6 | 6 | * Amit Daniel Kachhap <amit.kachhap@linaro.org> |
9d97e5c8 DK |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
9d97e5c8 | 24 | #include <linux/clk.h> |
9d97e5c8 | 25 | #include <linux/io.h> |
1b678641 ADK |
26 | #include <linux/interrupt.h> |
27 | #include <linux/module.h> | |
f22d9c03 | 28 | #include <linux/of.h> |
1b678641 | 29 | #include <linux/platform_device.h> |
1b678641 ADK |
30 | |
31 | #include "exynos_thermal_common.h" | |
0c1836a6 | 32 | #include "exynos_tmu.h" |
e6b7991e | 33 | #include "exynos_tmu_data.h" |
f22d9c03 | 34 | |
f22d9c03 ADK |
35 | struct exynos_tmu_data { |
36 | struct exynos_tmu_platform_data *pdata; | |
9d97e5c8 DK |
37 | struct resource *mem; |
38 | void __iomem *base; | |
39 | int irq; | |
f22d9c03 | 40 | enum soc_type soc; |
9d97e5c8 DK |
41 | struct work_struct irq_work; |
42 | struct mutex lock; | |
43 | struct clk *clk; | |
44 | u8 temp_error1, temp_error2; | |
45 | }; | |
46 | ||
47 | /* | |
48 | * TMU treats temperature as a mapped temperature code. | |
49 | * The temperature is converted differently depending on the calibration type. | |
50 | */ | |
f22d9c03 | 51 | static int temp_to_code(struct exynos_tmu_data *data, u8 temp) |
9d97e5c8 | 52 | { |
f22d9c03 | 53 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
54 | int temp_code; |
55 | ||
f22d9c03 ADK |
56 | if (data->soc == SOC_ARCH_EXYNOS4210) |
57 | /* temp should range between 25 and 125 */ | |
58 | if (temp < 25 || temp > 125) { | |
59 | temp_code = -EINVAL; | |
60 | goto out; | |
61 | } | |
9d97e5c8 DK |
62 | |
63 | switch (pdata->cal_type) { | |
64 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
65 | temp_code = (temp - pdata->first_point_trim) * |
66 | (data->temp_error2 - data->temp_error1) / | |
67 | (pdata->second_point_trim - pdata->first_point_trim) + | |
68 | data->temp_error1; | |
9d97e5c8 DK |
69 | break; |
70 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 71 | temp_code = temp + data->temp_error1 - pdata->first_point_trim; |
9d97e5c8 DK |
72 | break; |
73 | default: | |
bb34b4c8 | 74 | temp_code = temp + pdata->default_temp_offset; |
9d97e5c8 DK |
75 | break; |
76 | } | |
77 | out: | |
78 | return temp_code; | |
79 | } | |
80 | ||
81 | /* | |
82 | * Calculate a temperature value from a temperature code. | |
83 | * The unit of the temperature is degree Celsius. | |
84 | */ | |
f22d9c03 | 85 | static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code) |
9d97e5c8 | 86 | { |
f22d9c03 | 87 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
88 | int temp; |
89 | ||
f22d9c03 ADK |
90 | if (data->soc == SOC_ARCH_EXYNOS4210) |
91 | /* temp_code should range between 75 and 175 */ | |
92 | if (temp_code < 75 || temp_code > 175) { | |
93 | temp = -ENODATA; | |
94 | goto out; | |
95 | } | |
9d97e5c8 DK |
96 | |
97 | switch (pdata->cal_type) { | |
98 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
99 | temp = (temp_code - data->temp_error1) * |
100 | (pdata->second_point_trim - pdata->first_point_trim) / | |
101 | (data->temp_error2 - data->temp_error1) + | |
102 | pdata->first_point_trim; | |
9d97e5c8 DK |
103 | break; |
104 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 105 | temp = temp_code - data->temp_error1 + pdata->first_point_trim; |
9d97e5c8 DK |
106 | break; |
107 | default: | |
bb34b4c8 | 108 | temp = temp_code - pdata->default_temp_offset; |
9d97e5c8 DK |
109 | break; |
110 | } | |
111 | out: | |
112 | return temp; | |
113 | } | |
114 | ||
f22d9c03 | 115 | static int exynos_tmu_initialize(struct platform_device *pdev) |
9d97e5c8 | 116 | { |
f22d9c03 ADK |
117 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
118 | struct exynos_tmu_platform_data *pdata = data->pdata; | |
b8d582b9 | 119 | const struct exynos_tmu_registers *reg = pdata->registers; |
7ca04e58 | 120 | unsigned int status, trim_info = 0, con; |
4f0a6847 JL |
121 | unsigned int rising_threshold = 0, falling_threshold = 0; |
122 | int ret = 0, threshold_code, i, trigger_levs = 0; | |
9d97e5c8 DK |
123 | |
124 | mutex_lock(&data->lock); | |
125 | clk_enable(data->clk); | |
126 | ||
b8d582b9 | 127 | status = readb(data->base + reg->tmu_status); |
9d97e5c8 DK |
128 | if (!status) { |
129 | ret = -EBUSY; | |
130 | goto out; | |
131 | } | |
132 | ||
b8d582b9 ADK |
133 | if (data->soc == SOC_ARCH_EXYNOS) |
134 | __raw_writel(1, data->base + reg->triminfo_ctrl); | |
135 | ||
9d97e5c8 | 136 | /* Save trimming info in order to perform calibration */ |
b8d582b9 ADK |
137 | trim_info = readl(data->base + reg->triminfo_data); |
138 | data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; | |
139 | data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) & | |
140 | EXYNOS_TMU_TEMP_MASK); | |
f22d9c03 | 141 | |
bb34b4c8 ADK |
142 | if ((pdata->min_efuse_value > data->temp_error1) || |
143 | (data->temp_error1 > pdata->max_efuse_value) || | |
f22d9c03 ADK |
144 | (data->temp_error2 != 0)) |
145 | data->temp_error1 = pdata->efuse_value; | |
146 | ||
7ca04e58 ADK |
147 | if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) { |
148 | dev_err(&pdev->dev, "Invalid max trigger level\n"); | |
149 | goto out; | |
150 | } | |
151 | ||
152 | for (i = 0; i < pdata->max_trigger_level; i++) { | |
153 | if (!pdata->trigger_levels[i]) | |
154 | continue; | |
155 | ||
156 | if ((pdata->trigger_type[i] == HW_TRIP) && | |
157 | (!pdata->trigger_levels[pdata->max_trigger_level - 1])) { | |
158 | dev_err(&pdev->dev, "Invalid hw trigger level\n"); | |
159 | ret = -EINVAL; | |
160 | goto out; | |
161 | } | |
162 | ||
163 | /* Count trigger levels except the HW trip*/ | |
164 | if (!(pdata->trigger_type[i] == HW_TRIP)) | |
4f0a6847 | 165 | trigger_levs++; |
7ca04e58 | 166 | } |
4f0a6847 | 167 | |
f22d9c03 ADK |
168 | if (data->soc == SOC_ARCH_EXYNOS4210) { |
169 | /* Write temperature code for threshold */ | |
170 | threshold_code = temp_to_code(data, pdata->threshold); | |
171 | if (threshold_code < 0) { | |
172 | ret = threshold_code; | |
173 | goto out; | |
174 | } | |
175 | writeb(threshold_code, | |
b8d582b9 | 176 | data->base + reg->threshold_temp); |
4f0a6847 | 177 | for (i = 0; i < trigger_levs; i++) |
b8d582b9 ADK |
178 | writeb(pdata->trigger_levels[i], data->base + |
179 | reg->threshold_th0 + i * sizeof(reg->threshold_th0)); | |
f22d9c03 | 180 | |
b8d582b9 | 181 | writel(reg->inten_rise_mask, data->base + reg->tmu_intclear); |
f22d9c03 | 182 | } else if (data->soc == SOC_ARCH_EXYNOS) { |
4f0a6847 | 183 | /* Write temperature code for rising and falling threshold */ |
7ca04e58 ADK |
184 | for (i = 0; |
185 | i < trigger_levs && i < EXYNOS_MAX_TRIGGER_PER_REG; i++) { | |
4f0a6847 JL |
186 | threshold_code = temp_to_code(data, |
187 | pdata->trigger_levels[i]); | |
188 | if (threshold_code < 0) { | |
189 | ret = threshold_code; | |
190 | goto out; | |
191 | } | |
192 | rising_threshold |= threshold_code << 8 * i; | |
193 | if (pdata->threshold_falling) { | |
194 | threshold_code = temp_to_code(data, | |
195 | pdata->trigger_levels[i] - | |
196 | pdata->threshold_falling); | |
197 | if (threshold_code > 0) | |
198 | falling_threshold |= | |
199 | threshold_code << 8 * i; | |
200 | } | |
f22d9c03 | 201 | } |
f22d9c03 ADK |
202 | |
203 | writel(rising_threshold, | |
b8d582b9 | 204 | data->base + reg->threshold_th0); |
4f0a6847 | 205 | writel(falling_threshold, |
b8d582b9 | 206 | data->base + reg->threshold_th1); |
f22d9c03 | 207 | |
b8d582b9 ADK |
208 | writel((reg->inten_rise_mask << reg->inten_rise_shift) | |
209 | (reg->inten_fall_mask << reg->inten_fall_shift), | |
210 | data->base + reg->tmu_intclear); | |
7ca04e58 ADK |
211 | |
212 | /* if last threshold limit is also present */ | |
213 | i = pdata->max_trigger_level - 1; | |
214 | if (pdata->trigger_levels[i] && | |
215 | (pdata->trigger_type[i] == HW_TRIP)) { | |
216 | threshold_code = temp_to_code(data, | |
217 | pdata->trigger_levels[i]); | |
218 | if (threshold_code < 0) { | |
219 | ret = threshold_code; | |
220 | goto out; | |
221 | } | |
222 | rising_threshold |= threshold_code << 8 * i; | |
223 | writel(rising_threshold, | |
224 | data->base + reg->threshold_th0); | |
225 | con = readl(data->base + reg->tmu_ctrl); | |
226 | con |= (1 << reg->therm_trip_en_shift); | |
227 | writel(con, data->base + reg->tmu_ctrl); | |
228 | } | |
9d97e5c8 | 229 | } |
9d97e5c8 DK |
230 | out: |
231 | clk_disable(data->clk); | |
232 | mutex_unlock(&data->lock); | |
233 | ||
234 | return ret; | |
235 | } | |
236 | ||
f22d9c03 | 237 | static void exynos_tmu_control(struct platform_device *pdev, bool on) |
9d97e5c8 | 238 | { |
f22d9c03 ADK |
239 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
240 | struct exynos_tmu_platform_data *pdata = data->pdata; | |
b8d582b9 | 241 | const struct exynos_tmu_registers *reg = pdata->registers; |
9d97e5c8 DK |
242 | unsigned int con, interrupt_en; |
243 | ||
244 | mutex_lock(&data->lock); | |
245 | clk_enable(data->clk); | |
246 | ||
b8d582b9 | 247 | con = readl(data->base + reg->tmu_ctrl); |
f22d9c03 | 248 | |
d0a0ce3e | 249 | if (pdata->reference_voltage) { |
b8d582b9 ADK |
250 | con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift); |
251 | con |= pdata->reference_voltage << reg->buf_vref_sel_shift; | |
d0a0ce3e ADK |
252 | } |
253 | ||
254 | if (pdata->gain) { | |
b8d582b9 ADK |
255 | con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift); |
256 | con |= (pdata->gain << reg->buf_slope_sel_shift); | |
d0a0ce3e ADK |
257 | } |
258 | ||
259 | if (pdata->noise_cancel_mode) { | |
b8d582b9 ADK |
260 | con &= ~(reg->therm_trip_mode_mask << |
261 | reg->therm_trip_mode_shift); | |
262 | con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift); | |
f22d9c03 ADK |
263 | } |
264 | ||
9d97e5c8 | 265 | if (on) { |
b8d582b9 | 266 | con |= (1 << reg->core_en_shift); |
d0a0ce3e | 267 | interrupt_en = |
b8d582b9 ADK |
268 | pdata->trigger_enable[3] << reg->inten_rise3_shift | |
269 | pdata->trigger_enable[2] << reg->inten_rise2_shift | | |
270 | pdata->trigger_enable[1] << reg->inten_rise1_shift | | |
271 | pdata->trigger_enable[0] << reg->inten_rise0_shift; | |
4f0a6847 | 272 | if (pdata->threshold_falling) |
d0a0ce3e | 273 | interrupt_en |= |
b8d582b9 | 274 | interrupt_en << reg->inten_fall0_shift; |
9d97e5c8 | 275 | } else { |
b8d582b9 | 276 | con &= ~(1 << reg->core_en_shift); |
9d97e5c8 DK |
277 | interrupt_en = 0; /* Disable all interrupts */ |
278 | } | |
b8d582b9 ADK |
279 | writel(interrupt_en, data->base + reg->tmu_inten); |
280 | writel(con, data->base + reg->tmu_ctrl); | |
9d97e5c8 DK |
281 | |
282 | clk_disable(data->clk); | |
283 | mutex_unlock(&data->lock); | |
284 | } | |
285 | ||
f22d9c03 | 286 | static int exynos_tmu_read(struct exynos_tmu_data *data) |
9d97e5c8 | 287 | { |
b8d582b9 ADK |
288 | struct exynos_tmu_platform_data *pdata = data->pdata; |
289 | const struct exynos_tmu_registers *reg = pdata->registers; | |
9d97e5c8 DK |
290 | u8 temp_code; |
291 | int temp; | |
292 | ||
293 | mutex_lock(&data->lock); | |
294 | clk_enable(data->clk); | |
295 | ||
b8d582b9 | 296 | temp_code = readb(data->base + reg->tmu_cur_temp); |
9d97e5c8 DK |
297 | temp = code_to_temp(data, temp_code); |
298 | ||
299 | clk_disable(data->clk); | |
300 | mutex_unlock(&data->lock); | |
301 | ||
302 | return temp; | |
303 | } | |
304 | ||
bffd1f8a ADK |
305 | #ifdef CONFIG_THERMAL_EMULATION |
306 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) | |
307 | { | |
308 | struct exynos_tmu_data *data = drv_data; | |
b8d582b9 ADK |
309 | struct exynos_tmu_platform_data *pdata = data->pdata; |
310 | const struct exynos_tmu_registers *reg = pdata->registers; | |
311 | unsigned int val; | |
bffd1f8a ADK |
312 | int ret = -EINVAL; |
313 | ||
314 | if (data->soc == SOC_ARCH_EXYNOS4210) | |
315 | goto out; | |
316 | ||
317 | if (temp && temp < MCELSIUS) | |
318 | goto out; | |
319 | ||
320 | mutex_lock(&data->lock); | |
321 | clk_enable(data->clk); | |
322 | ||
b8d582b9 | 323 | val = readl(data->base + reg->emul_con); |
bffd1f8a ADK |
324 | |
325 | if (temp) { | |
326 | temp /= MCELSIUS; | |
327 | ||
b8d582b9 | 328 | val = (EXYNOS_EMUL_TIME << reg->emul_time_shift) | |
bffd1f8a | 329 | (temp_to_code(data, temp) |
b8d582b9 | 330 | << reg->emul_temp_shift) | EXYNOS_EMUL_ENABLE; |
bffd1f8a | 331 | } else { |
b8d582b9 | 332 | val &= ~EXYNOS_EMUL_ENABLE; |
bffd1f8a ADK |
333 | } |
334 | ||
b8d582b9 | 335 | writel(val, data->base + reg->emul_con); |
bffd1f8a ADK |
336 | |
337 | clk_disable(data->clk); | |
338 | mutex_unlock(&data->lock); | |
339 | return 0; | |
340 | out: | |
341 | return ret; | |
342 | } | |
343 | #else | |
344 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) | |
345 | { return -EINVAL; } | |
346 | #endif/*CONFIG_THERMAL_EMULATION*/ | |
347 | ||
f22d9c03 | 348 | static void exynos_tmu_work(struct work_struct *work) |
9d97e5c8 | 349 | { |
f22d9c03 ADK |
350 | struct exynos_tmu_data *data = container_of(work, |
351 | struct exynos_tmu_data, irq_work); | |
b8d582b9 ADK |
352 | struct exynos_tmu_platform_data *pdata = data->pdata; |
353 | const struct exynos_tmu_registers *reg = pdata->registers; | |
9d97e5c8 | 354 | |
3ad9524a | 355 | exynos_report_trigger(); |
9d97e5c8 DK |
356 | mutex_lock(&data->lock); |
357 | clk_enable(data->clk); | |
b8d582b9 | 358 | |
f22d9c03 | 359 | if (data->soc == SOC_ARCH_EXYNOS) |
b8d582b9 ADK |
360 | writel((reg->inten_rise_mask << reg->inten_rise_shift) | |
361 | (reg->inten_fall_mask << reg->inten_fall_shift), | |
362 | data->base + reg->tmu_intclear); | |
f22d9c03 | 363 | else |
b8d582b9 ADK |
364 | writel(reg->inten_rise_mask, data->base + reg->tmu_intclear); |
365 | ||
9d97e5c8 DK |
366 | clk_disable(data->clk); |
367 | mutex_unlock(&data->lock); | |
3ad9524a | 368 | |
f22d9c03 | 369 | enable_irq(data->irq); |
9d97e5c8 DK |
370 | } |
371 | ||
f22d9c03 | 372 | static irqreturn_t exynos_tmu_irq(int irq, void *id) |
9d97e5c8 | 373 | { |
f22d9c03 | 374 | struct exynos_tmu_data *data = id; |
9d97e5c8 DK |
375 | |
376 | disable_irq_nosync(irq); | |
377 | schedule_work(&data->irq_work); | |
378 | ||
379 | return IRQ_HANDLED; | |
380 | } | |
7e0b55e6 ADK |
381 | static struct thermal_sensor_conf exynos_sensor_conf = { |
382 | .name = "exynos-therm", | |
383 | .read_temperature = (int (*)(void *))exynos_tmu_read, | |
bffd1f8a | 384 | .write_emul_temp = exynos_tmu_set_emulation, |
17be868e ADK |
385 | }; |
386 | ||
17be868e ADK |
387 | #ifdef CONFIG_OF |
388 | static const struct of_device_id exynos_tmu_match[] = { | |
389 | { | |
390 | .compatible = "samsung,exynos4210-tmu", | |
391 | .data = (void *)EXYNOS4210_TMU_DRV_DATA, | |
392 | }, | |
b6cee53c SK |
393 | { |
394 | .compatible = "samsung,exynos4412-tmu", | |
e6b7991e | 395 | .data = (void *)EXYNOS5250_TMU_DRV_DATA, |
b6cee53c | 396 | }, |
17be868e ADK |
397 | { |
398 | .compatible = "samsung,exynos5250-tmu", | |
e6b7991e | 399 | .data = (void *)EXYNOS5250_TMU_DRV_DATA, |
17be868e ADK |
400 | }, |
401 | {}, | |
402 | }; | |
403 | MODULE_DEVICE_TABLE(of, exynos_tmu_match); | |
17be868e ADK |
404 | #endif |
405 | ||
406 | static struct platform_device_id exynos_tmu_driver_ids[] = { | |
407 | { | |
408 | .name = "exynos4210-tmu", | |
409 | .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA, | |
410 | }, | |
411 | { | |
412 | .name = "exynos5250-tmu", | |
e6b7991e | 413 | .driver_data = (kernel_ulong_t)EXYNOS5250_TMU_DRV_DATA, |
17be868e ADK |
414 | }, |
415 | { }, | |
416 | }; | |
3ae53b1e | 417 | MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids); |
17be868e ADK |
418 | |
419 | static inline struct exynos_tmu_platform_data *exynos_get_driver_data( | |
420 | struct platform_device *pdev) | |
421 | { | |
422 | #ifdef CONFIG_OF | |
423 | if (pdev->dev.of_node) { | |
424 | const struct of_device_id *match; | |
425 | match = of_match_node(exynos_tmu_match, pdev->dev.of_node); | |
426 | if (!match) | |
427 | return NULL; | |
428 | return (struct exynos_tmu_platform_data *) match->data; | |
429 | } | |
430 | #endif | |
431 | return (struct exynos_tmu_platform_data *) | |
432 | platform_get_device_id(pdev)->driver_data; | |
7e0b55e6 | 433 | } |
bbf63be4 | 434 | |
4eab7a9e | 435 | static int exynos_tmu_probe(struct platform_device *pdev) |
9d97e5c8 | 436 | { |
f22d9c03 ADK |
437 | struct exynos_tmu_data *data; |
438 | struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data; | |
7e0b55e6 | 439 | int ret, i; |
9d97e5c8 | 440 | |
17be868e ADK |
441 | if (!pdata) |
442 | pdata = exynos_get_driver_data(pdev); | |
443 | ||
9d97e5c8 DK |
444 | if (!pdata) { |
445 | dev_err(&pdev->dev, "No platform init data supplied.\n"); | |
446 | return -ENODEV; | |
447 | } | |
79e093c3 ADK |
448 | data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), |
449 | GFP_KERNEL); | |
9d97e5c8 DK |
450 | if (!data) { |
451 | dev_err(&pdev->dev, "Failed to allocate driver structure\n"); | |
452 | return -ENOMEM; | |
453 | } | |
454 | ||
455 | data->irq = platform_get_irq(pdev, 0); | |
456 | if (data->irq < 0) { | |
9d97e5c8 | 457 | dev_err(&pdev->dev, "Failed to get platform irq\n"); |
79e093c3 | 458 | return data->irq; |
9d97e5c8 DK |
459 | } |
460 | ||
f22d9c03 | 461 | INIT_WORK(&data->irq_work, exynos_tmu_work); |
9d97e5c8 DK |
462 | |
463 | data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
ca36b1ba TR |
464 | data->base = devm_ioremap_resource(&pdev->dev, data->mem); |
465 | if (IS_ERR(data->base)) | |
466 | return PTR_ERR(data->base); | |
9d97e5c8 | 467 | |
79e093c3 | 468 | ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, |
f22d9c03 | 469 | IRQF_TRIGGER_RISING, "exynos-tmu", data); |
9d97e5c8 DK |
470 | if (ret) { |
471 | dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); | |
79e093c3 | 472 | return ret; |
9d97e5c8 DK |
473 | } |
474 | ||
2a16279c | 475 | data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); |
9d97e5c8 | 476 | if (IS_ERR(data->clk)) { |
9d97e5c8 | 477 | dev_err(&pdev->dev, "Failed to get clock\n"); |
79e093c3 | 478 | return PTR_ERR(data->clk); |
9d97e5c8 DK |
479 | } |
480 | ||
2a16279c SK |
481 | ret = clk_prepare(data->clk); |
482 | if (ret) | |
483 | return ret; | |
484 | ||
f22d9c03 ADK |
485 | if (pdata->type == SOC_ARCH_EXYNOS || |
486 | pdata->type == SOC_ARCH_EXYNOS4210) | |
487 | data->soc = pdata->type; | |
488 | else { | |
489 | ret = -EINVAL; | |
490 | dev_err(&pdev->dev, "Platform not supported\n"); | |
491 | goto err_clk; | |
492 | } | |
493 | ||
9d97e5c8 DK |
494 | data->pdata = pdata; |
495 | platform_set_drvdata(pdev, data); | |
496 | mutex_init(&data->lock); | |
497 | ||
f22d9c03 | 498 | ret = exynos_tmu_initialize(pdev); |
9d97e5c8 DK |
499 | if (ret) { |
500 | dev_err(&pdev->dev, "Failed to initialize TMU\n"); | |
501 | goto err_clk; | |
502 | } | |
503 | ||
f22d9c03 | 504 | exynos_tmu_control(pdev, true); |
9d97e5c8 | 505 | |
7e0b55e6 ADK |
506 | /* Register the sensor with thermal management interface */ |
507 | (&exynos_sensor_conf)->private_data = data; | |
bb34b4c8 ADK |
508 | exynos_sensor_conf.trip_data.trip_count = pdata->trigger_enable[0] + |
509 | pdata->trigger_enable[1] + pdata->trigger_enable[2]+ | |
510 | pdata->trigger_enable[3]; | |
7e0b55e6 ADK |
511 | |
512 | for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++) | |
513 | exynos_sensor_conf.trip_data.trip_val[i] = | |
514 | pdata->threshold + pdata->trigger_levels[i]; | |
515 | ||
4f0a6847 JL |
516 | exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling; |
517 | ||
7e0b55e6 ADK |
518 | exynos_sensor_conf.cooling_data.freq_clip_count = |
519 | pdata->freq_tab_count; | |
520 | for (i = 0; i < pdata->freq_tab_count; i++) { | |
521 | exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max = | |
522 | pdata->freq_tab[i].freq_clip_max; | |
523 | exynos_sensor_conf.cooling_data.freq_data[i].temp_level = | |
524 | pdata->freq_tab[i].temp_level; | |
525 | } | |
526 | ||
527 | ret = exynos_register_thermal(&exynos_sensor_conf); | |
528 | if (ret) { | |
529 | dev_err(&pdev->dev, "Failed to register thermal interface\n"); | |
530 | goto err_clk; | |
531 | } | |
bbf63be4 | 532 | |
9d97e5c8 | 533 | return 0; |
9d97e5c8 | 534 | err_clk: |
2a16279c | 535 | clk_unprepare(data->clk); |
9d97e5c8 DK |
536 | return ret; |
537 | } | |
538 | ||
4eab7a9e | 539 | static int exynos_tmu_remove(struct platform_device *pdev) |
9d97e5c8 | 540 | { |
f22d9c03 | 541 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
9d97e5c8 | 542 | |
f22d9c03 | 543 | exynos_tmu_control(pdev, false); |
9d97e5c8 | 544 | |
7e0b55e6 ADK |
545 | exynos_unregister_thermal(); |
546 | ||
2a16279c | 547 | clk_unprepare(data->clk); |
9d97e5c8 | 548 | |
9d97e5c8 DK |
549 | return 0; |
550 | } | |
551 | ||
08cd6753 | 552 | #ifdef CONFIG_PM_SLEEP |
f22d9c03 | 553 | static int exynos_tmu_suspend(struct device *dev) |
9d97e5c8 | 554 | { |
f22d9c03 | 555 | exynos_tmu_control(to_platform_device(dev), false); |
9d97e5c8 DK |
556 | |
557 | return 0; | |
558 | } | |
559 | ||
f22d9c03 | 560 | static int exynos_tmu_resume(struct device *dev) |
9d97e5c8 | 561 | { |
08cd6753 RW |
562 | struct platform_device *pdev = to_platform_device(dev); |
563 | ||
f22d9c03 ADK |
564 | exynos_tmu_initialize(pdev); |
565 | exynos_tmu_control(pdev, true); | |
9d97e5c8 DK |
566 | |
567 | return 0; | |
568 | } | |
08cd6753 | 569 | |
f22d9c03 ADK |
570 | static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, |
571 | exynos_tmu_suspend, exynos_tmu_resume); | |
572 | #define EXYNOS_TMU_PM (&exynos_tmu_pm) | |
9d97e5c8 | 573 | #else |
f22d9c03 | 574 | #define EXYNOS_TMU_PM NULL |
9d97e5c8 DK |
575 | #endif |
576 | ||
f22d9c03 | 577 | static struct platform_driver exynos_tmu_driver = { |
9d97e5c8 | 578 | .driver = { |
f22d9c03 | 579 | .name = "exynos-tmu", |
9d97e5c8 | 580 | .owner = THIS_MODULE, |
f22d9c03 | 581 | .pm = EXYNOS_TMU_PM, |
caa5cbd5 | 582 | .of_match_table = of_match_ptr(exynos_tmu_match), |
9d97e5c8 | 583 | }, |
f22d9c03 | 584 | .probe = exynos_tmu_probe, |
4eab7a9e | 585 | .remove = exynos_tmu_remove, |
17be868e | 586 | .id_table = exynos_tmu_driver_ids, |
9d97e5c8 DK |
587 | }; |
588 | ||
f22d9c03 | 589 | module_platform_driver(exynos_tmu_driver); |
9d97e5c8 | 590 | |
f22d9c03 | 591 | MODULE_DESCRIPTION("EXYNOS TMU Driver"); |
9d97e5c8 DK |
592 | MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); |
593 | MODULE_LICENSE("GPL"); | |
f22d9c03 | 594 | MODULE_ALIAS("platform:exynos-tmu"); |