thermal: exynos: Move register definitions from driver to data file
[deliverable/linux.git] / drivers / thermal / samsung / exynos_tmu.c
CommitLineData
9d97e5c8 1/*
59dfa54c 2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
9d97e5c8
DK
3 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
c48cbba6 6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
9d97e5c8
DK
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
9d97e5c8 24#include <linux/clk.h>
9d97e5c8 25#include <linux/io.h>
1b678641
ADK
26#include <linux/interrupt.h>
27#include <linux/module.h>
f22d9c03 28#include <linux/of.h>
1b678641 29#include <linux/platform_device.h>
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ADK
30
31#include "exynos_thermal_common.h"
0c1836a6 32#include "exynos_tmu.h"
e6b7991e 33#include "exynos_tmu_data.h"
f22d9c03 34
f22d9c03
ADK
35struct exynos_tmu_data {
36 struct exynos_tmu_platform_data *pdata;
9d97e5c8
DK
37 struct resource *mem;
38 void __iomem *base;
39 int irq;
f22d9c03 40 enum soc_type soc;
9d97e5c8
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41 struct work_struct irq_work;
42 struct mutex lock;
43 struct clk *clk;
44 u8 temp_error1, temp_error2;
45};
46
47/*
48 * TMU treats temperature as a mapped temperature code.
49 * The temperature is converted differently depending on the calibration type.
50 */
f22d9c03 51static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
9d97e5c8 52{
f22d9c03 53 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK
54 int temp_code;
55
f22d9c03
ADK
56 if (data->soc == SOC_ARCH_EXYNOS4210)
57 /* temp should range between 25 and 125 */
58 if (temp < 25 || temp > 125) {
59 temp_code = -EINVAL;
60 goto out;
61 }
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DK
62
63 switch (pdata->cal_type) {
64 case TYPE_TWO_POINT_TRIMMING:
bb34b4c8
ADK
65 temp_code = (temp - pdata->first_point_trim) *
66 (data->temp_error2 - data->temp_error1) /
67 (pdata->second_point_trim - pdata->first_point_trim) +
68 data->temp_error1;
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DK
69 break;
70 case TYPE_ONE_POINT_TRIMMING:
bb34b4c8 71 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
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72 break;
73 default:
bb34b4c8 74 temp_code = temp + pdata->default_temp_offset;
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75 break;
76 }
77out:
78 return temp_code;
79}
80
81/*
82 * Calculate a temperature value from a temperature code.
83 * The unit of the temperature is degree Celsius.
84 */
f22d9c03 85static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
9d97e5c8 86{
f22d9c03 87 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK
88 int temp;
89
f22d9c03
ADK
90 if (data->soc == SOC_ARCH_EXYNOS4210)
91 /* temp_code should range between 75 and 175 */
92 if (temp_code < 75 || temp_code > 175) {
93 temp = -ENODATA;
94 goto out;
95 }
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DK
96
97 switch (pdata->cal_type) {
98 case TYPE_TWO_POINT_TRIMMING:
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ADK
99 temp = (temp_code - data->temp_error1) *
100 (pdata->second_point_trim - pdata->first_point_trim) /
101 (data->temp_error2 - data->temp_error1) +
102 pdata->first_point_trim;
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DK
103 break;
104 case TYPE_ONE_POINT_TRIMMING:
bb34b4c8 105 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
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DK
106 break;
107 default:
bb34b4c8 108 temp = temp_code - pdata->default_temp_offset;
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DK
109 break;
110 }
111out:
112 return temp;
113}
114
f22d9c03 115static int exynos_tmu_initialize(struct platform_device *pdev)
9d97e5c8 116{
f22d9c03
ADK
117 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
118 struct exynos_tmu_platform_data *pdata = data->pdata;
b8d582b9 119 const struct exynos_tmu_registers *reg = pdata->registers;
4f0a6847
JL
120 unsigned int status, trim_info;
121 unsigned int rising_threshold = 0, falling_threshold = 0;
122 int ret = 0, threshold_code, i, trigger_levs = 0;
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DK
123
124 mutex_lock(&data->lock);
125 clk_enable(data->clk);
126
b8d582b9 127 status = readb(data->base + reg->tmu_status);
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DK
128 if (!status) {
129 ret = -EBUSY;
130 goto out;
131 }
132
b8d582b9
ADK
133 if (data->soc == SOC_ARCH_EXYNOS)
134 __raw_writel(1, data->base + reg->triminfo_ctrl);
135
9d97e5c8 136 /* Save trimming info in order to perform calibration */
b8d582b9
ADK
137 trim_info = readl(data->base + reg->triminfo_data);
138 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
139 data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
140 EXYNOS_TMU_TEMP_MASK);
f22d9c03 141
bb34b4c8
ADK
142 if ((pdata->min_efuse_value > data->temp_error1) ||
143 (data->temp_error1 > pdata->max_efuse_value) ||
f22d9c03
ADK
144 (data->temp_error2 != 0))
145 data->temp_error1 = pdata->efuse_value;
146
4f0a6847
JL
147 /* Count trigger levels to be enabled */
148 for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
149 if (pdata->trigger_levels[i])
150 trigger_levs++;
151
f22d9c03
ADK
152 if (data->soc == SOC_ARCH_EXYNOS4210) {
153 /* Write temperature code for threshold */
154 threshold_code = temp_to_code(data, pdata->threshold);
155 if (threshold_code < 0) {
156 ret = threshold_code;
157 goto out;
158 }
159 writeb(threshold_code,
b8d582b9 160 data->base + reg->threshold_temp);
4f0a6847 161 for (i = 0; i < trigger_levs; i++)
b8d582b9
ADK
162 writeb(pdata->trigger_levels[i], data->base +
163 reg->threshold_th0 + i * sizeof(reg->threshold_th0));
f22d9c03 164
b8d582b9 165 writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
f22d9c03 166 } else if (data->soc == SOC_ARCH_EXYNOS) {
4f0a6847
JL
167 /* Write temperature code for rising and falling threshold */
168 for (i = 0; i < trigger_levs; i++) {
169 threshold_code = temp_to_code(data,
170 pdata->trigger_levels[i]);
171 if (threshold_code < 0) {
172 ret = threshold_code;
173 goto out;
174 }
175 rising_threshold |= threshold_code << 8 * i;
176 if (pdata->threshold_falling) {
177 threshold_code = temp_to_code(data,
178 pdata->trigger_levels[i] -
179 pdata->threshold_falling);
180 if (threshold_code > 0)
181 falling_threshold |=
182 threshold_code << 8 * i;
183 }
f22d9c03 184 }
f22d9c03
ADK
185
186 writel(rising_threshold,
b8d582b9 187 data->base + reg->threshold_th0);
4f0a6847 188 writel(falling_threshold,
b8d582b9 189 data->base + reg->threshold_th1);
f22d9c03 190
b8d582b9
ADK
191 writel((reg->inten_rise_mask << reg->inten_rise_shift) |
192 (reg->inten_fall_mask << reg->inten_fall_shift),
193 data->base + reg->tmu_intclear);
9d97e5c8 194 }
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DK
195out:
196 clk_disable(data->clk);
197 mutex_unlock(&data->lock);
198
199 return ret;
200}
201
f22d9c03 202static void exynos_tmu_control(struct platform_device *pdev, bool on)
9d97e5c8 203{
f22d9c03
ADK
204 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
205 struct exynos_tmu_platform_data *pdata = data->pdata;
b8d582b9 206 const struct exynos_tmu_registers *reg = pdata->registers;
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DK
207 unsigned int con, interrupt_en;
208
209 mutex_lock(&data->lock);
210 clk_enable(data->clk);
211
b8d582b9 212 con = readl(data->base + reg->tmu_ctrl);
f22d9c03 213
d0a0ce3e 214 if (pdata->reference_voltage) {
b8d582b9
ADK
215 con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift);
216 con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
d0a0ce3e
ADK
217 }
218
219 if (pdata->gain) {
b8d582b9
ADK
220 con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift);
221 con |= (pdata->gain << reg->buf_slope_sel_shift);
d0a0ce3e
ADK
222 }
223
224 if (pdata->noise_cancel_mode) {
b8d582b9
ADK
225 con &= ~(reg->therm_trip_mode_mask <<
226 reg->therm_trip_mode_shift);
227 con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);
f22d9c03
ADK
228 }
229
9d97e5c8 230 if (on) {
b8d582b9 231 con |= (1 << reg->core_en_shift);
d0a0ce3e 232 interrupt_en =
b8d582b9
ADK
233 pdata->trigger_enable[3] << reg->inten_rise3_shift |
234 pdata->trigger_enable[2] << reg->inten_rise2_shift |
235 pdata->trigger_enable[1] << reg->inten_rise1_shift |
236 pdata->trigger_enable[0] << reg->inten_rise0_shift;
4f0a6847 237 if (pdata->threshold_falling)
d0a0ce3e 238 interrupt_en |=
b8d582b9 239 interrupt_en << reg->inten_fall0_shift;
9d97e5c8 240 } else {
b8d582b9 241 con &= ~(1 << reg->core_en_shift);
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DK
242 interrupt_en = 0; /* Disable all interrupts */
243 }
b8d582b9
ADK
244 writel(interrupt_en, data->base + reg->tmu_inten);
245 writel(con, data->base + reg->tmu_ctrl);
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DK
246
247 clk_disable(data->clk);
248 mutex_unlock(&data->lock);
249}
250
f22d9c03 251static int exynos_tmu_read(struct exynos_tmu_data *data)
9d97e5c8 252{
b8d582b9
ADK
253 struct exynos_tmu_platform_data *pdata = data->pdata;
254 const struct exynos_tmu_registers *reg = pdata->registers;
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DK
255 u8 temp_code;
256 int temp;
257
258 mutex_lock(&data->lock);
259 clk_enable(data->clk);
260
b8d582b9 261 temp_code = readb(data->base + reg->tmu_cur_temp);
9d97e5c8
DK
262 temp = code_to_temp(data, temp_code);
263
264 clk_disable(data->clk);
265 mutex_unlock(&data->lock);
266
267 return temp;
268}
269
bffd1f8a
ADK
270#ifdef CONFIG_THERMAL_EMULATION
271static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
272{
273 struct exynos_tmu_data *data = drv_data;
b8d582b9
ADK
274 struct exynos_tmu_platform_data *pdata = data->pdata;
275 const struct exynos_tmu_registers *reg = pdata->registers;
276 unsigned int val;
bffd1f8a
ADK
277 int ret = -EINVAL;
278
279 if (data->soc == SOC_ARCH_EXYNOS4210)
280 goto out;
281
282 if (temp && temp < MCELSIUS)
283 goto out;
284
285 mutex_lock(&data->lock);
286 clk_enable(data->clk);
287
b8d582b9 288 val = readl(data->base + reg->emul_con);
bffd1f8a
ADK
289
290 if (temp) {
291 temp /= MCELSIUS;
292
b8d582b9 293 val = (EXYNOS_EMUL_TIME << reg->emul_time_shift) |
bffd1f8a 294 (temp_to_code(data, temp)
b8d582b9 295 << reg->emul_temp_shift) | EXYNOS_EMUL_ENABLE;
bffd1f8a 296 } else {
b8d582b9 297 val &= ~EXYNOS_EMUL_ENABLE;
bffd1f8a
ADK
298 }
299
b8d582b9 300 writel(val, data->base + reg->emul_con);
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ADK
301
302 clk_disable(data->clk);
303 mutex_unlock(&data->lock);
304 return 0;
305out:
306 return ret;
307}
308#else
309static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
310 { return -EINVAL; }
311#endif/*CONFIG_THERMAL_EMULATION*/
312
f22d9c03 313static void exynos_tmu_work(struct work_struct *work)
9d97e5c8 314{
f22d9c03
ADK
315 struct exynos_tmu_data *data = container_of(work,
316 struct exynos_tmu_data, irq_work);
b8d582b9
ADK
317 struct exynos_tmu_platform_data *pdata = data->pdata;
318 const struct exynos_tmu_registers *reg = pdata->registers;
9d97e5c8 319
3ad9524a 320 exynos_report_trigger();
9d97e5c8
DK
321 mutex_lock(&data->lock);
322 clk_enable(data->clk);
b8d582b9 323
f22d9c03 324 if (data->soc == SOC_ARCH_EXYNOS)
b8d582b9
ADK
325 writel((reg->inten_rise_mask << reg->inten_rise_shift) |
326 (reg->inten_fall_mask << reg->inten_fall_shift),
327 data->base + reg->tmu_intclear);
f22d9c03 328 else
b8d582b9
ADK
329 writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
330
9d97e5c8
DK
331 clk_disable(data->clk);
332 mutex_unlock(&data->lock);
3ad9524a 333
f22d9c03 334 enable_irq(data->irq);
9d97e5c8
DK
335}
336
f22d9c03 337static irqreturn_t exynos_tmu_irq(int irq, void *id)
9d97e5c8 338{
f22d9c03 339 struct exynos_tmu_data *data = id;
9d97e5c8
DK
340
341 disable_irq_nosync(irq);
342 schedule_work(&data->irq_work);
343
344 return IRQ_HANDLED;
345}
7e0b55e6
ADK
346static struct thermal_sensor_conf exynos_sensor_conf = {
347 .name = "exynos-therm",
348 .read_temperature = (int (*)(void *))exynos_tmu_read,
bffd1f8a 349 .write_emul_temp = exynos_tmu_set_emulation,
17be868e
ADK
350};
351
17be868e
ADK
352#ifdef CONFIG_OF
353static const struct of_device_id exynos_tmu_match[] = {
354 {
355 .compatible = "samsung,exynos4210-tmu",
356 .data = (void *)EXYNOS4210_TMU_DRV_DATA,
357 },
b6cee53c
SK
358 {
359 .compatible = "samsung,exynos4412-tmu",
e6b7991e 360 .data = (void *)EXYNOS5250_TMU_DRV_DATA,
b6cee53c 361 },
17be868e
ADK
362 {
363 .compatible = "samsung,exynos5250-tmu",
e6b7991e 364 .data = (void *)EXYNOS5250_TMU_DRV_DATA,
17be868e
ADK
365 },
366 {},
367};
368MODULE_DEVICE_TABLE(of, exynos_tmu_match);
17be868e
ADK
369#endif
370
371static struct platform_device_id exynos_tmu_driver_ids[] = {
372 {
373 .name = "exynos4210-tmu",
374 .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
375 },
376 {
377 .name = "exynos5250-tmu",
e6b7991e 378 .driver_data = (kernel_ulong_t)EXYNOS5250_TMU_DRV_DATA,
17be868e
ADK
379 },
380 { },
381};
3ae53b1e 382MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
17be868e
ADK
383
384static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
385 struct platform_device *pdev)
386{
387#ifdef CONFIG_OF
388 if (pdev->dev.of_node) {
389 const struct of_device_id *match;
390 match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
391 if (!match)
392 return NULL;
393 return (struct exynos_tmu_platform_data *) match->data;
394 }
395#endif
396 return (struct exynos_tmu_platform_data *)
397 platform_get_device_id(pdev)->driver_data;
7e0b55e6 398}
bbf63be4 399
4eab7a9e 400static int exynos_tmu_probe(struct platform_device *pdev)
9d97e5c8 401{
f22d9c03
ADK
402 struct exynos_tmu_data *data;
403 struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
7e0b55e6 404 int ret, i;
9d97e5c8 405
17be868e
ADK
406 if (!pdata)
407 pdata = exynos_get_driver_data(pdev);
408
9d97e5c8
DK
409 if (!pdata) {
410 dev_err(&pdev->dev, "No platform init data supplied.\n");
411 return -ENODEV;
412 }
79e093c3
ADK
413 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
414 GFP_KERNEL);
9d97e5c8
DK
415 if (!data) {
416 dev_err(&pdev->dev, "Failed to allocate driver structure\n");
417 return -ENOMEM;
418 }
419
420 data->irq = platform_get_irq(pdev, 0);
421 if (data->irq < 0) {
9d97e5c8 422 dev_err(&pdev->dev, "Failed to get platform irq\n");
79e093c3 423 return data->irq;
9d97e5c8
DK
424 }
425
f22d9c03 426 INIT_WORK(&data->irq_work, exynos_tmu_work);
9d97e5c8
DK
427
428 data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ca36b1ba
TR
429 data->base = devm_ioremap_resource(&pdev->dev, data->mem);
430 if (IS_ERR(data->base))
431 return PTR_ERR(data->base);
9d97e5c8 432
79e093c3 433 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
f22d9c03 434 IRQF_TRIGGER_RISING, "exynos-tmu", data);
9d97e5c8
DK
435 if (ret) {
436 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
79e093c3 437 return ret;
9d97e5c8
DK
438 }
439
2a16279c 440 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
9d97e5c8 441 if (IS_ERR(data->clk)) {
9d97e5c8 442 dev_err(&pdev->dev, "Failed to get clock\n");
79e093c3 443 return PTR_ERR(data->clk);
9d97e5c8
DK
444 }
445
2a16279c
SK
446 ret = clk_prepare(data->clk);
447 if (ret)
448 return ret;
449
f22d9c03
ADK
450 if (pdata->type == SOC_ARCH_EXYNOS ||
451 pdata->type == SOC_ARCH_EXYNOS4210)
452 data->soc = pdata->type;
453 else {
454 ret = -EINVAL;
455 dev_err(&pdev->dev, "Platform not supported\n");
456 goto err_clk;
457 }
458
9d97e5c8
DK
459 data->pdata = pdata;
460 platform_set_drvdata(pdev, data);
461 mutex_init(&data->lock);
462
f22d9c03 463 ret = exynos_tmu_initialize(pdev);
9d97e5c8
DK
464 if (ret) {
465 dev_err(&pdev->dev, "Failed to initialize TMU\n");
466 goto err_clk;
467 }
468
f22d9c03 469 exynos_tmu_control(pdev, true);
9d97e5c8 470
7e0b55e6
ADK
471 /* Register the sensor with thermal management interface */
472 (&exynos_sensor_conf)->private_data = data;
bb34b4c8
ADK
473 exynos_sensor_conf.trip_data.trip_count = pdata->trigger_enable[0] +
474 pdata->trigger_enable[1] + pdata->trigger_enable[2]+
475 pdata->trigger_enable[3];
7e0b55e6
ADK
476
477 for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
478 exynos_sensor_conf.trip_data.trip_val[i] =
479 pdata->threshold + pdata->trigger_levels[i];
480
4f0a6847
JL
481 exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;
482
7e0b55e6
ADK
483 exynos_sensor_conf.cooling_data.freq_clip_count =
484 pdata->freq_tab_count;
485 for (i = 0; i < pdata->freq_tab_count; i++) {
486 exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
487 pdata->freq_tab[i].freq_clip_max;
488 exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
489 pdata->freq_tab[i].temp_level;
490 }
491
492 ret = exynos_register_thermal(&exynos_sensor_conf);
493 if (ret) {
494 dev_err(&pdev->dev, "Failed to register thermal interface\n");
495 goto err_clk;
496 }
bbf63be4 497
9d97e5c8 498 return 0;
9d97e5c8 499err_clk:
2a16279c 500 clk_unprepare(data->clk);
9d97e5c8
DK
501 return ret;
502}
503
4eab7a9e 504static int exynos_tmu_remove(struct platform_device *pdev)
9d97e5c8 505{
f22d9c03 506 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
9d97e5c8 507
f22d9c03 508 exynos_tmu_control(pdev, false);
9d97e5c8 509
7e0b55e6
ADK
510 exynos_unregister_thermal();
511
2a16279c 512 clk_unprepare(data->clk);
9d97e5c8 513
9d97e5c8
DK
514 return 0;
515}
516
08cd6753 517#ifdef CONFIG_PM_SLEEP
f22d9c03 518static int exynos_tmu_suspend(struct device *dev)
9d97e5c8 519{
f22d9c03 520 exynos_tmu_control(to_platform_device(dev), false);
9d97e5c8
DK
521
522 return 0;
523}
524
f22d9c03 525static int exynos_tmu_resume(struct device *dev)
9d97e5c8 526{
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527 struct platform_device *pdev = to_platform_device(dev);
528
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529 exynos_tmu_initialize(pdev);
530 exynos_tmu_control(pdev, true);
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531
532 return 0;
533}
08cd6753 534
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535static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
536 exynos_tmu_suspend, exynos_tmu_resume);
537#define EXYNOS_TMU_PM (&exynos_tmu_pm)
9d97e5c8 538#else
f22d9c03 539#define EXYNOS_TMU_PM NULL
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540#endif
541
f22d9c03 542static struct platform_driver exynos_tmu_driver = {
9d97e5c8 543 .driver = {
f22d9c03 544 .name = "exynos-tmu",
9d97e5c8 545 .owner = THIS_MODULE,
f22d9c03 546 .pm = EXYNOS_TMU_PM,
caa5cbd5 547 .of_match_table = of_match_ptr(exynos_tmu_match),
9d97e5c8 548 },
f22d9c03 549 .probe = exynos_tmu_probe,
4eab7a9e 550 .remove = exynos_tmu_remove,
17be868e 551 .id_table = exynos_tmu_driver_ids,
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552};
553
f22d9c03 554module_platform_driver(exynos_tmu_driver);
9d97e5c8 555
f22d9c03 556MODULE_DESCRIPTION("EXYNOS TMU Driver");
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557MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
558MODULE_LICENSE("GPL");
f22d9c03 559MODULE_ALIAS("platform:exynos-tmu");
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