[deliverable/linux.git] / drivers / thermal / samsung / exynos_tmu.c

/*
 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
 *
 *  Copyright (C) 2011 Samsung Electronics
 *  Donggeun Kim <dg77.kim@samsung.com>
 *  Amit Daniel Kachhap <amit.kachhap@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#include "exynos_thermal_common.h"
#include "exynos_tmu.h"
#include "exynos_tmu_data.h"

/* Exynos generic registers */
#define EXYNOS_TMU_REG_TRIMINFO		0x0
#define EXYNOS_TMU_REG_CONTROL		0x20
#define EXYNOS_TMU_REG_STATUS		0x28
#define EXYNOS_TMU_REG_CURRENT_TEMP	0x40
#define EXYNOS_TMU_REG_INTEN		0x70
#define EXYNOS_TMU_REG_INTSTAT		0x74
#define EXYNOS_TMU_REG_INTCLEAR		0x78

#define EXYNOS_TMU_TRIM_TEMP_MASK	0xff
#define EXYNOS_TMU_GAIN_SHIFT		8
#define EXYNOS_TMU_GAIN_MASK		0xf
#define EXYNOS_TMU_REF_VOLTAGE_SHIFT	24
#define EXYNOS_TMU_REF_VOLTAGE_MASK	0x1f
#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK	0xf
#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT	8
#define EXYNOS_TMU_CORE_EN_SHIFT	0

/* Exynos4210 specific registers */
#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP	0x44
#define EXYNOS4210_TMU_REG_TRIG_LEVEL0	0x50
#define EXYNOS4210_TMU_REG_TRIG_LEVEL1	0x54
#define EXYNOS4210_TMU_REG_TRIG_LEVEL2	0x58
#define EXYNOS4210_TMU_REG_TRIG_LEVEL3	0x5C
#define EXYNOS4210_TMU_REG_PAST_TEMP0	0x60
#define EXYNOS4210_TMU_REG_PAST_TEMP1	0x64
#define EXYNOS4210_TMU_REG_PAST_TEMP2	0x68
#define EXYNOS4210_TMU_REG_PAST_TEMP3	0x6C

#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK	0x1
#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK	0x10
#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK	0x100
#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK	0x1000
#define EXYNOS4210_TMU_TRIG_LEVEL_MASK	0x1111
#define EXYNOS4210_TMU_INTCLEAR_VAL	0x1111

/* Exynos5250 and Exynos4412 specific registers */
#define EXYNOS_TMU_TRIMINFO_CON	0x14
#define EXYNOS_THD_TEMP_RISE		0x50
#define EXYNOS_THD_TEMP_FALL		0x54
#define EXYNOS_EMUL_CON		0x80

#define EXYNOS_TRIMINFO_RELOAD		0x1
#define EXYNOS_TRIMINFO_SHIFT		0x0
#define EXYNOS_TMU_RISE_INT_MASK	0x111
#define EXYNOS_TMU_RISE_INT_SHIFT	0
#define EXYNOS_TMU_FALL_INT_MASK	0x111
#define EXYNOS_TMU_FALL_INT_SHIFT	12
#define EXYNOS_TMU_CLEAR_RISE_INT	0x111
#define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
#define EXYNOS_TMU_TRIP_MODE_SHIFT	13
#define EXYNOS_TMU_TRIP_MODE_MASK	0x7

#define EXYNOS_TMU_INTEN_RISE0_SHIFT	0
#define EXYNOS_TMU_INTEN_RISE1_SHIFT	4
#define EXYNOS_TMU_INTEN_RISE2_SHIFT	8
#define EXYNOS_TMU_INTEN_RISE3_SHIFT	12
#define EXYNOS_TMU_INTEN_FALL0_SHIFT	16
#define EXYNOS_TMU_INTEN_FALL1_SHIFT	20
#define EXYNOS_TMU_INTEN_FALL2_SHIFT	24

#ifdef CONFIG_THERMAL_EMULATION
#define EXYNOS_EMUL_TIME	0x57F0
#define EXYNOS_EMUL_TIME_MASK	0xffff
#define EXYNOS_EMUL_TIME_SHIFT	16
#define EXYNOS_EMUL_DATA_SHIFT	8
#define EXYNOS_EMUL_DATA_MASK	0xFF
#define EXYNOS_EMUL_ENABLE	0x1
#endif /* CONFIG_THERMAL_EMULATION */

struct exynos_tmu_data {
	struct exynos_tmu_platform_data *pdata;
	struct resource *mem;
	void __iomem *base;
	int irq;
	enum soc_type soc;
	struct work_struct irq_work;
	struct mutex lock;
	struct clk *clk;
	u8 temp_error1, temp_error2;
};

/*
 * TMU treats temperature as a mapped temperature code.
 * The temperature is converted differently depending on the calibration type.
 */
static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
{
	struct exynos_tmu_platform_data *pdata = data->pdata;
	int temp_code;

	if (data->soc == SOC_ARCH_EXYNOS4210)
		/* temp should range between 25 and 125 */
		if (temp < 25 || temp > 125) {
			temp_code = -EINVAL;
			goto out;
		}

	switch (pdata->cal_type) {
	case TYPE_TWO_POINT_TRIMMING:
		temp_code = (temp - pdata->first_point_trim) *
			(data->temp_error2 - data->temp_error1) /
			(pdata->second_point_trim - pdata->first_point_trim) +
			data->temp_error1;
		break;
	case TYPE_ONE_POINT_TRIMMING:
		temp_code = temp + data->temp_error1 - pdata->first_point_trim;
		break;
	default:
		temp_code = temp + pdata->default_temp_offset;
		break;
	}
out:
	return temp_code;
}

/*
 * Calculate a temperature value from a temperature code.
 * The unit of the temperature is degree Celsius.
 */
static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
{
	struct exynos_tmu_platform_data *pdata = data->pdata;
	int temp;

	if (data->soc == SOC_ARCH_EXYNOS4210)
		/* temp_code should range between 75 and 175 */
		if (temp_code < 75 || temp_code > 175) {
			temp = -ENODATA;
			goto out;
		}

	switch (pdata->cal_type) {
	case TYPE_TWO_POINT_TRIMMING:
		temp = (temp_code - data->temp_error1) *
			(pdata->second_point_trim - pdata->first_point_trim) /
			(data->temp_error2 - data->temp_error1) +
			pdata->first_point_trim;
		break;
	case TYPE_ONE_POINT_TRIMMING:
		temp = temp_code - data->temp_error1 + pdata->first_point_trim;
		break;
	default:
		temp = temp_code - pdata->default_temp_offset;
		break;
	}
out:
	return temp;
}

static int exynos_tmu_initialize(struct platform_device *pdev)
{
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
	struct exynos_tmu_platform_data *pdata = data->pdata;
	unsigned int status, trim_info;
	unsigned int rising_threshold = 0, falling_threshold = 0;
	int ret = 0, threshold_code, i, trigger_levs = 0;

	mutex_lock(&data->lock);
	clk_enable(data->clk);

	status = readb(data->base + EXYNOS_TMU_REG_STATUS);
	if (!status) {
		ret = -EBUSY;
		goto out;
	}

	if (data->soc == SOC_ARCH_EXYNOS) {
		__raw_writel(EXYNOS_TRIMINFO_RELOAD,
				data->base + EXYNOS_TMU_TRIMINFO_CON);
	}
	/* Save trimming info in order to perform calibration */
	trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
	data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
	data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);

	if ((pdata->min_efuse_value > data->temp_error1) ||
			(data->temp_error1 > pdata->max_efuse_value) ||
			(data->temp_error2 != 0))
		data->temp_error1 = pdata->efuse_value;

	/* Count trigger levels to be enabled */
	for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
		if (pdata->trigger_levels[i])
			trigger_levs++;

	if (data->soc == SOC_ARCH_EXYNOS4210) {
		/* Write temperature code for threshold */
		threshold_code = temp_to_code(data, pdata->threshold);
		if (threshold_code < 0) {
			ret = threshold_code;
			goto out;
		}
		writeb(threshold_code,
			data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
		for (i = 0; i < trigger_levs; i++)
			writeb(pdata->trigger_levels[i],
			data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);

		writel(EXYNOS4210_TMU_INTCLEAR_VAL,
			data->base + EXYNOS_TMU_REG_INTCLEAR);
	} else if (data->soc == SOC_ARCH_EXYNOS) {
		/* Write temperature code for rising and falling threshold */
		for (i = 0; i < trigger_levs; i++) {
			threshold_code = temp_to_code(data,
						pdata->trigger_levels[i]);
			if (threshold_code < 0) {
				ret = threshold_code;
				goto out;
			}
			rising_threshold |= threshold_code << 8 * i;
			if (pdata->threshold_falling) {
				threshold_code = temp_to_code(data,
						pdata->trigger_levels[i] -
						pdata->threshold_falling);
				if (threshold_code > 0)
					falling_threshold |=
						threshold_code << 8 * i;
			}
		}

		writel(rising_threshold,
				data->base + EXYNOS_THD_TEMP_RISE);
		writel(falling_threshold,
				data->base + EXYNOS_THD_TEMP_FALL);

		writel(EXYNOS_TMU_CLEAR_RISE_INT | EXYNOS_TMU_CLEAR_FALL_INT,
				data->base + EXYNOS_TMU_REG_INTCLEAR);
	}
out:
	clk_disable(data->clk);
	mutex_unlock(&data->lock);

	return ret;
}

static void exynos_tmu_control(struct platform_device *pdev, bool on)
{
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
	struct exynos_tmu_platform_data *pdata = data->pdata;
	unsigned int con, interrupt_en;

	mutex_lock(&data->lock);
	clk_enable(data->clk);

	con = readl(data->base + EXYNOS_TMU_REG_CONTROL);

	if (pdata->reference_voltage) {
		con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK <<
				EXYNOS_TMU_REF_VOLTAGE_SHIFT);
		con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
	}

	if (pdata->gain) {
		con &= ~(EXYNOS_TMU_GAIN_MASK << EXYNOS_TMU_GAIN_SHIFT);
		con |= (pdata->gain << EXYNOS_TMU_GAIN_SHIFT);
	}

	if (pdata->noise_cancel_mode) {
		con &= ~(EXYNOS_TMU_TRIP_MODE_MASK <<
					EXYNOS_TMU_TRIP_MODE_SHIFT);
		con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
	}

	if (on) {
		con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
		interrupt_en =
		pdata->trigger_enable[3] << EXYNOS_TMU_INTEN_RISE3_SHIFT |
		pdata->trigger_enable[2] << EXYNOS_TMU_INTEN_RISE2_SHIFT |
		pdata->trigger_enable[1] << EXYNOS_TMU_INTEN_RISE1_SHIFT |
		pdata->trigger_enable[0] << EXYNOS_TMU_INTEN_RISE0_SHIFT;
		if (pdata->threshold_falling)
			interrupt_en |=
				interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
	} else {
		con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
		interrupt_en = 0; /* Disable all interrupts */
	}
	writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
	writel(con, data->base + EXYNOS_TMU_REG_CONTROL);

	clk_disable(data->clk);
	mutex_unlock(&data->lock);
}

static int exynos_tmu_read(struct exynos_tmu_data *data)
{
	u8 temp_code;
	int temp;

	mutex_lock(&data->lock);
	clk_enable(data->clk);

	temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
	temp = code_to_temp(data, temp_code);

	clk_disable(data->clk);
	mutex_unlock(&data->lock);

	return temp;
}

#ifdef CONFIG_THERMAL_EMULATION
static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
{
	struct exynos_tmu_data *data = drv_data;
	unsigned int reg;
	int ret = -EINVAL;

	if (data->soc == SOC_ARCH_EXYNOS4210)
		goto out;

	if (temp && temp < MCELSIUS)
		goto out;

	mutex_lock(&data->lock);
	clk_enable(data->clk);

	reg = readl(data->base + EXYNOS_EMUL_CON);

	if (temp) {
		temp /= MCELSIUS;

		reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) |
			(temp_to_code(data, temp)
			 << EXYNOS_EMUL_DATA_SHIFT) | EXYNOS_EMUL_ENABLE;
	} else {
		reg &= ~EXYNOS_EMUL_ENABLE;
	}

	writel(reg, data->base + EXYNOS_EMUL_CON);

	clk_disable(data->clk);
	mutex_unlock(&data->lock);
	return 0;
out:
	return ret;
}
#else
static int exynos_tmu_set_emulation(void *drv_data,	unsigned long temp)
	{ return -EINVAL; }
#endif/*CONFIG_THERMAL_EMULATION*/

static void exynos_tmu_work(struct work_struct *work)
{
	struct exynos_tmu_data *data = container_of(work,
			struct exynos_tmu_data, irq_work);

	exynos_report_trigger();
	mutex_lock(&data->lock);
	clk_enable(data->clk);
	if (data->soc == SOC_ARCH_EXYNOS)
		writel(EXYNOS_TMU_CLEAR_RISE_INT |
				EXYNOS_TMU_CLEAR_FALL_INT,
				data->base + EXYNOS_TMU_REG_INTCLEAR);
	else
		writel(EXYNOS4210_TMU_INTCLEAR_VAL,
				data->base + EXYNOS_TMU_REG_INTCLEAR);
	clk_disable(data->clk);
	mutex_unlock(&data->lock);

	enable_irq(data->irq);
}

static irqreturn_t exynos_tmu_irq(int irq, void *id)
{
	struct exynos_tmu_data *data = id;

	disable_irq_nosync(irq);
	schedule_work(&data->irq_work);

	return IRQ_HANDLED;
}
static struct thermal_sensor_conf exynos_sensor_conf = {
	.name			= "exynos-therm",
	.read_temperature	= (int (*)(void *))exynos_tmu_read,
	.write_emul_temp	= exynos_tmu_set_emulation,
};

#ifdef CONFIG_OF
static const struct of_device_id exynos_tmu_match[] = {
	{
		.compatible = "samsung,exynos4210-tmu",
		.data = (void *)EXYNOS4210_TMU_DRV_DATA,
	},
	{
		.compatible = "samsung,exynos4412-tmu",
		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
	},
	{
		.compatible = "samsung,exynos5250-tmu",
		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
	},
	{},
};
MODULE_DEVICE_TABLE(of, exynos_tmu_match);
#endif

static struct platform_device_id exynos_tmu_driver_ids[] = {
	{
		.name		= "exynos4210-tmu",
		.driver_data    = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
	},
	{
		.name		= "exynos5250-tmu",
		.driver_data    = (kernel_ulong_t)EXYNOS5250_TMU_DRV_DATA,
	},
	{ },
};
MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);

static inline struct  exynos_tmu_platform_data *exynos_get_driver_data(
			struct platform_device *pdev)
{
#ifdef CONFIG_OF
	if (pdev->dev.of_node) {
		const struct of_device_id *match;
		match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
		if (!match)
			return NULL;
		return (struct exynos_tmu_platform_data *) match->data;
	}
#endif
	return (struct exynos_tmu_platform_data *)
			platform_get_device_id(pdev)->driver_data;
}

static int exynos_tmu_probe(struct platform_device *pdev)
{
	struct exynos_tmu_data *data;
	struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
	int ret, i;

	if (!pdata)
		pdata = exynos_get_driver_data(pdev);

	if (!pdata) {
		dev_err(&pdev->dev, "No platform init data supplied.\n");
		return -ENODEV;
	}
	data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
					GFP_KERNEL);
	if (!data) {
		dev_err(&pdev->dev, "Failed to allocate driver structure\n");
		return -ENOMEM;
	}

	data->irq = platform_get_irq(pdev, 0);
	if (data->irq < 0) {
		dev_err(&pdev->dev, "Failed to get platform irq\n");
		return data->irq;
	}

	INIT_WORK(&data->irq_work, exynos_tmu_work);

	data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->base = devm_ioremap_resource(&pdev->dev, data->mem);
	if (IS_ERR(data->base))
		return PTR_ERR(data->base);

	ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
		IRQF_TRIGGER_RISING, "exynos-tmu", data);
	if (ret) {
		dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
		return ret;
	}

	data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
	if (IS_ERR(data->clk)) {
		dev_err(&pdev->dev, "Failed to get clock\n");
		return  PTR_ERR(data->clk);
	}

	ret = clk_prepare(data->clk);
	if (ret)
		return ret;

	if (pdata->type == SOC_ARCH_EXYNOS ||
				pdata->type == SOC_ARCH_EXYNOS4210)
		data->soc = pdata->type;
	else {
		ret = -EINVAL;
		dev_err(&pdev->dev, "Platform not supported\n");
		goto err_clk;
	}

	data->pdata = pdata;
	platform_set_drvdata(pdev, data);
	mutex_init(&data->lock);

	ret = exynos_tmu_initialize(pdev);
	if (ret) {
		dev_err(&pdev->dev, "Failed to initialize TMU\n");
		goto err_clk;
	}

	exynos_tmu_control(pdev, true);

	/* Register the sensor with thermal management interface */
	(&exynos_sensor_conf)->private_data = data;
	exynos_sensor_conf.trip_data.trip_count = pdata->trigger_enable[0] +
			pdata->trigger_enable[1] + pdata->trigger_enable[2]+
			pdata->trigger_enable[3];

	for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
		exynos_sensor_conf.trip_data.trip_val[i] =
			pdata->threshold + pdata->trigger_levels[i];

	exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;

	exynos_sensor_conf.cooling_data.freq_clip_count =
						pdata->freq_tab_count;
	for (i = 0; i < pdata->freq_tab_count; i++) {
		exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
					pdata->freq_tab[i].freq_clip_max;
		exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
					pdata->freq_tab[i].temp_level;
	}

	ret = exynos_register_thermal(&exynos_sensor_conf);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register thermal interface\n");
		goto err_clk;
	}

	return 0;
err_clk:
	clk_unprepare(data->clk);
	return ret;
}

static int exynos_tmu_remove(struct platform_device *pdev)
{
	struct exynos_tmu_data *data = platform_get_drvdata(pdev);

	exynos_tmu_control(pdev, false);

	exynos_unregister_thermal();

	clk_unprepare(data->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int exynos_tmu_suspend(struct device *dev)
{
	exynos_tmu_control(to_platform_device(dev), false);

	return 0;
}

static int exynos_tmu_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);

	exynos_tmu_initialize(pdev);
	exynos_tmu_control(pdev, true);

	return 0;
}

static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
			 exynos_tmu_suspend, exynos_tmu_resume);
#define EXYNOS_TMU_PM	(&exynos_tmu_pm)
#else
#define EXYNOS_TMU_PM	NULL
#endif

static struct platform_driver exynos_tmu_driver = {
	.driver = {
		.name   = "exynos-tmu",
		.owner  = THIS_MODULE,
		.pm     = EXYNOS_TMU_PM,
		.of_match_table = of_match_ptr(exynos_tmu_match),
	},
	.probe = exynos_tmu_probe,
	.remove	= exynos_tmu_remove,
	.id_table = exynos_tmu_driver_ids,
};

module_platform_driver(exynos_tmu_driver);

MODULE_DESCRIPTION("EXYNOS TMU Driver");
MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:exynos-tmu");
Commit	Line	Data
9d97e5c8	1	/*
59dfa54c	2	* exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
9d97e5c8 DK	3	*
	4	* Copyright (C) 2011 Samsung Electronics
	5	* Donggeun Kim <dg77.kim@samsung.com>
c48cbba6	6	* Amit Daniel Kachhap <amit.kachhap@linaro.org>
9d97e5c8 DK	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*/
	23
9d97e5c8	24	#include <linux/clk.h>
9d97e5c8	25	#include <linux/io.h>
1b678641 ADK	26	#include <linux/interrupt.h>
1b678641 ADK	27	#include <linux/module.h>
f22d9c03	28	#include <linux/of.h>
1b678641	29	#include <linux/platform_device.h>
1b678641 ADK	30
1b678641 ADK	31	#include "exynos_thermal_common.h"
0c1836a6	32	#include "exynos_tmu.h"
e6b7991e	33	#include "exynos_tmu_data.h"
f22d9c03	34
f22d9c03 ADK	35	/* Exynos generic registers */
	36	#define EXYNOS_TMU_REG_TRIMINFO 0x0
	37	#define EXYNOS_TMU_REG_CONTROL 0x20
	38	#define EXYNOS_TMU_REG_STATUS 0x28
	39	#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
	40	#define EXYNOS_TMU_REG_INTEN 0x70
	41	#define EXYNOS_TMU_REG_INTSTAT 0x74
	42	#define EXYNOS_TMU_REG_INTCLEAR 0x78
	43
	44	#define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
	45	#define EXYNOS_TMU_GAIN_SHIFT 8
d0a0ce3e	46	#define EXYNOS_TMU_GAIN_MASK 0xf
f22d9c03	47	#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
d0a0ce3e ADK	48	#define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
	49	#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
	50	#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
	51	#define EXYNOS_TMU_CORE_EN_SHIFT 0
f22d9c03 ADK	52
	53	/* Exynos4210 specific registers */
	54	#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
	55	#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
	56	#define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
	57	#define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
	58	#define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
	59	#define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
	60	#define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
	61	#define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
	62	#define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
	63
	64	#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
	65	#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
	66	#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
	67	#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
d0a0ce3e	68	#define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111
f22d9c03 ADK	69	#define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
	70
	71	/* Exynos5250 and Exynos4412 specific registers */
	72	#define EXYNOS_TMU_TRIMINFO_CON 0x14
	73	#define EXYNOS_THD_TEMP_RISE 0x50
	74	#define EXYNOS_THD_TEMP_FALL 0x54
	75	#define EXYNOS_EMUL_CON 0x80
	76
	77	#define EXYNOS_TRIMINFO_RELOAD 0x1
d0a0ce3e ADK	78	#define EXYNOS_TRIMINFO_SHIFT 0x0
	79	#define EXYNOS_TMU_RISE_INT_MASK 0x111
	80	#define EXYNOS_TMU_RISE_INT_SHIFT 0
	81	#define EXYNOS_TMU_FALL_INT_MASK 0x111
	82	#define EXYNOS_TMU_FALL_INT_SHIFT 12
f22d9c03	83	#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
3ad9524a	84	#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
f22d9c03	85	#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
d0a0ce3e ADK	86	#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
	87
	88	#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
	89	#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
	90	#define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
	91	#define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
	92	#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
	93	#define EXYNOS_TMU_INTEN_FALL1_SHIFT 20
	94	#define EXYNOS_TMU_INTEN_FALL2_SHIFT 24
f22d9c03	95
bffd1f8a	96	#ifdef CONFIG_THERMAL_EMULATION
bbf63be4	97	#define EXYNOS_EMUL_TIME 0x57F0
d0a0ce3e	98	#define EXYNOS_EMUL_TIME_MASK 0xffff
bbf63be4 JL	99	#define EXYNOS_EMUL_TIME_SHIFT 16
	100	#define EXYNOS_EMUL_DATA_SHIFT 8
	101	#define EXYNOS_EMUL_DATA_MASK 0xFF
	102	#define EXYNOS_EMUL_ENABLE 0x1
bffd1f8a	103	#endif /* CONFIG_THERMAL_EMULATION */
bbf63be4	104
f22d9c03 ADK	105	struct exynos_tmu_data {
f22d9c03 ADK	106	struct exynos_tmu_platform_data *pdata;
9d97e5c8 DK	107	struct resource *mem;
	108	void __iomem *base;
	109	int irq;
f22d9c03	110	enum soc_type soc;
9d97e5c8 DK	111	struct work_struct irq_work;
	112	struct mutex lock;
	113	struct clk *clk;
	114	u8 temp_error1, temp_error2;
	115	};
	116
	117	/*
	118	* TMU treats temperature as a mapped temperature code.
	119	* The temperature is converted differently depending on the calibration type.
	120	*/
f22d9c03	121	static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
9d97e5c8	122	{
f22d9c03	123	struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8 DK	124	int temp_code;
9d97e5c8 DK	125
f22d9c03 ADK	126	if (data->soc == SOC_ARCH_EXYNOS4210)
	127	/* temp should range between 25 and 125 */
	128	if (temp < 25 \|\| temp > 125) {
	129	temp_code = -EINVAL;
	130	goto out;
	131	}
9d97e5c8 DK	132
	133	switch (pdata->cal_type) {
	134	case TYPE_TWO_POINT_TRIMMING:
bb34b4c8 ADK	135	temp_code = (temp - pdata->first_point_trim) *
	136	(data->temp_error2 - data->temp_error1) /
	137	(pdata->second_point_trim - pdata->first_point_trim) +
	138	data->temp_error1;
9d97e5c8 DK	139	break;
9d97e5c8 DK	140	case TYPE_ONE_POINT_TRIMMING:
bb34b4c8	141	temp_code = temp + data->temp_error1 - pdata->first_point_trim;
9d97e5c8 DK	142	break;
9d97e5c8 DK	143	default:
bb34b4c8	144	temp_code = temp + pdata->default_temp_offset;
9d97e5c8 DK	145	break;
	146	}
	147	out:
	148	return temp_code;
	149	}
	150
	151	/*
	152	* Calculate a temperature value from a temperature code.
	153	* The unit of the temperature is degree Celsius.
	154	*/
f22d9c03	155	static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
9d97e5c8	156	{
f22d9c03	157	struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8 DK	158	int temp;
9d97e5c8 DK	159
f22d9c03 ADK	160	if (data->soc == SOC_ARCH_EXYNOS4210)
	161	/* temp_code should range between 75 and 175 */
	162	if (temp_code < 75 \|\| temp_code > 175) {
	163	temp = -ENODATA;
	164	goto out;
	165	}
9d97e5c8 DK	166
	167	switch (pdata->cal_type) {
	168	case TYPE_TWO_POINT_TRIMMING:
bb34b4c8 ADK	169	temp = (temp_code - data->temp_error1) *
	170	(pdata->second_point_trim - pdata->first_point_trim) /
	171	(data->temp_error2 - data->temp_error1) +
	172	pdata->first_point_trim;
9d97e5c8 DK	173	break;
9d97e5c8 DK	174	case TYPE_ONE_POINT_TRIMMING:
bb34b4c8	175	temp = temp_code - data->temp_error1 + pdata->first_point_trim;
9d97e5c8 DK	176	break;
9d97e5c8 DK	177	default:
bb34b4c8	178	temp = temp_code - pdata->default_temp_offset;
9d97e5c8 DK	179	break;
	180	}
	181	out:
	182	return temp;
	183	}
	184
f22d9c03	185	static int exynos_tmu_initialize(struct platform_device *pdev)
9d97e5c8	186	{
f22d9c03 ADK	187	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
f22d9c03 ADK	188	struct exynos_tmu_platform_data *pdata = data->pdata;
4f0a6847 JL	189	unsigned int status, trim_info;
	190	unsigned int rising_threshold = 0, falling_threshold = 0;
	191	int ret = 0, threshold_code, i, trigger_levs = 0;
9d97e5c8 DK	192
	193	mutex_lock(&data->lock);
	194	clk_enable(data->clk);
	195
f22d9c03	196	status = readb(data->base + EXYNOS_TMU_REG_STATUS);
9d97e5c8 DK	197	if (!status) {
	198	ret = -EBUSY;
	199	goto out;
	200	}
	201
f22d9c03 ADK	202	if (data->soc == SOC_ARCH_EXYNOS) {
	203	__raw_writel(EXYNOS_TRIMINFO_RELOAD,
	204	data->base + EXYNOS_TMU_TRIMINFO_CON);
	205	}
9d97e5c8	206	/* Save trimming info in order to perform calibration */
f22d9c03 ADK	207	trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
	208	data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
	209	data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
	210
bb34b4c8 ADK	211	if ((pdata->min_efuse_value > data->temp_error1) \|\|
bb34b4c8 ADK	212	(data->temp_error1 > pdata->max_efuse_value) \|\|
f22d9c03 ADK	213	(data->temp_error2 != 0))
	214	data->temp_error1 = pdata->efuse_value;
	215
4f0a6847 JL	216	/* Count trigger levels to be enabled */
	217	for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
	218	if (pdata->trigger_levels[i])
	219	trigger_levs++;
	220
f22d9c03 ADK	221	if (data->soc == SOC_ARCH_EXYNOS4210) {
	222	/* Write temperature code for threshold */
	223	threshold_code = temp_to_code(data, pdata->threshold);
	224	if (threshold_code < 0) {
	225	ret = threshold_code;
	226	goto out;
	227	}
	228	writeb(threshold_code,
	229	data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
4f0a6847 JL	230	for (i = 0; i < trigger_levs; i++)
	231	writeb(pdata->trigger_levels[i],
	232	data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
f22d9c03 ADK	233
	234	writel(EXYNOS4210_TMU_INTCLEAR_VAL,
	235	data->base + EXYNOS_TMU_REG_INTCLEAR);
	236	} else if (data->soc == SOC_ARCH_EXYNOS) {
4f0a6847 JL	237	/* Write temperature code for rising and falling threshold */
	238	for (i = 0; i < trigger_levs; i++) {
	239	threshold_code = temp_to_code(data,
	240	pdata->trigger_levels[i]);
	241	if (threshold_code < 0) {
	242	ret = threshold_code;
	243	goto out;
	244	}
	245	rising_threshold \|= threshold_code << 8 * i;
	246	if (pdata->threshold_falling) {
	247	threshold_code = temp_to_code(data,
	248	pdata->trigger_levels[i] -
	249	pdata->threshold_falling);
	250	if (threshold_code > 0)
	251	falling_threshold \|=
	252	threshold_code << 8 * i;
	253	}
f22d9c03	254	}
f22d9c03 ADK	255
	256	writel(rising_threshold,
	257	data->base + EXYNOS_THD_TEMP_RISE);
4f0a6847 JL	258	writel(falling_threshold,
4f0a6847 JL	259	data->base + EXYNOS_THD_TEMP_FALL);
f22d9c03	260
4f0a6847	261	writel(EXYNOS_TMU_CLEAR_RISE_INT \| EXYNOS_TMU_CLEAR_FALL_INT,
f22d9c03	262	data->base + EXYNOS_TMU_REG_INTCLEAR);
9d97e5c8	263	}
9d97e5c8 DK	264	out:
	265	clk_disable(data->clk);
	266	mutex_unlock(&data->lock);
	267
	268	return ret;
	269	}
	270
f22d9c03	271	static void exynos_tmu_control(struct platform_device *pdev, bool on)
9d97e5c8	272	{
f22d9c03 ADK	273	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
f22d9c03 ADK	274	struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8 DK	275	unsigned int con, interrupt_en;
	276
	277	mutex_lock(&data->lock);
	278	clk_enable(data->clk);
	279
d0a0ce3e	280	con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
f22d9c03	281
d0a0ce3e ADK	282	if (pdata->reference_voltage) {
	283	con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK <<
	284	EXYNOS_TMU_REF_VOLTAGE_SHIFT);
	285	con \|= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
	286	}
	287
	288	if (pdata->gain) {
	289	con &= ~(EXYNOS_TMU_GAIN_MASK << EXYNOS_TMU_GAIN_SHIFT);
	290	con \|= (pdata->gain << EXYNOS_TMU_GAIN_SHIFT);
	291	}
	292
	293	if (pdata->noise_cancel_mode) {
	294	con &= ~(EXYNOS_TMU_TRIP_MODE_MASK <<
	295	EXYNOS_TMU_TRIP_MODE_SHIFT);
	296	con \|= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
f22d9c03 ADK	297	}
f22d9c03 ADK	298
9d97e5c8	299	if (on) {
d0a0ce3e ADK	300	con \|= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
d0a0ce3e ADK	301	interrupt_en =
bb34b4c8 ADK	302	pdata->trigger_enable[3] << EXYNOS_TMU_INTEN_RISE3_SHIFT \|
	303	pdata->trigger_enable[2] << EXYNOS_TMU_INTEN_RISE2_SHIFT \|
	304	pdata->trigger_enable[1] << EXYNOS_TMU_INTEN_RISE1_SHIFT \|
	305	pdata->trigger_enable[0] << EXYNOS_TMU_INTEN_RISE0_SHIFT;
4f0a6847	306	if (pdata->threshold_falling)
d0a0ce3e ADK	307	interrupt_en \|=
d0a0ce3e ADK	308	interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
9d97e5c8	309	} else {
d0a0ce3e	310	con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
9d97e5c8 DK	311	interrupt_en = 0; /* Disable all interrupts */
9d97e5c8 DK	312	}
f22d9c03 ADK	313	writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
f22d9c03 ADK	314	writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
9d97e5c8 DK	315
	316	clk_disable(data->clk);
	317	mutex_unlock(&data->lock);
	318	}
	319
f22d9c03	320	static int exynos_tmu_read(struct exynos_tmu_data *data)
9d97e5c8 DK	321	{
	322	u8 temp_code;
	323	int temp;
	324
	325	mutex_lock(&data->lock);
	326	clk_enable(data->clk);
	327
f22d9c03	328	temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
9d97e5c8 DK	329	temp = code_to_temp(data, temp_code);
	330
	331	clk_disable(data->clk);
	332	mutex_unlock(&data->lock);
	333
	334	return temp;
	335	}
	336
bffd1f8a ADK	337	#ifdef CONFIG_THERMAL_EMULATION
	338	static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
	339	{
	340	struct exynos_tmu_data *data = drv_data;
	341	unsigned int reg;
	342	int ret = -EINVAL;
	343
	344	if (data->soc == SOC_ARCH_EXYNOS4210)
	345	goto out;
	346
	347	if (temp && temp < MCELSIUS)
	348	goto out;
	349
	350	mutex_lock(&data->lock);
	351	clk_enable(data->clk);
	352
	353	reg = readl(data->base + EXYNOS_EMUL_CON);
	354
	355	if (temp) {
	356	temp /= MCELSIUS;
	357
	358	reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) \|
	359	(temp_to_code(data, temp)
	360	<< EXYNOS_EMUL_DATA_SHIFT) \| EXYNOS_EMUL_ENABLE;
	361	} else {
	362	reg &= ~EXYNOS_EMUL_ENABLE;
	363	}
	364
	365	writel(reg, data->base + EXYNOS_EMUL_CON);
	366
	367	clk_disable(data->clk);
	368	mutex_unlock(&data->lock);
	369	return 0;
	370	out:
	371	return ret;
	372	}
	373	#else
	374	static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
	375	{ return -EINVAL; }
	376	#endif/CONFIG_THERMAL_EMULATION/
	377
f22d9c03	378	static void exynos_tmu_work(struct work_struct *work)
9d97e5c8	379	{
f22d9c03 ADK	380	struct exynos_tmu_data *data = container_of(work,
f22d9c03 ADK	381	struct exynos_tmu_data, irq_work);
9d97e5c8	382
3ad9524a	383	exynos_report_trigger();
9d97e5c8 DK	384	mutex_lock(&data->lock);
9d97e5c8 DK	385	clk_enable(data->clk);
f22d9c03	386	if (data->soc == SOC_ARCH_EXYNOS)
4f0a6847 JL	387	writel(EXYNOS_TMU_CLEAR_RISE_INT \|
4f0a6847 JL	388	EXYNOS_TMU_CLEAR_FALL_INT,
f22d9c03 ADK	389	data->base + EXYNOS_TMU_REG_INTCLEAR);
	390	else
	391	writel(EXYNOS4210_TMU_INTCLEAR_VAL,
	392	data->base + EXYNOS_TMU_REG_INTCLEAR);
9d97e5c8 DK	393	clk_disable(data->clk);
9d97e5c8 DK	394	mutex_unlock(&data->lock);
3ad9524a	395
f22d9c03	396	enable_irq(data->irq);
9d97e5c8 DK	397	}
9d97e5c8 DK	398
f22d9c03	399	static irqreturn_t exynos_tmu_irq(int irq, void *id)
9d97e5c8	400	{
f22d9c03	401	struct exynos_tmu_data *data = id;
9d97e5c8 DK	402
	403	disable_irq_nosync(irq);
	404	schedule_work(&data->irq_work);
	405
	406	return IRQ_HANDLED;
	407	}
7e0b55e6 ADK	408	static struct thermal_sensor_conf exynos_sensor_conf = {
	409	.name = "exynos-therm",
	410	.read_temperature = (int ()(void ))exynos_tmu_read,
bffd1f8a	411	.write_emul_temp = exynos_tmu_set_emulation,
17be868e ADK	412	};
17be868e ADK	413
17be868e ADK	414	#ifdef CONFIG_OF
	415	static const struct of_device_id exynos_tmu_match[] = {
	416	{
	417	.compatible = "samsung,exynos4210-tmu",
	418	.data = (void *)EXYNOS4210_TMU_DRV_DATA,
	419	},
b6cee53c SK	420	{
b6cee53c SK	421	.compatible = "samsung,exynos4412-tmu",
e6b7991e	422	.data = (void *)EXYNOS5250_TMU_DRV_DATA,
b6cee53c	423	},
17be868e ADK	424	{
17be868e ADK	425	.compatible = "samsung,exynos5250-tmu",
e6b7991e	426	.data = (void *)EXYNOS5250_TMU_DRV_DATA,
17be868e ADK	427	},
	428	{},
	429	};
	430	MODULE_DEVICE_TABLE(of, exynos_tmu_match);
17be868e ADK	431	#endif
	432
	433	static struct platform_device_id exynos_tmu_driver_ids[] = {
	434	{
	435	.name = "exynos4210-tmu",
	436	.driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
	437	},
	438	{
	439	.name = "exynos5250-tmu",
e6b7991e	440	.driver_data = (kernel_ulong_t)EXYNOS5250_TMU_DRV_DATA,
17be868e ADK	441	},
	442	{ },
	443	};
3ae53b1e	444	MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
17be868e ADK	445
	446	static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
	447	struct platform_device *pdev)
	448	{
	449	#ifdef CONFIG_OF
	450	if (pdev->dev.of_node) {
	451	const struct of_device_id *match;
	452	match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
	453	if (!match)
	454	return NULL;
	455	return (struct exynos_tmu_platform_data *) match->data;
	456	}
	457	#endif
	458	return (struct exynos_tmu_platform_data *)
	459	platform_get_device_id(pdev)->driver_data;
7e0b55e6	460	}
bbf63be4	461
4eab7a9e	462	static int exynos_tmu_probe(struct platform_device *pdev)
9d97e5c8	463	{
f22d9c03 ADK	464	struct exynos_tmu_data *data;
f22d9c03 ADK	465	struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
7e0b55e6	466	int ret, i;
9d97e5c8	467
17be868e ADK	468	if (!pdata)
	469	pdata = exynos_get_driver_data(pdev);
	470
9d97e5c8 DK	471	if (!pdata) {
	472	dev_err(&pdev->dev, "No platform init data supplied.\n");
	473	return -ENODEV;
	474	}
79e093c3 ADK	475	data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
79e093c3 ADK	476	GFP_KERNEL);
9d97e5c8 DK	477	if (!data) {
	478	dev_err(&pdev->dev, "Failed to allocate driver structure\n");
	479	return -ENOMEM;
	480	}
	481
	482	data->irq = platform_get_irq(pdev, 0);
	483	if (data->irq < 0) {
9d97e5c8	484	dev_err(&pdev->dev, "Failed to get platform irq\n");
79e093c3	485	return data->irq;
9d97e5c8 DK	486	}
9d97e5c8 DK	487
f22d9c03	488	INIT_WORK(&data->irq_work, exynos_tmu_work);
9d97e5c8 DK	489
9d97e5c8 DK	490	data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ca36b1ba TR	491	data->base = devm_ioremap_resource(&pdev->dev, data->mem);
	492	if (IS_ERR(data->base))
	493	return PTR_ERR(data->base);
9d97e5c8	494
79e093c3	495	ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
f22d9c03	496	IRQF_TRIGGER_RISING, "exynos-tmu", data);
9d97e5c8 DK	497	if (ret) {
9d97e5c8 DK	498	dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
79e093c3	499	return ret;
9d97e5c8 DK	500	}
9d97e5c8 DK	501
2a16279c	502	data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
9d97e5c8	503	if (IS_ERR(data->clk)) {
9d97e5c8	504	dev_err(&pdev->dev, "Failed to get clock\n");
79e093c3	505	return PTR_ERR(data->clk);
9d97e5c8 DK	506	}
9d97e5c8 DK	507
2a16279c SK	508	ret = clk_prepare(data->clk);
	509	if (ret)
	510	return ret;
	511
f22d9c03 ADK	512	if (pdata->type == SOC_ARCH_EXYNOS \|\|
	513	pdata->type == SOC_ARCH_EXYNOS4210)
	514	data->soc = pdata->type;
	515	else {
	516	ret = -EINVAL;
	517	dev_err(&pdev->dev, "Platform not supported\n");
	518	goto err_clk;
	519	}
	520
9d97e5c8 DK	521	data->pdata = pdata;
	522	platform_set_drvdata(pdev, data);
	523	mutex_init(&data->lock);
	524
f22d9c03	525	ret = exynos_tmu_initialize(pdev);
9d97e5c8 DK	526	if (ret) {
	527	dev_err(&pdev->dev, "Failed to initialize TMU\n");
	528	goto err_clk;
	529	}
	530
f22d9c03	531	exynos_tmu_control(pdev, true);
9d97e5c8	532
7e0b55e6 ADK	533	/* Register the sensor with thermal management interface */
7e0b55e6 ADK	534	(&exynos_sensor_conf)->private_data = data;
bb34b4c8 ADK	535	exynos_sensor_conf.trip_data.trip_count = pdata->trigger_enable[0] +
	536	pdata->trigger_enable[1] + pdata->trigger_enable[2]+
	537	pdata->trigger_enable[3];
7e0b55e6 ADK	538
	539	for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
	540	exynos_sensor_conf.trip_data.trip_val[i] =
	541	pdata->threshold + pdata->trigger_levels[i];
	542
4f0a6847 JL	543	exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;
4f0a6847 JL	544
7e0b55e6 ADK	545	exynos_sensor_conf.cooling_data.freq_clip_count =
	546	pdata->freq_tab_count;
	547	for (i = 0; i < pdata->freq_tab_count; i++) {
	548	exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
	549	pdata->freq_tab[i].freq_clip_max;
	550	exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
	551	pdata->freq_tab[i].temp_level;
	552	}
	553
	554	ret = exynos_register_thermal(&exynos_sensor_conf);
	555	if (ret) {
	556	dev_err(&pdev->dev, "Failed to register thermal interface\n");
	557	goto err_clk;
	558	}
bbf63be4	559
9d97e5c8	560	return 0;
9d97e5c8	561	err_clk:
2a16279c	562	clk_unprepare(data->clk);
9d97e5c8 DK	563	return ret;
	564	}
	565
4eab7a9e	566	static int exynos_tmu_remove(struct platform_device *pdev)
9d97e5c8	567	{
f22d9c03	568	struct exynos_tmu_data *data = platform_get_drvdata(pdev);
9d97e5c8	569
f22d9c03	570	exynos_tmu_control(pdev, false);
9d97e5c8	571
7e0b55e6 ADK	572	exynos_unregister_thermal();
7e0b55e6 ADK	573
2a16279c	574	clk_unprepare(data->clk);
9d97e5c8	575
9d97e5c8 DK	576	return 0;
	577	}
	578
08cd6753	579	#ifdef CONFIG_PM_SLEEP
f22d9c03	580	static int exynos_tmu_suspend(struct device *dev)
9d97e5c8	581	{
f22d9c03	582	exynos_tmu_control(to_platform_device(dev), false);
9d97e5c8 DK	583
	584	return 0;
	585	}
	586
f22d9c03	587	static int exynos_tmu_resume(struct device *dev)
9d97e5c8	588	{
08cd6753 RW	589	struct platform_device *pdev = to_platform_device(dev);
08cd6753 RW	590
f22d9c03 ADK	591	exynos_tmu_initialize(pdev);
f22d9c03 ADK	592	exynos_tmu_control(pdev, true);
9d97e5c8 DK	593
	594	return 0;
	595	}
08cd6753	596
f22d9c03 ADK	597	static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
	598	exynos_tmu_suspend, exynos_tmu_resume);
	599	#define EXYNOS_TMU_PM (&exynos_tmu_pm)
9d97e5c8	600	#else
f22d9c03	601	#define EXYNOS_TMU_PM NULL
9d97e5c8 DK	602	#endif
9d97e5c8 DK	603
f22d9c03	604	static struct platform_driver exynos_tmu_driver = {
9d97e5c8	605	.driver = {
f22d9c03	606	.name = "exynos-tmu",
9d97e5c8	607	.owner = THIS_MODULE,
f22d9c03	608	.pm = EXYNOS_TMU_PM,
caa5cbd5	609	.of_match_table = of_match_ptr(exynos_tmu_match),
9d97e5c8	610	},
f22d9c03	611	.probe = exynos_tmu_probe,
4eab7a9e	612	.remove = exynos_tmu_remove,
17be868e	613	.id_table = exynos_tmu_driver_ids,
9d97e5c8 DK	614	};
9d97e5c8 DK	615
f22d9c03	616	module_platform_driver(exynos_tmu_driver);
9d97e5c8	617
f22d9c03	618	MODULE_DESCRIPTION("EXYNOS TMU Driver");
9d97e5c8 DK	619	MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
9d97e5c8 DK	620	MODULE_LICENSE("GPL");
f22d9c03	621	MODULE_ALIAS("platform:exynos-tmu");