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9d97e5c8 | 1 | /* |
0c1836a6 | 2 | * exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit) |
9d97e5c8 DK |
3 | * |
4 | * Copyright (C) 2011 Samsung Electronics | |
5 | * Donggeun Kim <dg77.kim@samsung.com> | |
0c1836a6 | 6 | * Amit Daniel Kachhap <amit.daniel@samsung.com> |
9d97e5c8 DK |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
0c1836a6 ADK |
23 | #ifndef _EXYNOS_TMU_H |
24 | #define _EXYNOS_TMU_H | |
7e0b55e6 | 25 | #include <linux/cpu_cooling.h> |
9d97e5c8 | 26 | |
0c1836a6 ADK |
27 | #include "exynos_thermal_common.h" |
28 | ||
9d97e5c8 DK |
29 | enum calibration_type { |
30 | TYPE_ONE_POINT_TRIMMING, | |
1928457e ADK |
31 | TYPE_ONE_POINT_TRIMMING_25, |
32 | TYPE_ONE_POINT_TRIMMING_85, | |
9d97e5c8 DK |
33 | TYPE_TWO_POINT_TRIMMING, |
34 | TYPE_NONE, | |
35 | }; | |
36 | ||
bb34b4c8 ADK |
37 | enum calibration_mode { |
38 | SW_MODE, | |
39 | HW_MODE, | |
40 | }; | |
41 | ||
f22d9c03 ADK |
42 | enum soc_type { |
43 | SOC_ARCH_EXYNOS4210 = 1, | |
14ddfaec LM |
44 | SOC_ARCH_EXYNOS4412, |
45 | SOC_ARCH_EXYNOS5250, | |
a0395eee | 46 | SOC_ARCH_EXYNOS5440, |
f22d9c03 | 47 | }; |
7e0b55e6 | 48 | |
f4dae753 ADK |
49 | /** |
50 | * EXYNOS TMU supported features. | |
51 | * TMU_SUPPORT_EMULATION - This features is used to set user defined | |
52 | * temperature to the TMU controller. | |
53 | * TMU_SUPPORT_MULTI_INST - This features denotes that the soc | |
54 | * has many instances of TMU. | |
55 | * TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can | |
56 | * be reloaded. | |
57 | * TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can | |
58 | * be registered for falling trips also. | |
59 | * TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current | |
60 | * state(active/idle) can be checked. | |
61 | * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation | |
62 | * sample time. | |
63 | * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU | |
64 | * sensors shares some common registers. | |
65 | * TMU_SUPPORT - macro to compare the above features with the supplied. | |
66 | */ | |
67 | #define TMU_SUPPORT_EMULATION BIT(0) | |
68 | #define TMU_SUPPORT_MULTI_INST BIT(1) | |
69 | #define TMU_SUPPORT_TRIM_RELOAD BIT(2) | |
70 | #define TMU_SUPPORT_FALLING_TRIP BIT(3) | |
71 | #define TMU_SUPPORT_READY_STATUS BIT(4) | |
72 | #define TMU_SUPPORT_EMUL_TIME BIT(5) | |
73 | #define TMU_SUPPORT_SHARED_MEMORY BIT(6) | |
74 | ||
75 | #define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b) | |
76 | ||
b8d582b9 ADK |
77 | /** |
78 | * struct exynos_tmu_register - register descriptors to access registers and | |
79 | * bitfields. The register validity, offsets and bitfield values may vary | |
80 | * slightly across different exynos SOC's. | |
81 | * @triminfo_data: register containing 2 pont trimming data | |
82 | * @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg. | |
83 | * @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg. | |
84 | * @triminfo_ctrl: trim info controller register. | |
85 | * @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl | |
86 | reg. | |
87 | * @tmu_ctrl: TMU main controller register. | |
86f5362e | 88 | * @test_mux_addr_shift: shift bits of test mux address. |
b8d582b9 ADK |
89 | * @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register. |
90 | * @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register. | |
91 | * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register. | |
92 | * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register. | |
93 | * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register. | |
94 | * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl | |
95 | register. | |
96 | * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register. | |
1928457e ADK |
97 | * @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl |
98 | register. | |
99 | * @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl | |
100 | register. | |
b8d582b9 ADK |
101 | * @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in |
102 | tmu_ctrl register. | |
103 | * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register. | |
104 | * @tmu_status: register drescribing the TMU status. | |
105 | * @tmu_cur_temp: register containing the current temperature of the TMU. | |
106 | * @tmu_cur_temp_shift: shift bits of current temp value in tmu_cur_temp | |
107 | register. | |
108 | * @threshold_temp: register containing the base threshold level. | |
109 | * @threshold_th0: Register containing first set of rising levels. | |
110 | * @threshold_th0_l0_shift: shift bits of level0 threshold temperature. | |
111 | * @threshold_th0_l1_shift: shift bits of level1 threshold temperature. | |
112 | * @threshold_th0_l2_shift: shift bits of level2 threshold temperature. | |
113 | * @threshold_th0_l3_shift: shift bits of level3 threshold temperature. | |
114 | * @threshold_th1: Register containing second set of rising levels. | |
115 | * @threshold_th1_l0_shift: shift bits of level0 threshold temperature. | |
116 | * @threshold_th1_l1_shift: shift bits of level1 threshold temperature. | |
117 | * @threshold_th1_l2_shift: shift bits of level2 threshold temperature. | |
118 | * @threshold_th1_l3_shift: shift bits of level3 threshold temperature. | |
119 | * @threshold_th2: Register containing third set of rising levels. | |
120 | * @threshold_th2_l0_shift: shift bits of level0 threshold temperature. | |
121 | * @threshold_th3: Register containing fourth set of rising levels. | |
122 | * @threshold_th3_l0_shift: shift bits of level0 threshold temperature. | |
123 | * @tmu_inten: register containing the different threshold interrupt | |
124 | enable bits. | |
125 | * @inten_rise_shift: shift bits of all rising interrupt bits. | |
126 | * @inten_rise_mask: mask bits of all rising interrupt bits. | |
127 | * @inten_fall_shift: shift bits of all rising interrupt bits. | |
128 | * @inten_fall_mask: mask bits of all rising interrupt bits. | |
129 | * @inten_rise0_shift: shift bits of rising 0 interrupt bits. | |
130 | * @inten_rise1_shift: shift bits of rising 1 interrupt bits. | |
131 | * @inten_rise2_shift: shift bits of rising 2 interrupt bits. | |
132 | * @inten_rise3_shift: shift bits of rising 3 interrupt bits. | |
133 | * @inten_fall0_shift: shift bits of falling 0 interrupt bits. | |
134 | * @inten_fall1_shift: shift bits of falling 1 interrupt bits. | |
135 | * @inten_fall2_shift: shift bits of falling 2 interrupt bits. | |
136 | * @inten_fall3_shift: shift bits of falling 3 interrupt bits. | |
137 | * @tmu_intstat: Register containing the interrupt status values. | |
138 | * @tmu_intclear: Register for clearing the raised interrupt status. | |
139 | * @emul_con: TMU emulation controller register. | |
140 | * @emul_temp_shift: shift bits of emulation temperature. | |
141 | * @emul_time_shift: shift bits of emulation time. | |
142 | * @emul_time_mask: mask bits of emulation time. | |
a0395eee ADK |
143 | * @tmu_irqstatus: register to find which TMU generated interrupts. |
144 | * @tmu_pmin: register to get/set the Pmin value. | |
b8d582b9 ADK |
145 | */ |
146 | struct exynos_tmu_registers { | |
147 | u32 triminfo_data; | |
148 | u32 triminfo_25_shift; | |
149 | u32 triminfo_85_shift; | |
150 | ||
151 | u32 triminfo_ctrl; | |
152 | u32 triminfo_reload_shift; | |
153 | ||
154 | u32 tmu_ctrl; | |
86f5362e | 155 | u32 test_mux_addr_shift; |
b8d582b9 ADK |
156 | u32 buf_vref_sel_shift; |
157 | u32 buf_vref_sel_mask; | |
158 | u32 therm_trip_mode_shift; | |
159 | u32 therm_trip_mode_mask; | |
160 | u32 therm_trip_en_shift; | |
161 | u32 buf_slope_sel_shift; | |
162 | u32 buf_slope_sel_mask; | |
1928457e ADK |
163 | u32 calib_mode_shift; |
164 | u32 calib_mode_mask; | |
b8d582b9 ADK |
165 | u32 therm_trip_tq_en_shift; |
166 | u32 core_en_shift; | |
167 | ||
168 | u32 tmu_status; | |
169 | ||
170 | u32 tmu_cur_temp; | |
171 | u32 tmu_cur_temp_shift; | |
172 | ||
173 | u32 threshold_temp; | |
174 | ||
175 | u32 threshold_th0; | |
176 | u32 threshold_th0_l0_shift; | |
177 | u32 threshold_th0_l1_shift; | |
178 | u32 threshold_th0_l2_shift; | |
179 | u32 threshold_th0_l3_shift; | |
180 | ||
181 | u32 threshold_th1; | |
182 | u32 threshold_th1_l0_shift; | |
183 | u32 threshold_th1_l1_shift; | |
184 | u32 threshold_th1_l2_shift; | |
185 | u32 threshold_th1_l3_shift; | |
186 | ||
187 | u32 threshold_th2; | |
188 | u32 threshold_th2_l0_shift; | |
189 | ||
190 | u32 threshold_th3; | |
191 | u32 threshold_th3_l0_shift; | |
192 | ||
193 | u32 tmu_inten; | |
194 | u32 inten_rise_shift; | |
195 | u32 inten_rise_mask; | |
196 | u32 inten_fall_shift; | |
197 | u32 inten_fall_mask; | |
198 | u32 inten_rise0_shift; | |
199 | u32 inten_rise1_shift; | |
200 | u32 inten_rise2_shift; | |
201 | u32 inten_rise3_shift; | |
202 | u32 inten_fall0_shift; | |
203 | u32 inten_fall1_shift; | |
204 | u32 inten_fall2_shift; | |
205 | u32 inten_fall3_shift; | |
206 | ||
207 | u32 tmu_intstat; | |
208 | ||
209 | u32 tmu_intclear; | |
210 | ||
211 | u32 emul_con; | |
212 | u32 emul_temp_shift; | |
213 | u32 emul_time_shift; | |
214 | u32 emul_time_mask; | |
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215 | |
216 | u32 tmu_irqstatus; | |
217 | u32 tmu_pmin; | |
b8d582b9 ADK |
218 | }; |
219 | ||
9d97e5c8 | 220 | /** |
f22d9c03 | 221 | * struct exynos_tmu_platform_data |
9d97e5c8 DK |
222 | * @threshold: basic temperature for generating interrupt |
223 | * 25 <= threshold <= 125 [unit: degree Celsius] | |
4f0a6847 JL |
224 | * @threshold_falling: differntial value for setting threshold |
225 | * of temperature falling interrupt. | |
9d97e5c8 DK |
226 | * @trigger_levels: array for each interrupt levels |
227 | * [unit: degree Celsius] | |
228 | * 0: temperature for trigger_level0 interrupt | |
229 | * condition for trigger_level0 interrupt: | |
230 | * current temperature > threshold + trigger_levels[0] | |
231 | * 1: temperature for trigger_level1 interrupt | |
232 | * condition for trigger_level1 interrupt: | |
233 | * current temperature > threshold + trigger_levels[1] | |
234 | * 2: temperature for trigger_level2 interrupt | |
235 | * condition for trigger_level2 interrupt: | |
236 | * current temperature > threshold + trigger_levels[2] | |
237 | * 3: temperature for trigger_level3 interrupt | |
238 | * condition for trigger_level3 interrupt: | |
239 | * current temperature > threshold + trigger_levels[3] | |
bb34b4c8 ADK |
240 | * @trigger_type: defines the type of trigger. Possible values are, |
241 | * THROTTLE_ACTIVE trigger type | |
242 | * THROTTLE_PASSIVE trigger type | |
243 | * SW_TRIP trigger type | |
244 | * HW_TRIP | |
245 | * @trigger_enable[]: array to denote which trigger levels are enabled. | |
246 | * 1 = enable trigger_level[] interrupt, | |
247 | * 0 = disable trigger_level[] interrupt | |
248 | * @max_trigger_level: max trigger level supported by the TMU | |
9d97e5c8 DK |
249 | * @gain: gain of amplifier in the positive-TC generator block |
250 | * 0 <= gain <= 15 | |
251 | * @reference_voltage: reference voltage of amplifier | |
252 | * in the positive-TC generator block | |
253 | * 0 <= reference_voltage <= 31 | |
f22d9c03 ADK |
254 | * @noise_cancel_mode: noise cancellation mode |
255 | * 000, 100, 101, 110 and 111 can be different modes | |
256 | * @type: determines the type of SOC | |
257 | * @efuse_value: platform defined fuse value | |
bb34b4c8 ADK |
258 | * @min_efuse_value: minimum valid trimming data |
259 | * @max_efuse_value: maximum valid trimming data | |
260 | * @first_point_trim: temp value of the first point trimming | |
261 | * @second_point_trim: temp value of the second point trimming | |
262 | * @default_temp_offset: default temperature offset in case of no trimming | |
86f5362e | 263 | * @test_mux; information if SoC supports test MUX |
9d97e5c8 | 264 | * @cal_type: calibration type for temperature |
bb34b4c8 | 265 | * @cal_mode: calibration mode for temperature |
7e0b55e6 ADK |
266 | * @freq_clip_table: Table representing frequency reduction percentage. |
267 | * @freq_tab_count: Count of the above table as frequency reduction may | |
268 | * applicable to only some of the trigger levels. | |
b8d582b9 ADK |
269 | * @registers: Pointer to structure containing all the TMU controller registers |
270 | * and bitfields shifts and masks. | |
f4dae753 ADK |
271 | * @features: a bitfield value indicating the features supported in SOC like |
272 | * emulation, multi instance etc | |
9d97e5c8 | 273 | * |
f22d9c03 | 274 | * This structure is required for configuration of exynos_tmu driver. |
9d97e5c8 | 275 | */ |
f22d9c03 | 276 | struct exynos_tmu_platform_data { |
9d97e5c8 | 277 | u8 threshold; |
4f0a6847 | 278 | u8 threshold_falling; |
bb34b4c8 ADK |
279 | u8 trigger_levels[MAX_TRIP_COUNT]; |
280 | enum trigger_type trigger_type[MAX_TRIP_COUNT]; | |
281 | bool trigger_enable[MAX_TRIP_COUNT]; | |
282 | u8 max_trigger_level; | |
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283 | u8 gain; |
284 | u8 reference_voltage; | |
f22d9c03 | 285 | u8 noise_cancel_mode; |
bb34b4c8 | 286 | |
f22d9c03 | 287 | u32 efuse_value; |
bb34b4c8 ADK |
288 | u32 min_efuse_value; |
289 | u32 max_efuse_value; | |
290 | u8 first_point_trim; | |
291 | u8 second_point_trim; | |
292 | u8 default_temp_offset; | |
86f5362e | 293 | u8 test_mux; |
9d97e5c8 DK |
294 | |
295 | enum calibration_type cal_type; | |
bb34b4c8 | 296 | enum calibration_mode cal_mode; |
f22d9c03 | 297 | enum soc_type type; |
7e0b55e6 ADK |
298 | struct freq_clip_table freq_tab[4]; |
299 | unsigned int freq_tab_count; | |
b8d582b9 | 300 | const struct exynos_tmu_registers *registers; |
f4dae753 | 301 | unsigned int features; |
9d97e5c8 | 302 | }; |
cebe7373 ADK |
303 | |
304 | /** | |
305 | * struct exynos_tmu_init_data | |
306 | * @tmu_count: number of TMU instances. | |
307 | * @tmu_data: platform data of all TMU instances. | |
308 | * This structure is required to store data for multi-instance exynos tmu | |
309 | * driver. | |
310 | */ | |
311 | struct exynos_tmu_init_data { | |
312 | int tmu_count; | |
313 | struct exynos_tmu_platform_data tmu_data[]; | |
314 | }; | |
315 | ||
0c1836a6 | 316 | #endif /* _EXYNOS_TMU_H */ |