[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_dw.c

/*
 * Synopsys DesignWare 8250 driver.
 *
 * Copyright 2011 Picochip, Jamie Iles.
 * Copyright 2013 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
 * LCR is written whilst busy.  If it is, then a busy detect interrupt is
 * raised, the LCR needs to be rewritten and the uart status register read.
 */
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/serial_8250.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>

#include <asm/byteorder.h>

#include "8250.h"

/* Offsets for the DesignWare specific registers */
#define DW_UART_USR	0x1f /* UART Status Register */
#define DW_UART_CPR	0xf4 /* Component Parameter Register */
#define DW_UART_UCV	0xf8 /* UART Component Version */

/* Component Parameter Register bits */
#define DW_UART_CPR_ABP_DATA_WIDTH	(3 << 0)
#define DW_UART_CPR_AFCE_MODE		(1 << 4)
#define DW_UART_CPR_THRE_MODE		(1 << 5)
#define DW_UART_CPR_SIR_MODE		(1 << 6)
#define DW_UART_CPR_SIR_LP_MODE		(1 << 7)
#define DW_UART_CPR_ADDITIONAL_FEATURES	(1 << 8)
#define DW_UART_CPR_FIFO_ACCESS		(1 << 9)
#define DW_UART_CPR_FIFO_STAT		(1 << 10)
#define DW_UART_CPR_SHADOW		(1 << 11)
#define DW_UART_CPR_ENCODED_PARMS	(1 << 12)
#define DW_UART_CPR_DMA_EXTRA		(1 << 13)
#define DW_UART_CPR_FIFO_MODE		(0xff << 16)
/* Helper for fifo size calculation */
#define DW_UART_CPR_FIFO_SIZE(a)	(((a >> 16) & 0xff) * 16)


struct dw8250_data {
	u8			usr_reg;
	int			last_mcr;
	int			line;
	struct clk		*clk;
	struct uart_8250_dma	dma;
};

static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
{
	struct dw8250_data *d = p->private_data;

	/* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
	if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
		value |= UART_MSR_CTS;
		value &= ~UART_MSR_DCTS;
	}

	return value;
}

static void dw8250_force_idle(struct uart_port *p)
{
	serial8250_clear_and_reinit_fifos(container_of
					  (p, struct uart_8250_port, port));
	(void)p->serial_in(p, UART_RX);
}

static void dw8250_serial_out(struct uart_port *p, int offset, int value)
{
	struct dw8250_data *d = p->private_data;

	if (offset == UART_MCR)
		d->last_mcr = value;

	writeb(value, p->membase + (offset << p->regshift));

	/* Make sure LCR write wasn't ignored */
	if (offset == UART_LCR) {
		int tries = 1000;
		while (tries--) {
			if (value == p->serial_in(p, UART_LCR))
				return;
			dw8250_force_idle(p);
			writeb(value, p->membase + (UART_LCR << p->regshift));
		}
		dev_err(p->dev, "Couldn't set LCR to %d\n", value);
	}
}

static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
{
	unsigned int value = readb(p->membase + (offset << p->regshift));

	return dw8250_modify_msr(p, offset, value);
}

/* Read Back (rb) version to ensure register access ording. */
static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
{
	dw8250_serial_out(p, offset, value);
	dw8250_serial_in(p, UART_LCR);
}

static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
{
	struct dw8250_data *d = p->private_data;

	if (offset == UART_MCR)
		d->last_mcr = value;

	writel(value, p->membase + (offset << p->regshift));

	/* Make sure LCR write wasn't ignored */
	if (offset == UART_LCR) {
		int tries = 1000;
		while (tries--) {
			if (value == p->serial_in(p, UART_LCR))
				return;
			dw8250_force_idle(p);
			writel(value, p->membase + (UART_LCR << p->regshift));
		}
		dev_err(p->dev, "Couldn't set LCR to %d\n", value);
	}
}

static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
{
	unsigned int value = readl(p->membase + (offset << p->regshift));

	return dw8250_modify_msr(p, offset, value);
}

static int dw8250_handle_irq(struct uart_port *p)
{
	struct dw8250_data *d = p->private_data;
	unsigned int iir = p->serial_in(p, UART_IIR);

	if (serial8250_handle_irq(p, iir)) {
		return 1;
	} else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
		/* Clear the USR */
		(void)p->serial_in(p, d->usr_reg);

		return 1;
	}

	return 0;
}

static void
dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
{
	if (!state)
		pm_runtime_get_sync(port->dev);

	serial8250_do_pm(port, state, old);

	if (state)
		pm_runtime_put_sync_suspend(port->dev);
}

static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
{
	struct dw8250_data *data = param;

	return chan->chan_id == data->dma.tx_chan_id ||
	       chan->chan_id == data->dma.rx_chan_id;
}

static void dw8250_setup_port(struct uart_8250_port *up)
{
	struct uart_port	*p = &up->port;
	u32			reg = readl(p->membase + DW_UART_UCV);

	/*
	 * If the Component Version Register returns zero, we know that
	 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
	 */
	if (!reg)
		return;

	dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
		(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);

	reg = readl(p->membase + DW_UART_CPR);
	if (!reg)
		return;

	/* Select the type based on fifo */
	if (reg & DW_UART_CPR_FIFO_MODE) {
		p->type = PORT_16550A;
		p->flags |= UPF_FIXED_TYPE;
		p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
		up->tx_loadsz = p->fifosize;
		up->capabilities = UART_CAP_FIFO;
	}

	if (reg & DW_UART_CPR_AFCE_MODE)
		up->capabilities |= UART_CAP_AFE;
}

static int dw8250_probe_of(struct uart_port *p,
			   struct dw8250_data *data)
{
	struct device_node	*np = p->dev->of_node;
	u32			val;
	bool has_ucv = true;

	if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
#ifdef __BIG_ENDIAN
		/*
		 * Low order bits of these 64-bit registers, when
		 * accessed as a byte, are 7 bytes further down in the
		 * address space in big endian mode.
		 */
		p->membase += 7;
#endif
		p->serial_out = dw8250_serial_out_rb;
		p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
		p->type = PORT_OCTEON;
		data->usr_reg = 0x27;
		has_ucv = false;
	} else if (!of_property_read_u32(np, "reg-io-width", &val)) {
		switch (val) {
		case 1:
			break;
		case 4:
			p->iotype = UPIO_MEM32;
			p->serial_in = dw8250_serial_in32;
			p->serial_out = dw8250_serial_out32;
			break;
		default:
			dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
			return -EINVAL;
		}
	}
	if (has_ucv)
		dw8250_setup_port(container_of(p, struct uart_8250_port, port));

	if (!of_property_read_u32(np, "reg-shift", &val))
		p->regshift = val;

	/* clock got configured through clk api, all done */
	if (p->uartclk)
		return 0;

	/* try to find out clock frequency from DT as fallback */
	if (of_property_read_u32(np, "clock-frequency", &val)) {
		dev_err(p->dev, "clk or clock-frequency not defined\n");
		return -EINVAL;
	}
	p->uartclk = val;

	return 0;
}

#ifdef CONFIG_ACPI
static int dw8250_probe_acpi(struct uart_8250_port *up,
			     struct dw8250_data *data)
{
	const struct acpi_device_id *id;
	struct uart_port *p = &up->port;

	dw8250_setup_port(up);

	id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
	if (!id)
		return -ENODEV;

	p->iotype = UPIO_MEM32;
	p->serial_in = dw8250_serial_in32;
	p->serial_out = dw8250_serial_out32;
	p->regshift = 2;

	if (!p->uartclk)
		p->uartclk = (unsigned int)id->driver_data;

	up->dma = &data->dma;

	up->dma->rxconf.src_maxburst = p->fifosize / 4;
	up->dma->txconf.dst_maxburst = p->fifosize / 4;

	return 0;
}
#else
static inline int dw8250_probe_acpi(struct uart_8250_port *up,
				    struct dw8250_data *data)
{
	return -ENODEV;
}
#endif /* CONFIG_ACPI */

static int dw8250_probe(struct platform_device *pdev)
{
	struct uart_8250_port uart = {};
	struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	struct dw8250_data *data;
	int err;

	if (!regs || !irq) {
		dev_err(&pdev->dev, "no registers/irq defined\n");
		return -EINVAL;
	}

	spin_lock_init(&uart.port.lock);
	uart.port.mapbase = regs->start;
	uart.port.irq = irq->start;
	uart.port.handle_irq = dw8250_handle_irq;
	uart.port.pm = dw8250_do_pm;
	uart.port.type = PORT_8250;
	uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
	uart.port.dev = &pdev->dev;

	uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
					 resource_size(regs));
	if (!uart.port.membase)
		return -ENOMEM;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->usr_reg = DW_UART_USR;
	data->clk = devm_clk_get(&pdev->dev, NULL);
	if (!IS_ERR(data->clk)) {
		clk_prepare_enable(data->clk);
		uart.port.uartclk = clk_get_rate(data->clk);
	}

	data->dma.rx_chan_id = -1;
	data->dma.tx_chan_id = -1;
	data->dma.rx_param = data;
	data->dma.tx_param = data;
	data->dma.fn = dw8250_dma_filter;

	uart.port.iotype = UPIO_MEM;
	uart.port.serial_in = dw8250_serial_in;
	uart.port.serial_out = dw8250_serial_out;
	uart.port.private_data = data;

	if (pdev->dev.of_node) {
		err = dw8250_probe_of(&uart.port, data);
		if (err)
			return err;
	} else if (ACPI_HANDLE(&pdev->dev)) {
		err = dw8250_probe_acpi(&uart, data);
		if (err)
			return err;
	} else {
		return -ENODEV;
	}

	data->line = serial8250_register_8250_port(&uart);
	if (data->line < 0)
		return data->line;

	platform_set_drvdata(pdev, data);

	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

	return 0;
}

static int dw8250_remove(struct platform_device *pdev)
{
	struct dw8250_data *data = platform_get_drvdata(pdev);

	pm_runtime_get_sync(&pdev->dev);

	serial8250_unregister_port(data->line);

	if (!IS_ERR(data->clk))
		clk_disable_unprepare(data->clk);

	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM
static int dw8250_suspend(struct device *dev)
{
	struct dw8250_data *data = dev_get_drvdata(dev);

	serial8250_suspend_port(data->line);

	return 0;
}

static int dw8250_resume(struct device *dev)
{
	struct dw8250_data *data = dev_get_drvdata(dev);

	serial8250_resume_port(data->line);

	return 0;
}
#endif /* CONFIG_PM */

#ifdef CONFIG_PM_RUNTIME
static int dw8250_runtime_suspend(struct device *dev)
{
	struct dw8250_data *data = dev_get_drvdata(dev);

	if (!IS_ERR(data->clk))
		clk_disable_unprepare(data->clk);

	return 0;
}

static int dw8250_runtime_resume(struct device *dev)
{
	struct dw8250_data *data = dev_get_drvdata(dev);

	if (!IS_ERR(data->clk))
		clk_prepare_enable(data->clk);

	return 0;
}
#endif

static const struct dev_pm_ops dw8250_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
	SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
};

static const struct of_device_id dw8250_of_match[] = {
	{ .compatible = "snps,dw-apb-uart" },
	{ .compatible = "cavium,octeon-3860-uart" },
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw8250_of_match);

static const struct acpi_device_id dw8250_acpi_match[] = {
	{ "INT33C4", 0 },
	{ "INT33C5", 0 },
	{ "80860F0A", 0 },
	{ },
};
MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);

static struct platform_driver dw8250_platform_driver = {
	.driver = {
		.name		= "dw-apb-uart",
		.owner		= THIS_MODULE,
		.pm		= &dw8250_pm_ops,
		.of_match_table	= dw8250_of_match,
		.acpi_match_table = ACPI_PTR(dw8250_acpi_match),
	},
	.probe			= dw8250_probe,
	.remove			= dw8250_remove,
};

module_platform_driver(dw8250_platform_driver);

MODULE_AUTHOR("Jamie Iles");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
Commit	Line	Data
7d4008eb JI	1	/*
	2	* Synopsys DesignWare 8250 driver.
	3	*
	4	* Copyright 2011 Picochip, Jamie Iles.
6a7320c4	5	* Copyright 2013 Intel Corporation
7d4008eb JI	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
	13	* LCR is written whilst busy. If it is, then a busy detect interrupt is
	14	* raised, the LCR needs to be rewritten and the uart status register read.
	15	*/
	16	#include <linux/device.h>
	17	#include <linux/init.h>
	18	#include <linux/io.h>
	19	#include <linux/module.h>
	20	#include <linux/serial_8250.h>
	21	#include <linux/serial_core.h>
	22	#include <linux/serial_reg.h>
	23	#include <linux/of.h>
	24	#include <linux/of_irq.h>
	25	#include <linux/of_platform.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/slab.h>
6a7320c4	28	#include <linux/acpi.h>
e302cd93	29	#include <linux/clk.h>
ffc3ae6d	30	#include <linux/pm_runtime.h>
7d4008eb	31
d5f1af7e DD	32	#include <asm/byteorder.h>
d5f1af7e DD	33
7277b2a1 HK	34	#include "8250.h"
7277b2a1 HK	35
30046df2 HK	36	/* Offsets for the DesignWare specific registers */
	37	#define DW_UART_USR 0x1f /* UART Status Register */
	38	#define DW_UART_CPR 0xf4 /* Component Parameter Register */
	39	#define DW_UART_UCV 0xf8 /* UART Component Version */
	40
	41	/* Component Parameter Register bits */
	42	#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
	43	#define DW_UART_CPR_AFCE_MODE (1 << 4)
	44	#define DW_UART_CPR_THRE_MODE (1 << 5)
	45	#define DW_UART_CPR_SIR_MODE (1 << 6)
	46	#define DW_UART_CPR_SIR_LP_MODE (1 << 7)
	47	#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
	48	#define DW_UART_CPR_FIFO_ACCESS (1 << 9)
	49	#define DW_UART_CPR_FIFO_STAT (1 << 10)
	50	#define DW_UART_CPR_SHADOW (1 << 11)
	51	#define DW_UART_CPR_ENCODED_PARMS (1 << 12)
	52	#define DW_UART_CPR_DMA_EXTRA (1 << 13)
	53	#define DW_UART_CPR_FIFO_MODE (0xff << 16)
	54	/* Helper for fifo size calculation */
	55	#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
	56
	57
7d4008eb	58	struct dw8250_data {
fe958555	59	u8 usr_reg;
fe958555 HK	60	int last_mcr;
	61	int line;
	62	struct clk *clk;
	63	struct uart_8250_dma dma;
7d4008eb JI	64	};
7d4008eb JI	65
33acbb82 TK	66	static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
	67	{
	68	struct dw8250_data *d = p->private_data;
	69
	70	/* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
	71	if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
	72	value \|= UART_MSR_CTS;
	73	value &= ~UART_MSR_DCTS;
	74	}
	75
	76	return value;
	77	}
	78
c49436b6 TK	79	static void dw8250_force_idle(struct uart_port *p)
	80	{
	81	serial8250_clear_and_reinit_fifos(container_of
	82	(p, struct uart_8250_port, port));
	83	(void)p->serial_in(p, UART_RX);
	84	}
	85
7d4008eb JI	86	static void dw8250_serial_out(struct uart_port *p, int offset, int value)
	87	{
	88	struct dw8250_data *d = p->private_data;
	89
33acbb82 TK	90	if (offset == UART_MCR)
	91	d->last_mcr = value;
	92
	93	writeb(value, p->membase + (offset << p->regshift));
c49436b6 TK	94
	95	/* Make sure LCR write wasn't ignored */
	96	if (offset == UART_LCR) {
	97	int tries = 1000;
	98	while (tries--) {
	99	if (value == p->serial_in(p, UART_LCR))
	100	return;
	101	dw8250_force_idle(p);
	102	writeb(value, p->membase + (UART_LCR << p->regshift));
	103	}
	104	dev_err(p->dev, "Couldn't set LCR to %d\n", value);
	105	}
7d4008eb JI	106	}
	107
	108	static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
	109	{
33acbb82	110	unsigned int value = readb(p->membase + (offset << p->regshift));
7d4008eb	111
33acbb82	112	return dw8250_modify_msr(p, offset, value);
7d4008eb JI	113	}
7d4008eb JI	114
d5f1af7e DD	115	/* Read Back (rb) version to ensure register access ording. */
	116	static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
	117	{
	118	dw8250_serial_out(p, offset, value);
	119	dw8250_serial_in(p, UART_LCR);
	120	}
	121
7d4008eb JI	122	static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
	123	{
	124	struct dw8250_data *d = p->private_data;
	125
33acbb82 TK	126	if (offset == UART_MCR)
	127	d->last_mcr = value;
	128
	129	writel(value, p->membase + (offset << p->regshift));
c49436b6 TK	130
	131	/* Make sure LCR write wasn't ignored */
	132	if (offset == UART_LCR) {
	133	int tries = 1000;
	134	while (tries--) {
	135	if (value == p->serial_in(p, UART_LCR))
	136	return;
	137	dw8250_force_idle(p);
	138	writel(value, p->membase + (UART_LCR << p->regshift));
	139	}
	140	dev_err(p->dev, "Couldn't set LCR to %d\n", value);
	141	}
7d4008eb JI	142	}
	143
	144	static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
	145	{
33acbb82	146	unsigned int value = readl(p->membase + (offset << p->regshift));
7d4008eb	147
33acbb82	148	return dw8250_modify_msr(p, offset, value);
7d4008eb JI	149	}
7d4008eb JI	150
7d4008eb JI	151	static int dw8250_handle_irq(struct uart_port *p)
	152	{
	153	struct dw8250_data *d = p->private_data;
	154	unsigned int iir = p->serial_in(p, UART_IIR);
	155
	156	if (serial8250_handle_irq(p, iir)) {
	157	return 1;
	158	} else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
c49436b6	159	/* Clear the USR */
d5f1af7e	160	(void)p->serial_in(p, d->usr_reg);
7d4008eb JI	161
	162	return 1;
	163	}
	164
	165	return 0;
	166	}
	167
ffc3ae6d HK	168	static void
	169	dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
	170	{
	171	if (!state)
	172	pm_runtime_get_sync(port->dev);
	173
	174	serial8250_do_pm(port, state, old);
	175
	176	if (state)
	177	pm_runtime_put_sync_suspend(port->dev);
	178	}
	179
7fb8c56c HK	180	static bool dw8250_dma_filter(struct dma_chan chan, void param)
	181	{
	182	struct dw8250_data *data = param;
	183
	184	return chan->chan_id == data->dma.tx_chan_id \|\|
	185	chan->chan_id == data->dma.rx_chan_id;
	186	}
	187
d5f1af7e DD	188	static void dw8250_setup_port(struct uart_8250_port *up)
	189	{
	190	struct uart_port *p = &up->port;
	191	u32 reg = readl(p->membase + DW_UART_UCV);
	192
	193	/*
	194	* If the Component Version Register returns zero, we know that
	195	* ADDITIONAL_FEATURES are not enabled. No need to go any further.
	196	*/
	197	if (!reg)
	198	return;
	199
	200	dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
	201	(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
	202
	203	reg = readl(p->membase + DW_UART_CPR);
	204	if (!reg)
	205	return;
	206
	207	/* Select the type based on fifo */
	208	if (reg & DW_UART_CPR_FIFO_MODE) {
	209	p->type = PORT_16550A;
	210	p->flags \|= UPF_FIXED_TYPE;
	211	p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
	212	up->tx_loadsz = p->fifosize;
	213	up->capabilities = UART_CAP_FIFO;
	214	}
	215
	216	if (reg & DW_UART_CPR_AFCE_MODE)
	217	up->capabilities \|= UART_CAP_AFE;
	218	}
	219
	220	static int dw8250_probe_of(struct uart_port *p,
	221	struct dw8250_data *data)
a7260c8c HK	222	{
	223	struct device_node *np = p->dev->of_node;
	224	u32 val;
d5f1af7e DD	225	bool has_ucv = true;
	226
	227	if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
	228	#ifdef __BIG_ENDIAN
	229	/*
	230	* Low order bits of these 64-bit registers, when
	231	* accessed as a byte, are 7 bytes further down in the
	232	* address space in big endian mode.
	233	*/
	234	p->membase += 7;
	235	#endif
	236	p->serial_out = dw8250_serial_out_rb;
	237	p->flags = ASYNC_SKIP_TEST \| UPF_SHARE_IRQ \| UPF_FIXED_TYPE;
	238	p->type = PORT_OCTEON;
	239	data->usr_reg = 0x27;
	240	has_ucv = false;
	241	} else if (!of_property_read_u32(np, "reg-io-width", &val)) {
a7260c8c HK	242	switch (val) {
	243	case 1:
	244	break;
	245	case 4:
	246	p->iotype = UPIO_MEM32;
	247	p->serial_in = dw8250_serial_in32;
	248	p->serial_out = dw8250_serial_out32;
	249	break;
	250	default:
	251	dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
	252	return -EINVAL;
	253	}
	254	}
d5f1af7e DD	255	if (has_ucv)
d5f1af7e DD	256	dw8250_setup_port(container_of(p, struct uart_8250_port, port));
a7260c8c HK	257
	258	if (!of_property_read_u32(np, "reg-shift", &val))
	259	p->regshift = val;
	260
e302cd93 EL	261	/* clock got configured through clk api, all done */
	262	if (p->uartclk)
	263	return 0;
	264
	265	/* try to find out clock frequency from DT as fallback */
a7260c8c	266	if (of_property_read_u32(np, "clock-frequency", &val)) {
e302cd93	267	dev_err(p->dev, "clk or clock-frequency not defined\n");
a7260c8c HK	268	return -EINVAL;
	269	}
	270	p->uartclk = val;
	271
	272	return 0;
	273	}
	274
053fac36	275	#ifdef CONFIG_ACPI
fe958555 HK	276	static int dw8250_probe_acpi(struct uart_8250_port *up,
fe958555 HK	277	struct dw8250_data *data)
6a7320c4 HK	278	{
6a7320c4 HK	279	const struct acpi_device_id *id;
94b2b47c	280	struct uart_port *p = &up->port;
6a7320c4	281
d5f1af7e DD	282	dw8250_setup_port(up);
d5f1af7e DD	283
6a7320c4 HK	284	id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
	285	if (!id)
	286	return -ENODEV;
	287
	288	p->iotype = UPIO_MEM32;
	289	p->serial_in = dw8250_serial_in32;
	290	p->serial_out = dw8250_serial_out32;
	291	p->regshift = 2;
aea02e87 HK	292
	293	if (!p->uartclk)
	294	p->uartclk = (unsigned int)id->driver_data;
6a7320c4	295
fe958555	296	up->dma = &data->dma;
94b2b47c HK	297
	298	up->dma->rxconf.src_maxburst = p->fifosize / 4;
	299	up->dma->txconf.dst_maxburst = p->fifosize / 4;
7277b2a1	300
6a7320c4 HK	301	return 0;
6a7320c4 HK	302	}
053fac36	303	#else
05855573 HK	304	static inline int dw8250_probe_acpi(struct uart_8250_port *up,
05855573 HK	305	struct dw8250_data *data)
053fac36 HK	306	{
	307	return -ENODEV;
	308	}
	309	#endif /* CONFIG_ACPI */
6a7320c4	310
9671f099	311	static int dw8250_probe(struct platform_device *pdev)
7d4008eb	312	{
2655a2c7	313	struct uart_8250_port uart = {};
7d4008eb JI	314	struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7d4008eb JI	315	struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
7d4008eb	316	struct dw8250_data *data;
a7260c8c	317	int err;
7d4008eb JI	318
	319	if (!regs \|\| !irq) {
	320	dev_err(&pdev->dev, "no registers/irq defined\n");
	321	return -EINVAL;
	322	}
	323
2655a2c7 AC	324	spin_lock_init(&uart.port.lock);
	325	uart.port.mapbase = regs->start;
	326	uart.port.irq = irq->start;
	327	uart.port.handle_irq = dw8250_handle_irq;
ffc3ae6d	328	uart.port.pm = dw8250_do_pm;
2655a2c7	329	uart.port.type = PORT_8250;
f93366ff	330	uart.port.flags = UPF_SHARE_IRQ \| UPF_BOOT_AUTOCONF \| UPF_FIXED_PORT;
2655a2c7	331	uart.port.dev = &pdev->dev;
7d4008eb	332
b88d0826 HK	333	uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
b88d0826 HK	334	resource_size(regs));
f93366ff HK	335	if (!uart.port.membase)
	336	return -ENOMEM;
	337
e302cd93 EL	338	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	339	if (!data)
	340	return -ENOMEM;
	341
d5f1af7e	342	data->usr_reg = DW_UART_USR;
e302cd93 EL	343	data->clk = devm_clk_get(&pdev->dev, NULL);
	344	if (!IS_ERR(data->clk)) {
	345	clk_prepare_enable(data->clk);
	346	uart.port.uartclk = clk_get_rate(data->clk);
	347	}
	348
7fb8c56c HK	349	data->dma.rx_chan_id = -1;
	350	data->dma.tx_chan_id = -1;
	351	data->dma.rx_param = data;
	352	data->dma.tx_param = data;
	353	data->dma.fn = dw8250_dma_filter;
	354
2655a2c7 AC	355	uart.port.iotype = UPIO_MEM;
	356	uart.port.serial_in = dw8250_serial_in;
	357	uart.port.serial_out = dw8250_serial_out;
e302cd93	358	uart.port.private_data = data;
a7260c8c HK	359
a7260c8c HK	360	if (pdev->dev.of_node) {
d5f1af7e	361	err = dw8250_probe_of(&uart.port, data);
a7260c8c HK	362	if (err)
a7260c8c HK	363	return err;
6a7320c4	364	} else if (ACPI_HANDLE(&pdev->dev)) {
fe958555	365	err = dw8250_probe_acpi(&uart, data);
6a7320c4 HK	366	if (err)
6a7320c4 HK	367	return err;
a7260c8c HK	368	} else {
a7260c8c HK	369	return -ENODEV;
7d4008eb JI	370	}
7d4008eb JI	371
2655a2c7	372	data->line = serial8250_register_8250_port(&uart);
7d4008eb JI	373	if (data->line < 0)
	374	return data->line;
	375
	376	platform_set_drvdata(pdev, data);
	377
ffc3ae6d HK	378	pm_runtime_set_active(&pdev->dev);
	379	pm_runtime_enable(&pdev->dev);
	380
7d4008eb JI	381	return 0;
	382	}
	383
ae8d8a14	384	static int dw8250_remove(struct platform_device *pdev)
7d4008eb JI	385	{
	386	struct dw8250_data *data = platform_get_drvdata(pdev);
	387
ffc3ae6d HK	388	pm_runtime_get_sync(&pdev->dev);
ffc3ae6d HK	389
7d4008eb JI	390	serial8250_unregister_port(data->line);
7d4008eb JI	391
e302cd93 EL	392	if (!IS_ERR(data->clk))
	393	clk_disable_unprepare(data->clk);
	394
ffc3ae6d HK	395	pm_runtime_disable(&pdev->dev);
	396	pm_runtime_put_noidle(&pdev->dev);
	397
7d4008eb JI	398	return 0;
	399	}
	400
b61c5ed5	401	#ifdef CONFIG_PM
ffc3ae6d	402	static int dw8250_suspend(struct device *dev)
b61c5ed5	403	{
ffc3ae6d	404	struct dw8250_data *data = dev_get_drvdata(dev);
b61c5ed5 JH	405
	406	serial8250_suspend_port(data->line);
	407
	408	return 0;
	409	}
	410
ffc3ae6d	411	static int dw8250_resume(struct device *dev)
b61c5ed5	412	{
ffc3ae6d	413	struct dw8250_data *data = dev_get_drvdata(dev);
b61c5ed5 JH	414
	415	serial8250_resume_port(data->line);
	416
	417	return 0;
	418	}
b61c5ed5 JH	419	#endif /* CONFIG_PM */
b61c5ed5 JH	420
ffc3ae6d HK	421	#ifdef CONFIG_PM_RUNTIME
	422	static int dw8250_runtime_suspend(struct device *dev)
	423	{
	424	struct dw8250_data *data = dev_get_drvdata(dev);
	425
dbd2df85 EG	426	if (!IS_ERR(data->clk))
dbd2df85 EG	427	clk_disable_unprepare(data->clk);
ffc3ae6d HK	428
	429	return 0;
	430	}
	431
	432	static int dw8250_runtime_resume(struct device *dev)
	433	{
	434	struct dw8250_data *data = dev_get_drvdata(dev);
	435
dbd2df85 EG	436	if (!IS_ERR(data->clk))
dbd2df85 EG	437	clk_prepare_enable(data->clk);
ffc3ae6d HK	438
	439	return 0;
	440	}
	441	#endif
	442
	443	static const struct dev_pm_ops dw8250_pm_ops = {
	444	SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
	445	SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
	446	};
	447
a7260c8c	448	static const struct of_device_id dw8250_of_match[] = {
7d4008eb	449	{ .compatible = "snps,dw-apb-uart" },
d5f1af7e	450	{ .compatible = "cavium,octeon-3860-uart" },
7d4008eb JI	451	{ /* Sentinel */ }
7d4008eb JI	452	};
a7260c8c	453	MODULE_DEVICE_TABLE(of, dw8250_of_match);
7d4008eb	454
6a7320c4	455	static const struct acpi_device_id dw8250_acpi_match[] = {
aea02e87 HK	456	{ "INT33C4", 0 },
aea02e87 HK	457	{ "INT33C5", 0 },
9d83e180	458	{ "80860F0A", 0 },
6a7320c4 HK	459	{ },
	460	};
	461	MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
	462
7d4008eb JI	463	static struct platform_driver dw8250_platform_driver = {
	464	.driver = {
	465	.name = "dw-apb-uart",
	466	.owner = THIS_MODULE,
ffc3ae6d	467	.pm = &dw8250_pm_ops,
a7260c8c	468	.of_match_table = dw8250_of_match,
6a7320c4	469	.acpi_match_table = ACPI_PTR(dw8250_acpi_match),
7d4008eb JI	470	},
7d4008eb JI	471	.probe = dw8250_probe,
2d47b716	472	.remove = dw8250_remove,
7d4008eb JI	473	};
7d4008eb JI	474
c8381c15	475	module_platform_driver(dw8250_platform_driver);
7d4008eb JI	476
	477	MODULE_AUTHOR("Jamie Iles");
	478	MODULE_LICENSE("GPL");
	479	MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");