projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tty: xuartps: Update copyright information
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4
LT		 13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
1da177e4
LT		 16#include <linux/string.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/delay.h>
20#include <linux/tty.h>
0ad372b9 21#include <linux/serial_reg.h>
1da177e4
LT		 22#include <linux/serial_core.h>
23#include <linux/8250_pci.h>
24#include <linux/bitops.h>
25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
29#include "8250.h"
30
1da177e4
LT		 31/*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
5bf8f501 42 int (*probe)(struct pci_dev *dev);
1da177e4 43 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 44 int (*setup)(struct serial_private *,
45 const struct pciserial_board *,
2655a2c7 46 struct uart_8250_port *, int);
1da177e4
LT		 47 void (*exit)(struct pci_dev *dev);
48};
49
50#define PCI_NUM_BAR_RESOURCES 6
51
52struct serial_private {
70db3d91 53 struct pci_dev *dev;
1da177e4
LT		 54 unsigned int nr;
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
57 int line[0];
58};
59
7808edcd 60static int pci_default_setup(struct serial_private*,
2655a2c7 61 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 62
1da177e4
LT		 63static void moan_device(const char *str, struct pci_dev *dev)
64{
af8c5b8d 65 dev_err(&dev->dev,
ad361c98
JP		 66 "%s: %s\n"
67 "Please send the output of lspci -vv, this\n"
68 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69 "manufacturer and name of serial board or\n"
70 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 71 pci_name(dev), str, dev->vendor, dev->device,
72 dev->subsystem_vendor, dev->subsystem_device);
73}
74
75static int
2655a2c7 76setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 77 int bar, int offset, int regshift)
78{
70db3d91 79 struct pci_dev *dev = priv->dev;
1da177e4
LT		 80 unsigned long base, len;
81
82 if (bar >= PCI_NUM_BAR_RESOURCES)
83 return -EINVAL;
84
72ce9a83
RK		 85 base = pci_resource_start(dev, bar);
86
1da177e4 87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 88 len = pci_resource_len(dev, bar);
89
90 if (!priv->remapped_bar[bar])
6f441fe9 91 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 92 if (!priv->remapped_bar[bar])
93 return -ENOMEM;
94
2655a2c7
AC		 95 port->port.iotype = UPIO_MEM;
96 port->port.iobase = 0;
97 port->port.mapbase = base + offset;
98 port->port.membase = priv->remapped_bar[bar] + offset;
99 port->port.regshift = regshift;
1da177e4 100 } else {
2655a2c7
AC		 101 port->port.iotype = UPIO_PORT;
102 port->port.iobase = base + offset;
103 port->port.mapbase = 0;
104 port->port.membase = NULL;
105 port->port.regshift = 0;
1da177e4
LT		 106 }
107 return 0;
108}
109
02c9b5cf
KJ		 110/*
111 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 */
113static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 114 const struct pciserial_board *board,
2655a2c7 115 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 116{
117 unsigned int bar = 0, offset = board->first_offset;
118 bar = FL_GET_BASE(board->flags);
119
120 if (idx < 2) {
121 offset += idx * board->uart_offset;
122 } else if ((idx >= 2) && (idx < 4)) {
123 bar += 1;
124 offset += ((idx - 2) * board->uart_offset);
125 } else if ((idx >= 4) && (idx < 6)) {
126 bar += 2;
127 offset += ((idx - 4) * board->uart_offset);
128 } else if (idx >= 6) {
129 bar += 3;
130 offset += ((idx - 6) * board->uart_offset);
131 }
132
133 return setup_port(priv, port, bar, offset, board->reg_shift);
134}
135
1da177e4
LT		 136/*
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
139 */
140static int
975a1a7d 141afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 142 struct uart_8250_port *port, int idx)
1da177e4
LT		 143{
144 unsigned int bar, offset = board->first_offset;
5756ee99 145
1da177e4
LT		 146 bar = FL_GET_BASE(board->flags);
147 if (idx < 4)
148 bar += idx;
149 else {
150 bar = 4;
151 offset += (idx - 4) * board->uart_offset;
152 }
153
70db3d91 154 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 155}
156
157/*
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
163 */
61a116ef 164static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 165{
166 int rc = 0;
167
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 rc = 3;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 rc = 2;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 rc = 4;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 182 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 183 rc = 1;
184 break;
185 }
186
187 return rc;
188}
189
190/*
191 * HP's Diva chip puts the 4th/5th serial port further out, and
192 * some serial ports are supposed to be hidden on certain models.
193 */
194static int
975a1a7d
RK		 195pci_hp_diva_setup(struct serial_private *priv,
196 const struct pciserial_board *board,
2655a2c7 197 struct uart_8250_port *port, int idx)
1da177e4
LT		 198{
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
70db3d91 202 switch (priv->dev->subsystem_device) {
1da177e4
LT		 203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
70db3d91 219 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 220}
221
222/*
223 * Added for EKF Intel i960 serial boards
224 */
61a116ef 225static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 226{
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
5756ee99
AC		 233 pci_read_config_dword(dev, 0x44, (void *)&oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 235 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 236 return -ENODEV;
237 }
238 return 0;
239}
240
241/*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
61a116ef 247static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 248{
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
add7b58e 258 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 259 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 260 irq_config = 0x43;
5756ee99 261
1da177e4 262 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 263 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 264 /*
265 * As the megawolf cards have the int pins active
266 * high, and have 2 UART chips, both ints must be
267 * enabled on the 9050. Also, the UARTS are set in
268 * 16450 mode by default, so we have to enable the
269 * 16C950 'enhanced' mode so that we can use the
270 * deep FIFOs
271 */
272 irq_config = 0x5b;
1da177e4
LT		 273 /*
274 * enable/disable interrupts
275 */
6f441fe9 276 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288}
289
ae8d8a14 290static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 291{
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
6f441fe9 300 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310}
311
04bf7e74
WP		 312#define NI8420_INT_ENABLE_REG 0x38
313#define NI8420_INT_ENABLE_BIT 0x2000
314
ae8d8a14 315static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 316{
317 void __iomem *p;
318 unsigned long base, len;
319 unsigned int bar = 0;
320
321 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322 moan_device("no memory in bar", dev);
323 return;
324 }
325
326 base = pci_resource_start(dev, bar);
327 len = pci_resource_len(dev, bar);
328 p = ioremap_nocache(base, len);
329 if (p == NULL)
330 return;
331
332 /* Disable the CPU Interrupt */
333 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334 p + NI8420_INT_ENABLE_REG);
335 iounmap(p);
336}
337
338
46a0fac9
SB		 339/* MITE registers */
340#define MITE_IOWBSR1 0xc4
341#define MITE_IOWCR1 0xf4
342#define MITE_LCIMR1 0x08
343#define MITE_LCIMR2 0x10
344
345#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346
ae8d8a14 347static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 348{
349 void __iomem *p;
350 unsigned long base, len;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 base = pci_resource_start(dev, bar);
359 len = pci_resource_len(dev, bar);
360 p = ioremap_nocache(base, len);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367}
368
1da177e4
LT		 369/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370static int
975a1a7d 371sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 372 struct uart_8250_port *port, int idx)
1da177e4
LT		 373{
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
70db3d91 387 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 388}
389
390/*
391* This does initialization for PMC OCTALPRO cards:
392* maps the device memory, resets the UARTs (needed, bc
393* if the module is removed and inserted again, the card
394* is in the sleep mode) and enables global interrupt.
395*/
396
397/* global control register offset for SBS PMC-OctalPro */
398#define OCT_REG_CR_OFF 0x500
399
61a116ef 400static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 401{
402 u8 __iomem *p;
403
24ed3aba 404 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 409 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 410 udelay(50);
5756ee99 411 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418}
419
420/*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
ae8d8a14 424static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 425{
426 u8 __iomem *p;
427
24ed3aba 428 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
1da177e4 431 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 432 iounmap(p);
433}
434
435/*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
25985edc 438 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 447 *
1da177e4
LT		 448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
67d74b87
RK		 453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
fbc0dc0d
AP		 456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
1da177e4
LT		 459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465static int pci_siig10x_init(struct pci_dev *dev)
466{
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
6f441fe9 482 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490}
491
492#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495static int pci_siig20x_init(struct pci_dev *dev)
496{
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510}
511
67d74b87
RK		 512static int pci_siig_init(struct pci_dev *dev)
513{
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523}
524
3ec9c594 525static int pci_siig_setup(struct serial_private *priv,
975a1a7d 526 const struct pciserial_board *board,
2655a2c7 527 struct uart_8250_port *port, int idx)
3ec9c594
AP		 528{
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537}
538
1da177e4
LT		 539/*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
e9422e09 544static const unsigned short timedia_single_port[] = {
1da177e4
LT		 545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546};
547
e9422e09 548static const unsigned short timedia_dual_port[] = {
1da177e4 549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554};
555
e9422e09 556static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561};
562
e9422e09 563static const unsigned short timedia_eight_port[] = {
5756ee99 564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566};
567
cb3592be 568static const struct timedia_struct {
1da177e4 569 int num;
e9422e09 570 const unsigned short *ids;
1da177e4
LT		 571} timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
e9422e09 575 { 8, timedia_eight_port }
1da177e4
LT		 576};
577
b9b24558
FB		 578/*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584static int pci_timedia_probe(struct pci_dev *dev)
585{
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598}
599
61a116ef 600static int pci_timedia_init(struct pci_dev *dev)
1da177e4 601{
e9422e09 602 const unsigned short *ids;
1da177e4
LT		 603 int i, j;
604
e9422e09 605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612}
613
614/*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618static int
975a1a7d
RK		 619pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
2655a2c7 621 struct uart_8250_port *port, int idx)
1da177e4
LT		 622{
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
c2cd6d3c 638 /* FALLTHROUGH */
1da177e4
LT		 639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
70db3d91 646 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 647}
648
649/*
650 * Some Titan cards are also a little weird
651 */
652static int
70db3d91 653titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 654 const struct pciserial_board *board,
2655a2c7 655 struct uart_8250_port *port, int idx)
1da177e4
LT		 656{
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
70db3d91 671 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 672}
673
61a116ef 674static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 675{
676 msleep(100);
677 return 0;
678}
679
04bf7e74
WP		 680static int pci_ni8420_init(struct pci_dev *dev)
681{
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar = 0;
685
686 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687 moan_device("no memory in bar", dev);
688 return 0;
689 }
690
691 base = pci_resource_start(dev, bar);
692 len = pci_resource_len(dev, bar);
693 p = ioremap_nocache(base, len);
694 if (p == NULL)
695 return -ENOMEM;
696
697 /* Enable CPU Interrupt */
698 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699 p + NI8420_INT_ENABLE_REG);
700
701 iounmap(p);
702 return 0;
703}
704
46a0fac9
SB		 705#define MITE_IOWBSR1_WSIZE 0xa
706#define MITE_IOWBSR1_WIN_OFFSET 0x800
707#define MITE_IOWBSR1_WENAB (1 << 7)
708#define MITE_LCIMR1_IO_IE_0 (1 << 24)
709#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
710#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712static int pci_ni8430_init(struct pci_dev *dev)
713{
714 void __iomem *p;
715 unsigned long base, len;
716 u32 device_window;
717 unsigned int bar = 0;
718
719 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720 moan_device("no memory in bar", dev);
721 return 0;
722 }
723
724 base = pci_resource_start(dev, bar);
725 len = pci_resource_len(dev, bar);
726 p = ioremap_nocache(base, len);
727 if (p == NULL)
728 return -ENOMEM;
729
730 /* Set device window address and size in BAR0 */
731 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747}
748
749/* UART Port Control Register */
750#define NI8430_PORTCON 0x0f
751#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753static int
bf538fe4
AC		 754pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
2655a2c7 756 struct uart_8250_port *port, int idx)
46a0fac9
SB		 757{
758 void __iomem *p;
759 unsigned long base, len;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 base = pci_resource_start(priv->dev, bar);
769 len = pci_resource_len(priv->dev, bar);
770 p = ioremap_nocache(base, len);
771
7c9d440e 772 /* enable the transceiver */
46a0fac9
SB		 773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779}
780
7808edcd
NG		 781static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
2655a2c7 783 struct uart_8250_port *port, int idx)
7808edcd
NG		 784{
785 unsigned int bar;
786
787 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797}
798
799/* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807static int pci_netmos_9900_numports(struct pci_dev *dev)
808{
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
af8c5b8d 829 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
7808edcd
NG		 830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836}
46a0fac9 837
61a116ef 838static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 839{
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
ac6ec5b1
IS		 843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 845 return 0;
7808edcd 846
25cf9bc1
JS		 847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
7808edcd
NG		 851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
1da177e4
LT		 865 if (num_serial == 0)
866 return -ENODEV;
7808edcd 867
1da177e4
LT		 868 return num_serial;
869}
870
84f8c6fc 871/*
84f8c6fc
NV		 872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881/* registers */
882#define ITE_887x_MISCR 0x9c
883#define ITE_887x_INTCBAR 0x78
884#define ITE_887x_UARTBAR 0x7c
885#define ITE_887x_PS0BAR 0x10
886#define ITE_887x_POSIO0 0x60
887
888/* I/O space size */
889#define ITE_887x_IOSIZE 32
890/* I/O space size (bits 26-24; 8 bytes = 011b) */
891#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892/* I/O space size (bits 26-24; 32 bytes = 101b) */
893#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895#define ITE_887x_POSIO_SPEED (3 << 29)
896/* enable IO_Space bit */
897#define ITE_887x_POSIO_ENABLE (1 << 31)
898
f79abb82 899static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 900{
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
5756ee99
AC		 919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
84f8c6fc
NV		 921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
af8c5b8d 933 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991}
992
ae8d8a14 993static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 994{
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000}
1001
9f2a036a
RK		 1002/*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008{
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
af8c5b8d 1026 dev_dbg(&dev->dev,
9f2a036a 1027 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1028 number_uarts);
9f2a036a
RK		 1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032}
1033
eb26dfe8
AC		 1034static int pci_asix_setup(struct serial_private *priv,
1035 const struct pciserial_board *board,
1036 struct uart_8250_port *port, int idx)
1037{
1038 port->bugs |= UART_BUG_PARITY;
1039 return pci_default_setup(priv, board, port, idx);
1040}
1041
55c7c0fd
AC		 1042/* Quatech devices have their own extra interface features */
1043
1044struct quatech_feature {
1045 u16 devid;
1046 bool amcc;
1047};
1048
1049#define QPCR_TEST_FOR1 0x3F
1050#define QPCR_TEST_GET1 0x00
1051#define QPCR_TEST_FOR2 0x40
1052#define QPCR_TEST_GET2 0x40
1053#define QPCR_TEST_FOR3 0x80
1054#define QPCR_TEST_GET3 0x40
1055#define QPCR_TEST_FOR4 0xC0
1056#define QPCR_TEST_GET4 0x80
1057
1058#define QOPR_CLOCK_X1 0x0000
1059#define QOPR_CLOCK_X2 0x0001
1060#define QOPR_CLOCK_X4 0x0002
1061#define QOPR_CLOCK_X8 0x0003
1062#define QOPR_CLOCK_RATE_MASK 0x0003
1063
1064
1065static struct quatech_feature quatech_cards[] = {
1066 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1067 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1069 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1071 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1073 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1074 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1076 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1078 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1085 { 0, }
1086};
1087
1088static int pci_quatech_amcc(u16 devid)
1089{
1090 struct quatech_feature *qf = &quatech_cards[0];
1091 while (qf->devid) {
1092 if (qf->devid == devid)
1093 return qf->amcc;
1094 qf++;
1095 }
1096 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1097 return 0;
1098};
1099
1100static int pci_quatech_rqopr(struct uart_8250_port *port)
1101{
1102 unsigned long base = port->port.iobase;
1103 u8 LCR, val;
1104
1105 LCR = inb(base + UART_LCR);
1106 outb(0xBF, base + UART_LCR);
1107 val = inb(base + UART_SCR);
1108 outb(LCR, base + UART_LCR);
1109 return val;
1110}
1111
1112static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1113{
1114 unsigned long base = port->port.iobase;
1115 u8 LCR, val;
1116
1117 LCR = inb(base + UART_LCR);
1118 outb(0xBF, base + UART_LCR);
1119 val = inb(base + UART_SCR);
1120 outb(qopr, base + UART_SCR);
1121 outb(LCR, base + UART_LCR);
1122}
1123
1124static int pci_quatech_rqmcr(struct uart_8250_port *port)
1125{
1126 unsigned long base = port->port.iobase;
1127 u8 LCR, val, qmcr;
1128
1129 LCR = inb(base + UART_LCR);
1130 outb(0xBF, base + UART_LCR);
1131 val = inb(base + UART_SCR);
1132 outb(val | 0x10, base + UART_SCR);
1133 qmcr = inb(base + UART_MCR);
1134 outb(val, base + UART_SCR);
1135 outb(LCR, base + UART_LCR);
1136
1137 return qmcr;
1138}
1139
1140static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1141{
1142 unsigned long base = port->port.iobase;
1143 u8 LCR, val;
1144
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(val | 0x10, base + UART_SCR);
1149 outb(qmcr, base + UART_MCR);
1150 outb(val, base + UART_SCR);
1151 outb(LCR, base + UART_LCR);
1152}
1153
1154static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1155{
1156 unsigned long base = port->port.iobase;
1157 u8 LCR, val;
1158
1159 LCR = inb(base + UART_LCR);
1160 outb(0xBF, base + UART_LCR);
1161 val = inb(base + UART_SCR);
1162 if (val & 0x20) {
1163 outb(0x80, UART_LCR);
1164 if (!(inb(UART_SCR) & 0x20)) {
1165 outb(LCR, base + UART_LCR);
1166 return 1;
1167 }
1168 }
1169 return 0;
1170}
1171
1172static int pci_quatech_test(struct uart_8250_port *port)
1173{
1174 u8 reg;
1175 u8 qopr = pci_quatech_rqopr(port);
1176 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1177 reg = pci_quatech_rqopr(port) & 0xC0;
1178 if (reg != QPCR_TEST_GET1)
1179 return -EINVAL;
1180 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1181 reg = pci_quatech_rqopr(port) & 0xC0;
1182 if (reg != QPCR_TEST_GET2)
1183 return -EINVAL;
1184 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1185 reg = pci_quatech_rqopr(port) & 0xC0;
1186 if (reg != QPCR_TEST_GET3)
1187 return -EINVAL;
1188 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1189 reg = pci_quatech_rqopr(port) & 0xC0;
1190 if (reg != QPCR_TEST_GET4)
1191 return -EINVAL;
1192
1193 pci_quatech_wqopr(port, qopr);
1194 return 0;
1195}
1196
1197static int pci_quatech_clock(struct uart_8250_port *port)
1198{
1199 u8 qopr, reg, set;
1200 unsigned long clock;
1201
1202 if (pci_quatech_test(port) < 0)
1203 return 1843200;
1204
1205 qopr = pci_quatech_rqopr(port);
1206
1207 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1208 reg = pci_quatech_rqopr(port);
1209 if (reg & QOPR_CLOCK_X8) {
1210 clock = 1843200;
1211 goto out;
1212 }
1213 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1214 reg = pci_quatech_rqopr(port);
1215 if (!(reg & QOPR_CLOCK_X8)) {
1216 clock = 1843200;
1217 goto out;
1218 }
1219 reg &= QOPR_CLOCK_X8;
1220 if (reg == QOPR_CLOCK_X2) {
1221 clock = 3685400;
1222 set = QOPR_CLOCK_X2;
1223 } else if (reg == QOPR_CLOCK_X4) {
1224 clock = 7372800;
1225 set = QOPR_CLOCK_X4;
1226 } else if (reg == QOPR_CLOCK_X8) {
1227 clock = 14745600;
1228 set = QOPR_CLOCK_X8;
1229 } else {
1230 clock = 1843200;
1231 set = QOPR_CLOCK_X1;
1232 }
1233 qopr &= ~QOPR_CLOCK_RATE_MASK;
1234 qopr |= set;
1235
1236out:
1237 pci_quatech_wqopr(port, qopr);
1238 return clock;
1239}
1240
1241static int pci_quatech_rs422(struct uart_8250_port *port)
1242{
1243 u8 qmcr;
1244 int rs422 = 0;
1245
1246 if (!pci_quatech_has_qmcr(port))
1247 return 0;
1248 qmcr = pci_quatech_rqmcr(port);
1249 pci_quatech_wqmcr(port, 0xFF);
1250 if (pci_quatech_rqmcr(port))
1251 rs422 = 1;
1252 pci_quatech_wqmcr(port, qmcr);
1253 return rs422;
1254}
1255
1256static int pci_quatech_init(struct pci_dev *dev)
1257{
1258 if (pci_quatech_amcc(dev->device)) {
1259 unsigned long base = pci_resource_start(dev, 0);
1260 if (base) {
1261 u32 tmp;
1262 outl(inl(base + 0x38), base + 0x38);
1263 tmp = inl(base + 0x3c);
1264 outl(tmp | 0x01000000, base + 0x3c);
1265 outl(tmp, base + 0x3c);
1266 }
1267 }
1268 return 0;
1269}
1270
1271static int pci_quatech_setup(struct serial_private *priv,
1272 const struct pciserial_board *board,
1273 struct uart_8250_port *port, int idx)
1274{
1275 /* Needed by pci_quatech calls below */
1276 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1277 /* Set up the clocking */
1278 port->port.uartclk = pci_quatech_clock(port);
1279 /* For now just warn about RS422 */
1280 if (pci_quatech_rs422(port))
1281 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1282 return pci_default_setup(priv, board, port, idx);
1283}
1284
d73dfc6a 1285static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1286{
1287}
1288
eb26dfe8 1289static int pci_default_setup(struct serial_private *priv,
975a1a7d 1290 const struct pciserial_board *board,
2655a2c7 1291 struct uart_8250_port *port, int idx)
1da177e4
LT		 1292{
1293 unsigned int bar, offset = board->first_offset, maxnr;
1294
1295 bar = FL_GET_BASE(board->flags);
1296 if (board->flags & FL_BASE_BARS)
1297 bar += idx;
1298 else
1299 offset += idx * board->uart_offset;
1300
2427ddd8
GKH		 1301 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1302 (board->reg_shift + 3);
1da177e4
LT		 1303
1304 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1305 return 1;
5756ee99 1306
70db3d91 1307 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1308}
1309
095e24b0
DB		 1310static int
1311ce4100_serial_setup(struct serial_private *priv,
1312 const struct pciserial_board *board,
2655a2c7 1313 struct uart_8250_port *port, int idx)
095e24b0
DB		 1314{
1315 int ret;
1316
08ec212c 1317 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1318 port->port.iotype = UPIO_MEM32;
1319 port->port.type = PORT_XSCALE;
1320 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1321 port->port.regshift = 2;
095e24b0
DB		 1322
1323 return ret;
1324}
1325
b15e5691
HK		 1326#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1327#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1328
1329#define BYT_PRV_CLK 0x800
1330#define BYT_PRV_CLK_EN (1 << 0)
1331#define BYT_PRV_CLK_M_VAL_SHIFT 1
1332#define BYT_PRV_CLK_N_VAL_SHIFT 16
1333#define BYT_PRV_CLK_UPDATE (1 << 31)
1334
1335#define BYT_GENERAL_REG 0x808
1336#define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3)
1337
1338#define BYT_TX_OVF_INT 0x820
1339#define BYT_TX_OVF_INT_MASK (1 << 1)
1340
1341static void
1342byt_set_termios(struct uart_port *p, struct ktermios *termios,
1343 struct ktermios *old)
1344{
1345 unsigned int baud = tty_termios_baud_rate(termios);
1346 unsigned int m = 6912;
1347 unsigned int n = 15625;
1348 u32 reg;
1349
1350 /* For baud rates 1M, 2M, 3M and 4M the dividers must be adjusted. */
1351 if (baud == 1000000 || baud == 2000000 || baud == 4000000) {
1352 m = 64;
1353 n = 100;
1354
1355 p->uartclk = 64000000;
1356 } else if (baud == 3000000) {
1357 m = 48;
1358 n = 100;
1359
1360 p->uartclk = 48000000;
1361 } else {
1362 p->uartclk = 44236800;
1363 }
1364
1365 /* Reset the clock */
1366 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1367 writel(reg, p->membase + BYT_PRV_CLK);
1368 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1369 writel(reg, p->membase + BYT_PRV_CLK);
1370
1371 /*
1372 * If auto-handshake mechanism is not enabled,
1373 * disable rts_n override
1374 */
1375 reg = readl(p->membase + BYT_GENERAL_REG);
1376 reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1377 if (termios->c_cflag & CRTSCTS)
1378 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1379 writel(reg, p->membase + BYT_GENERAL_REG);
1380
1381 serial8250_do_set_termios(p, termios, old);
1382}
1383
1384static bool byt_dma_filter(struct dma_chan *chan, void *param)
1385{
1386 return chan->chan_id == *(int *)param;
1387}
1388
1389static int
1390byt_serial_setup(struct serial_private *priv,
1391 const struct pciserial_board *board,
1392 struct uart_8250_port *port, int idx)
1393{
1394 struct uart_8250_dma *dma;
1395 int ret;
1396
1397 dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL);
1398 if (!dma)
1399 return -ENOMEM;
1400
1401 switch (priv->dev->device) {
1402 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1403 dma->rx_chan_id = 3;
1404 dma->tx_chan_id = 2;
1405 break;
1406 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1407 dma->rx_chan_id = 5;
1408 dma->tx_chan_id = 4;
1409 break;
1410 default:
1411 return -EINVAL;
1412 }
1413
1414 dma->rxconf.slave_id = dma->rx_chan_id;
1415 dma->rxconf.src_maxburst = 16;
1416
1417 dma->txconf.slave_id = dma->tx_chan_id;
1418 dma->txconf.dst_maxburst = 16;
1419
1420 dma->fn = byt_dma_filter;
1421 dma->rx_param = &dma->rx_chan_id;
1422 dma->tx_param = &dma->tx_chan_id;
1423
1424 ret = pci_default_setup(priv, board, port, idx);
1425 port->port.iotype = UPIO_MEM;
1426 port->port.type = PORT_16550A;
1427 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1428 port->port.set_termios = byt_set_termios;
1429 port->port.fifosize = 64;
1430 port->tx_loadsz = 64;
1431 port->dma = dma;
1432 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1433
1434 /* Disable Tx counter interrupts */
1435 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1436
1437 return ret;
1438}
1439
d9a0fbfd
AP		 1440static int
1441pci_omegapci_setup(struct serial_private *priv,
1798ca13 1442 const struct pciserial_board *board,
2655a2c7 1443 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1444{
1445 return setup_port(priv, port, 2, idx * 8, 0);
1446}
1447
ebebd49a
SH		 1448static int
1449pci_brcm_trumanage_setup(struct serial_private *priv,
1450 const struct pciserial_board *board,
1451 struct uart_8250_port *port, int idx)
1452{
1453 int ret = pci_default_setup(priv, board, port, idx);
1454
1455 port->port.type = PORT_BRCM_TRUMANAGE;
1456 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1457 return ret;
1458}
1459
2c62a3c8
GKH		 1460static int pci_fintek_setup(struct serial_private *priv,
1461 const struct pciserial_board *board,
1462 struct uart_8250_port *port, int idx)
1463{
1464 struct pci_dev *pdev = priv->dev;
1465 unsigned long base;
1466 unsigned long iobase;
1467 unsigned long ciobase = 0;
1468 u8 config_base;
1469
1470 /*
1471 * We are supposed to be able to read these from the PCI config space,
1472 * but the values there don't seem to match what we need to use, so
1473 * just use these hard-coded values for now, as they are correct.
1474 */
1475 switch (idx) {
1476 case 0: iobase = 0xe000; config_base = 0x40; break;
1477 case 1: iobase = 0xe008; config_base = 0x48; break;
1478 case 2: iobase = 0xe010; config_base = 0x50; break;
1479 case 3: iobase = 0xe018; config_base = 0x58; break;
1480 case 4: iobase = 0xe020; config_base = 0x60; break;
1481 case 5: iobase = 0xe028; config_base = 0x68; break;
1482 case 6: iobase = 0xe030; config_base = 0x70; break;
1483 case 7: iobase = 0xe038; config_base = 0x78; break;
1484 case 8: iobase = 0xe040; config_base = 0x80; break;
1485 case 9: iobase = 0xe048; config_base = 0x88; break;
1486 case 10: iobase = 0xe050; config_base = 0x90; break;
1487 case 11: iobase = 0xe058; config_base = 0x98; break;
1488 default:
1489 /* Unknown number of ports, get out of here */
1490 return -EINVAL;
1491 }
1492
1493 if (idx < 4) {
1494 base = pci_resource_start(priv->dev, 3);
1495 ciobase = (int)(base + (0x8 * idx));
1496 }
1497
1498 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1499 __func__, idx, iobase, ciobase, config_base);
1500
1501 /* Enable UART I/O port */
1502 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1503
1504 /* Select 128-byte FIFO and 8x FIFO threshold */
1505 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1506
1507 /* LSB UART */
1508 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1509
1510 /* MSB UART */
1511 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1512
1513 /* irq number, this usually fails, but the spec says to do it anyway. */
1514 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1515
1516 port->port.iotype = UPIO_PORT;
1517 port->port.iobase = iobase;
1518 port->port.mapbase = 0;
1519 port->port.membase = NULL;
1520 port->port.regshift = 0;
1521
1522 return 0;
1523}
1524
b6adea33
MCC		 1525static int skip_tx_en_setup(struct serial_private *priv,
1526 const struct pciserial_board *board,
2655a2c7 1527 struct uart_8250_port *port, int idx)
b6adea33 1528{
2655a2c7 1529 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1530 dev_dbg(&priv->dev->dev,
1531 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1532 priv->dev->vendor, priv->dev->device,
1533 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1534
1535 return pci_default_setup(priv, board, port, idx);
1536}
1537
0ad372b9
SM		 1538static void kt_handle_break(struct uart_port *p)
1539{
1540 struct uart_8250_port *up =
1541 container_of(p, struct uart_8250_port, port);
1542 /*
1543 * On receipt of a BI, serial device in Intel ME (Intel
1544 * management engine) needs to have its fifos cleared for sane
1545 * SOL (Serial Over Lan) output.
1546 */
1547 serial8250_clear_and_reinit_fifos(up);
1548}
1549
1550static unsigned int kt_serial_in(struct uart_port *p, int offset)
1551{
1552 struct uart_8250_port *up =
1553 container_of(p, struct uart_8250_port, port);
1554 unsigned int val;
1555
1556 /*
1557 * When the Intel ME (management engine) gets reset its serial
1558 * port registers could return 0 momentarily. Functions like
1559 * serial8250_console_write, read and save the IER, perform
1560 * some operation and then restore it. In order to avoid
1561 * setting IER register inadvertently to 0, if the value read
1562 * is 0, double check with ier value in uart_8250_port and use
1563 * that instead. up->ier should be the same value as what is
1564 * currently configured.
1565 */
1566 val = inb(p->iobase + offset);
1567 if (offset == UART_IER) {
1568 if (val == 0)
1569 val = up->ier;
1570 }
1571 return val;
1572}
1573
bc02d15a
DW		 1574static int kt_serial_setup(struct serial_private *priv,
1575 const struct pciserial_board *board,
2655a2c7 1576 struct uart_8250_port *port, int idx)
bc02d15a 1577{
2655a2c7
AC		 1578 port->port.flags |= UPF_BUG_THRE;
1579 port->port.serial_in = kt_serial_in;
1580 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1581 return skip_tx_en_setup(priv, board, port, idx);
1582}
1583
eb7073db
TM		 1584static int pci_eg20t_init(struct pci_dev *dev)
1585{
1586#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1587 return -ENODEV;
1588#else
1589 return 0;
1590#endif
1591}
1592
06315348
SH		 1593static int
1594pci_xr17c154_setup(struct serial_private *priv,
1595 const struct pciserial_board *board,
2655a2c7 1596 struct uart_8250_port *port, int idx)
06315348 1597{
2655a2c7 1598 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1599 return pci_default_setup(priv, board, port, idx);
1600}
1601
dc96efb7
MS		 1602static int
1603pci_xr17v35x_setup(struct serial_private *priv,
1604 const struct pciserial_board *board,
1605 struct uart_8250_port *port, int idx)
1606{
1607 u8 __iomem *p;
1608
1609 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1610 if (p == NULL)
1611 return -ENOMEM;
dc96efb7
MS		 1612
1613 port->port.flags |= UPF_EXAR_EFR;
1614
1615 /*
1616 * Setup Multipurpose Input/Output pins.
1617 */
1618 if (idx == 0) {
1619 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1620 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1621 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1622 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1623 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1624 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1625 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1626 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1627 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1628 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1629 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1630 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1631 }
f965b9c4
MS		 1632 writeb(0x00, p + UART_EXAR_8XMODE);
1633 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1634 writeb(128, p + UART_EXAR_TXTRG);
1635 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1636 iounmap(p);
1637
1638 return pci_default_setup(priv, board, port, idx);
1639}
1640
14faa8cc
MS		 1641#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1642#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1643#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1644#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1645
1646static int
1647pci_fastcom335_setup(struct serial_private *priv,
1648 const struct pciserial_board *board,
1649 struct uart_8250_port *port, int idx)
1650{
1651 u8 __iomem *p;
1652
1653 p = pci_ioremap_bar(priv->dev, 0);
1654 if (p == NULL)
1655 return -ENOMEM;
1656
1657 port->port.flags |= UPF_EXAR_EFR;
1658
1659 /*
1660 * Setup Multipurpose Input/Output pins.
1661 */
1662 if (idx == 0) {
1663 switch (priv->dev->device) {
1664 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1665 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1666 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1667 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1668 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1669 break;
1670 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1671 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1672 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1673 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1674 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1675 break;
1676 }
1677 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1678 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1679 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1680 }
1681 writeb(0x00, p + UART_EXAR_8XMODE);
1682 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1683 writeb(32, p + UART_EXAR_TXTRG);
1684 writeb(32, p + UART_EXAR_RXTRG);
1685 iounmap(p);
1686
1687 return pci_default_setup(priv, board, port, idx);
1688}
1689
6971c635
GA		 1690static int
1691pci_wch_ch353_setup(struct serial_private *priv,
1692 const struct pciserial_board *board,
1693 struct uart_8250_port *port, int idx)
1694{
1695 port->port.flags |= UPF_FIXED_TYPE;
1696 port->port.type = PORT_16550A;
06315348
SH		 1697 return pci_default_setup(priv, board, port, idx);
1698}
1699
1da177e4
LT		 1700#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1701#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1702#define PCI_DEVICE_ID_OCTPRO 0x0001
1703#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1704#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1705#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1706#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1707#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1708#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1709#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1710#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1711#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1712#define PCI_DEVICE_ID_TITAN_200I 0x8028
1713#define PCI_DEVICE_ID_TITAN_400I 0x8048
1714#define PCI_DEVICE_ID_TITAN_800I 0x8088
1715#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1716#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1717#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1718#define PCI_DEVICE_ID_TITAN_100E 0xA010
1719#define PCI_DEVICE_ID_TITAN_200E 0xA012
1720#define PCI_DEVICE_ID_TITAN_400E 0xA013
1721#define PCI_DEVICE_ID_TITAN_800E 0xA014
1722#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1723#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1e9deb11
YY		 1724#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1725#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1726#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1727#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1728#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1729#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1730#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1731#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1732#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1733#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1734#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1735#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1736#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 1737#define PCI_VENDOR_ID_AGESTAR 0x5372
1738#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1739#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 1740#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1741#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 1742#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 1743#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 1744#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
14faa8cc 1745
abd7baca
SC		 1746#define PCI_VENDOR_ID_SUNIX 0x1fd4
1747#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1748
1da177e4 1749
b76c5a07
CB		 1750/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1751#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 1752#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 1753
1da177e4
LT		 1754/*
1755 * Master list of serial port init/setup/exit quirks.
1756 * This does not describe the general nature of the port.
1757 * (ie, baud base, number and location of ports, etc)
1758 *
1759 * This list is ordered alphabetically by vendor then device.
1760 * Specific entries must come before more generic entries.
1761 */
7a63ce5a 1762static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1763 /*
1764 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1765 */
1766 {
086231f7 1767 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 1768 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 1769 .subvendor = PCI_ANY_ID,
1770 .subdevice = PCI_ANY_ID,
1771 .setup = addidata_apci7800_setup,
1772 },
1da177e4 1773 /*
61a116ef 1774 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1775 * It is not clear whether this applies to all products.
1776 */
1777 {
1778 .vendor = PCI_VENDOR_ID_AFAVLAB,
1779 .device = PCI_ANY_ID,
1780 .subvendor = PCI_ANY_ID,
1781 .subdevice = PCI_ANY_ID,
1782 .setup = afavlab_setup,
1783 },
1784 /*
1785 * HP Diva
1786 */
1787 {
1788 .vendor = PCI_VENDOR_ID_HP,
1789 .device = PCI_DEVICE_ID_HP_DIVA,
1790 .subvendor = PCI_ANY_ID,
1791 .subdevice = PCI_ANY_ID,
1792 .init = pci_hp_diva_init,
1793 .setup = pci_hp_diva_setup,
1794 },
1795 /*
1796 * Intel
1797 */
1798 {
1799 .vendor = PCI_VENDOR_ID_INTEL,
1800 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1801 .subvendor = 0xe4bf,
1802 .subdevice = PCI_ANY_ID,
1803 .init = pci_inteli960ni_init,
1804 .setup = pci_default_setup,
1805 },
b6adea33
MCC		 1806 {
1807 .vendor = PCI_VENDOR_ID_INTEL,
1808 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1809 .subvendor = PCI_ANY_ID,
1810 .subdevice = PCI_ANY_ID,
1811 .setup = skip_tx_en_setup,
1812 },
1813 {
1814 .vendor = PCI_VENDOR_ID_INTEL,
1815 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1816 .subvendor = PCI_ANY_ID,
1817 .subdevice = PCI_ANY_ID,
1818 .setup = skip_tx_en_setup,
1819 },
1820 {
1821 .vendor = PCI_VENDOR_ID_INTEL,
1822 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1823 .subvendor = PCI_ANY_ID,
1824 .subdevice = PCI_ANY_ID,
1825 .setup = skip_tx_en_setup,
1826 },
095e24b0
DB		 1827 {
1828 .vendor = PCI_VENDOR_ID_INTEL,
1829 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1830 .subvendor = PCI_ANY_ID,
1831 .subdevice = PCI_ANY_ID,
1832 .setup = ce4100_serial_setup,
1833 },
bc02d15a
DW		 1834 {
1835 .vendor = PCI_VENDOR_ID_INTEL,
1836 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1837 .subvendor = PCI_ANY_ID,
1838 .subdevice = PCI_ANY_ID,
1839 .setup = kt_serial_setup,
1840 },
b15e5691
HK		 1841 {
1842 .vendor = PCI_VENDOR_ID_INTEL,
1843 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1844 .subvendor = PCI_ANY_ID,
1845 .subdevice = PCI_ANY_ID,
1846 .setup = byt_serial_setup,
1847 },
1848 {
1849 .vendor = PCI_VENDOR_ID_INTEL,
1850 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1851 .subvendor = PCI_ANY_ID,
1852 .subdevice = PCI_ANY_ID,
1853 .setup = byt_serial_setup,
1854 },
84f8c6fc
NV		 1855 /*
1856 * ITE
1857 */
1858 {
1859 .vendor = PCI_VENDOR_ID_ITE,
1860 .device = PCI_DEVICE_ID_ITE_8872,
1861 .subvendor = PCI_ANY_ID,
1862 .subdevice = PCI_ANY_ID,
1863 .init = pci_ite887x_init,
1864 .setup = pci_default_setup,
2d47b716 1865 .exit = pci_ite887x_exit,
84f8c6fc 1866 },
46a0fac9
SB		 1867 /*
1868 * National Instruments
1869 */
04bf7e74
WP		 1870 {
1871 .vendor = PCI_VENDOR_ID_NI,
1872 .device = PCI_DEVICE_ID_NI_PCI23216,
1873 .subvendor = PCI_ANY_ID,
1874 .subdevice = PCI_ANY_ID,
1875 .init = pci_ni8420_init,
1876 .setup = pci_default_setup,
2d47b716 1877 .exit = pci_ni8420_exit,
04bf7e74
WP		 1878 },
1879 {
1880 .vendor = PCI_VENDOR_ID_NI,
1881 .device = PCI_DEVICE_ID_NI_PCI2328,
1882 .subvendor = PCI_ANY_ID,
1883 .subdevice = PCI_ANY_ID,
1884 .init = pci_ni8420_init,
1885 .setup = pci_default_setup,
2d47b716 1886 .exit = pci_ni8420_exit,
04bf7e74
WP		 1887 },
1888 {
1889 .vendor = PCI_VENDOR_ID_NI,
1890 .device = PCI_DEVICE_ID_NI_PCI2324,
1891 .subvendor = PCI_ANY_ID,
1892 .subdevice = PCI_ANY_ID,
1893 .init = pci_ni8420_init,
1894 .setup = pci_default_setup,
2d47b716 1895 .exit = pci_ni8420_exit,
04bf7e74
WP		 1896 },
1897 {
1898 .vendor = PCI_VENDOR_ID_NI,
1899 .device = PCI_DEVICE_ID_NI_PCI2322,
1900 .subvendor = PCI_ANY_ID,
1901 .subdevice = PCI_ANY_ID,
1902 .init = pci_ni8420_init,
1903 .setup = pci_default_setup,
2d47b716 1904 .exit = pci_ni8420_exit,
04bf7e74
WP		 1905 },
1906 {
1907 .vendor = PCI_VENDOR_ID_NI,
1908 .device = PCI_DEVICE_ID_NI_PCI2324I,
1909 .subvendor = PCI_ANY_ID,
1910 .subdevice = PCI_ANY_ID,
1911 .init = pci_ni8420_init,
1912 .setup = pci_default_setup,
2d47b716 1913 .exit = pci_ni8420_exit,
04bf7e74
WP		 1914 },
1915 {
1916 .vendor = PCI_VENDOR_ID_NI,
1917 .device = PCI_DEVICE_ID_NI_PCI2322I,
1918 .subvendor = PCI_ANY_ID,
1919 .subdevice = PCI_ANY_ID,
1920 .init = pci_ni8420_init,
1921 .setup = pci_default_setup,
2d47b716 1922 .exit = pci_ni8420_exit,
04bf7e74
WP		 1923 },
1924 {
1925 .vendor = PCI_VENDOR_ID_NI,
1926 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1927 .subvendor = PCI_ANY_ID,
1928 .subdevice = PCI_ANY_ID,
1929 .init = pci_ni8420_init,
1930 .setup = pci_default_setup,
2d47b716 1931 .exit = pci_ni8420_exit,
04bf7e74
WP		 1932 },
1933 {
1934 .vendor = PCI_VENDOR_ID_NI,
1935 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1936 .subvendor = PCI_ANY_ID,
1937 .subdevice = PCI_ANY_ID,
1938 .init = pci_ni8420_init,
1939 .setup = pci_default_setup,
2d47b716 1940 .exit = pci_ni8420_exit,
04bf7e74
WP		 1941 },
1942 {
1943 .vendor = PCI_VENDOR_ID_NI,
1944 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1945 .subvendor = PCI_ANY_ID,
1946 .subdevice = PCI_ANY_ID,
1947 .init = pci_ni8420_init,
1948 .setup = pci_default_setup,
2d47b716 1949 .exit = pci_ni8420_exit,
04bf7e74
WP		 1950 },
1951 {
1952 .vendor = PCI_VENDOR_ID_NI,
1953 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1954 .subvendor = PCI_ANY_ID,
1955 .subdevice = PCI_ANY_ID,
1956 .init = pci_ni8420_init,
1957 .setup = pci_default_setup,
2d47b716 1958 .exit = pci_ni8420_exit,
04bf7e74
WP		 1959 },
1960 {
1961 .vendor = PCI_VENDOR_ID_NI,
1962 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1963 .subvendor = PCI_ANY_ID,
1964 .subdevice = PCI_ANY_ID,
1965 .init = pci_ni8420_init,
1966 .setup = pci_default_setup,
2d47b716 1967 .exit = pci_ni8420_exit,
04bf7e74
WP		 1968 },
1969 {
1970 .vendor = PCI_VENDOR_ID_NI,
1971 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1972 .subvendor = PCI_ANY_ID,
1973 .subdevice = PCI_ANY_ID,
1974 .init = pci_ni8420_init,
1975 .setup = pci_default_setup,
2d47b716 1976 .exit = pci_ni8420_exit,
04bf7e74 1977 },
46a0fac9
SB		 1978 {
1979 .vendor = PCI_VENDOR_ID_NI,
1980 .device = PCI_ANY_ID,
1981 .subvendor = PCI_ANY_ID,
1982 .subdevice = PCI_ANY_ID,
1983 .init = pci_ni8430_init,
1984 .setup = pci_ni8430_setup,
2d47b716 1985 .exit = pci_ni8430_exit,
46a0fac9 1986 },
55c7c0fd
AC		 1987 /* Quatech */
1988 {
1989 .vendor = PCI_VENDOR_ID_QUATECH,
1990 .device = PCI_ANY_ID,
1991 .subvendor = PCI_ANY_ID,
1992 .subdevice = PCI_ANY_ID,
1993 .init = pci_quatech_init,
1994 .setup = pci_quatech_setup,
d73dfc6a 1995 .exit = pci_quatech_exit,
55c7c0fd 1996 },
1da177e4
LT		 1997 /*
1998 * Panacom
1999 */
2000 {
2001 .vendor = PCI_VENDOR_ID_PANACOM,
2002 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .init = pci_plx9050_init,
2006 .setup = pci_default_setup,
2d47b716 2007 .exit = pci_plx9050_exit,
5756ee99 2008 },
1da177e4
LT		 2009 {
2010 .vendor = PCI_VENDOR_ID_PANACOM,
2011 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2012 .subvendor = PCI_ANY_ID,
2013 .subdevice = PCI_ANY_ID,
2014 .init = pci_plx9050_init,
2015 .setup = pci_default_setup,
2d47b716 2016 .exit = pci_plx9050_exit,
1da177e4
LT		 2017 },
2018 /*
2019 * PLX
2020 */
48212008
TH		 2021 {
2022 .vendor = PCI_VENDOR_ID_PLX,
2023 .device = PCI_DEVICE_ID_PLX_9030,
2024 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2025 .subdevice = PCI_ANY_ID,
2026 .setup = pci_default_setup,
2027 },
add7b58e
BH		 2028 {
2029 .vendor = PCI_VENDOR_ID_PLX,
2030 .device = PCI_DEVICE_ID_PLX_9050,
2031 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2032 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2033 .init = pci_plx9050_init,
2034 .setup = pci_default_setup,
2d47b716 2035 .exit = pci_plx9050_exit,
add7b58e 2036 },
1da177e4
LT		 2037 {
2038 .vendor = PCI_VENDOR_ID_PLX,
2039 .device = PCI_DEVICE_ID_PLX_9050,
2040 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2041 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2042 .init = pci_plx9050_init,
2043 .setup = pci_default_setup,
2d47b716 2044 .exit = pci_plx9050_exit,
1da177e4
LT		 2045 },
2046 {
2047 .vendor = PCI_VENDOR_ID_PLX,
2048 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2049 .subvendor = PCI_VENDOR_ID_PLX,
2050 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2051 .init = pci_plx9050_init,
2052 .setup = pci_default_setup,
2d47b716 2053 .exit = pci_plx9050_exit,
1da177e4
LT		 2054 },
2055 /*
2056 * SBS Technologies, Inc., PMC-OCTALPRO 232
2057 */
2058 {
2059 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2060 .device = PCI_DEVICE_ID_OCTPRO,
2061 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2062 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2063 .init = sbs_init,
2064 .setup = sbs_setup,
2d47b716 2065 .exit = sbs_exit,
1da177e4
LT		 2066 },
2067 /*
2068 * SBS Technologies, Inc., PMC-OCTALPRO 422
2069 */
2070 {
2071 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2072 .device = PCI_DEVICE_ID_OCTPRO,
2073 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2074 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2075 .init = sbs_init,
2076 .setup = sbs_setup,
2d47b716 2077 .exit = sbs_exit,
1da177e4
LT		 2078 },
2079 /*
2080 * SBS Technologies, Inc., P-Octal 232
2081 */
2082 {
2083 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2084 .device = PCI_DEVICE_ID_OCTPRO,
2085 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2086 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2087 .init = sbs_init,
2088 .setup = sbs_setup,
2d47b716 2089 .exit = sbs_exit,
1da177e4
LT		 2090 },
2091 /*
2092 * SBS Technologies, Inc., P-Octal 422
2093 */
2094 {
2095 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2096 .device = PCI_DEVICE_ID_OCTPRO,
2097 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2098 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2099 .init = sbs_init,
2100 .setup = sbs_setup,
2d47b716 2101 .exit = sbs_exit,
1da177e4 2102 },
1da177e4 2103 /*
61a116ef 2104 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2105 */
2106 {
2107 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2108 .device = PCI_ANY_ID,
1da177e4
LT		 2109 .subvendor = PCI_ANY_ID,
2110 .subdevice = PCI_ANY_ID,
67d74b87 2111 .init = pci_siig_init,
3ec9c594 2112 .setup = pci_siig_setup,
1da177e4
LT		 2113 },
2114 /*
2115 * Titan cards
2116 */
2117 {
2118 .vendor = PCI_VENDOR_ID_TITAN,
2119 .device = PCI_DEVICE_ID_TITAN_400L,
2120 .subvendor = PCI_ANY_ID,
2121 .subdevice = PCI_ANY_ID,
2122 .setup = titan_400l_800l_setup,
2123 },
2124 {
2125 .vendor = PCI_VENDOR_ID_TITAN,
2126 .device = PCI_DEVICE_ID_TITAN_800L,
2127 .subvendor = PCI_ANY_ID,
2128 .subdevice = PCI_ANY_ID,
2129 .setup = titan_400l_800l_setup,
2130 },
2131 /*
2132 * Timedia cards
2133 */
2134 {
2135 .vendor = PCI_VENDOR_ID_TIMEDIA,
2136 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2137 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2138 .subdevice = PCI_ANY_ID,
b9b24558 2139 .probe = pci_timedia_probe,
1da177e4
LT		 2140 .init = pci_timedia_init,
2141 .setup = pci_timedia_setup,
2142 },
2143 {
2144 .vendor = PCI_VENDOR_ID_TIMEDIA,
2145 .device = PCI_ANY_ID,
2146 .subvendor = PCI_ANY_ID,
2147 .subdevice = PCI_ANY_ID,
2148 .setup = pci_timedia_setup,
2149 },
abd7baca
SC		 2150 /*
2151 * SUNIX (Timedia) cards
2152 * Do not "probe" for these cards as there is at least one combination
2153 * card that should be handled by parport_pc that doesn't match the
2154 * rule in pci_timedia_probe.
2155 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2156 * There are some boards with part number SER5037AL that report
2157 * subdevice ID 0x0002.
2158 */
2159 {
2160 .vendor = PCI_VENDOR_ID_SUNIX,
2161 .device = PCI_DEVICE_ID_SUNIX_1999,
2162 .subvendor = PCI_VENDOR_ID_SUNIX,
2163 .subdevice = PCI_ANY_ID,
2164 .init = pci_timedia_init,
2165 .setup = pci_timedia_setup,
2166 },
06315348
SH		 2167 /*
2168 * Exar cards
2169 */
2170 {
2171 .vendor = PCI_VENDOR_ID_EXAR,
2172 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2173 .subvendor = PCI_ANY_ID,
2174 .subdevice = PCI_ANY_ID,
2175 .setup = pci_xr17c154_setup,
2176 },
2177 {
2178 .vendor = PCI_VENDOR_ID_EXAR,
2179 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2180 .subvendor = PCI_ANY_ID,
2181 .subdevice = PCI_ANY_ID,
2182 .setup = pci_xr17c154_setup,
2183 },
2184 {
2185 .vendor = PCI_VENDOR_ID_EXAR,
2186 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2187 .subvendor = PCI_ANY_ID,
2188 .subdevice = PCI_ANY_ID,
2189 .setup = pci_xr17c154_setup,
2190 },
dc96efb7
MS		 2191 {
2192 .vendor = PCI_VENDOR_ID_EXAR,
2193 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .setup = pci_xr17v35x_setup,
2197 },
2198 {
2199 .vendor = PCI_VENDOR_ID_EXAR,
2200 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .setup = pci_xr17v35x_setup,
2204 },
2205 {
2206 .vendor = PCI_VENDOR_ID_EXAR,
2207 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2208 .subvendor = PCI_ANY_ID,
2209 .subdevice = PCI_ANY_ID,
2210 .setup = pci_xr17v35x_setup,
2211 },
1da177e4
LT		 2212 /*
2213 * Xircom cards
2214 */
2215 {
2216 .vendor = PCI_VENDOR_ID_XIRCOM,
2217 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2218 .subvendor = PCI_ANY_ID,
2219 .subdevice = PCI_ANY_ID,
2220 .init = pci_xircom_init,
2221 .setup = pci_default_setup,
2222 },
2223 /*
61a116ef 2224 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2225 */
2226 {
2227 .vendor = PCI_VENDOR_ID_NETMOS,
2228 .device = PCI_ANY_ID,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .init = pci_netmos_init,
7808edcd 2232 .setup = pci_netmos_9900_setup,
1da177e4 2233 },
9f2a036a 2234 /*
aa273ae5 2235 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2236 */
2237 {
2238 .vendor = PCI_VENDOR_ID_OXSEMI,
2239 .device = PCI_ANY_ID,
2240 .subvendor = PCI_ANY_ID,
2241 .subdevice = PCI_ANY_ID,
2242 .init = pci_oxsemi_tornado_init,
2243 .setup = pci_default_setup,
2244 },
2245 {
2246 .vendor = PCI_VENDOR_ID_MAINPINE,
2247 .device = PCI_ANY_ID,
2248 .subvendor = PCI_ANY_ID,
2249 .subdevice = PCI_ANY_ID,
2250 .init = pci_oxsemi_tornado_init,
2251 .setup = pci_default_setup,
2252 },
aa273ae5
SK		 2253 {
2254 .vendor = PCI_VENDOR_ID_DIGI,
2255 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2256 .subvendor = PCI_SUBVENDOR_ID_IBM,
2257 .subdevice = PCI_ANY_ID,
2258 .init = pci_oxsemi_tornado_init,
2259 .setup = pci_default_setup,
2260 },
eb7073db
TM		 2261 {
2262 .vendor = PCI_VENDOR_ID_INTEL,
2263 .device = 0x8811,
aaa10eb1
AP		 2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
eb7073db 2266 .init = pci_eg20t_init,
64d91cfa 2267 .setup = pci_default_setup,
eb7073db
TM		 2268 },
2269 {
2270 .vendor = PCI_VENDOR_ID_INTEL,
2271 .device = 0x8812,
aaa10eb1
AP		 2272 .subvendor = PCI_ANY_ID,
2273 .subdevice = PCI_ANY_ID,
eb7073db 2274 .init = pci_eg20t_init,
64d91cfa 2275 .setup = pci_default_setup,
eb7073db
TM		 2276 },
2277 {
2278 .vendor = PCI_VENDOR_ID_INTEL,
2279 .device = 0x8813,
aaa10eb1
AP		 2280 .subvendor = PCI_ANY_ID,
2281 .subdevice = PCI_ANY_ID,
eb7073db 2282 .init = pci_eg20t_init,
64d91cfa 2283 .setup = pci_default_setup,
eb7073db
TM		 2284 },
2285 {
2286 .vendor = PCI_VENDOR_ID_INTEL,
2287 .device = 0x8814,
aaa10eb1
AP		 2288 .subvendor = PCI_ANY_ID,
2289 .subdevice = PCI_ANY_ID,
eb7073db 2290 .init = pci_eg20t_init,
64d91cfa 2291 .setup = pci_default_setup,
eb7073db
TM		 2292 },
2293 {
2294 .vendor = 0x10DB,
2295 .device = 0x8027,
aaa10eb1
AP		 2296 .subvendor = PCI_ANY_ID,
2297 .subdevice = PCI_ANY_ID,
eb7073db 2298 .init = pci_eg20t_init,
64d91cfa 2299 .setup = pci_default_setup,
eb7073db
TM		 2300 },
2301 {
2302 .vendor = 0x10DB,
2303 .device = 0x8028,
aaa10eb1
AP		 2304 .subvendor = PCI_ANY_ID,
2305 .subdevice = PCI_ANY_ID,
eb7073db 2306 .init = pci_eg20t_init,
64d91cfa 2307 .setup = pci_default_setup,
eb7073db
TM		 2308 },
2309 {
2310 .vendor = 0x10DB,
2311 .device = 0x8029,
aaa10eb1
AP		 2312 .subvendor = PCI_ANY_ID,
2313 .subdevice = PCI_ANY_ID,
eb7073db 2314 .init = pci_eg20t_init,
64d91cfa 2315 .setup = pci_default_setup,
eb7073db
TM		 2316 },
2317 {
2318 .vendor = 0x10DB,
2319 .device = 0x800C,
aaa10eb1
AP		 2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
eb7073db 2322 .init = pci_eg20t_init,
64d91cfa 2323 .setup = pci_default_setup,
eb7073db
TM		 2324 },
2325 {
2326 .vendor = 0x10DB,
2327 .device = 0x800D,
aaa10eb1
AP		 2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
eb7073db 2330 .init = pci_eg20t_init,
64d91cfa 2331 .setup = pci_default_setup,
eb7073db 2332 },
d9a0fbfd
AP		 2333 /*
2334 * Cronyx Omega PCI (PLX-chip based)
2335 */
2336 {
2337 .vendor = PCI_VENDOR_ID_PLX,
2338 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2339 .subvendor = PCI_ANY_ID,
2340 .subdevice = PCI_ANY_ID,
2341 .setup = pci_omegapci_setup,
eb26dfe8 2342 },
6971c635
GA		 2343 /* WCH CH353 2S1P card (16550 clone) */
2344 {
27788c5f
AC		 2345 .vendor = PCI_VENDOR_ID_WCH,
2346 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2347 .subvendor = PCI_ANY_ID,
2348 .subdevice = PCI_ANY_ID,
2349 .setup = pci_wch_ch353_setup,
2350 },
2351 /* WCH CH353 4S card (16550 clone) */
2352 {
2353 .vendor = PCI_VENDOR_ID_WCH,
2354 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2355 .subvendor = PCI_ANY_ID,
2356 .subdevice = PCI_ANY_ID,
2357 .setup = pci_wch_ch353_setup,
2358 },
2359 /* WCH CH353 2S1PF card (16550 clone) */
2360 {
2361 .vendor = PCI_VENDOR_ID_WCH,
2362 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2363 .subvendor = PCI_ANY_ID,
2364 .subdevice = PCI_ANY_ID,
6971c635
GA		 2365 .setup = pci_wch_ch353_setup,
2366 },
8b5c913f
WY		 2367 /* WCH CH352 2S card (16550 clone) */
2368 {
2369 .vendor = PCI_VENDOR_ID_WCH,
2370 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2371 .subvendor = PCI_ANY_ID,
2372 .subdevice = PCI_ANY_ID,
2373 .setup = pci_wch_ch353_setup,
2374 },
eb26dfe8
AC		 2375 /*
2376 * ASIX devices with FIFO bug
2377 */
2378 {
2379 .vendor = PCI_VENDOR_ID_ASIX,
2380 .device = PCI_ANY_ID,
2381 .subvendor = PCI_ANY_ID,
2382 .subdevice = PCI_ANY_ID,
2383 .setup = pci_asix_setup,
2384 },
14faa8cc
MS		 2385 /*
2386 * Commtech, Inc. Fastcom adapters
2387 *
2388 */
2389 {
2390 .vendor = PCI_VENDOR_ID_COMMTECH,
2391 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2392 .subvendor = PCI_ANY_ID,
2393 .subdevice = PCI_ANY_ID,
2394 .setup = pci_fastcom335_setup,
2395 },
2396 {
2397 .vendor = PCI_VENDOR_ID_COMMTECH,
2398 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2399 .subvendor = PCI_ANY_ID,
2400 .subdevice = PCI_ANY_ID,
2401 .setup = pci_fastcom335_setup,
2402 },
2403 {
2404 .vendor = PCI_VENDOR_ID_COMMTECH,
2405 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2406 .subvendor = PCI_ANY_ID,
2407 .subdevice = PCI_ANY_ID,
2408 .setup = pci_fastcom335_setup,
2409 },
2410 {
2411 .vendor = PCI_VENDOR_ID_COMMTECH,
2412 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2413 .subvendor = PCI_ANY_ID,
2414 .subdevice = PCI_ANY_ID,
2415 .setup = pci_fastcom335_setup,
2416 },
2417 {
2418 .vendor = PCI_VENDOR_ID_COMMTECH,
2419 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2420 .subvendor = PCI_ANY_ID,
2421 .subdevice = PCI_ANY_ID,
2422 .setup = pci_xr17v35x_setup,
2423 },
2424 {
2425 .vendor = PCI_VENDOR_ID_COMMTECH,
2426 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2427 .subvendor = PCI_ANY_ID,
2428 .subdevice = PCI_ANY_ID,
2429 .setup = pci_xr17v35x_setup,
2430 },
2431 {
2432 .vendor = PCI_VENDOR_ID_COMMTECH,
2433 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2434 .subvendor = PCI_ANY_ID,
2435 .subdevice = PCI_ANY_ID,
2436 .setup = pci_xr17v35x_setup,
2437 },
ebebd49a
SH		 2438 /*
2439 * Broadcom TruManage (NetXtreme)
2440 */
2441 {
2442 .vendor = PCI_VENDOR_ID_BROADCOM,
2443 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2444 .subvendor = PCI_ANY_ID,
2445 .subdevice = PCI_ANY_ID,
2446 .setup = pci_brcm_trumanage_setup,
2447 },
2c62a3c8
GKH		 2448 {
2449 .vendor = 0x1c29,
2450 .device = 0x1104,
2451 .subvendor = PCI_ANY_ID,
2452 .subdevice = PCI_ANY_ID,
2453 .setup = pci_fintek_setup,
2454 },
2455 {
2456 .vendor = 0x1c29,
2457 .device = 0x1108,
2458 .subvendor = PCI_ANY_ID,
2459 .subdevice = PCI_ANY_ID,
2460 .setup = pci_fintek_setup,
2461 },
2462 {
2463 .vendor = 0x1c29,
2464 .device = 0x1112,
2465 .subvendor = PCI_ANY_ID,
2466 .subdevice = PCI_ANY_ID,
2467 .setup = pci_fintek_setup,
2468 },
ebebd49a 2469
1da177e4
LT		 2470 /*
2471 * Default "match everything" terminator entry
2472 */
2473 {
2474 .vendor = PCI_ANY_ID,
2475 .device = PCI_ANY_ID,
2476 .subvendor = PCI_ANY_ID,
2477 .subdevice = PCI_ANY_ID,
2478 .setup = pci_default_setup,
2479 }
2480};
2481
2482static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2483{
2484 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2485}
2486
2487static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2488{
2489 struct pci_serial_quirk *quirk;
2490
2491 for (quirk = pci_serial_quirks; ; quirk++)
2492 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2493 quirk_id_matches(quirk->device, dev->device) &&
2494 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2495 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2496 break;
1da177e4
LT		 2497 return quirk;
2498}
2499
dd68e88c 2500static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2501 const struct pciserial_board *board)
1da177e4
LT		 2502{
2503 if (board->flags & FL_NOIRQ)
2504 return 0;
2505 else
2506 return dev->irq;
2507}
2508
2509/*
2510 * This is the configuration table for all of the PCI serial boards
2511 * which we support. It is directly indexed by the pci_board_num_t enum
2512 * value, which is encoded in the pci_device_id PCI probe table's
2513 * driver_data member.
2514 *
2515 * The makeup of these names are:
26e92861 2516 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2517 *
26e92861
GH		 2518 * bn = PCI BAR number
2519 * bt = Index using PCI BARs
2520 * n = number of serial ports
2521 * baud = baud rate
2522 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2523 *
26e92861 2524 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2525 *
1da177e4
LT		 2526 * Please note: in theory if n = 1, _bt infix should make no difference.
2527 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2528 */
2529enum pci_board_num_t {
2530 pbn_default = 0,
2531
2532 pbn_b0_1_115200,
2533 pbn_b0_2_115200,
2534 pbn_b0_4_115200,
2535 pbn_b0_5_115200,
bf0df636 2536 pbn_b0_8_115200,
1da177e4
LT		 2537
2538 pbn_b0_1_921600,
2539 pbn_b0_2_921600,
2540 pbn_b0_4_921600,
2541
db1de159
DR		 2542 pbn_b0_2_1130000,
2543
fbc0dc0d
AP		 2544 pbn_b0_4_1152000,
2545
14faa8cc
MS		 2546 pbn_b0_2_1152000_200,
2547 pbn_b0_4_1152000_200,
2548 pbn_b0_8_1152000_200,
2549
26e92861
GH		 2550 pbn_b0_2_1843200,
2551 pbn_b0_4_1843200,
2552
2553 pbn_b0_2_1843200_200,
2554 pbn_b0_4_1843200_200,
2555 pbn_b0_8_1843200_200,
2556
7106b4e3
LH		 2557 pbn_b0_1_4000000,
2558
1da177e4
LT		 2559 pbn_b0_bt_1_115200,
2560 pbn_b0_bt_2_115200,
ac6ec5b1 2561 pbn_b0_bt_4_115200,
1da177e4
LT		 2562 pbn_b0_bt_8_115200,
2563
2564 pbn_b0_bt_1_460800,
2565 pbn_b0_bt_2_460800,
2566 pbn_b0_bt_4_460800,
2567
2568 pbn_b0_bt_1_921600,
2569 pbn_b0_bt_2_921600,
2570 pbn_b0_bt_4_921600,
2571 pbn_b0_bt_8_921600,
2572
2573 pbn_b1_1_115200,
2574 pbn_b1_2_115200,
2575 pbn_b1_4_115200,
2576 pbn_b1_8_115200,
04bf7e74 2577 pbn_b1_16_115200,
1da177e4
LT		 2578
2579 pbn_b1_1_921600,
2580 pbn_b1_2_921600,
2581 pbn_b1_4_921600,
2582 pbn_b1_8_921600,
2583
26e92861
GH		 2584 pbn_b1_2_1250000,
2585
84f8c6fc 2586 pbn_b1_bt_1_115200,
04bf7e74
WP		 2587 pbn_b1_bt_2_115200,
2588 pbn_b1_bt_4_115200,
2589
1da177e4
LT		 2590 pbn_b1_bt_2_921600,
2591
2592 pbn_b1_1_1382400,
2593 pbn_b1_2_1382400,
2594 pbn_b1_4_1382400,
2595 pbn_b1_8_1382400,
2596
2597 pbn_b2_1_115200,
737c1756 2598 pbn_b2_2_115200,
a9cccd34 2599 pbn_b2_4_115200,
1da177e4
LT		 2600 pbn_b2_8_115200,
2601
2602 pbn_b2_1_460800,
2603 pbn_b2_4_460800,
2604 pbn_b2_8_460800,
2605 pbn_b2_16_460800,
2606
2607 pbn_b2_1_921600,
2608 pbn_b2_4_921600,
2609 pbn_b2_8_921600,
2610
e847003f
LB		 2611 pbn_b2_8_1152000,
2612
1da177e4
LT		 2613 pbn_b2_bt_1_115200,
2614 pbn_b2_bt_2_115200,
2615 pbn_b2_bt_4_115200,
2616
2617 pbn_b2_bt_2_921600,
2618 pbn_b2_bt_4_921600,
2619
d9004eb4 2620 pbn_b3_2_115200,
1da177e4
LT		 2621 pbn_b3_4_115200,
2622 pbn_b3_8_115200,
2623
66169ad1
YY		 2624 pbn_b4_bt_2_921600,
2625 pbn_b4_bt_4_921600,
2626 pbn_b4_bt_8_921600,
2627
1da177e4
LT		 2628 /*
2629 * Board-specific versions.
2630 */
2631 pbn_panacom,
2632 pbn_panacom2,
2633 pbn_panacom4,
2634 pbn_plx_romulus,
2635 pbn_oxsemi,
7106b4e3
LH		 2636 pbn_oxsemi_1_4000000,
2637 pbn_oxsemi_2_4000000,
2638 pbn_oxsemi_4_4000000,
2639 pbn_oxsemi_8_4000000,
1da177e4
LT		 2640 pbn_intel_i960,
2641 pbn_sgi_ioc3,
1da177e4
LT		 2642 pbn_computone_4,
2643 pbn_computone_6,
2644 pbn_computone_8,
2645 pbn_sbsxrsio,
2646 pbn_exar_XR17C152,
2647 pbn_exar_XR17C154,
2648 pbn_exar_XR17C158,
dc96efb7
MS		 2649 pbn_exar_XR17V352,
2650 pbn_exar_XR17V354,
2651 pbn_exar_XR17V358,
c68d2b15 2652 pbn_exar_ibm_saturn,
aa798505 2653 pbn_pasemi_1682M,
46a0fac9
SB		 2654 pbn_ni8430_2,
2655 pbn_ni8430_4,
2656 pbn_ni8430_8,
2657 pbn_ni8430_16,
1b62cbf2
KJ		 2658 pbn_ADDIDATA_PCIe_1_3906250,
2659 pbn_ADDIDATA_PCIe_2_3906250,
2660 pbn_ADDIDATA_PCIe_4_3906250,
2661 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2662 pbn_ce4100_1_115200,
b15e5691 2663 pbn_byt,
d9a0fbfd 2664 pbn_omegapci,
7808edcd 2665 pbn_NETMOS9900_2s_115200,
ebebd49a 2666 pbn_brcm_trumanage,
2c62a3c8
GKH		 2667 pbn_fintek_4,
2668 pbn_fintek_8,
2669 pbn_fintek_12,
1da177e4
LT		 2670};
2671
2672/*
2673 * uart_offset - the space between channels
2674 * reg_shift - describes how the UART registers are mapped
2675 * to PCI memory by the card.
2676 * For example IER register on SBS, Inc. PMC-OctPro is located at
2677 * offset 0x10 from the UART base, while UART_IER is defined as 1
2678 * in include/linux/serial_reg.h,
2679 * see first lines of serial_in() and serial_out() in 8250.c
2680*/
2681
de88b340 2682static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2683 [pbn_default] = {
2684 .flags = FL_BASE0,
2685 .num_ports = 1,
2686 .base_baud = 115200,
2687 .uart_offset = 8,
2688 },
2689 [pbn_b0_1_115200] = {
2690 .flags = FL_BASE0,
2691 .num_ports = 1,
2692 .base_baud = 115200,
2693 .uart_offset = 8,
2694 },
2695 [pbn_b0_2_115200] = {
2696 .flags = FL_BASE0,
2697 .num_ports = 2,
2698 .base_baud = 115200,
2699 .uart_offset = 8,
2700 },
2701 [pbn_b0_4_115200] = {
2702 .flags = FL_BASE0,
2703 .num_ports = 4,
2704 .base_baud = 115200,
2705 .uart_offset = 8,
2706 },
2707 [pbn_b0_5_115200] = {
2708 .flags = FL_BASE0,
2709 .num_ports = 5,
2710 .base_baud = 115200,
2711 .uart_offset = 8,
2712 },
bf0df636
AC		 2713 [pbn_b0_8_115200] = {
2714 .flags = FL_BASE0,
2715 .num_ports = 8,
2716 .base_baud = 115200,
2717 .uart_offset = 8,
2718 },
1da177e4
LT		 2719 [pbn_b0_1_921600] = {
2720 .flags = FL_BASE0,
2721 .num_ports = 1,
2722 .base_baud = 921600,
2723 .uart_offset = 8,
2724 },
2725 [pbn_b0_2_921600] = {
2726 .flags = FL_BASE0,
2727 .num_ports = 2,
2728 .base_baud = 921600,
2729 .uart_offset = 8,
2730 },
2731 [pbn_b0_4_921600] = {
2732 .flags = FL_BASE0,
2733 .num_ports = 4,
2734 .base_baud = 921600,
2735 .uart_offset = 8,
2736 },
db1de159
DR		 2737
2738 [pbn_b0_2_1130000] = {
2739 .flags = FL_BASE0,
2740 .num_ports = 2,
2741 .base_baud = 1130000,
2742 .uart_offset = 8,
2743 },
2744
fbc0dc0d
AP		 2745 [pbn_b0_4_1152000] = {
2746 .flags = FL_BASE0,
2747 .num_ports = 4,
2748 .base_baud = 1152000,
2749 .uart_offset = 8,
2750 },
1da177e4 2751
14faa8cc
MS		 2752 [pbn_b0_2_1152000_200] = {
2753 .flags = FL_BASE0,
2754 .num_ports = 2,
2755 .base_baud = 1152000,
2756 .uart_offset = 0x200,
2757 },
2758
2759 [pbn_b0_4_1152000_200] = {
2760 .flags = FL_BASE0,
2761 .num_ports = 4,
2762 .base_baud = 1152000,
2763 .uart_offset = 0x200,
2764 },
2765
2766 [pbn_b0_8_1152000_200] = {
2767 .flags = FL_BASE0,
4f7d67d0 2768 .num_ports = 8,
14faa8cc
MS		 2769 .base_baud = 1152000,
2770 .uart_offset = 0x200,
2771 },
2772
26e92861
GH		 2773 [pbn_b0_2_1843200] = {
2774 .flags = FL_BASE0,
2775 .num_ports = 2,
2776 .base_baud = 1843200,
2777 .uart_offset = 8,
2778 },
2779 [pbn_b0_4_1843200] = {
2780 .flags = FL_BASE0,
2781 .num_ports = 4,
2782 .base_baud = 1843200,
2783 .uart_offset = 8,
2784 },
2785
2786 [pbn_b0_2_1843200_200] = {
2787 .flags = FL_BASE0,
2788 .num_ports = 2,
2789 .base_baud = 1843200,
2790 .uart_offset = 0x200,
2791 },
2792 [pbn_b0_4_1843200_200] = {
2793 .flags = FL_BASE0,
2794 .num_ports = 4,
2795 .base_baud = 1843200,
2796 .uart_offset = 0x200,
2797 },
2798 [pbn_b0_8_1843200_200] = {
2799 .flags = FL_BASE0,
2800 .num_ports = 8,
2801 .base_baud = 1843200,
2802 .uart_offset = 0x200,
2803 },
7106b4e3
LH		 2804 [pbn_b0_1_4000000] = {
2805 .flags = FL_BASE0,
2806 .num_ports = 1,
2807 .base_baud = 4000000,
2808 .uart_offset = 8,
2809 },
26e92861 2810
1da177e4
LT		 2811 [pbn_b0_bt_1_115200] = {
2812 .flags = FL_BASE0|FL_BASE_BARS,
2813 .num_ports = 1,
2814 .base_baud = 115200,
2815 .uart_offset = 8,
2816 },
2817 [pbn_b0_bt_2_115200] = {
2818 .flags = FL_BASE0|FL_BASE_BARS,
2819 .num_ports = 2,
2820 .base_baud = 115200,
2821 .uart_offset = 8,
2822 },
ac6ec5b1
IS		 2823 [pbn_b0_bt_4_115200] = {
2824 .flags = FL_BASE0|FL_BASE_BARS,
2825 .num_ports = 4,
2826 .base_baud = 115200,
2827 .uart_offset = 8,
2828 },
1da177e4
LT		 2829 [pbn_b0_bt_8_115200] = {
2830 .flags = FL_BASE0|FL_BASE_BARS,
2831 .num_ports = 8,
2832 .base_baud = 115200,
2833 .uart_offset = 8,
2834 },
2835
2836 [pbn_b0_bt_1_460800] = {
2837 .flags = FL_BASE0|FL_BASE_BARS,
2838 .num_ports = 1,
2839 .base_baud = 460800,
2840 .uart_offset = 8,
2841 },
2842 [pbn_b0_bt_2_460800] = {
2843 .flags = FL_BASE0|FL_BASE_BARS,
2844 .num_ports = 2,
2845 .base_baud = 460800,
2846 .uart_offset = 8,
2847 },
2848 [pbn_b0_bt_4_460800] = {
2849 .flags = FL_BASE0|FL_BASE_BARS,
2850 .num_ports = 4,
2851 .base_baud = 460800,
2852 .uart_offset = 8,
2853 },
2854
2855 [pbn_b0_bt_1_921600] = {
2856 .flags = FL_BASE0|FL_BASE_BARS,
2857 .num_ports = 1,
2858 .base_baud = 921600,
2859 .uart_offset = 8,
2860 },
2861 [pbn_b0_bt_2_921600] = {
2862 .flags = FL_BASE0|FL_BASE_BARS,
2863 .num_ports = 2,
2864 .base_baud = 921600,
2865 .uart_offset = 8,
2866 },
2867 [pbn_b0_bt_4_921600] = {
2868 .flags = FL_BASE0|FL_BASE_BARS,
2869 .num_ports = 4,
2870 .base_baud = 921600,
2871 .uart_offset = 8,
2872 },
2873 [pbn_b0_bt_8_921600] = {
2874 .flags = FL_BASE0|FL_BASE_BARS,
2875 .num_ports = 8,
2876 .base_baud = 921600,
2877 .uart_offset = 8,
2878 },
2879
2880 [pbn_b1_1_115200] = {
2881 .flags = FL_BASE1,
2882 .num_ports = 1,
2883 .base_baud = 115200,
2884 .uart_offset = 8,
2885 },
2886 [pbn_b1_2_115200] = {
2887 .flags = FL_BASE1,
2888 .num_ports = 2,
2889 .base_baud = 115200,
2890 .uart_offset = 8,
2891 },
2892 [pbn_b1_4_115200] = {
2893 .flags = FL_BASE1,
2894 .num_ports = 4,
2895 .base_baud = 115200,
2896 .uart_offset = 8,
2897 },
2898 [pbn_b1_8_115200] = {
2899 .flags = FL_BASE1,
2900 .num_ports = 8,
2901 .base_baud = 115200,
2902 .uart_offset = 8,
2903 },
04bf7e74
WP		 2904 [pbn_b1_16_115200] = {
2905 .flags = FL_BASE1,
2906 .num_ports = 16,
2907 .base_baud = 115200,
2908 .uart_offset = 8,
2909 },
1da177e4
LT		 2910
2911 [pbn_b1_1_921600] = {
2912 .flags = FL_BASE1,
2913 .num_ports = 1,
2914 .base_baud = 921600,
2915 .uart_offset = 8,
2916 },
2917 [pbn_b1_2_921600] = {
2918 .flags = FL_BASE1,
2919 .num_ports = 2,
2920 .base_baud = 921600,
2921 .uart_offset = 8,
2922 },
2923 [pbn_b1_4_921600] = {
2924 .flags = FL_BASE1,
2925 .num_ports = 4,
2926 .base_baud = 921600,
2927 .uart_offset = 8,
2928 },
2929 [pbn_b1_8_921600] = {
2930 .flags = FL_BASE1,
2931 .num_ports = 8,
2932 .base_baud = 921600,
2933 .uart_offset = 8,
2934 },
26e92861
GH		 2935 [pbn_b1_2_1250000] = {
2936 .flags = FL_BASE1,
2937 .num_ports = 2,
2938 .base_baud = 1250000,
2939 .uart_offset = 8,
2940 },
1da177e4 2941
84f8c6fc
NV		 2942 [pbn_b1_bt_1_115200] = {
2943 .flags = FL_BASE1|FL_BASE_BARS,
2944 .num_ports = 1,
2945 .base_baud = 115200,
2946 .uart_offset = 8,
2947 },
04bf7e74
WP		 2948 [pbn_b1_bt_2_115200] = {
2949 .flags = FL_BASE1|FL_BASE_BARS,
2950 .num_ports = 2,
2951 .base_baud = 115200,
2952 .uart_offset = 8,
2953 },
2954 [pbn_b1_bt_4_115200] = {
2955 .flags = FL_BASE1|FL_BASE_BARS,
2956 .num_ports = 4,
2957 .base_baud = 115200,
2958 .uart_offset = 8,
2959 },
84f8c6fc 2960
1da177e4
LT		 2961 [pbn_b1_bt_2_921600] = {
2962 .flags = FL_BASE1|FL_BASE_BARS,
2963 .num_ports = 2,
2964 .base_baud = 921600,
2965 .uart_offset = 8,
2966 },
2967
2968 [pbn_b1_1_1382400] = {
2969 .flags = FL_BASE1,
2970 .num_ports = 1,
2971 .base_baud = 1382400,
2972 .uart_offset = 8,
2973 },
2974 [pbn_b1_2_1382400] = {
2975 .flags = FL_BASE1,
2976 .num_ports = 2,
2977 .base_baud = 1382400,
2978 .uart_offset = 8,
2979 },
2980 [pbn_b1_4_1382400] = {
2981 .flags = FL_BASE1,
2982 .num_ports = 4,
2983 .base_baud = 1382400,
2984 .uart_offset = 8,
2985 },
2986 [pbn_b1_8_1382400] = {
2987 .flags = FL_BASE1,
2988 .num_ports = 8,
2989 .base_baud = 1382400,
2990 .uart_offset = 8,
2991 },
2992
2993 [pbn_b2_1_115200] = {
2994 .flags = FL_BASE2,
2995 .num_ports = 1,
2996 .base_baud = 115200,
2997 .uart_offset = 8,
2998 },
737c1756
PH		 2999 [pbn_b2_2_115200] = {
3000 .flags = FL_BASE2,
3001 .num_ports = 2,
3002 .base_baud = 115200,
3003 .uart_offset = 8,
3004 },
a9cccd34
MF		 3005 [pbn_b2_4_115200] = {
3006 .flags = FL_BASE2,
3007 .num_ports = 4,
3008 .base_baud = 115200,
3009 .uart_offset = 8,
3010 },
1da177e4
LT		 3011 [pbn_b2_8_115200] = {
3012 .flags = FL_BASE2,
3013 .num_ports = 8,
3014 .base_baud = 115200,
3015 .uart_offset = 8,
3016 },
3017
3018 [pbn_b2_1_460800] = {
3019 .flags = FL_BASE2,
3020 .num_ports = 1,
3021 .base_baud = 460800,
3022 .uart_offset = 8,
3023 },
3024 [pbn_b2_4_460800] = {
3025 .flags = FL_BASE2,
3026 .num_ports = 4,
3027 .base_baud = 460800,
3028 .uart_offset = 8,
3029 },
3030 [pbn_b2_8_460800] = {
3031 .flags = FL_BASE2,
3032 .num_ports = 8,
3033 .base_baud = 460800,
3034 .uart_offset = 8,
3035 },
3036 [pbn_b2_16_460800] = {
3037 .flags = FL_BASE2,
3038 .num_ports = 16,
3039 .base_baud = 460800,
3040 .uart_offset = 8,
3041 },
3042
3043 [pbn_b2_1_921600] = {
3044 .flags = FL_BASE2,
3045 .num_ports = 1,
3046 .base_baud = 921600,
3047 .uart_offset = 8,
3048 },
3049 [pbn_b2_4_921600] = {
3050 .flags = FL_BASE2,
3051 .num_ports = 4,
3052 .base_baud = 921600,
3053 .uart_offset = 8,
3054 },
3055 [pbn_b2_8_921600] = {
3056 .flags = FL_BASE2,
3057 .num_ports = 8,
3058 .base_baud = 921600,
3059 .uart_offset = 8,
3060 },
3061
e847003f
LB		 3062 [pbn_b2_8_1152000] = {
3063 .flags = FL_BASE2,
3064 .num_ports = 8,
3065 .base_baud = 1152000,
3066 .uart_offset = 8,
3067 },
3068
1da177e4
LT		 3069 [pbn_b2_bt_1_115200] = {
3070 .flags = FL_BASE2|FL_BASE_BARS,
3071 .num_ports = 1,
3072 .base_baud = 115200,
3073 .uart_offset = 8,
3074 },
3075 [pbn_b2_bt_2_115200] = {
3076 .flags = FL_BASE2|FL_BASE_BARS,
3077 .num_ports = 2,
3078 .base_baud = 115200,
3079 .uart_offset = 8,
3080 },
3081 [pbn_b2_bt_4_115200] = {
3082 .flags = FL_BASE2|FL_BASE_BARS,
3083 .num_ports = 4,
3084 .base_baud = 115200,
3085 .uart_offset = 8,
3086 },
3087
3088 [pbn_b2_bt_2_921600] = {
3089 .flags = FL_BASE2|FL_BASE_BARS,
3090 .num_ports = 2,
3091 .base_baud = 921600,
3092 .uart_offset = 8,
3093 },
3094 [pbn_b2_bt_4_921600] = {
3095 .flags = FL_BASE2|FL_BASE_BARS,
3096 .num_ports = 4,
3097 .base_baud = 921600,
3098 .uart_offset = 8,
3099 },
3100
d9004eb4
ABL		 3101 [pbn_b3_2_115200] = {
3102 .flags = FL_BASE3,
3103 .num_ports = 2,
3104 .base_baud = 115200,
3105 .uart_offset = 8,
3106 },
1da177e4
LT		 3107 [pbn_b3_4_115200] = {
3108 .flags = FL_BASE3,
3109 .num_ports = 4,
3110 .base_baud = 115200,
3111 .uart_offset = 8,
3112 },
3113 [pbn_b3_8_115200] = {
3114 .flags = FL_BASE3,
3115 .num_ports = 8,
3116 .base_baud = 115200,
3117 .uart_offset = 8,
3118 },
3119
66169ad1
YY		 3120 [pbn_b4_bt_2_921600] = {
3121 .flags = FL_BASE4,
3122 .num_ports = 2,
3123 .base_baud = 921600,
3124 .uart_offset = 8,
3125 },
3126 [pbn_b4_bt_4_921600] = {
3127 .flags = FL_BASE4,
3128 .num_ports = 4,
3129 .base_baud = 921600,
3130 .uart_offset = 8,
3131 },
3132 [pbn_b4_bt_8_921600] = {
3133 .flags = FL_BASE4,
3134 .num_ports = 8,
3135 .base_baud = 921600,
3136 .uart_offset = 8,
3137 },
3138
1da177e4
LT		 3139 /*
3140 * Entries following this are board-specific.
3141 */
3142
3143 /*
3144 * Panacom - IOMEM
3145 */
3146 [pbn_panacom] = {
3147 .flags = FL_BASE2,
3148 .num_ports = 2,
3149 .base_baud = 921600,
3150 .uart_offset = 0x400,
3151 .reg_shift = 7,
3152 },
3153 [pbn_panacom2] = {
3154 .flags = FL_BASE2|FL_BASE_BARS,
3155 .num_ports = 2,
3156 .base_baud = 921600,
3157 .uart_offset = 0x400,
3158 .reg_shift = 7,
3159 },
3160 [pbn_panacom4] = {
3161 .flags = FL_BASE2|FL_BASE_BARS,
3162 .num_ports = 4,
3163 .base_baud = 921600,
3164 .uart_offset = 0x400,
3165 .reg_shift = 7,
3166 },
3167
3168 /* I think this entry is broken - the first_offset looks wrong --rmk */
3169 [pbn_plx_romulus] = {
3170 .flags = FL_BASE2,
3171 .num_ports = 4,
3172 .base_baud = 921600,
3173 .uart_offset = 8 << 2,
3174 .reg_shift = 2,
3175 .first_offset = 0x03,
3176 },
3177
3178 /*
3179 * This board uses the size of PCI Base region 0 to
3180 * signal now many ports are available
3181 */
3182 [pbn_oxsemi] = {
3183 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3184 .num_ports = 32,
3185 .base_baud = 115200,
3186 .uart_offset = 8,
3187 },
7106b4e3
LH		 3188 [pbn_oxsemi_1_4000000] = {
3189 .flags = FL_BASE0,
3190 .num_ports = 1,
3191 .base_baud = 4000000,
3192 .uart_offset = 0x200,
3193 .first_offset = 0x1000,
3194 },
3195 [pbn_oxsemi_2_4000000] = {
3196 .flags = FL_BASE0,
3197 .num_ports = 2,
3198 .base_baud = 4000000,
3199 .uart_offset = 0x200,
3200 .first_offset = 0x1000,
3201 },
3202 [pbn_oxsemi_4_4000000] = {
3203 .flags = FL_BASE0,
3204 .num_ports = 4,
3205 .base_baud = 4000000,
3206 .uart_offset = 0x200,
3207 .first_offset = 0x1000,
3208 },
3209 [pbn_oxsemi_8_4000000] = {
3210 .flags = FL_BASE0,
3211 .num_ports = 8,
3212 .base_baud = 4000000,
3213 .uart_offset = 0x200,
3214 .first_offset = 0x1000,
3215 },
3216
1da177e4
LT		 3217
3218 /*
3219 * EKF addition for i960 Boards form EKF with serial port.
3220 * Max 256 ports.
3221 */
3222 [pbn_intel_i960] = {
3223 .flags = FL_BASE0,
3224 .num_ports = 32,
3225 .base_baud = 921600,
3226 .uart_offset = 8 << 2,
3227 .reg_shift = 2,
3228 .first_offset = 0x10000,
3229 },
3230 [pbn_sgi_ioc3] = {
3231 .flags = FL_BASE0|FL_NOIRQ,
3232 .num_ports = 1,
3233 .base_baud = 458333,
3234 .uart_offset = 8,
3235 .reg_shift = 0,
3236 .first_offset = 0x20178,
3237 },
3238
1da177e4
LT		 3239 /*
3240 * Computone - uses IOMEM.
3241 */
3242 [pbn_computone_4] = {
3243 .flags = FL_BASE0,
3244 .num_ports = 4,
3245 .base_baud = 921600,
3246 .uart_offset = 0x40,
3247 .reg_shift = 2,
3248 .first_offset = 0x200,
3249 },
3250 [pbn_computone_6] = {
3251 .flags = FL_BASE0,
3252 .num_ports = 6,
3253 .base_baud = 921600,
3254 .uart_offset = 0x40,
3255 .reg_shift = 2,
3256 .first_offset = 0x200,
3257 },
3258 [pbn_computone_8] = {
3259 .flags = FL_BASE0,
3260 .num_ports = 8,
3261 .base_baud = 921600,
3262 .uart_offset = 0x40,
3263 .reg_shift = 2,
3264 .first_offset = 0x200,
3265 },
3266 [pbn_sbsxrsio] = {
3267 .flags = FL_BASE0,
3268 .num_ports = 8,
3269 .base_baud = 460800,
3270 .uart_offset = 256,
3271 .reg_shift = 4,
3272 },
3273 /*
3274 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3275 * Only basic 16550A support.
3276 * XR17C15[24] are not tested, but they should work.
3277 */
3278 [pbn_exar_XR17C152] = {
3279 .flags = FL_BASE0,
3280 .num_ports = 2,
3281 .base_baud = 921600,
3282 .uart_offset = 0x200,
3283 },
3284 [pbn_exar_XR17C154] = {
3285 .flags = FL_BASE0,
3286 .num_ports = 4,
3287 .base_baud = 921600,
3288 .uart_offset = 0x200,
3289 },
3290 [pbn_exar_XR17C158] = {
3291 .flags = FL_BASE0,
3292 .num_ports = 8,
3293 .base_baud = 921600,
3294 .uart_offset = 0x200,
3295 },
dc96efb7
MS		 3296 [pbn_exar_XR17V352] = {
3297 .flags = FL_BASE0,
3298 .num_ports = 2,
3299 .base_baud = 7812500,
3300 .uart_offset = 0x400,
3301 .reg_shift = 0,
3302 .first_offset = 0,
3303 },
3304 [pbn_exar_XR17V354] = {
3305 .flags = FL_BASE0,
3306 .num_ports = 4,
3307 .base_baud = 7812500,
3308 .uart_offset = 0x400,
3309 .reg_shift = 0,
3310 .first_offset = 0,
3311 },
3312 [pbn_exar_XR17V358] = {
3313 .flags = FL_BASE0,
3314 .num_ports = 8,
3315 .base_baud = 7812500,
3316 .uart_offset = 0x400,
3317 .reg_shift = 0,
3318 .first_offset = 0,
3319 },
c68d2b15
BH		 3320 [pbn_exar_ibm_saturn] = {
3321 .flags = FL_BASE0,
3322 .num_ports = 1,
3323 .base_baud = 921600,
3324 .uart_offset = 0x200,
3325 },
3326
aa798505
OJ		 3327 /*
3328 * PA Semi PWRficient PA6T-1682M on-chip UART
3329 */
3330 [pbn_pasemi_1682M] = {
3331 .flags = FL_BASE0,
3332 .num_ports = 1,
3333 .base_baud = 8333333,
3334 },
46a0fac9
SB		 3335 /*
3336 * National Instruments 843x
3337 */
3338 [pbn_ni8430_16] = {
3339 .flags = FL_BASE0,
3340 .num_ports = 16,
3341 .base_baud = 3686400,
3342 .uart_offset = 0x10,
3343 .first_offset = 0x800,
3344 },
3345 [pbn_ni8430_8] = {
3346 .flags = FL_BASE0,
3347 .num_ports = 8,
3348 .base_baud = 3686400,
3349 .uart_offset = 0x10,
3350 .first_offset = 0x800,
3351 },
3352 [pbn_ni8430_4] = {
3353 .flags = FL_BASE0,
3354 .num_ports = 4,
3355 .base_baud = 3686400,
3356 .uart_offset = 0x10,
3357 .first_offset = 0x800,
3358 },
3359 [pbn_ni8430_2] = {
3360 .flags = FL_BASE0,
3361 .num_ports = 2,
3362 .base_baud = 3686400,
3363 .uart_offset = 0x10,
3364 .first_offset = 0x800,
3365 },
1b62cbf2
KJ		 3366 /*
3367 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3368 */
3369 [pbn_ADDIDATA_PCIe_1_3906250] = {
3370 .flags = FL_BASE0,
3371 .num_ports = 1,
3372 .base_baud = 3906250,
3373 .uart_offset = 0x200,
3374 .first_offset = 0x1000,
3375 },
3376 [pbn_ADDIDATA_PCIe_2_3906250] = {
3377 .flags = FL_BASE0,
3378 .num_ports = 2,
3379 .base_baud = 3906250,
3380 .uart_offset = 0x200,
3381 .first_offset = 0x1000,
3382 },
3383 [pbn_ADDIDATA_PCIe_4_3906250] = {
3384 .flags = FL_BASE0,
3385 .num_ports = 4,
3386 .base_baud = 3906250,
3387 .uart_offset = 0x200,
3388 .first_offset = 0x1000,
3389 },
3390 [pbn_ADDIDATA_PCIe_8_3906250] = {
3391 .flags = FL_BASE0,
3392 .num_ports = 8,
3393 .base_baud = 3906250,
3394 .uart_offset = 0x200,
3395 .first_offset = 0x1000,
3396 },
095e24b0 3397 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3398 .flags = FL_BASE_BARS,
3399 .num_ports = 2,
095e24b0
DB		 3400 .base_baud = 921600,
3401 .reg_shift = 2,
3402 },
b15e5691
HK		 3403 [pbn_byt] = {
3404 .flags = FL_BASE0,
3405 .num_ports = 1,
3406 .base_baud = 2764800,
3407 .uart_offset = 0x80,
3408 .reg_shift = 2,
3409 },
d9a0fbfd
AP		 3410 [pbn_omegapci] = {
3411 .flags = FL_BASE0,
3412 .num_ports = 8,
3413 .base_baud = 115200,
3414 .uart_offset = 0x200,
3415 },
7808edcd
NG		 3416 [pbn_NETMOS9900_2s_115200] = {
3417 .flags = FL_BASE0,
3418 .num_ports = 2,
3419 .base_baud = 115200,
3420 },
ebebd49a
SH		 3421 [pbn_brcm_trumanage] = {
3422 .flags = FL_BASE0,
3423 .num_ports = 1,
3424 .reg_shift = 2,
3425 .base_baud = 115200,
3426 },
2c62a3c8
GKH		 3427 [pbn_fintek_4] = {
3428 .num_ports = 4,
3429 .uart_offset = 8,
3430 .base_baud = 115200,
3431 .first_offset = 0x40,
3432 },
3433 [pbn_fintek_8] = {
3434 .num_ports = 8,
3435 .uart_offset = 8,
3436 .base_baud = 115200,
3437 .first_offset = 0x40,
3438 },
3439 [pbn_fintek_12] = {
3440 .num_ports = 12,
3441 .uart_offset = 8,
3442 .base_baud = 115200,
3443 .first_offset = 0x40,
3444 },
1da177e4
LT		 3445};
3446
6971c635
GA		 3447static const struct pci_device_id blacklist[] = {
3448 /* softmodems */
5756ee99 3449 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3450 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3451 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3452
3453 /* multi-io cards handled by parport_serial */
3454 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
436bbd43
CS		 3455};
3456
1da177e4
LT		 3457/*
3458 * Given a complete unknown PCI device, try to use some heuristics to
3459 * guess what the configuration might be, based on the pitiful PCI
3460 * serial specs. Returns 0 on success, 1 on failure.
3461 */
9671f099 3462static int
1c7c1fe5 3463serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3464{
6971c635 3465 const struct pci_device_id *bldev;
1da177e4 3466 int num_iomem, num_port, first_port = -1, i;
5756ee99 3467
1da177e4
LT		 3468 /*
3469 * If it is not a communications device or the programming
3470 * interface is greater than 6, give up.
3471 *
3472 * (Should we try to make guesses for multiport serial devices
5756ee99 3473 * later?)
1da177e4
LT		 3474 */
3475 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3476 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3477 (dev->class & 0xff) > 6)
3478 return -ENODEV;
3479
436bbd43
CS		 3480 /*
3481 * Do not access blacklisted devices that are known not to
6971c635 3482 * feature serial ports or are handled by other modules.
436bbd43 3483 */
6971c635
GA		 3484 for (bldev = blacklist;
3485 bldev < blacklist + ARRAY_SIZE(blacklist);
3486 bldev++) {
3487 if (dev->vendor == bldev->vendor &&
3488 dev->device == bldev->device)
436bbd43
CS		 3489 return -ENODEV;
3490 }
3491
1da177e4
LT		 3492 num_iomem = num_port = 0;
3493 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3494 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3495 num_port++;
3496 if (first_port == -1)
3497 first_port = i;
3498 }
3499 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3500 num_iomem++;
3501 }
3502
3503 /*
3504 * If there is 1 or 0 iomem regions, and exactly one port,
3505 * use it. We guess the number of ports based on the IO
3506 * region size.
3507 */
3508 if (num_iomem <= 1 && num_port == 1) {
3509 board->flags = first_port;
3510 board->num_ports = pci_resource_len(dev, first_port) / 8;
3511 return 0;
3512 }
3513
3514 /*
3515 * Now guess if we've got a board which indexes by BARs.
3516 * Each IO BAR should be 8 bytes, and they should follow
3517 * consecutively.
3518 */
3519 first_port = -1;
3520 num_port = 0;
3521 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3522 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3523 pci_resource_len(dev, i) == 8 &&
3524 (first_port == -1 || (first_port + num_port) == i)) {
3525 num_port++;
3526 if (first_port == -1)
3527 first_port = i;
3528 }
3529 }
3530
3531 if (num_port > 1) {
3532 board->flags = first_port | FL_BASE_BARS;
3533 board->num_ports = num_port;
3534 return 0;
3535 }
3536
3537 return -ENODEV;
3538}
3539
3540static inline int
975a1a7d
RK		 3541serial_pci_matches(const struct pciserial_board *board,
3542 const struct pciserial_board *guessed)
1da177e4
LT		 3543{
3544 return
3545 board->num_ports == guessed->num_ports &&
3546 board->base_baud == guessed->base_baud &&
3547 board->uart_offset == guessed->uart_offset &&
3548 board->reg_shift == guessed->reg_shift &&
3549 board->first_offset == guessed->first_offset;
3550}
3551
241fc436 3552struct serial_private *
975a1a7d 3553pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3554{
2655a2c7 3555 struct uart_8250_port uart;
1da177e4 3556 struct serial_private *priv;
1da177e4
LT		 3557 struct pci_serial_quirk *quirk;
3558 int rc, nr_ports, i;
3559
1da177e4
LT		 3560 nr_ports = board->num_ports;
3561
3562 /*
3563 * Find an init and setup quirks.
3564 */
3565 quirk = find_quirk(dev);
3566
3567 /*
3568 * Run the new-style initialization function.
3569 * The initialization function returns:
3570 * <0 - error
3571 * 0 - use board->num_ports
3572 * >0 - number of ports
3573 */
3574 if (quirk->init) {
3575 rc = quirk->init(dev);
241fc436
RK		 3576 if (rc < 0) {
3577 priv = ERR_PTR(rc);
3578 goto err_out;
3579 }
1da177e4
LT		 3580 if (rc)
3581 nr_ports = rc;
3582 }
3583
8f31bb39 3584 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3585 sizeof(unsigned int) * nr_ports,
3586 GFP_KERNEL);
3587 if (!priv) {
241fc436
RK		 3588 priv = ERR_PTR(-ENOMEM);
3589 goto err_deinit;
1da177e4
LT		 3590 }
3591
70db3d91 3592 priv->dev = dev;
1da177e4 3593 priv->quirk = quirk;
1da177e4 3594
2655a2c7
AC		 3595 memset(&uart, 0, sizeof(uart));
3596 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3597 uart.port.uartclk = board->base_baud * 16;
3598 uart.port.irq = get_pci_irq(dev, board);
3599 uart.port.dev = &dev->dev;
72ce9a83 3600
1da177e4 3601 for (i = 0; i < nr_ports; i++) {
2655a2c7 3602 if (quirk->setup(priv, board, &uart, i))
1da177e4 3603 break;
72ce9a83 3604
af8c5b8d
GKH		 3605 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3606 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 3607
2655a2c7 3608 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 3609 if (priv->line[i] < 0) {
af8c5b8d
GKH		 3610 dev_err(&dev->dev,
3611 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3612 uart.port.iobase, uart.port.irq,
3613 uart.port.iotype, priv->line[i]);
1da177e4
LT		 3614 break;
3615 }
3616 }
1da177e4 3617 priv->nr = i;
241fc436 3618 return priv;
1da177e4 3619
5756ee99 3620err_deinit:
1da177e4
LT		 3621 if (quirk->exit)
3622 quirk->exit(dev);
5756ee99 3623err_out:
241fc436 3624 return priv;
1da177e4 3625}
241fc436 3626EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 3627
241fc436 3628void pciserial_remove_ports(struct serial_private *priv)
1da177e4 3629{
056a8763
RK		 3630 struct pci_serial_quirk *quirk;
3631 int i;
1da177e4 3632
056a8763
RK		 3633 for (i = 0; i < priv->nr; i++)
3634 serial8250_unregister_port(priv->line[i]);
1da177e4 3635
056a8763
RK		 3636 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3637 if (priv->remapped_bar[i])
3638 iounmap(priv->remapped_bar[i]);
3639 priv->remapped_bar[i] = NULL;
3640 }
1da177e4 3641
056a8763
RK		 3642 /*
3643 * Find the exit quirks.
3644 */
241fc436 3645 quirk = find_quirk(priv->dev);
056a8763 3646 if (quirk->exit)
241fc436
RK		 3647 quirk->exit(priv->dev);
3648
3649 kfree(priv);
3650}
3651EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3652
3653void pciserial_suspend_ports(struct serial_private *priv)
3654{
3655 int i;
3656
3657 for (i = 0; i < priv->nr; i++)
3658 if (priv->line[i] >= 0)
3659 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 3660
3661 /*
3662 * Ensure that every init quirk is properly torn down
3663 */
3664 if (priv->quirk->exit)
3665 priv->quirk->exit(priv->dev);
241fc436
RK		 3666}
3667EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3668
3669void pciserial_resume_ports(struct serial_private *priv)
3670{
3671 int i;
3672
3673 /*
3674 * Ensure that the board is correctly configured.
3675 */
3676 if (priv->quirk->init)
3677 priv->quirk->init(priv->dev);
3678
3679 for (i = 0; i < priv->nr; i++)
3680 if (priv->line[i] >= 0)
3681 serial8250_resume_port(priv->line[i]);
3682}
3683EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3684
3685/*
3686 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3687 * to the arrangement of serial ports on a PCI card.
3688 */
9671f099 3689static int
241fc436
RK		 3690pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3691{
5bf8f501 3692 struct pci_serial_quirk *quirk;
241fc436 3693 struct serial_private *priv;
975a1a7d
RK		 3694 const struct pciserial_board *board;
3695 struct pciserial_board tmp;
241fc436
RK		 3696 int rc;
3697
5bf8f501
FB		 3698 quirk = find_quirk(dev);
3699 if (quirk->probe) {
3700 rc = quirk->probe(dev);
3701 if (rc)
3702 return rc;
3703 }
3704
241fc436 3705 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 3706 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 3707 ent->driver_data);
3708 return -EINVAL;
3709 }
3710
3711 board = &pci_boards[ent->driver_data];
3712
3713 rc = pci_enable_device(dev);
2807190b 3714 pci_save_state(dev);
241fc436
RK		 3715 if (rc)
3716 return rc;
3717
3718 if (ent->driver_data == pbn_default) {
3719 /*
3720 * Use a copy of the pci_board entry for this;
3721 * avoid changing entries in the table.
3722 */
3723 memcpy(&tmp, board, sizeof(struct pciserial_board));
3724 board = &tmp;
3725
3726 /*
3727 * We matched one of our class entries. Try to
3728 * determine the parameters of this board.
3729 */
975a1a7d 3730 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 3731 if (rc)
3732 goto disable;
3733 } else {
3734 /*
3735 * We matched an explicit entry. If we are able to
3736 * detect this boards settings with our heuristic,
3737 * then we no longer need this entry.
3738 */
3739 memcpy(&tmp, &pci_boards[pbn_default],
3740 sizeof(struct pciserial_board));
3741 rc = serial_pci_guess_board(dev, &tmp);
3742 if (rc == 0 && serial_pci_matches(board, &tmp))
3743 moan_device("Redundant entry in serial pci_table.",
3744 dev);
3745 }
3746
3747 priv = pciserial_init_ports(dev, board);
3748 if (!IS_ERR(priv)) {
3749 pci_set_drvdata(dev, priv);
3750 return 0;
3751 }
3752
3753 rc = PTR_ERR(priv);
1da177e4 3754
241fc436 3755 disable:
056a8763 3756 pci_disable_device(dev);
241fc436
RK		 3757 return rc;
3758}
1da177e4 3759
ae8d8a14 3760static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3761{
3762 struct serial_private *priv = pci_get_drvdata(dev);
3763
241fc436
RK		 3764 pciserial_remove_ports(priv);
3765
3766 pci_disable_device(dev);
1da177e4
LT		 3767}
3768
1d5e7996 3769#ifdef CONFIG_PM
1da177e4
LT		 3770static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3771{
3772 struct serial_private *priv = pci_get_drvdata(dev);
3773
241fc436
RK		 3774 if (priv)
3775 pciserial_suspend_ports(priv);
1da177e4 3776
1da177e4
LT		 3777 pci_save_state(dev);
3778 pci_set_power_state(dev, pci_choose_state(dev, state));
3779 return 0;
3780}
3781
3782static int pciserial_resume_one(struct pci_dev *dev)
3783{
ccb9d59e 3784 int err;
1da177e4
LT		 3785 struct serial_private *priv = pci_get_drvdata(dev);
3786
3787 pci_set_power_state(dev, PCI_D0);
3788 pci_restore_state(dev);
3789
3790 if (priv) {
1da177e4
LT		 3791 /*
3792 * The device may have been disabled. Re-enable it.
3793 */
ccb9d59e 3794 err = pci_enable_device(dev);
40836c48 3795 /* FIXME: We cannot simply error out here */
ccb9d59e 3796 if (err)
af8c5b8d 3797 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 3798 pciserial_resume_ports(priv);
1da177e4
LT		 3799 }
3800 return 0;
3801}
1d5e7996 3802#endif
1da177e4
LT		 3803
3804static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3805 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3806 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3807 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3808 pbn_b2_8_921600 },
1da177e4
LT		 3809 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3810 PCI_SUBVENDOR_ID_CONNECT_TECH,
3811 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3812 pbn_b1_8_1382400 },
3813 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3814 PCI_SUBVENDOR_ID_CONNECT_TECH,
3815 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3816 pbn_b1_4_1382400 },
3817 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3818 PCI_SUBVENDOR_ID_CONNECT_TECH,
3819 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3820 pbn_b1_2_1382400 },
3821 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3822 PCI_SUBVENDOR_ID_CONNECT_TECH,
3823 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3824 pbn_b1_8_1382400 },
3825 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3826 PCI_SUBVENDOR_ID_CONNECT_TECH,
3827 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3828 pbn_b1_4_1382400 },
3829 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3830 PCI_SUBVENDOR_ID_CONNECT_TECH,
3831 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3832 pbn_b1_2_1382400 },
3833 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3834 PCI_SUBVENDOR_ID_CONNECT_TECH,
3835 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3836 pbn_b1_8_921600 },
3837 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3838 PCI_SUBVENDOR_ID_CONNECT_TECH,
3839 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3840 pbn_b1_8_921600 },
3841 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3842 PCI_SUBVENDOR_ID_CONNECT_TECH,
3843 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3844 pbn_b1_4_921600 },
3845 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3846 PCI_SUBVENDOR_ID_CONNECT_TECH,
3847 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3848 pbn_b1_4_921600 },
3849 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3850 PCI_SUBVENDOR_ID_CONNECT_TECH,
3851 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3852 pbn_b1_2_921600 },
3853 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3854 PCI_SUBVENDOR_ID_CONNECT_TECH,
3855 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3856 pbn_b1_8_921600 },
3857 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3858 PCI_SUBVENDOR_ID_CONNECT_TECH,
3859 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3860 pbn_b1_8_921600 },
3861 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3862 PCI_SUBVENDOR_ID_CONNECT_TECH,
3863 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3864 pbn_b1_4_921600 },
26e92861
GH		 3865 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3866 PCI_SUBVENDOR_ID_CONNECT_TECH,
3867 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3868 pbn_b1_2_1250000 },
3869 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3870 PCI_SUBVENDOR_ID_CONNECT_TECH,
3871 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3872 pbn_b0_2_1843200 },
3873 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3874 PCI_SUBVENDOR_ID_CONNECT_TECH,
3875 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3876 pbn_b0_4_1843200 },
85d1494e
YY		 3877 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3878 PCI_VENDOR_ID_AFAVLAB,
3879 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3880 pbn_b0_4_1152000 },
26e92861
GH		 3881 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3882 PCI_SUBVENDOR_ID_CONNECT_TECH,
3883 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3884 pbn_b0_2_1843200_200 },
3885 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3886 PCI_SUBVENDOR_ID_CONNECT_TECH,
3887 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3888 pbn_b0_4_1843200_200 },
3889 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3890 PCI_SUBVENDOR_ID_CONNECT_TECH,
3891 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3892 pbn_b0_8_1843200_200 },
3893 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3894 PCI_SUBVENDOR_ID_CONNECT_TECH,
3895 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3896 pbn_b0_2_1843200_200 },
3897 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3898 PCI_SUBVENDOR_ID_CONNECT_TECH,
3899 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3900 pbn_b0_4_1843200_200 },
3901 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3902 PCI_SUBVENDOR_ID_CONNECT_TECH,
3903 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3904 pbn_b0_8_1843200_200 },
3905 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3906 PCI_SUBVENDOR_ID_CONNECT_TECH,
3907 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3908 pbn_b0_2_1843200_200 },
3909 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3910 PCI_SUBVENDOR_ID_CONNECT_TECH,
3911 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3912 pbn_b0_4_1843200_200 },
3913 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3914 PCI_SUBVENDOR_ID_CONNECT_TECH,
3915 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3916 pbn_b0_8_1843200_200 },
3917 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3918 PCI_SUBVENDOR_ID_CONNECT_TECH,
3919 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3920 pbn_b0_2_1843200_200 },
3921 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3922 PCI_SUBVENDOR_ID_CONNECT_TECH,
3923 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3924 pbn_b0_4_1843200_200 },
3925 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3926 PCI_SUBVENDOR_ID_CONNECT_TECH,
3927 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3928 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3929 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3930 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3931 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3932
3933 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3935 pbn_b2_bt_1_115200 },
3936 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3938 pbn_b2_bt_2_115200 },
3939 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3941 pbn_b2_bt_4_115200 },
3942 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3944 pbn_b2_bt_2_115200 },
3945 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3947 pbn_b2_bt_4_115200 },
3948 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3950 pbn_b2_8_115200 },
e65f0f82
FL		 3951 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 pbn_b2_8_460800 },
1da177e4
LT		 3954 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3956 pbn_b2_8_115200 },
3957
3958 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3960 pbn_b2_bt_2_115200 },
3961 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3963 pbn_b2_bt_2_921600 },
3964 /*
3965 * VScom SPCOM800, from sl@s.pl
3966 */
5756ee99
AC		 3967 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3969 pbn_b2_8_921600 },
3970 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 3971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3972 pbn_b2_4_921600 },
b76c5a07
CB		 3973 /* Unknown card - subdevice 0x1584 */
3974 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3975 PCI_VENDOR_ID_PLX,
3976 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 3977 pbn_b2_4_115200 },
3978 /* Unknown card - subdevice 0x1588 */
3979 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3980 PCI_VENDOR_ID_PLX,
3981 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3982 pbn_b2_8_115200 },
1da177e4
LT		 3983 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3984 PCI_SUBVENDOR_ID_KEYSPAN,
3985 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3986 pbn_panacom },
3987 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989 pbn_panacom4 },
3990 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992 pbn_panacom2 },
a9cccd34
MF		 3993 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3994 PCI_VENDOR_ID_ESDGMBH,
3995 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3996 pbn_b2_4_115200 },
1da177e4
LT		 3997 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3998 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3999 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4000 pbn_b2_4_460800 },
4001 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4002 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4003 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4004 pbn_b2_8_460800 },
4005 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4006 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4007 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4008 pbn_b2_16_460800 },
4009 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4010 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4011 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4012 pbn_b2_16_460800 },
4013 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4014 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4015 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4016 pbn_b2_4_460800 },
4017 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4018 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4019 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4020 pbn_b2_8_460800 },
add7b58e
BH		 4021 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4022 PCI_SUBVENDOR_ID_EXSYS,
4023 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4024 pbn_b2_4_115200 },
1da177e4
LT		 4025 /*
4026 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4027 * (Exoray@isys.ca)
4028 */
4029 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4030 0x10b5, 0x106a, 0, 0,
4031 pbn_plx_romulus },
55c7c0fd
AC		 4032 /*
4033 * Quatech cards. These actually have configurable clocks but for
4034 * now we just use the default.
4035 *
4036 * 100 series are RS232, 200 series RS422,
4037 */
1da177e4
LT		 4038 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4040 pbn_b1_4_115200 },
4041 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4043 pbn_b1_2_115200 },
55c7c0fd
AC		 4044 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4046 pbn_b2_2_115200 },
4047 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4049 pbn_b1_2_115200 },
4050 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4052 pbn_b2_2_115200 },
4053 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4055 pbn_b1_4_115200 },
1da177e4
LT		 4056 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4058 pbn_b1_8_115200 },
4059 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4061 pbn_b1_8_115200 },
55c7c0fd
AC		 4062 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4064 pbn_b1_4_115200 },
4065 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4067 pbn_b1_2_115200 },
4068 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4070 pbn_b1_4_115200 },
4071 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4073 pbn_b1_2_115200 },
4074 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4076 pbn_b2_4_115200 },
4077 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4079 pbn_b2_2_115200 },
4080 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4082 pbn_b2_1_115200 },
4083 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085 pbn_b2_4_115200 },
4086 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088 pbn_b2_2_115200 },
4089 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091 pbn_b2_1_115200 },
4092 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094 pbn_b0_8_115200 },
4095
1da177e4 4096 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4097 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4098 0, 0,
1da177e4 4099 pbn_b0_4_921600 },
fbc0dc0d 4100 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4101 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4102 0, 0,
fbc0dc0d 4103 pbn_b0_4_1152000 },
c9bd9d01
MP		 4104 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4106 pbn_b0_bt_2_921600 },
db1de159
DR		 4107
4108 /*
4109 * The below card is a little controversial since it is the
4110 * subject of a PCI vendor/device ID clash. (See
4111 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4112 * For now just used the hex ID 0x950a.
4113 */
39aced68 4114 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4115 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4116 0, 0, pbn_b0_2_115200 },
4117 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4118 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4119 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4120 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4122 pbn_b0_2_1130000 },
70fd8fde
AP		 4123 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4124 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4125 pbn_b0_1_921600 },
1da177e4
LT		 4126 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128 pbn_b0_4_115200 },
4129 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 pbn_b0_bt_2_921600 },
e847003f
LB		 4132 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4133 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4134 pbn_b2_8_1152000 },
1da177e4 4135
7106b4e3
LH		 4136 /*
4137 * Oxford Semiconductor Inc. Tornado PCI express device range.
4138 */
4139 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4141 pbn_b0_1_4000000 },
4142 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4144 pbn_b0_1_4000000 },
4145 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4147 pbn_oxsemi_1_4000000 },
4148 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4150 pbn_oxsemi_1_4000000 },
4151 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4153 pbn_b0_1_4000000 },
4154 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4156 pbn_b0_1_4000000 },
4157 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4159 pbn_oxsemi_1_4000000 },
4160 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4162 pbn_oxsemi_1_4000000 },
4163 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4165 pbn_b0_1_4000000 },
4166 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4168 pbn_b0_1_4000000 },
4169 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4171 pbn_b0_1_4000000 },
4172 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4174 pbn_b0_1_4000000 },
4175 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177 pbn_oxsemi_2_4000000 },
4178 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180 pbn_oxsemi_2_4000000 },
4181 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4183 pbn_oxsemi_4_4000000 },
4184 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186 pbn_oxsemi_4_4000000 },
4187 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 pbn_oxsemi_8_4000000 },
4190 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192 pbn_oxsemi_8_4000000 },
4193 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195 pbn_oxsemi_1_4000000 },
4196 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198 pbn_oxsemi_1_4000000 },
4199 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201 pbn_oxsemi_1_4000000 },
4202 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204 pbn_oxsemi_1_4000000 },
4205 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207 pbn_oxsemi_1_4000000 },
4208 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 pbn_oxsemi_1_4000000 },
4211 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213 pbn_oxsemi_1_4000000 },
4214 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 pbn_oxsemi_1_4000000 },
4217 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 pbn_oxsemi_1_4000000 },
4220 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 pbn_oxsemi_1_4000000 },
4223 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225 pbn_oxsemi_1_4000000 },
4226 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 pbn_oxsemi_1_4000000 },
4229 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 pbn_oxsemi_1_4000000 },
4232 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 pbn_oxsemi_1_4000000 },
4235 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 pbn_oxsemi_1_4000000 },
4238 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240 pbn_oxsemi_1_4000000 },
4241 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 pbn_oxsemi_1_4000000 },
4244 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246 pbn_oxsemi_1_4000000 },
4247 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249 pbn_oxsemi_1_4000000 },
4250 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252 pbn_oxsemi_1_4000000 },
4253 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_oxsemi_1_4000000 },
4256 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_oxsemi_1_4000000 },
4259 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_oxsemi_1_4000000 },
4262 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_oxsemi_1_4000000 },
4265 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_oxsemi_1_4000000 },
4268 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_oxsemi_1_4000000 },
b80de369
LH		 4271 /*
4272 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4273 */
4274 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4275 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4276 pbn_oxsemi_1_4000000 },
4277 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4278 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4279 pbn_oxsemi_2_4000000 },
4280 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4281 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4282 pbn_oxsemi_4_4000000 },
4283 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4284 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4285 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4286
4287 /*
4288 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4289 */
4290 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4291 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4292 pbn_oxsemi_2_4000000 },
4293
1da177e4
LT		 4294 /*
4295 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4296 * from skokodyn@yahoo.com
4297 */
4298 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4299 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4300 pbn_sbsxrsio },
4301 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4302 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4303 pbn_sbsxrsio },
4304 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4305 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4306 pbn_sbsxrsio },
4307 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4308 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4309 pbn_sbsxrsio },
4310
4311 /*
4312 * Digitan DS560-558, from jimd@esoft.com
4313 */
4314 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4316 pbn_b1_1_115200 },
4317
4318 /*
4319 * Titan Electronic cards
4320 * The 400L and 800L have a custom setup quirk.
4321 */
4322 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4324 pbn_b0_1_921600 },
4325 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4327 pbn_b0_2_921600 },
4328 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4330 pbn_b0_4_921600 },
4331 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4333 pbn_b0_4_921600 },
4334 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b1_1_921600 },
4337 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b1_bt_2_921600 },
4340 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b0_bt_4_921600 },
4343 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_b0_bt_8_921600 },
66169ad1
YY		 4346 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b4_bt_2_921600 },
4349 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b4_bt_4_921600 },
4352 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_b4_bt_8_921600 },
4355 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_b0_4_921600 },
4358 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b0_4_921600 },
4361 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 pbn_b0_4_921600 },
4364 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366 pbn_oxsemi_1_4000000 },
4367 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369 pbn_oxsemi_2_4000000 },
4370 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 pbn_oxsemi_4_4000000 },
4373 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375 pbn_oxsemi_8_4000000 },
4376 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378 pbn_oxsemi_2_4000000 },
4379 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381 pbn_oxsemi_2_4000000 },
1e9deb11
YY		 4382 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384 pbn_b0_4_921600 },
4385 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387 pbn_b0_4_921600 },
4388 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390 pbn_b0_4_921600 },
4391 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393 pbn_b0_4_921600 },
1da177e4
LT		 4394
4395 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397 pbn_b2_1_460800 },
4398 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 pbn_b2_1_460800 },
4401 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_b2_1_460800 },
4404 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_b2_bt_2_921600 },
4407 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_b2_bt_2_921600 },
4410 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_b2_bt_2_921600 },
4413 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_b2_bt_4_921600 },
4416 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_b2_bt_4_921600 },
4419 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_b2_bt_4_921600 },
4422 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 pbn_b0_1_921600 },
4425 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_b0_1_921600 },
4428 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_b0_1_921600 },
4431 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_b0_bt_2_921600 },
4434 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_b0_bt_2_921600 },
4437 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_b0_bt_2_921600 },
4440 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_b0_bt_4_921600 },
4443 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_b0_bt_4_921600 },
4446 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4449 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_b0_bt_8_921600 },
4452 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_b0_bt_8_921600 },
4455 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_b0_bt_8_921600 },
1da177e4
LT		 4458
4459 /*
4460 * Computone devices submitted by Doug McNash dmcnash@computone.com
4461 */
4462 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4463 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4464 0, 0, pbn_computone_4 },
4465 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4466 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4467 0, 0, pbn_computone_8 },
4468 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4469 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4470 0, 0, pbn_computone_6 },
4471
4472 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_oxsemi },
4475 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4476 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4477 pbn_b0_bt_1_921600 },
4478
abd7baca
SC		 4479 /*
4480 * SUNIX (TIMEDIA)
4481 */
4482 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4483 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4484 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4485 pbn_b0_bt_1_921600 },
4486
4487 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4488 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4489 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4490 pbn_b0_bt_1_921600 },
4491
1da177e4
LT		 4492 /*
4493 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4494 */
4495 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_b0_bt_8_115200 },
4498 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_b0_bt_8_115200 },
4501
4502 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 pbn_b0_bt_2_115200 },
4505 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_b0_bt_2_115200 },
4508 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4511 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 pbn_b0_bt_2_115200 },
4514 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_b0_bt_2_115200 },
1da177e4
LT		 4517 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 pbn_b0_bt_4_460800 },
4520 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 pbn_b0_bt_4_460800 },
4523 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 pbn_b0_bt_2_460800 },
4526 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528 pbn_b0_bt_2_460800 },
4529 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 pbn_b0_bt_2_460800 },
4532 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534 pbn_b0_bt_1_115200 },
4535 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537 pbn_b0_bt_1_460800 },
4538
1fb8cacc
RK		 4539 /*
4540 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4541 * Cards are identified by their subsystem vendor IDs, which
4542 * (in hex) match the model number.
4543 *
4544 * Note that JC140x are RS422/485 cards which require ox950
4545 * ACR = 0x10, and as such are not currently fully supported.
4546 */
4547 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4548 0x1204, 0x0004, 0, 0,
4549 pbn_b0_4_921600 },
4550 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4551 0x1208, 0x0004, 0, 0,
4552 pbn_b0_4_921600 },
4553/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4554 0x1402, 0x0002, 0, 0,
4555 pbn_b0_2_921600 }, */
4556/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4557 0x1404, 0x0004, 0, 0,
4558 pbn_b0_4_921600 }, */
4559 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4560 0x1208, 0x0004, 0, 0,
4561 pbn_b0_4_921600 },
4562
2a52fcb5
KY		 4563 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4564 0x1204, 0x0004, 0, 0,
4565 pbn_b0_4_921600 },
4566 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4567 0x1208, 0x0004, 0, 0,
4568 pbn_b0_4_921600 },
4569 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4570 0x1208, 0x0004, 0, 0,
4571 pbn_b0_4_921600 },
1da177e4
LT		 4572 /*
4573 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4574 */
4575 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_b1_1_1382400 },
4578
4579 /*
4580 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4581 */
4582 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_b1_1_1382400 },
4585
4586 /*
4587 * RAStel 2 port modem, gerg@moreton.com.au
4588 */
4589 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591 pbn_b2_bt_2_115200 },
4592
4593 /*
4594 * EKF addition for i960 Boards form EKF with serial port
4595 */
4596 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4597 0xE4BF, PCI_ANY_ID, 0, 0,
4598 pbn_intel_i960 },
4599
4600 /*
4601 * Xircom Cardbus/Ethernet combos
4602 */
4603 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b0_1_115200 },
4606 /*
4607 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4608 */
4609 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b0_1_115200 },
4612
4613 /*
4614 * Untested PCI modems, sent in from various folks...
4615 */
4616
4617 /*
4618 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4619 */
4620 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4621 0x1048, 0x1500, 0, 0,
4622 pbn_b1_1_115200 },
4623
4624 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4625 0xFF00, 0, 0, 0,
4626 pbn_sgi_ioc3 },
4627
4628 /*
4629 * HP Diva card
4630 */
4631 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4632 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4633 pbn_b1_1_115200 },
4634 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_b0_5_115200 },
4637 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_b2_1_115200 },
4640
d9004eb4
ABL		 4641 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 pbn_b3_2_115200 },
1da177e4
LT		 4644 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_b3_4_115200 },
4647 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_b3_8_115200 },
4650
4651 /*
4652 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4653 */
4654 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4655 PCI_ANY_ID, PCI_ANY_ID,
4656 0,
4657 0, pbn_exar_XR17C152 },
4658 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4659 PCI_ANY_ID, PCI_ANY_ID,
4660 0,
4661 0, pbn_exar_XR17C154 },
4662 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4663 PCI_ANY_ID, PCI_ANY_ID,
4664 0,
4665 0, pbn_exar_XR17C158 },
dc96efb7
MS		 4666 /*
4667 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4668 */
4669 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4670 PCI_ANY_ID, PCI_ANY_ID,
4671 0,
4672 0, pbn_exar_XR17V352 },
4673 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4674 PCI_ANY_ID, PCI_ANY_ID,
4675 0,
4676 0, pbn_exar_XR17V354 },
4677 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4678 PCI_ANY_ID, PCI_ANY_ID,
4679 0,
4680 0, pbn_exar_XR17V358 },
1da177e4
LT		 4681
4682 /*
4683 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4684 */
4685 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_1_115200 },
84f8c6fc
NV		 4688 /*
4689 * ITE
4690 */
4691 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4692 PCI_ANY_ID, PCI_ANY_ID,
4693 0, 0,
4694 pbn_b1_bt_1_115200 },
1da177e4 4695
737c1756
PH		 4696 /*
4697 * IntaShield IS-200
4698 */
4699 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4701 pbn_b2_2_115200 },
4b6f6ce9
IGP		 4702 /*
4703 * IntaShield IS-400
4704 */
4705 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4707 pbn_b2_4_115200 },
48212008
TH		 4708 /*
4709 * Perle PCI-RAS cards
4710 */
4711 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4712 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4713 0, 0, pbn_b2_4_921600 },
4714 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4715 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4716 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 4717
4718 /*
4719 * Mainpine series cards: Fairly standard layout but fools
4720 * parts of the autodetect in some cases and uses otherwise
4721 * unmatched communications subclasses in the PCI Express case
4722 */
4723
4724 { /* RockForceDUO */
4725 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4726 PCI_VENDOR_ID_MAINPINE, 0x0200,
4727 0, 0, pbn_b0_2_115200 },
4728 { /* RockForceQUATRO */
4729 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4730 PCI_VENDOR_ID_MAINPINE, 0x0300,
4731 0, 0, pbn_b0_4_115200 },
4732 { /* RockForceDUO+ */
4733 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4734 PCI_VENDOR_ID_MAINPINE, 0x0400,
4735 0, 0, pbn_b0_2_115200 },
4736 { /* RockForceQUATRO+ */
4737 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4738 PCI_VENDOR_ID_MAINPINE, 0x0500,
4739 0, 0, pbn_b0_4_115200 },
4740 { /* RockForce+ */
4741 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4742 PCI_VENDOR_ID_MAINPINE, 0x0600,
4743 0, 0, pbn_b0_2_115200 },
4744 { /* RockForce+ */
4745 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4746 PCI_VENDOR_ID_MAINPINE, 0x0700,
4747 0, 0, pbn_b0_4_115200 },
4748 { /* RockForceOCTO+ */
4749 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4750 PCI_VENDOR_ID_MAINPINE, 0x0800,
4751 0, 0, pbn_b0_8_115200 },
4752 { /* RockForceDUO+ */
4753 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4754 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4755 0, 0, pbn_b0_2_115200 },
4756 { /* RockForceQUARTRO+ */
4757 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4758 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4759 0, 0, pbn_b0_4_115200 },
4760 { /* RockForceOCTO+ */
4761 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4762 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4763 0, 0, pbn_b0_8_115200 },
4764 { /* RockForceD1 */
4765 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4766 PCI_VENDOR_ID_MAINPINE, 0x2000,
4767 0, 0, pbn_b0_1_115200 },
4768 { /* RockForceF1 */
4769 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4770 PCI_VENDOR_ID_MAINPINE, 0x2100,
4771 0, 0, pbn_b0_1_115200 },
4772 { /* RockForceD2 */
4773 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4774 PCI_VENDOR_ID_MAINPINE, 0x2200,
4775 0, 0, pbn_b0_2_115200 },
4776 { /* RockForceF2 */
4777 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4778 PCI_VENDOR_ID_MAINPINE, 0x2300,
4779 0, 0, pbn_b0_2_115200 },
4780 { /* RockForceD4 */
4781 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4782 PCI_VENDOR_ID_MAINPINE, 0x2400,
4783 0, 0, pbn_b0_4_115200 },
4784 { /* RockForceF4 */
4785 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4786 PCI_VENDOR_ID_MAINPINE, 0x2500,
4787 0, 0, pbn_b0_4_115200 },
4788 { /* RockForceD8 */
4789 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4790 PCI_VENDOR_ID_MAINPINE, 0x2600,
4791 0, 0, pbn_b0_8_115200 },
4792 { /* RockForceF8 */
4793 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4794 PCI_VENDOR_ID_MAINPINE, 0x2700,
4795 0, 0, pbn_b0_8_115200 },
4796 { /* IQ Express D1 */
4797 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4798 PCI_VENDOR_ID_MAINPINE, 0x3000,
4799 0, 0, pbn_b0_1_115200 },
4800 { /* IQ Express F1 */
4801 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4802 PCI_VENDOR_ID_MAINPINE, 0x3100,
4803 0, 0, pbn_b0_1_115200 },
4804 { /* IQ Express D2 */
4805 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4806 PCI_VENDOR_ID_MAINPINE, 0x3200,
4807 0, 0, pbn_b0_2_115200 },
4808 { /* IQ Express F2 */
4809 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4810 PCI_VENDOR_ID_MAINPINE, 0x3300,
4811 0, 0, pbn_b0_2_115200 },
4812 { /* IQ Express D4 */
4813 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4814 PCI_VENDOR_ID_MAINPINE, 0x3400,
4815 0, 0, pbn_b0_4_115200 },
4816 { /* IQ Express F4 */
4817 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4818 PCI_VENDOR_ID_MAINPINE, 0x3500,
4819 0, 0, pbn_b0_4_115200 },
4820 { /* IQ Express D8 */
4821 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4822 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4823 0, 0, pbn_b0_8_115200 },
4824 { /* IQ Express F8 */
4825 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4826 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4827 0, 0, pbn_b0_8_115200 },
4828
4829
aa798505
OJ		 4830 /*
4831 * PA Semi PA6T-1682M on-chip UART
4832 */
4833 { PCI_VENDOR_ID_PASEMI, 0xa004,
4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835 pbn_pasemi_1682M },
4836
46a0fac9
SB		 4837 /*
4838 * National Instruments
4839 */
04bf7e74
WP		 4840 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4842 pbn_b1_16_115200 },
4843 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4845 pbn_b1_8_115200 },
4846 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4848 pbn_b1_bt_4_115200 },
4849 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 pbn_b1_bt_2_115200 },
4852 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_b1_bt_4_115200 },
4855 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 pbn_b1_bt_2_115200 },
4858 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_b1_16_115200 },
4861 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4863 pbn_b1_8_115200 },
4864 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4866 pbn_b1_bt_4_115200 },
4867 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869 pbn_b1_bt_2_115200 },
4870 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872 pbn_b1_bt_4_115200 },
4873 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 pbn_b1_bt_2_115200 },
46a0fac9
SB		 4876 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878 pbn_ni8430_2 },
4879 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4881 pbn_ni8430_2 },
4882 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884 pbn_ni8430_4 },
4885 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 pbn_ni8430_4 },
4888 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890 pbn_ni8430_8 },
4891 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 pbn_ni8430_8 },
4894 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 pbn_ni8430_16 },
4897 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 pbn_ni8430_16 },
4900 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_ni8430_2 },
4903 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_ni8430_2 },
4906 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_ni8430_4 },
4909 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_ni8430_4 },
4912
02c9b5cf
KJ		 4913 /*
4914 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4915 */
4916 { PCI_VENDOR_ID_ADDIDATA,
4917 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4918 PCI_ANY_ID,
4919 PCI_ANY_ID,
4920 0,
4921 0,
4922 pbn_b0_4_115200 },
4923
4924 { PCI_VENDOR_ID_ADDIDATA,
4925 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4926 PCI_ANY_ID,
4927 PCI_ANY_ID,
4928 0,
4929 0,
4930 pbn_b0_2_115200 },
4931
4932 { PCI_VENDOR_ID_ADDIDATA,
4933 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4934 PCI_ANY_ID,
4935 PCI_ANY_ID,
4936 0,
4937 0,
4938 pbn_b0_1_115200 },
4939
086231f7 4940 { PCI_VENDOR_ID_AMCC,
57c1f0e9 4941 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 4942 PCI_ANY_ID,
4943 PCI_ANY_ID,
4944 0,
4945 0,
4946 pbn_b1_8_115200 },
4947
4948 { PCI_VENDOR_ID_ADDIDATA,
4949 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4950 PCI_ANY_ID,
4951 PCI_ANY_ID,
4952 0,
4953 0,
4954 pbn_b0_4_115200 },
4955
4956 { PCI_VENDOR_ID_ADDIDATA,
4957 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4958 PCI_ANY_ID,
4959 PCI_ANY_ID,
4960 0,
4961 0,
4962 pbn_b0_2_115200 },
4963
4964 { PCI_VENDOR_ID_ADDIDATA,
4965 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4966 PCI_ANY_ID,
4967 PCI_ANY_ID,
4968 0,
4969 0,
4970 pbn_b0_1_115200 },
4971
4972 { PCI_VENDOR_ID_ADDIDATA,
4973 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4974 PCI_ANY_ID,
4975 PCI_ANY_ID,
4976 0,
4977 0,
4978 pbn_b0_4_115200 },
4979
4980 { PCI_VENDOR_ID_ADDIDATA,
4981 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4982 PCI_ANY_ID,
4983 PCI_ANY_ID,
4984 0,
4985 0,
4986 pbn_b0_2_115200 },
4987
4988 { PCI_VENDOR_ID_ADDIDATA,
4989 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4990 PCI_ANY_ID,
4991 PCI_ANY_ID,
4992 0,
4993 0,
4994 pbn_b0_1_115200 },
4995
4996 { PCI_VENDOR_ID_ADDIDATA,
4997 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4998 PCI_ANY_ID,
4999 PCI_ANY_ID,
5000 0,
5001 0,
5002 pbn_b0_8_115200 },
5003
1b62cbf2
KJ		 5004 { PCI_VENDOR_ID_ADDIDATA,
5005 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5006 PCI_ANY_ID,
5007 PCI_ANY_ID,
5008 0,
5009 0,
5010 pbn_ADDIDATA_PCIe_4_3906250 },
5011
5012 { PCI_VENDOR_ID_ADDIDATA,
5013 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5014 PCI_ANY_ID,
5015 PCI_ANY_ID,
5016 0,
5017 0,
5018 pbn_ADDIDATA_PCIe_2_3906250 },
5019
5020 { PCI_VENDOR_ID_ADDIDATA,
5021 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5022 PCI_ANY_ID,
5023 PCI_ANY_ID,
5024 0,
5025 0,
5026 pbn_ADDIDATA_PCIe_1_3906250 },
5027
5028 { PCI_VENDOR_ID_ADDIDATA,
5029 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5030 PCI_ANY_ID,
5031 PCI_ANY_ID,
5032 0,
5033 0,
5034 pbn_ADDIDATA_PCIe_8_3906250 },
5035
25cf9bc1
JS		 5036 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5037 PCI_VENDOR_ID_IBM, 0x0299,
5038 0, 0, pbn_b0_bt_2_115200 },
5039
972ce085
SS		 5040 /*
5041 * other NetMos 9835 devices are most likely handled by the
5042 * parport_serial driver, check drivers/parport/parport_serial.c
5043 * before adding them here.
5044 */
5045
c4285b47
MB		 5046 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5047 0xA000, 0x1000,
5048 0, 0, pbn_b0_1_115200 },
5049
7808edcd
NG		 5050 /* the 9901 is a rebranded 9912 */
5051 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5052 0xA000, 0x1000,
5053 0, 0, pbn_b0_1_115200 },
5054
5055 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5056 0xA000, 0x1000,
5057 0, 0, pbn_b0_1_115200 },
5058
5059 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5060 0xA000, 0x1000,
5061 0, 0, pbn_b0_1_115200 },
5062
5063 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5064 0xA000, 0x1000,
5065 0, 0, pbn_b0_1_115200 },
5066
5067 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5068 0xA000, 0x3002,
5069 0, 0, pbn_NETMOS9900_2s_115200 },
5070
ac6ec5b1 5071 /*
44178176 5072 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5073 */
5074
5075 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5076 0xA000, 0x1000,
5077 0, 0, pbn_b0_1_115200 },
5078
44178176
ES		 5079 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5080 0xA000, 0x3002,
5081 0, 0, pbn_b0_bt_2_115200 },
5082
ac6ec5b1
IS		 5083 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5084 0xA000, 0x3004,
5085 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5086 /* Intel CE4100 */
5087 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5089 pbn_ce4100_1_115200 },
b15e5691
HK		 5090 /* Intel BayTrail */
5091 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5092 PCI_ANY_ID, PCI_ANY_ID,
5093 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5094 pbn_byt },
5095 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5096 PCI_ANY_ID, PCI_ANY_ID,
5097 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5098 pbn_byt },
095e24b0 5099
d9a0fbfd
AP		 5100 /*
5101 * Cronyx Omega PCI
5102 */
5103 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5105 pbn_omegapci },
ac6ec5b1 5106
ebebd49a
SH		 5107 /*
5108 * Broadcom TruManage
5109 */
5110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5112 pbn_brcm_trumanage },
5113
6683549e
AC		 5114 /*
5115 * AgeStar as-prs2-009
5116 */
5117 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5118 PCI_ANY_ID, PCI_ANY_ID,
5119 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5120
5121 /*
5122 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5123 * so not listed here.
5124 */
5125 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5126 PCI_ANY_ID, PCI_ANY_ID,
5127 0, 0, pbn_b0_bt_4_115200 },
5128
5129 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5130 PCI_ANY_ID, PCI_ANY_ID,
5131 0, 0, pbn_b0_bt_2_115200 },
5132
8b5c913f
WY		 5133 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5134 PCI_ANY_ID, PCI_ANY_ID,
5135 0, 0, pbn_b0_bt_2_115200 },
5136
14faa8cc
MS		 5137 /*
5138 * Commtech, Inc. Fastcom adapters
5139 */
5140 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5141 PCI_ANY_ID, PCI_ANY_ID,
5142 0,
5143 0, pbn_b0_2_1152000_200 },
5144 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5145 PCI_ANY_ID, PCI_ANY_ID,
5146 0,
5147 0, pbn_b0_4_1152000_200 },
5148 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5149 PCI_ANY_ID, PCI_ANY_ID,
5150 0,
5151 0, pbn_b0_4_1152000_200 },
5152 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5153 PCI_ANY_ID, PCI_ANY_ID,
5154 0,
5155 0, pbn_b0_8_1152000_200 },
5156 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5157 PCI_ANY_ID, PCI_ANY_ID,
5158 0,
5159 0, pbn_exar_XR17V352 },
5160 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5161 PCI_ANY_ID, PCI_ANY_ID,
5162 0,
5163 0, pbn_exar_XR17V354 },
5164 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5165 PCI_ANY_ID, PCI_ANY_ID,
5166 0,
5167 0, pbn_exar_XR17V358 },
5168
2c62a3c8
GKH		 5169 /* Fintek PCI serial cards */
5170 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5171 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5172 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5173
1da177e4
LT		 5174 /*
5175 * These entries match devices with class COMMUNICATION_SERIAL,
5176 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5177 */
5178 { PCI_ANY_ID, PCI_ANY_ID,
5179 PCI_ANY_ID, PCI_ANY_ID,
5180 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5181 0xffff00, pbn_default },
5182 { PCI_ANY_ID, PCI_ANY_ID,
5183 PCI_ANY_ID, PCI_ANY_ID,
5184 PCI_CLASS_COMMUNICATION_MODEM << 8,
5185 0xffff00, pbn_default },
5186 { PCI_ANY_ID, PCI_ANY_ID,
5187 PCI_ANY_ID, PCI_ANY_ID,
5188 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5189 0xffff00, pbn_default },
5190 { 0, }
5191};
5192
2807190b
MR		 5193static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5194 pci_channel_state_t state)
5195{
5196 struct serial_private *priv = pci_get_drvdata(dev);
5197
5198 if (state == pci_channel_io_perm_failure)
5199 return PCI_ERS_RESULT_DISCONNECT;
5200
5201 if (priv)
5202 pciserial_suspend_ports(priv);
5203
5204 pci_disable_device(dev);
5205
5206 return PCI_ERS_RESULT_NEED_RESET;
5207}
5208
5209static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5210{
5211 int rc;
5212
5213 rc = pci_enable_device(dev);
5214
5215 if (rc)
5216 return PCI_ERS_RESULT_DISCONNECT;
5217
5218 pci_restore_state(dev);
5219 pci_save_state(dev);
5220
5221 return PCI_ERS_RESULT_RECOVERED;
5222}
5223
5224static void serial8250_io_resume(struct pci_dev *dev)
5225{
5226 struct serial_private *priv = pci_get_drvdata(dev);
5227
5228 if (priv)
5229 pciserial_resume_ports(priv);
5230}
5231
1d352035 5232static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5233 .error_detected = serial8250_io_error_detected,
5234 .slot_reset = serial8250_io_slot_reset,
5235 .resume = serial8250_io_resume,
5236};
5237
1da177e4
LT		 5238static struct pci_driver serial_pci_driver = {
5239 .name = "serial",
5240 .probe = pciserial_init_one,
2d47b716 5241 .remove = pciserial_remove_one,
1d5e7996 5242#ifdef CONFIG_PM
1da177e4
LT		 5243 .suspend = pciserial_suspend_one,
5244 .resume = pciserial_resume_one,
1d5e7996 5245#endif
1da177e4 5246 .id_table = serial_pci_tbl,
2807190b 5247 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5248};
5249
15a12e83 5250module_pci_driver(serial_pci_driver);
1da177e4
LT		 5251
5252MODULE_LICENSE("GPL");
5253MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5254MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
This page took 0.94572 seconds and 5 git commands to generate.