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serial: mpc52xx: let tx_empty callback return either 0 or TIOCSER_TEMT
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4 13#include <linux/module.h>
1da177e4 14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
21947ba6 24#include <linux/rational.h>
1da177e4
LT		 25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
9a1870ce
AS		 29#include <linux/dmaengine.h>
30#include <linux/platform_data/dma-dw.h>
f549e94e 31#include <linux/platform_data/dma-hsu.h>
9a1870ce 32
1da177e4
LT		 33#include "8250.h"
34
1da177e4
LT		 35/*
36 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
5bf8f501 46 int (*probe)(struct pci_dev *dev);
1da177e4 47 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 48 int (*setup)(struct serial_private *,
49 const struct pciserial_board *,
2655a2c7 50 struct uart_8250_port *, int);
1da177e4
LT		 51 void (*exit)(struct pci_dev *dev);
52};
53
54#define PCI_NUM_BAR_RESOURCES 6
55
56struct serial_private {
70db3d91 57 struct pci_dev *dev;
1da177e4
LT		 58 unsigned int nr;
59 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
60 struct pci_serial_quirk *quirk;
61 int line[0];
62};
63
7808edcd 64static int pci_default_setup(struct serial_private*,
2655a2c7 65 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 66
1da177e4
LT		 67static void moan_device(const char *str, struct pci_dev *dev)
68{
af8c5b8d 69 dev_err(&dev->dev,
ad361c98
JP		 70 "%s: %s\n"
71 "Please send the output of lspci -vv, this\n"
72 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
73 "manufacturer and name of serial board or\n"
f2e0ea86 74 "modem board to <linux-serial@vger.kernel.org>.\n",
1da177e4
LT		 75 pci_name(dev), str, dev->vendor, dev->device,
76 dev->subsystem_vendor, dev->subsystem_device);
77}
78
79static int
2655a2c7 80setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 81 int bar, int offset, int regshift)
82{
70db3d91 83 struct pci_dev *dev = priv->dev;
1da177e4
LT		 84
85 if (bar >= PCI_NUM_BAR_RESOURCES)
86 return -EINVAL;
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4 89 if (!priv->remapped_bar[bar])
398a9db6 90 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
1da177e4
LT		 91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
2655a2c7
AC		 94 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
398a9db6 96 port->port.mapbase = pci_resource_start(dev, bar) + offset;
2655a2c7
AC		 97 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
1da177e4 99 } else {
2655a2c7 100 port->port.iotype = UPIO_PORT;
398a9db6 101 port->port.iobase = pci_resource_start(dev, bar) + offset;
2655a2c7
AC		 102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
1da177e4
LT		 105 }
106 return 0;
107}
108
02c9b5cf
KJ		 109/*
110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 */
112static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 113 const struct pciserial_board *board,
2655a2c7 114 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 115{
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
118
119 if (idx < 2) {
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
122 bar += 1;
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
125 bar += 2;
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
128 bar += 3;
129 offset += ((idx - 6) * board->uart_offset);
130 }
131
132 return setup_port(priv, port, bar, offset, board->reg_shift);
133}
134
1da177e4
LT		 135/*
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139static int
975a1a7d 140afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 141 struct uart_8250_port *port, int idx)
1da177e4
LT		 142{
143 unsigned int bar, offset = board->first_offset;
5756ee99 144
1da177e4
LT		 145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
70db3d91 153 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 154}
155
156/*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
61a116ef 163static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 164{
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 182 rc = 1;
183 break;
184 }
185
186 return rc;
187}
188
189/*
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
192 */
193static int
975a1a7d
RK		 194pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
2655a2c7 196 struct uart_8250_port *port, int idx)
1da177e4
LT		 197{
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
200
70db3d91 201 switch (priv->dev->subsystem_device) {
1da177e4
LT		 202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203 if (idx == 3)
204 idx++;
205 break;
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207 if (idx > 0)
208 idx++;
209 if (idx > 2)
210 idx++;
211 break;
212 }
213 if (idx > 2)
214 offset = 0x18;
215
216 offset += idx * board->uart_offset;
217
70db3d91 218 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 219}
220
221/*
222 * Added for EKF Intel i960 serial boards
223 */
61a116ef 224static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4 225{
0a0d412a 226 u32 oldval;
1da177e4
LT		 227
228 if (!(dev->subsystem_device & 0x1000))
229 return -ENODEV;
230
231 /* is firmware started? */
0a0d412a 232 pci_read_config_dword(dev, 0x44, &oldval);
5756ee99 233 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 235 return -ENODEV;
236 }
237 return 0;
238}
239
240/*
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
244 * mapped memory.
245 */
61a116ef 246static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 247{
248 u8 irq_config;
249 void __iomem *p;
250
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
253 return 0;
254 }
255
256 irq_config = 0x41;
add7b58e 257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 259 irq_config = 0x43;
5756ee99 260
1da177e4 261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 263 /*
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
269 * deep FIFOs
270 */
271 irq_config = 0x5b;
1da177e4
LT		 272 /*
273 * enable/disable interrupts
274 */
6f441fe9 275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 276 if (p == NULL)
277 return -ENOMEM;
278 writel(irq_config, p + 0x4c);
279
280 /*
281 * Read the register back to ensure that it took effect.
282 */
283 readl(p + 0x4c);
284 iounmap(p);
285
286 return 0;
287}
288
ae8d8a14 289static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 290{
291 u8 __iomem *p;
292
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294 return;
295
296 /*
297 * disable interrupts
298 */
6f441fe9 299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 300 if (p != NULL) {
301 writel(0, p + 0x4c);
302
303 /*
304 * Read the register back to ensure that it took effect.
305 */
306 readl(p + 0x4c);
307 iounmap(p);
308 }
309}
310
04bf7e74
WP		 311#define NI8420_INT_ENABLE_REG 0x38
312#define NI8420_INT_ENABLE_BIT 0x2000
313
ae8d8a14 314static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 315{
316 void __iomem *p;
04bf7e74
WP		 317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
398a9db6 324 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 325 if (p == NULL)
326 return;
327
328 /* Disable the CPU Interrupt */
329 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330 p + NI8420_INT_ENABLE_REG);
331 iounmap(p);
332}
333
334
46a0fac9
SB		 335/* MITE registers */
336#define MITE_IOWBSR1 0xc4
337#define MITE_IOWCR1 0xf4
338#define MITE_LCIMR1 0x08
339#define MITE_LCIMR2 0x10
340
341#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342
ae8d8a14 343static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 344{
345 void __iomem *p;
46a0fac9
SB		 346 unsigned int bar = 0;
347
348 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
349 moan_device("no memory in bar", dev);
350 return;
351 }
352
398a9db6 353 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 354 if (p == NULL)
355 return;
356
357 /* Disable the CPU Interrupt */
358 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
359 iounmap(p);
360}
361
1da177e4
LT		 362/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363static int
975a1a7d 364sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 365 struct uart_8250_port *port, int idx)
1da177e4
LT		 366{
367 unsigned int bar, offset = board->first_offset;
368
369 bar = 0;
370
371 if (idx < 4) {
372 /* first four channels map to 0, 0x100, 0x200, 0x300 */
373 offset += idx * board->uart_offset;
374 } else if (idx < 8) {
375 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
376 offset += idx * board->uart_offset + 0xC00;
377 } else /* we have only 8 ports on PMC-OCTALPRO */
378 return 1;
379
70db3d91 380 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 381}
382
383/*
384* This does initialization for PMC OCTALPRO cards:
385* maps the device memory, resets the UARTs (needed, bc
386* if the module is removed and inserted again, the card
387* is in the sleep mode) and enables global interrupt.
388*/
389
390/* global control register offset for SBS PMC-OctalPro */
391#define OCT_REG_CR_OFF 0x500
392
61a116ef 393static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 394{
395 u8 __iomem *p;
396
24ed3aba 397 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 398
399 if (p == NULL)
400 return -ENOMEM;
401 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 402 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 403 udelay(50);
5756ee99 404 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 405
406 /* Set bit-2 (INTENABLE) of Control Register */
407 writeb(0x4, p + OCT_REG_CR_OFF);
408 iounmap(p);
409
410 return 0;
411}
412
413/*
414 * Disables the global interrupt of PMC-OctalPro
415 */
416
ae8d8a14 417static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 418{
419 u8 __iomem *p;
420
24ed3aba 421 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 422 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423 if (p != NULL)
1da177e4 424 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 425 iounmap(p);
426}
427
428/*
429 * SIIG serial cards have an PCI interface chip which also controls
430 * the UART clocking frequency. Each UART can be clocked independently
25985edc 431 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 432 * are stored in the EEPROM chip. It can cause problems because this
433 * version of serial driver doesn't support differently clocked UART's
434 * on single PCI card. To prevent this, initialization functions set
435 * high frequency clocking for all UART's on given card. It is safe (I
436 * hope) because it doesn't touch EEPROM settings to prevent conflicts
437 * with other OSes (like M$ DOS).
438 *
439 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 440 *
1da177e4
LT		 441 * There is two family of SIIG serial cards with different PCI
442 * interface chip and different configuration methods:
443 * - 10x cards have control registers in IO and/or memory space;
444 * - 20x cards have control registers in standard PCI configuration space.
445 *
67d74b87
RK		 446 * Note: all 10x cards have PCI device ids 0x10..
447 * all 20x cards have PCI device ids 0x20..
448 *
fbc0dc0d
AP		 449 * There are also Quartet Serial cards which use Oxford Semiconductor
450 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451 *
1da177e4
LT		 452 * Note: some SIIG cards are probed by the parport_serial object.
453 */
454
455#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
456#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457
458static int pci_siig10x_init(struct pci_dev *dev)
459{
460 u16 data;
461 void __iomem *p;
462
463 switch (dev->device & 0xfff8) {
464 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
465 data = 0xffdf;
466 break;
467 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
468 data = 0xf7ff;
469 break;
470 default: /* 1S1P, 4S */
471 data = 0xfffb;
472 break;
473 }
474
6f441fe9 475 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 476 if (p == NULL)
477 return -ENOMEM;
478
479 writew(readw(p + 0x28) & data, p + 0x28);
480 readw(p + 0x28);
481 iounmap(p);
482 return 0;
483}
484
485#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
486#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487
488static int pci_siig20x_init(struct pci_dev *dev)
489{
490 u8 data;
491
492 /* Change clock frequency for the first UART. */
493 pci_read_config_byte(dev, 0x6f, &data);
494 pci_write_config_byte(dev, 0x6f, data & 0xef);
495
496 /* If this card has 2 UART, we have to do the same with second UART. */
497 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
498 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
499 pci_read_config_byte(dev, 0x73, &data);
500 pci_write_config_byte(dev, 0x73, data & 0xef);
501 }
502 return 0;
503}
504
67d74b87
RK		 505static int pci_siig_init(struct pci_dev *dev)
506{
507 unsigned int type = dev->device & 0xff00;
508
509 if (type == 0x1000)
510 return pci_siig10x_init(dev);
511 else if (type == 0x2000)
512 return pci_siig20x_init(dev);
513
514 moan_device("Unknown SIIG card", dev);
515 return -ENODEV;
516}
517
3ec9c594 518static int pci_siig_setup(struct serial_private *priv,
975a1a7d 519 const struct pciserial_board *board,
2655a2c7 520 struct uart_8250_port *port, int idx)
3ec9c594
AP		 521{
522 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
523
524 if (idx > 3) {
525 bar = 4;
526 offset = (idx - 4) * 8;
527 }
528
529 return setup_port(priv, port, bar, offset, 0);
530}
531
1da177e4
LT		 532/*
533 * Timedia has an explosion of boards, and to avoid the PCI table from
534 * growing *huge*, we use this function to collapse some 70 entries
535 * in the PCI table into one, for sanity's and compactness's sake.
536 */
e9422e09 537static const unsigned short timedia_single_port[] = {
1da177e4
LT		 538 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
539};
540
e9422e09 541static const unsigned short timedia_dual_port[] = {
1da177e4 542 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 543 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
544 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 545 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
546 0xD079, 0
547};
548
e9422e09 549static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 550 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
551 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 552 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
553 0xB157, 0
554};
555
e9422e09 556static const unsigned short timedia_eight_port[] = {
5756ee99 557 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 558 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
559};
560
cb3592be 561static const struct timedia_struct {
1da177e4 562 int num;
e9422e09 563 const unsigned short *ids;
1da177e4
LT		 564} timedia_data[] = {
565 { 1, timedia_single_port },
566 { 2, timedia_dual_port },
567 { 4, timedia_quad_port },
e9422e09 568 { 8, timedia_eight_port }
1da177e4
LT		 569};
570
b9b24558
FB		 571/*
572 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
573 * listing them individually, this driver merely grabs them all with
574 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
575 * and should be left free to be claimed by parport_serial instead.
576 */
577static int pci_timedia_probe(struct pci_dev *dev)
578{
579 /*
580 * Check the third digit of the subdevice ID
581 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582 */
583 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584 dev_info(&dev->dev,
585 "ignoring Timedia subdevice %04x for parport_serial\n",
586 dev->subsystem_device);
587 return -ENODEV;
588 }
589
590 return 0;
591}
592
61a116ef 593static int pci_timedia_init(struct pci_dev *dev)
1da177e4 594{
e9422e09 595 const unsigned short *ids;
1da177e4
LT		 596 int i, j;
597
e9422e09 598 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 599 ids = timedia_data[i].ids;
600 for (j = 0; ids[j]; j++)
601 if (dev->subsystem_device == ids[j])
602 return timedia_data[i].num;
603 }
604 return 0;
605}
606
607/*
608 * Timedia/SUNIX uses a mixture of BARs and offsets
609 * Ugh, this is ugly as all hell --- TYT
610 */
611static int
975a1a7d
RK		 612pci_timedia_setup(struct serial_private *priv,
613 const struct pciserial_board *board,
2655a2c7 614 struct uart_8250_port *port, int idx)
1da177e4
LT		 615{
616 unsigned int bar = 0, offset = board->first_offset;
617
618 switch (idx) {
619 case 0:
620 bar = 0;
621 break;
622 case 1:
623 offset = board->uart_offset;
624 bar = 0;
625 break;
626 case 2:
627 bar = 1;
628 break;
629 case 3:
630 offset = board->uart_offset;
c2cd6d3c 631 /* FALLTHROUGH */
1da177e4
LT		 632 case 4: /* BAR 2 */
633 case 5: /* BAR 3 */
634 case 6: /* BAR 4 */
635 case 7: /* BAR 5 */
636 bar = idx - 2;
637 }
638
70db3d91 639 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 640}
641
642/*
643 * Some Titan cards are also a little weird
644 */
645static int
70db3d91 646titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 647 const struct pciserial_board *board,
2655a2c7 648 struct uart_8250_port *port, int idx)
1da177e4
LT		 649{
650 unsigned int bar, offset = board->first_offset;
651
652 switch (idx) {
653 case 0:
654 bar = 1;
655 break;
656 case 1:
657 bar = 2;
658 break;
659 default:
660 bar = 4;
661 offset = (idx - 2) * board->uart_offset;
662 }
663
70db3d91 664 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 665}
666
61a116ef 667static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 668{
669 msleep(100);
670 return 0;
671}
672
04bf7e74
WP		 673static int pci_ni8420_init(struct pci_dev *dev)
674{
675 void __iomem *p;
04bf7e74
WP		 676 unsigned int bar = 0;
677
678 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
679 moan_device("no memory in bar", dev);
680 return 0;
681 }
682
398a9db6 683 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 684 if (p == NULL)
685 return -ENOMEM;
686
687 /* Enable CPU Interrupt */
688 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
689 p + NI8420_INT_ENABLE_REG);
690
691 iounmap(p);
692 return 0;
693}
694
46a0fac9
SB		 695#define MITE_IOWBSR1_WSIZE 0xa
696#define MITE_IOWBSR1_WIN_OFFSET 0x800
697#define MITE_IOWBSR1_WENAB (1 << 7)
698#define MITE_LCIMR1_IO_IE_0 (1 << 24)
699#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
700#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701
702static int pci_ni8430_init(struct pci_dev *dev)
703{
704 void __iomem *p;
398a9db6 705 struct pci_bus_region region;
46a0fac9
SB		 706 u32 device_window;
707 unsigned int bar = 0;
708
709 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
710 moan_device("no memory in bar", dev);
711 return 0;
712 }
713
398a9db6 714 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 715 if (p == NULL)
716 return -ENOMEM;
717
398a9db6
AS		 718 /*
719 * Set device window address and size in BAR0, while acknowledging that
720 * the resource structure may contain a translated address that differs
721 * from the address the device responds to.
722 */
723 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
724 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
46a0fac9
SB		 725 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
726 writel(device_window, p + MITE_IOWBSR1);
727
728 /* Set window access to go to RAMSEL IO address space */
729 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
730 p + MITE_IOWCR1);
731
732 /* Enable IO Bus Interrupt 0 */
733 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734
735 /* Enable CPU Interrupt */
736 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
737
738 iounmap(p);
739 return 0;
740}
741
742/* UART Port Control Register */
743#define NI8430_PORTCON 0x0f
744#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
745
746static int
bf538fe4
AC		 747pci_ni8430_setup(struct serial_private *priv,
748 const struct pciserial_board *board,
2655a2c7 749 struct uart_8250_port *port, int idx)
46a0fac9 750{
398a9db6 751 struct pci_dev *dev = priv->dev;
46a0fac9 752 void __iomem *p;
46a0fac9
SB		 753 unsigned int bar, offset = board->first_offset;
754
755 if (idx >= board->num_ports)
756 return 1;
757
758 bar = FL_GET_BASE(board->flags);
759 offset += idx * board->uart_offset;
760
398a9db6 761 p = pci_ioremap_bar(dev, bar);
5d14bba9
AS		 762 if (!p)
763 return -ENOMEM;
46a0fac9 764
7c9d440e 765 /* enable the transceiver */
46a0fac9
SB		 766 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
767 p + offset + NI8430_PORTCON);
768
769 iounmap(p);
770
771 return setup_port(priv, port, bar, offset, board->reg_shift);
772}
773
7808edcd
NG		 774static int pci_netmos_9900_setup(struct serial_private *priv,
775 const struct pciserial_board *board,
2655a2c7 776 struct uart_8250_port *port, int idx)
7808edcd
NG		 777{
778 unsigned int bar;
779
333c085e
DES		 780 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
781 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
7808edcd
NG		 782 /* netmos apparently orders BARs by datasheet layout, so serial
783 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
784 */
785 bar = 3 * idx;
786
787 return setup_port(priv, port, bar, 0, board->reg_shift);
788 } else {
789 return pci_default_setup(priv, board, port, idx);
790 }
791}
792
793/* the 99xx series comes with a range of device IDs and a variety
794 * of capabilities:
795 *
796 * 9900 has varying capabilities and can cascade to sub-controllers
797 * (cascading should be purely internal)
798 * 9904 is hardwired with 4 serial ports
799 * 9912 and 9922 are hardwired with 2 serial ports
800 */
801static int pci_netmos_9900_numports(struct pci_dev *dev)
802{
803 unsigned int c = dev->class;
804 unsigned int pi;
805 unsigned short sub_serports;
806
807 pi = (c & 0xff);
808
809 if (pi == 2) {
810 return 1;
811 } else if ((pi == 0) &&
812 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
813 /* two possibilities: 0x30ps encodes number of parallel and
814 * serial ports, or 0x1000 indicates *something*. This is not
815 * immediately obvious, since the 2s1p+4s configuration seems
816 * to offer all functionality on functions 0..2, while still
817 * advertising the same function 3 as the 4s+2s1p config.
818 */
819 sub_serports = dev->subsystem_device & 0xf;
820 if (sub_serports > 0) {
821 return sub_serports;
822 } else {
af8c5b8d 823 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
7808edcd
NG		 824 return 0;
825 }
826 }
827
828 moan_device("unknown NetMos/Mostech program interface", dev);
829 return 0;
830}
46a0fac9 831
61a116ef 832static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 833{
834 /* subdevice 0x00PS means <P> parallel, <S> serial */
835 unsigned int num_serial = dev->subsystem_device & 0xf;
836
ac6ec5b1
IS		 837 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
838 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 839 return 0;
7808edcd 840
25cf9bc1
JS		 841 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
842 dev->subsystem_device == 0x0299)
843 return 0;
844
7808edcd
NG		 845 switch (dev->device) { /* FALLTHROUGH on all */
846 case PCI_DEVICE_ID_NETMOS_9904:
847 case PCI_DEVICE_ID_NETMOS_9912:
848 case PCI_DEVICE_ID_NETMOS_9922:
849 case PCI_DEVICE_ID_NETMOS_9900:
850 num_serial = pci_netmos_9900_numports(dev);
851 break;
852
853 default:
854 if (num_serial == 0 ) {
855 moan_device("unknown NetMos/Mostech device", dev);
856 }
857 }
858
1da177e4
LT		 859 if (num_serial == 0)
860 return -ENODEV;
7808edcd 861
1da177e4
LT		 862 return num_serial;
863}
864
84f8c6fc 865/*
84f8c6fc
NV		 866 * These chips are available with optionally one parallel port and up to
867 * two serial ports. Unfortunately they all have the same product id.
868 *
869 * Basic configuration is done over a region of 32 I/O ports. The base
870 * ioport is called INTA or INTC, depending on docs/other drivers.
871 *
872 * The region of the 32 I/O ports is configured in POSIO0R...
873 */
874
875/* registers */
876#define ITE_887x_MISCR 0x9c
877#define ITE_887x_INTCBAR 0x78
878#define ITE_887x_UARTBAR 0x7c
879#define ITE_887x_PS0BAR 0x10
880#define ITE_887x_POSIO0 0x60
881
882/* I/O space size */
883#define ITE_887x_IOSIZE 32
884/* I/O space size (bits 26-24; 8 bytes = 011b) */
885#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
886/* I/O space size (bits 26-24; 32 bytes = 101b) */
887#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
888/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
889#define ITE_887x_POSIO_SPEED (3 << 29)
890/* enable IO_Space bit */
891#define ITE_887x_POSIO_ENABLE (1 << 31)
892
f79abb82 893static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 894{
895 /* inta_addr are the configuration addresses of the ITE */
896 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
897 0x200, 0x280, 0 };
898 int ret, i, type;
899 struct resource *iobase = NULL;
900 u32 miscr, uartbar, ioport;
901
902 /* search for the base-ioport */
903 i = 0;
904 while (inta_addr[i] && iobase == NULL) {
905 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906 "ite887x");
907 if (iobase != NULL) {
908 /* write POSIO0R - speed | size | ioport */
909 pci_write_config_dword(dev, ITE_887x_POSIO0,
910 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
911 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
912 /* write INTCBAR - ioport */
5756ee99
AC		 913 pci_write_config_dword(dev, ITE_887x_INTCBAR,
914 inta_addr[i]);
84f8c6fc
NV		 915 ret = inb(inta_addr[i]);
916 if (ret != 0xff) {
917 /* ioport connected */
918 break;
919 }
920 release_region(iobase->start, ITE_887x_IOSIZE);
921 iobase = NULL;
922 }
923 i++;
924 }
925
926 if (!inta_addr[i]) {
af8c5b8d 927 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 928 return -ENODEV;
929 }
930
931 /* start of undocumented type checking (see parport_pc.c) */
932 type = inb(iobase->start + 0x18) & 0x0f;
933
934 switch (type) {
935 case 0x2: /* ITE8871 (1P) */
936 case 0xa: /* ITE8875 (1P) */
937 ret = 0;
938 break;
939 case 0xe: /* ITE8872 (2S1P) */
940 ret = 2;
941 break;
942 case 0x6: /* ITE8873 (1S) */
943 ret = 1;
944 break;
945 case 0x8: /* ITE8874 (2S) */
946 ret = 2;
947 break;
948 default:
949 moan_device("Unknown ITE887x", dev);
950 ret = -ENODEV;
951 }
952
953 /* configure all serial ports */
954 for (i = 0; i < ret; i++) {
955 /* read the I/O port from the device */
956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 &ioport);
958 ioport &= 0x0000FF00; /* the actual base address */
959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
961 ITE_887x_POSIO_IOSIZE_8 | ioport);
962
963 /* write the ioport to the UARTBAR */
964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
966 uartbar |= (ioport << (16 * i)); /* set the ioport */
967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968
969 /* get current config */
970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
971 /* disable interrupts (UARTx_Routing[3:0]) */
972 miscr &= ~(0xf << (12 - 4 * i));
973 /* activate the UART (UARTx_En) */
974 miscr |= 1 << (23 - i);
975 /* write new config with activated UART */
976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
977 }
978
979 if (ret <= 0) {
980 /* the device has no UARTs if we get here */
981 release_region(iobase->start, ITE_887x_IOSIZE);
982 }
983
984 return ret;
985}
986
ae8d8a14 987static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 988{
989 u32 ioport;
990 /* the ioport is bit 0-15 in POSIO0R */
991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 ioport &= 0xffff;
993 release_region(ioport, ITE_887x_IOSIZE);
994}
995
1bc8cde4
MS		 996/*
997 * EndRun Technologies.
998 * Determine the number of ports available on the device.
999 */
1000#define PCI_VENDOR_ID_ENDRUN 0x7401
1001#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002
1003static int pci_endrun_init(struct pci_dev *dev)
1004{
1005 u8 __iomem *p;
1006 unsigned long deviceID;
1007 unsigned int number_uarts = 0;
1008
1009 /* EndRun device is all 0xexxx */
1010 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011 (dev->device & 0xf000) != 0xe000)
1012 return 0;
1013
1014 p = pci_iomap(dev, 0, 5);
1015 if (p == NULL)
1016 return -ENOMEM;
1017
1018 deviceID = ioread32(p);
1019 /* EndRun device */
1020 if (deviceID == 0x07000200) {
1021 number_uarts = ioread8(p + 4);
1022 dev_dbg(&dev->dev,
1023 "%d ports detected on EndRun PCI Express device\n",
1024 number_uarts);
1025 }
1026 pci_iounmap(dev, p);
1027 return number_uarts;
1028}
1029
9f2a036a
RK		 1030/*
1031 * Oxford Semiconductor Inc.
1032 * Check that device is part of the Tornado range of devices, then determine
1033 * the number of ports available on the device.
1034 */
1035static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036{
1037 u8 __iomem *p;
1038 unsigned long deviceID;
1039 unsigned int number_uarts = 0;
1040
1041 /* OxSemi Tornado devices are all 0xCxxx */
1042 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043 (dev->device & 0xF000) != 0xC000)
1044 return 0;
1045
1046 p = pci_iomap(dev, 0, 5);
1047 if (p == NULL)
1048 return -ENOMEM;
1049
1050 deviceID = ioread32(p);
1051 /* Tornado device */
1052 if (deviceID == 0x07000200) {
1053 number_uarts = ioread8(p + 4);
af8c5b8d 1054 dev_dbg(&dev->dev,
9f2a036a 1055 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1056 number_uarts);
9f2a036a
RK		 1057 }
1058 pci_iounmap(dev, p);
1059 return number_uarts;
1060}
1061
eb26dfe8
AC		 1062static int pci_asix_setup(struct serial_private *priv,
1063 const struct pciserial_board *board,
1064 struct uart_8250_port *port, int idx)
1065{
1066 port->bugs |= UART_BUG_PARITY;
1067 return pci_default_setup(priv, board, port, idx);
1068}
1069
55c7c0fd
AC		 1070/* Quatech devices have their own extra interface features */
1071
1072struct quatech_feature {
1073 u16 devid;
1074 bool amcc;
1075};
1076
1077#define QPCR_TEST_FOR1 0x3F
1078#define QPCR_TEST_GET1 0x00
1079#define QPCR_TEST_FOR2 0x40
1080#define QPCR_TEST_GET2 0x40
1081#define QPCR_TEST_FOR3 0x80
1082#define QPCR_TEST_GET3 0x40
1083#define QPCR_TEST_FOR4 0xC0
1084#define QPCR_TEST_GET4 0x80
1085
1086#define QOPR_CLOCK_X1 0x0000
1087#define QOPR_CLOCK_X2 0x0001
1088#define QOPR_CLOCK_X4 0x0002
1089#define QOPR_CLOCK_X8 0x0003
1090#define QOPR_CLOCK_RATE_MASK 0x0003
1091
1092
1093static struct quatech_feature quatech_cards[] = {
1094 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1098 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1099 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1100 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1101 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1103 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1104 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1105 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113 { 0, }
1114};
1115
1116static int pci_quatech_amcc(u16 devid)
1117{
1118 struct quatech_feature *qf = &quatech_cards[0];
1119 while (qf->devid) {
1120 if (qf->devid == devid)
1121 return qf->amcc;
1122 qf++;
1123 }
1124 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125 return 0;
1126};
1127
1128static int pci_quatech_rqopr(struct uart_8250_port *port)
1129{
1130 unsigned long base = port->port.iobase;
1131 u8 LCR, val;
1132
1133 LCR = inb(base + UART_LCR);
1134 outb(0xBF, base + UART_LCR);
1135 val = inb(base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137 return val;
1138}
1139
1140static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141{
1142 unsigned long base = port->port.iobase;
1143 u8 LCR, val;
1144
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(qopr, base + UART_SCR);
1149 outb(LCR, base + UART_LCR);
1150}
1151
1152static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153{
1154 unsigned long base = port->port.iobase;
1155 u8 LCR, val, qmcr;
1156
1157 LCR = inb(base + UART_LCR);
1158 outb(0xBF, base + UART_LCR);
1159 val = inb(base + UART_SCR);
1160 outb(val | 0x10, base + UART_SCR);
1161 qmcr = inb(base + UART_MCR);
1162 outb(val, base + UART_SCR);
1163 outb(LCR, base + UART_LCR);
1164
1165 return qmcr;
1166}
1167
1168static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169{
1170 unsigned long base = port->port.iobase;
1171 u8 LCR, val;
1172
1173 LCR = inb(base + UART_LCR);
1174 outb(0xBF, base + UART_LCR);
1175 val = inb(base + UART_SCR);
1176 outb(val | 0x10, base + UART_SCR);
1177 outb(qmcr, base + UART_MCR);
1178 outb(val, base + UART_SCR);
1179 outb(LCR, base + UART_LCR);
1180}
1181
1182static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183{
1184 unsigned long base = port->port.iobase;
1185 u8 LCR, val;
1186
1187 LCR = inb(base + UART_LCR);
1188 outb(0xBF, base + UART_LCR);
1189 val = inb(base + UART_SCR);
1190 if (val & 0x20) {
1191 outb(0x80, UART_LCR);
1192 if (!(inb(UART_SCR) & 0x20)) {
1193 outb(LCR, base + UART_LCR);
1194 return 1;
1195 }
1196 }
1197 return 0;
1198}
1199
1200static int pci_quatech_test(struct uart_8250_port *port)
1201{
1202 u8 reg;
1203 u8 qopr = pci_quatech_rqopr(port);
1204 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205 reg = pci_quatech_rqopr(port) & 0xC0;
1206 if (reg != QPCR_TEST_GET1)
1207 return -EINVAL;
1208 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209 reg = pci_quatech_rqopr(port) & 0xC0;
1210 if (reg != QPCR_TEST_GET2)
1211 return -EINVAL;
1212 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213 reg = pci_quatech_rqopr(port) & 0xC0;
1214 if (reg != QPCR_TEST_GET3)
1215 return -EINVAL;
1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217 reg = pci_quatech_rqopr(port) & 0xC0;
1218 if (reg != QPCR_TEST_GET4)
1219 return -EINVAL;
1220
1221 pci_quatech_wqopr(port, qopr);
1222 return 0;
1223}
1224
1225static int pci_quatech_clock(struct uart_8250_port *port)
1226{
1227 u8 qopr, reg, set;
1228 unsigned long clock;
1229
1230 if (pci_quatech_test(port) < 0)
1231 return 1843200;
1232
1233 qopr = pci_quatech_rqopr(port);
1234
1235 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236 reg = pci_quatech_rqopr(port);
1237 if (reg & QOPR_CLOCK_X8) {
1238 clock = 1843200;
1239 goto out;
1240 }
1241 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242 reg = pci_quatech_rqopr(port);
1243 if (!(reg & QOPR_CLOCK_X8)) {
1244 clock = 1843200;
1245 goto out;
1246 }
1247 reg &= QOPR_CLOCK_X8;
1248 if (reg == QOPR_CLOCK_X2) {
1249 clock = 3685400;
1250 set = QOPR_CLOCK_X2;
1251 } else if (reg == QOPR_CLOCK_X4) {
1252 clock = 7372800;
1253 set = QOPR_CLOCK_X4;
1254 } else if (reg == QOPR_CLOCK_X8) {
1255 clock = 14745600;
1256 set = QOPR_CLOCK_X8;
1257 } else {
1258 clock = 1843200;
1259 set = QOPR_CLOCK_X1;
1260 }
1261 qopr &= ~QOPR_CLOCK_RATE_MASK;
1262 qopr |= set;
1263
1264out:
1265 pci_quatech_wqopr(port, qopr);
1266 return clock;
1267}
1268
1269static int pci_quatech_rs422(struct uart_8250_port *port)
1270{
1271 u8 qmcr;
1272 int rs422 = 0;
1273
1274 if (!pci_quatech_has_qmcr(port))
1275 return 0;
1276 qmcr = pci_quatech_rqmcr(port);
1277 pci_quatech_wqmcr(port, 0xFF);
1278 if (pci_quatech_rqmcr(port))
1279 rs422 = 1;
1280 pci_quatech_wqmcr(port, qmcr);
1281 return rs422;
1282}
1283
1284static int pci_quatech_init(struct pci_dev *dev)
1285{
1286 if (pci_quatech_amcc(dev->device)) {
1287 unsigned long base = pci_resource_start(dev, 0);
1288 if (base) {
1289 u32 tmp;
9c5320f8 1290 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1291 tmp = inl(base + 0x3c);
1292 outl(tmp | 0x01000000, base + 0x3c);
9c5320f8 1293 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1294 }
1295 }
1296 return 0;
1297}
1298
1299static int pci_quatech_setup(struct serial_private *priv,
1300 const struct pciserial_board *board,
1301 struct uart_8250_port *port, int idx)
1302{
1303 /* Needed by pci_quatech calls below */
1304 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305 /* Set up the clocking */
1306 port->port.uartclk = pci_quatech_clock(port);
1307 /* For now just warn about RS422 */
1308 if (pci_quatech_rs422(port))
1309 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310 return pci_default_setup(priv, board, port, idx);
1311}
1312
d73dfc6a 1313static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1314{
1315}
1316
eb26dfe8 1317static int pci_default_setup(struct serial_private *priv,
975a1a7d 1318 const struct pciserial_board *board,
2655a2c7 1319 struct uart_8250_port *port, int idx)
1da177e4
LT		 1320{
1321 unsigned int bar, offset = board->first_offset, maxnr;
1322
1323 bar = FL_GET_BASE(board->flags);
1324 if (board->flags & FL_BASE_BARS)
1325 bar += idx;
1326 else
1327 offset += idx * board->uart_offset;
1328
2427ddd8
GKH		 1329 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330 (board->reg_shift + 3);
1da177e4
LT		 1331
1332 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333 return 1;
5756ee99 1334
70db3d91 1335 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1336}
1337
94341475
AB		 1338static int pci_pericom_setup(struct serial_private *priv,
1339 const struct pciserial_board *board,
1340 struct uart_8250_port *port, int idx)
1341{
1342 unsigned int bar, offset = board->first_offset, maxnr;
1343
1344 bar = FL_GET_BASE(board->flags);
1345 if (board->flags & FL_BASE_BARS)
1346 bar += idx;
1347 else
1348 offset += idx * board->uart_offset;
1349
1350 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351 (board->reg_shift + 3);
1352
1353 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354 return 1;
1355
1356 port->port.uartclk = 14745600;
1357
1358 return setup_port(priv, port, bar, offset, board->reg_shift);
1359}
1360
095e24b0
DB		 1361static int
1362ce4100_serial_setup(struct serial_private *priv,
1363 const struct pciserial_board *board,
2655a2c7 1364 struct uart_8250_port *port, int idx)
095e24b0
DB		 1365{
1366 int ret;
1367
08ec212c 1368 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1369 port->port.iotype = UPIO_MEM32;
1370 port->port.type = PORT_XSCALE;
1371 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372 port->port.regshift = 2;
095e24b0
DB		 1373
1374 return ret;
1375}
1376
b15e5691
HK		 1377#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1378#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1379
29897087
AC		 1380#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1381#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1382
b15e5691
HK		 1383#define BYT_PRV_CLK 0x800
1384#define BYT_PRV_CLK_EN (1 << 0)
1385#define BYT_PRV_CLK_M_VAL_SHIFT 1
1386#define BYT_PRV_CLK_N_VAL_SHIFT 16
1387#define BYT_PRV_CLK_UPDATE (1 << 31)
1388
b15e5691
HK		 1389#define BYT_TX_OVF_INT 0x820
1390#define BYT_TX_OVF_INT_MASK (1 << 1)
1391
1392static void
1393byt_set_termios(struct uart_port *p, struct ktermios *termios,
1394 struct ktermios *old)
1395{
1396 unsigned int baud = tty_termios_baud_rate(termios);
21947ba6
AS		 1397 unsigned long fref = 100000000, fuart = baud * 16;
1398 unsigned long w = BIT(15) - 1;
1399 unsigned long m, n;
b15e5691
HK		 1400 u32 reg;
1401
21947ba6
AS		 1402 /* Get Fuart closer to Fref */
1403 fuart *= rounddown_pow_of_two(fref / fuart);
1404
50825c57
AS		 1405 /*
1406 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1407 * dividers must be adjusted.
1408 *
1409 * uartclk = (m / n) * 100 MHz, where m <= n
1410 */
21947ba6
AS		 1411 rational_best_approximation(fuart, fref, w, w, &m, &n);
1412 p->uartclk = fuart;
b15e5691
HK		 1413
1414 /* Reset the clock */
1415 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1416 writel(reg, p->membase + BYT_PRV_CLK);
1417 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1418 writel(reg, p->membase + BYT_PRV_CLK);
1419
b15e5691
HK		 1420 serial8250_do_set_termios(p, termios, old);
1421}
1422
1423static bool byt_dma_filter(struct dma_chan *chan, void *param)
1424{
9a1870ce
AS		 1425 struct dw_dma_slave *dws = param;
1426
1427 if (dws->dma_dev != chan->device->dev)
1428 return false;
1429
1430 chan->private = dws;
1431 return true;
b15e5691
HK		 1432}
1433
1434static int
1435byt_serial_setup(struct serial_private *priv,
1436 const struct pciserial_board *board,
1437 struct uart_8250_port *port, int idx)
1438{
9a1870ce
AS		 1439 struct pci_dev *pdev = priv->dev;
1440 struct device *dev = port->port.dev;
b15e5691 1441 struct uart_8250_dma *dma;
9a1870ce
AS		 1442 struct dw_dma_slave *tx_param, *rx_param;
1443 struct pci_dev *dma_dev;
b15e5691
HK		 1444 int ret;
1445
9a1870ce 1446 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
b15e5691
HK		 1447 if (!dma)
1448 return -ENOMEM;
1449
9a1870ce
AS		 1450 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1451 if (!tx_param)
1452 return -ENOMEM;
1453
1454 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1455 if (!rx_param)
1456 return -ENOMEM;
1457
1458 switch (pdev->device) {
b15e5691 1459 case PCI_DEVICE_ID_INTEL_BYT_UART1:
29897087 1460 case PCI_DEVICE_ID_INTEL_BSW_UART1:
9a1870ce
AS		 1461 rx_param->src_id = 3;
1462 tx_param->dst_id = 2;
b15e5691
HK		 1463 break;
1464 case PCI_DEVICE_ID_INTEL_BYT_UART2:
29897087 1465 case PCI_DEVICE_ID_INTEL_BSW_UART2:
9a1870ce
AS		 1466 rx_param->src_id = 5;
1467 tx_param->dst_id = 4;
b15e5691
HK		 1468 break;
1469 default:
1470 return -EINVAL;
1471 }
1472
9a1870ce
AS		 1473 rx_param->src_master = 1;
1474 rx_param->dst_master = 0;
1475
b15e5691
HK		 1476 dma->rxconf.src_maxburst = 16;
1477
9a1870ce
AS		 1478 tx_param->src_master = 1;
1479 tx_param->dst_master = 0;
1480
b15e5691
HK		 1481 dma->txconf.dst_maxburst = 16;
1482
9a1870ce
AS		 1483 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1484 rx_param->dma_dev = &dma_dev->dev;
1485 tx_param->dma_dev = &dma_dev->dev;
1486
b15e5691 1487 dma->fn = byt_dma_filter;
9a1870ce
AS		 1488 dma->rx_param = rx_param;
1489 dma->tx_param = tx_param;
b15e5691
HK		 1490
1491 ret = pci_default_setup(priv, board, port, idx);
1492 port->port.iotype = UPIO_MEM;
1493 port->port.type = PORT_16550A;
1494 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1495 port->port.set_termios = byt_set_termios;
1496 port->port.fifosize = 64;
1497 port->tx_loadsz = 64;
1498 port->dma = dma;
1499 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1500
1501 /* Disable Tx counter interrupts */
1502 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1503
1504 return ret;
1505}
1506
f549e94e
AS		 1507#define INTEL_MID_UART_PS 0x30
1508#define INTEL_MID_UART_MUL 0x34
c1a67b48 1509#define INTEL_MID_UART_DIV 0x38
f549e94e 1510
c1a67b48
AS		 1511static void intel_mid_set_termios(struct uart_port *p,
1512 struct ktermios *termios,
1513 struct ktermios *old,
1514 unsigned long fref)
f549e94e
AS		 1515{
1516 unsigned int baud = tty_termios_baud_rate(termios);
c1a67b48
AS		 1517 unsigned short ps = 16;
1518 unsigned long fuart = baud * ps;
1519 unsigned long w = BIT(24) - 1;
1520 unsigned long mul, div;
1521
1522 if (fref < fuart) {
1523 /* Find prescaler value that satisfies Fuart < Fref */
1524 if (fref > baud)
1525 ps = fref / baud; /* baud rate too high */
1526 else
1527 ps = 1; /* PLL case */
1528 fuart = baud * ps;
1529 } else {
1530 /* Get Fuart closer to Fref */
1531 fuart *= rounddown_pow_of_two(fref / fuart);
f549e94e
AS		 1532 }
1533
c1a67b48
AS		 1534 rational_best_approximation(fuart, fref, w, w, &mul, &div);
1535 p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */
1536
f549e94e
AS		 1537 writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
1538 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
c1a67b48 1539 writel(div, p->membase + INTEL_MID_UART_DIV);
f549e94e
AS		 1540
1541 serial8250_do_set_termios(p, termios, old);
1542}
90b9aacf
AS		 1543
1544static void intel_mid_set_termios_38_4M(struct uart_port *p,
1545 struct ktermios *termios,
1546 struct ktermios *old)
1547{
1548 intel_mid_set_termios(p, termios, old, 38400000);
1549}
1550
c1a67b48
AS		 1551static void intel_mid_set_termios_50M(struct uart_port *p,
1552 struct ktermios *termios,
1553 struct ktermios *old)
1554{
1555 /*
1556 * The uart clk is 50Mhz, and the baud rate come from:
1557 * baud = 50M * MUL / (DIV * PS * DLAB)
1558 */
1559 intel_mid_set_termios(p, termios, old, 50000000);
1560}
f549e94e
AS		 1561
1562static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
1563{
1564 struct hsu_dma_slave *s = param;
1565
1566 if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
1567 return false;
1568
1569 chan->private = s;
1570 return true;
1571}
1572
1573static int intel_mid_serial_setup(struct serial_private *priv,
1574 const struct pciserial_board *board,
1575 struct uart_8250_port *port, int idx,
1576 int index, struct pci_dev *dma_dev)
1577{
1578 struct device *dev = port->port.dev;
1579 struct uart_8250_dma *dma;
1580 struct hsu_dma_slave *tx_param, *rx_param;
1581
1582 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1583 if (!dma)
1584 return -ENOMEM;
1585
1586 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1587 if (!tx_param)
1588 return -ENOMEM;
1589
1590 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1591 if (!rx_param)
1592 return -ENOMEM;
1593
1594 rx_param->chan_id = index * 2 + 1;
1595 tx_param->chan_id = index * 2;
1596
1597 dma->rxconf.src_maxburst = 64;
1598 dma->txconf.dst_maxburst = 64;
1599
1600 rx_param->dma_dev = &dma_dev->dev;
1601 tx_param->dma_dev = &dma_dev->dev;
1602
1603 dma->fn = intel_mid_dma_filter;
1604 dma->rx_param = rx_param;
1605 dma->tx_param = tx_param;
1606
1607 port->port.type = PORT_16750;
1608 port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
1609 port->dma = dma;
1610
1611 return pci_default_setup(priv, board, port, idx);
1612}
1613
1614#define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
1615#define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
1616#define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
1617
1618static int pnw_serial_setup(struct serial_private *priv,
1619 const struct pciserial_board *board,
1620 struct uart_8250_port *port, int idx)
1621{
1622 struct pci_dev *pdev = priv->dev;
1623 struct pci_dev *dma_dev;
1624 int index;
1625
1626 switch (pdev->device) {
1627 case PCI_DEVICE_ID_INTEL_PNW_UART1:
1628 index = 0;
1629 break;
1630 case PCI_DEVICE_ID_INTEL_PNW_UART2:
1631 index = 1;
1632 break;
1633 case PCI_DEVICE_ID_INTEL_PNW_UART3:
1634 index = 2;
1635 break;
1636 default:
1637 return -EINVAL;
1638 }
1639
1640 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
1641
1642 port->port.set_termios = intel_mid_set_termios_50M;
1643
1644 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1645}
1646
90b9aacf
AS		 1647#define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191
1648
1649static int tng_serial_setup(struct serial_private *priv,
1650 const struct pciserial_board *board,
1651 struct uart_8250_port *port, int idx)
1652{
1653 struct pci_dev *pdev = priv->dev;
1654 struct pci_dev *dma_dev;
1655 int index = PCI_FUNC(pdev->devfn);
1656
1657 /* Currently no support for HSU port0 */
1658 if (index-- == 0)
1659 return -ENODEV;
1660
1661 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
1662
1663 port->port.set_termios = intel_mid_set_termios_38_4M;
1664
1665 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1666}
1667
d9a0fbfd
AP		 1668static int
1669pci_omegapci_setup(struct serial_private *priv,
1798ca13 1670 const struct pciserial_board *board,
2655a2c7 1671 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1672{
1673 return setup_port(priv, port, 2, idx * 8, 0);
1674}
1675
ebebd49a
SH		 1676static int
1677pci_brcm_trumanage_setup(struct serial_private *priv,
1678 const struct pciserial_board *board,
1679 struct uart_8250_port *port, int idx)
1680{
1681 int ret = pci_default_setup(priv, board, port, idx);
1682
1683 port->port.type = PORT_BRCM_TRUMANAGE;
1684 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1685 return ret;
1686}
1687
fecf27a3
PH		 1688/* RTS will control by MCR if this bit is 0 */
1689#define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1690/* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1691#define FINTEK_RTS_INVERT BIT(5)
1692
1693/* We should do proper H/W transceiver setting before change to RS485 mode */
1694static int pci_fintek_rs485_config(struct uart_port *port,
1695 struct serial_rs485 *rs485)
1696{
1697 u8 setting;
1698 u8 *index = (u8 *) port->private_data;
1699 struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1700 dev);
1701
1702 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1703
1704 if (rs485->flags & SER_RS485_ENABLED)
1705 memset(rs485->padding, 0, sizeof(rs485->padding));
1706 else
1707 memset(rs485, 0, sizeof(*rs485));
1708
1709 /* F81504/508/512 not support RTS delay before or after send */
1710 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1711
1712 if (rs485->flags & SER_RS485_ENABLED) {
1713 /* Enable RTS H/W control mode */
1714 setting |= FINTEK_RTS_CONTROL_BY_HW;
1715
1716 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1717 /* RTS driving high on TX */
1718 setting &= ~FINTEK_RTS_INVERT;
1719 } else {
1720 /* RTS driving low on TX */
1721 setting |= FINTEK_RTS_INVERT;
1722 }
1723
1724 rs485->delay_rts_after_send = 0;
1725 rs485->delay_rts_before_send = 0;
1726 } else {
1727 /* Disable RTS H/W control mode */
1728 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1729 }
1730
1731 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1732 port->rs485 = *rs485;
1733 return 0;
1734}
1735
2c62a3c8
GKH		 1736static int pci_fintek_setup(struct serial_private *priv,
1737 const struct pciserial_board *board,
1738 struct uart_8250_port *port, int idx)
1739{
1740 struct pci_dev *pdev = priv->dev;
fecf27a3 1741 u8 *data;
2c62a3c8 1742 u8 config_base;
6a8bc239
PH		 1743 u16 iobase;
1744
1745 config_base = 0x40 + 0x08 * idx;
1746
1747 /* Get the io address from configuration space */
1748 pci_read_config_word(pdev, config_base + 4, &iobase);
1749
1750 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1751
1752 port->port.iotype = UPIO_PORT;
1753 port->port.iobase = iobase;
fecf27a3
PH		 1754 port->port.rs485_config = pci_fintek_rs485_config;
1755
1756 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1757 if (!data)
1758 return -ENOMEM;
1759
1760 /* preserve index in PCI configuration space */
1761 *data = idx;
1762 port->port.private_data = data;
6a8bc239
PH		 1763
1764 return 0;
1765}
1766
1767static int pci_fintek_init(struct pci_dev *dev)
1768{
1769 unsigned long iobase;
1770 u32 max_port, i;
cb8ee9f0 1771 u32 bar_data[3];
6a8bc239 1772 u8 config_base;
2c62a3c8 1773
6a8bc239
PH		 1774 switch (dev->device) {
1775 case 0x1104: /* 4 ports */
1776 case 0x1108: /* 8 ports */
1777 max_port = dev->device & 0xff;
cb8ee9f0 1778 break;
6a8bc239
PH		 1779 case 0x1112: /* 12 ports */
1780 max_port = 12;
cb8ee9f0 1781 break;
2c62a3c8 1782 default:
2c62a3c8
GKH		 1783 return -EINVAL;
1784 }
1785
cb8ee9f0 1786 /* Get the io address dispatch from the BIOS */
6a8bc239
PH		 1787 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1788 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1789 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
cb8ee9f0 1790
6a8bc239
PH		 1791 for (i = 0; i < max_port; ++i) {
1792 /* UART0 configuration offset start from 0x40 */
1793 config_base = 0x40 + 0x08 * i;
2c62a3c8 1794
6a8bc239
PH		 1795 /* Calculate Real IO Port */
1796 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
2c62a3c8 1797
6a8bc239
PH		 1798 /* Enable UART I/O port */
1799 pci_write_config_byte(dev, config_base + 0x00, 0x01);
2c62a3c8 1800
6a8bc239
PH		 1801 /* Select 128-byte FIFO and 8x FIFO threshold */
1802 pci_write_config_byte(dev, config_base + 0x01, 0x33);
2c62a3c8 1803
6a8bc239
PH		 1804 /* LSB UART */
1805 pci_write_config_byte(dev, config_base + 0x04,
1806 (u8)(iobase & 0xff));
2c62a3c8 1807
6a8bc239
PH		 1808 /* MSB UART */
1809 pci_write_config_byte(dev, config_base + 0x05,
1810 (u8)((iobase & 0xff00) >> 8));
2c62a3c8 1811
6a8bc239 1812 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
fecf27a3
PH		 1813
1814 /* force init to RS232 Mode */
1815 pci_write_config_byte(dev, config_base + 0x07, 0x01);
6a8bc239 1816 }
2c62a3c8 1817
6a8bc239 1818 return max_port;
2c62a3c8
GKH		 1819}
1820
b6adea33
MCC		 1821static int skip_tx_en_setup(struct serial_private *priv,
1822 const struct pciserial_board *board,
2655a2c7 1823 struct uart_8250_port *port, int idx)
b6adea33 1824{
2655a2c7 1825 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1826 dev_dbg(&priv->dev->dev,
1827 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1828 priv->dev->vendor, priv->dev->device,
1829 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1830
1831 return pci_default_setup(priv, board, port, idx);
1832}
1833
0ad372b9
SM		 1834static void kt_handle_break(struct uart_port *p)
1835{
b1261c86 1836 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1837 /*
1838 * On receipt of a BI, serial device in Intel ME (Intel
1839 * management engine) needs to have its fifos cleared for sane
1840 * SOL (Serial Over Lan) output.
1841 */
1842 serial8250_clear_and_reinit_fifos(up);
1843}
1844
1845static unsigned int kt_serial_in(struct uart_port *p, int offset)
1846{
b1261c86 1847 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1848 unsigned int val;
1849
1850 /*
1851 * When the Intel ME (management engine) gets reset its serial
1852 * port registers could return 0 momentarily. Functions like
1853 * serial8250_console_write, read and save the IER, perform
1854 * some operation and then restore it. In order to avoid
1855 * setting IER register inadvertently to 0, if the value read
1856 * is 0, double check with ier value in uart_8250_port and use
1857 * that instead. up->ier should be the same value as what is
1858 * currently configured.
1859 */
1860 val = inb(p->iobase + offset);
1861 if (offset == UART_IER) {
1862 if (val == 0)
1863 val = up->ier;
1864 }
1865 return val;
1866}
1867
bc02d15a
DW		 1868static int kt_serial_setup(struct serial_private *priv,
1869 const struct pciserial_board *board,
2655a2c7 1870 struct uart_8250_port *port, int idx)
bc02d15a 1871{
2655a2c7
AC		 1872 port->port.flags |= UPF_BUG_THRE;
1873 port->port.serial_in = kt_serial_in;
1874 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1875 return skip_tx_en_setup(priv, board, port, idx);
1876}
1877
eb7073db
TM		 1878static int pci_eg20t_init(struct pci_dev *dev)
1879{
1880#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1881 return -ENODEV;
1882#else
1883 return 0;
1884#endif
1885}
1886
899f0c1c
SG		 1887#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1888#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1889
06315348
SH		 1890static int
1891pci_xr17c154_setup(struct serial_private *priv,
1892 const struct pciserial_board *board,
2655a2c7 1893 struct uart_8250_port *port, int idx)
06315348 1894{
2655a2c7 1895 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1896 return pci_default_setup(priv, board, port, idx);
1897}
1898
899f0c1c
SG		 1899static inline int
1900xr17v35x_has_slave(struct serial_private *priv)
1901{
1902 const int dev_id = priv->dev->device;
1903
1904 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1905 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1906}
1907
dc96efb7
MS		 1908static int
1909pci_xr17v35x_setup(struct serial_private *priv,
1910 const struct pciserial_board *board,
1911 struct uart_8250_port *port, int idx)
1912{
1913 u8 __iomem *p;
1914
1915 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1916 if (p == NULL)
1917 return -ENOMEM;
dc96efb7
MS		 1918
1919 port->port.flags |= UPF_EXAR_EFR;
1920
899f0c1c
SG		 1921 /*
1922 * Setup the uart clock for the devices on expansion slot to
1923 * half the clock speed of the main chip (which is 125MHz)
1924 */
1925 if (xr17v35x_has_slave(priv) && idx >= 8)
1926 port->port.uartclk = (7812500 * 16 / 2);
1927
dc96efb7
MS		 1928 /*
1929 * Setup Multipurpose Input/Output pins.
1930 */
1931 if (idx == 0) {
1932 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1933 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1934 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1935 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1936 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1937 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1938 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1939 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1940 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1941 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1942 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1943 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1944 }
f965b9c4
MS		 1945 writeb(0x00, p + UART_EXAR_8XMODE);
1946 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1947 writeb(128, p + UART_EXAR_TXTRG);
1948 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1949 iounmap(p);
1950
1951 return pci_default_setup(priv, board, port, idx);
1952}
1953
14faa8cc
MS		 1954#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1955#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1956#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1957#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1958
1959static int
1960pci_fastcom335_setup(struct serial_private *priv,
1961 const struct pciserial_board *board,
1962 struct uart_8250_port *port, int idx)
1963{
1964 u8 __iomem *p;
1965
1966 p = pci_ioremap_bar(priv->dev, 0);
1967 if (p == NULL)
1968 return -ENOMEM;
1969
1970 port->port.flags |= UPF_EXAR_EFR;
1971
1972 /*
1973 * Setup Multipurpose Input/Output pins.
1974 */
1975 if (idx == 0) {
1976 switch (priv->dev->device) {
1977 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1978 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1979 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1980 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1981 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1982 break;
1983 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1984 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1985 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1986 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1987 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1988 break;
1989 }
1990 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1991 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1992 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1993 }
1994 writeb(0x00, p + UART_EXAR_8XMODE);
1995 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1996 writeb(32, p + UART_EXAR_TXTRG);
1997 writeb(32, p + UART_EXAR_RXTRG);
1998 iounmap(p);
1999
2000 return pci_default_setup(priv, board, port, idx);
2001}
2002
6971c635
GA		 2003static int
2004pci_wch_ch353_setup(struct serial_private *priv,
2005 const struct pciserial_board *board,
2006 struct uart_8250_port *port, int idx)
2007{
2008 port->port.flags |= UPF_FIXED_TYPE;
2009 port->port.type = PORT_16550A;
06315348
SH		 2010 return pci_default_setup(priv, board, port, idx);
2011}
2012
2fdd8c8c 2013static int
72a3c0e4 2014pci_wch_ch38x_setup(struct serial_private *priv,
2fdd8c8c
SP		 2015 const struct pciserial_board *board,
2016 struct uart_8250_port *port, int idx)
2017{
2018 port->port.flags |= UPF_FIXED_TYPE;
2019 port->port.type = PORT_16850;
2020 return pci_default_setup(priv, board, port, idx);
2021}
2022
1da177e4
LT		 2023#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
2024#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
2025#define PCI_DEVICE_ID_OCTPRO 0x0001
2026#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
2027#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
2028#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
2029#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 2030#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
2031#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 2032#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 2033#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 2034#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
0c6d774c
TW		 2035#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
2036#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
66169ad1
YY		 2037#define PCI_DEVICE_ID_TITAN_200I 0x8028
2038#define PCI_DEVICE_ID_TITAN_400I 0x8048
2039#define PCI_DEVICE_ID_TITAN_800I 0x8088
2040#define PCI_DEVICE_ID_TITAN_800EH 0xA007
2041#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
2042#define PCI_DEVICE_ID_TITAN_400EH 0xA009
2043#define PCI_DEVICE_ID_TITAN_100E 0xA010
2044#define PCI_DEVICE_ID_TITAN_200E 0xA012
2045#define PCI_DEVICE_ID_TITAN_400E 0xA013
2046#define PCI_DEVICE_ID_TITAN_800E 0xA014
2047#define PCI_DEVICE_ID_TITAN_200EI 0xA016
2048#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
48c0247d 2049#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 2050#define PCI_DEVICE_ID_TITAN_400V3 0xA310
2051#define PCI_DEVICE_ID_TITAN_410V3 0xA312
2052#define PCI_DEVICE_ID_TITAN_800V3 0xA314
2053#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 2054#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 2055#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 2056#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 2057#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 2058#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 2059#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 2060#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
2061#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
feb58142 2062#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
27788c5f 2063#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 2064#define PCI_VENDOR_ID_AGESTAR 0x5372
2065#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 2066#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 2067#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
2068#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 2069#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 2070#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 2071#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1ede7dcc 2072#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
14faa8cc 2073
abd7baca
SC		 2074#define PCI_VENDOR_ID_SUNIX 0x1fd4
2075#define PCI_DEVICE_ID_SUNIX_1999 0x1999
2076
2fdd8c8c
SP		 2077#define PCIE_VENDOR_ID_WCH 0x1c00
2078#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
72a3c0e4 2079#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1da177e4 2080
b76c5a07
CB		 2081/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2082#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 2083#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 2084
1da177e4
LT		 2085/*
2086 * Master list of serial port init/setup/exit quirks.
2087 * This does not describe the general nature of the port.
2088 * (ie, baud base, number and location of ports, etc)
2089 *
2090 * This list is ordered alphabetically by vendor then device.
2091 * Specific entries must come before more generic entries.
2092 */
7a63ce5a 2093static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 2094 /*
2095 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2096 */
2097 {
086231f7 2098 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 2099 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 2100 .subvendor = PCI_ANY_ID,
2101 .subdevice = PCI_ANY_ID,
2102 .setup = addidata_apci7800_setup,
2103 },
1da177e4 2104 /*
61a116ef 2105 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 2106 * It is not clear whether this applies to all products.
2107 */
2108 {
2109 .vendor = PCI_VENDOR_ID_AFAVLAB,
2110 .device = PCI_ANY_ID,
2111 .subvendor = PCI_ANY_ID,
2112 .subdevice = PCI_ANY_ID,
2113 .setup = afavlab_setup,
2114 },
2115 /*
2116 * HP Diva
2117 */
2118 {
2119 .vendor = PCI_VENDOR_ID_HP,
2120 .device = PCI_DEVICE_ID_HP_DIVA,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .init = pci_hp_diva_init,
2124 .setup = pci_hp_diva_setup,
2125 },
2126 /*
2127 * Intel
2128 */
2129 {
2130 .vendor = PCI_VENDOR_ID_INTEL,
2131 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2132 .subvendor = 0xe4bf,
2133 .subdevice = PCI_ANY_ID,
2134 .init = pci_inteli960ni_init,
2135 .setup = pci_default_setup,
2136 },
b6adea33
MCC		 2137 {
2138 .vendor = PCI_VENDOR_ID_INTEL,
2139 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2140 .subvendor = PCI_ANY_ID,
2141 .subdevice = PCI_ANY_ID,
2142 .setup = skip_tx_en_setup,
2143 },
2144 {
2145 .vendor = PCI_VENDOR_ID_INTEL,
2146 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2147 .subvendor = PCI_ANY_ID,
2148 .subdevice = PCI_ANY_ID,
2149 .setup = skip_tx_en_setup,
2150 },
2151 {
2152 .vendor = PCI_VENDOR_ID_INTEL,
2153 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2154 .subvendor = PCI_ANY_ID,
2155 .subdevice = PCI_ANY_ID,
2156 .setup = skip_tx_en_setup,
2157 },
095e24b0
DB		 2158 {
2159 .vendor = PCI_VENDOR_ID_INTEL,
2160 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2161 .subvendor = PCI_ANY_ID,
2162 .subdevice = PCI_ANY_ID,
2163 .setup = ce4100_serial_setup,
2164 },
bc02d15a
DW		 2165 {
2166 .vendor = PCI_VENDOR_ID_INTEL,
2167 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2168 .subvendor = PCI_ANY_ID,
2169 .subdevice = PCI_ANY_ID,
2170 .setup = kt_serial_setup,
2171 },
b15e5691
HK		 2172 {
2173 .vendor = PCI_VENDOR_ID_INTEL,
2174 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2175 .subvendor = PCI_ANY_ID,
2176 .subdevice = PCI_ANY_ID,
2177 .setup = byt_serial_setup,
2178 },
2179 {
2180 .vendor = PCI_VENDOR_ID_INTEL,
2181 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2182 .subvendor = PCI_ANY_ID,
2183 .subdevice = PCI_ANY_ID,
2184 .setup = byt_serial_setup,
2185 },
f549e94e
AS		 2186 {
2187 .vendor = PCI_VENDOR_ID_INTEL,
2188 .device = PCI_DEVICE_ID_INTEL_PNW_UART1,
2189 .subvendor = PCI_ANY_ID,
2190 .subdevice = PCI_ANY_ID,
2191 .setup = pnw_serial_setup,
2192 },
2193 {
2194 .vendor = PCI_VENDOR_ID_INTEL,
2195 .device = PCI_DEVICE_ID_INTEL_PNW_UART2,
2196 .subvendor = PCI_ANY_ID,
2197 .subdevice = PCI_ANY_ID,
2198 .setup = pnw_serial_setup,
2199 },
2200 {
2201 .vendor = PCI_VENDOR_ID_INTEL,
2202 .device = PCI_DEVICE_ID_INTEL_PNW_UART3,
2203 .subvendor = PCI_ANY_ID,
2204 .subdevice = PCI_ANY_ID,
2205 .setup = pnw_serial_setup,
2206 },
90b9aacf
AS		 2207 {
2208 .vendor = PCI_VENDOR_ID_INTEL,
2209 .device = PCI_DEVICE_ID_INTEL_TNG_UART,
2210 .subvendor = PCI_ANY_ID,
2211 .subdevice = PCI_ANY_ID,
2212 .setup = tng_serial_setup,
2213 },
29897087
AC		 2214 {
2215 .vendor = PCI_VENDOR_ID_INTEL,
2216 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2217 .subvendor = PCI_ANY_ID,
2218 .subdevice = PCI_ANY_ID,
2219 .setup = byt_serial_setup,
2220 },
2221 {
2222 .vendor = PCI_VENDOR_ID_INTEL,
2223 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2224 .subvendor = PCI_ANY_ID,
2225 .subdevice = PCI_ANY_ID,
2226 .setup = byt_serial_setup,
2227 },
84f8c6fc
NV		 2228 /*
2229 * ITE
2230 */
2231 {
2232 .vendor = PCI_VENDOR_ID_ITE,
2233 .device = PCI_DEVICE_ID_ITE_8872,
2234 .subvendor = PCI_ANY_ID,
2235 .subdevice = PCI_ANY_ID,
2236 .init = pci_ite887x_init,
2237 .setup = pci_default_setup,
2d47b716 2238 .exit = pci_ite887x_exit,
84f8c6fc 2239 },
46a0fac9
SB		 2240 /*
2241 * National Instruments
2242 */
04bf7e74
WP		 2243 {
2244 .vendor = PCI_VENDOR_ID_NI,
2245 .device = PCI_DEVICE_ID_NI_PCI23216,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .init = pci_ni8420_init,
2249 .setup = pci_default_setup,
2d47b716 2250 .exit = pci_ni8420_exit,
04bf7e74
WP		 2251 },
2252 {
2253 .vendor = PCI_VENDOR_ID_NI,
2254 .device = PCI_DEVICE_ID_NI_PCI2328,
2255 .subvendor = PCI_ANY_ID,
2256 .subdevice = PCI_ANY_ID,
2257 .init = pci_ni8420_init,
2258 .setup = pci_default_setup,
2d47b716 2259 .exit = pci_ni8420_exit,
04bf7e74
WP		 2260 },
2261 {
2262 .vendor = PCI_VENDOR_ID_NI,
2263 .device = PCI_DEVICE_ID_NI_PCI2324,
2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
2266 .init = pci_ni8420_init,
2267 .setup = pci_default_setup,
2d47b716 2268 .exit = pci_ni8420_exit,
04bf7e74
WP		 2269 },
2270 {
2271 .vendor = PCI_VENDOR_ID_NI,
2272 .device = PCI_DEVICE_ID_NI_PCI2322,
2273 .subvendor = PCI_ANY_ID,
2274 .subdevice = PCI_ANY_ID,
2275 .init = pci_ni8420_init,
2276 .setup = pci_default_setup,
2d47b716 2277 .exit = pci_ni8420_exit,
04bf7e74
WP		 2278 },
2279 {
2280 .vendor = PCI_VENDOR_ID_NI,
2281 .device = PCI_DEVICE_ID_NI_PCI2324I,
2282 .subvendor = PCI_ANY_ID,
2283 .subdevice = PCI_ANY_ID,
2284 .init = pci_ni8420_init,
2285 .setup = pci_default_setup,
2d47b716 2286 .exit = pci_ni8420_exit,
04bf7e74
WP		 2287 },
2288 {
2289 .vendor = PCI_VENDOR_ID_NI,
2290 .device = PCI_DEVICE_ID_NI_PCI2322I,
2291 .subvendor = PCI_ANY_ID,
2292 .subdevice = PCI_ANY_ID,
2293 .init = pci_ni8420_init,
2294 .setup = pci_default_setup,
2d47b716 2295 .exit = pci_ni8420_exit,
04bf7e74
WP		 2296 },
2297 {
2298 .vendor = PCI_VENDOR_ID_NI,
2299 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2300 .subvendor = PCI_ANY_ID,
2301 .subdevice = PCI_ANY_ID,
2302 .init = pci_ni8420_init,
2303 .setup = pci_default_setup,
2d47b716 2304 .exit = pci_ni8420_exit,
04bf7e74
WP		 2305 },
2306 {
2307 .vendor = PCI_VENDOR_ID_NI,
2308 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2309 .subvendor = PCI_ANY_ID,
2310 .subdevice = PCI_ANY_ID,
2311 .init = pci_ni8420_init,
2312 .setup = pci_default_setup,
2d47b716 2313 .exit = pci_ni8420_exit,
04bf7e74
WP		 2314 },
2315 {
2316 .vendor = PCI_VENDOR_ID_NI,
2317 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2318 .subvendor = PCI_ANY_ID,
2319 .subdevice = PCI_ANY_ID,
2320 .init = pci_ni8420_init,
2321 .setup = pci_default_setup,
2d47b716 2322 .exit = pci_ni8420_exit,
04bf7e74
WP		 2323 },
2324 {
2325 .vendor = PCI_VENDOR_ID_NI,
2326 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2327 .subvendor = PCI_ANY_ID,
2328 .subdevice = PCI_ANY_ID,
2329 .init = pci_ni8420_init,
2330 .setup = pci_default_setup,
2d47b716 2331 .exit = pci_ni8420_exit,
04bf7e74
WP		 2332 },
2333 {
2334 .vendor = PCI_VENDOR_ID_NI,
2335 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
2338 .init = pci_ni8420_init,
2339 .setup = pci_default_setup,
2d47b716 2340 .exit = pci_ni8420_exit,
04bf7e74
WP		 2341 },
2342 {
2343 .vendor = PCI_VENDOR_ID_NI,
2344 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2345 .subvendor = PCI_ANY_ID,
2346 .subdevice = PCI_ANY_ID,
2347 .init = pci_ni8420_init,
2348 .setup = pci_default_setup,
2d47b716 2349 .exit = pci_ni8420_exit,
04bf7e74 2350 },
46a0fac9
SB		 2351 {
2352 .vendor = PCI_VENDOR_ID_NI,
2353 .device = PCI_ANY_ID,
2354 .subvendor = PCI_ANY_ID,
2355 .subdevice = PCI_ANY_ID,
2356 .init = pci_ni8430_init,
2357 .setup = pci_ni8430_setup,
2d47b716 2358 .exit = pci_ni8430_exit,
46a0fac9 2359 },
55c7c0fd
AC		 2360 /* Quatech */
2361 {
2362 .vendor = PCI_VENDOR_ID_QUATECH,
2363 .device = PCI_ANY_ID,
2364 .subvendor = PCI_ANY_ID,
2365 .subdevice = PCI_ANY_ID,
2366 .init = pci_quatech_init,
2367 .setup = pci_quatech_setup,
d73dfc6a 2368 .exit = pci_quatech_exit,
55c7c0fd 2369 },
1da177e4
LT		 2370 /*
2371 * Panacom
2372 */
2373 {
2374 .vendor = PCI_VENDOR_ID_PANACOM,
2375 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2376 .subvendor = PCI_ANY_ID,
2377 .subdevice = PCI_ANY_ID,
2378 .init = pci_plx9050_init,
2379 .setup = pci_default_setup,
2d47b716 2380 .exit = pci_plx9050_exit,
5756ee99 2381 },
1da177e4
LT		 2382 {
2383 .vendor = PCI_VENDOR_ID_PANACOM,
2384 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2385 .subvendor = PCI_ANY_ID,
2386 .subdevice = PCI_ANY_ID,
2387 .init = pci_plx9050_init,
2388 .setup = pci_default_setup,
2d47b716 2389 .exit = pci_plx9050_exit,
1da177e4 2390 },
94341475
AB		 2391 /*
2392 * Pericom
2393 */
2394 {
2395 .vendor = 0x12d8,
2396 .device = 0x7952,
2397 .subvendor = PCI_ANY_ID,
2398 .subdevice = PCI_ANY_ID,
2399 .setup = pci_pericom_setup,
2400 },
2401 {
2402 .vendor = 0x12d8,
2403 .device = 0x7954,
2404 .subvendor = PCI_ANY_ID,
2405 .subdevice = PCI_ANY_ID,
2406 .setup = pci_pericom_setup,
2407 },
2408 {
2409 .vendor = 0x12d8,
2410 .device = 0x7958,
2411 .subvendor = PCI_ANY_ID,
2412 .subdevice = PCI_ANY_ID,
2413 .setup = pci_pericom_setup,
2414 },
2415
1da177e4
LT		 2416 /*
2417 * PLX
2418 */
add7b58e
BH		 2419 {
2420 .vendor = PCI_VENDOR_ID_PLX,
2421 .device = PCI_DEVICE_ID_PLX_9050,
2422 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2423 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2424 .init = pci_plx9050_init,
2425 .setup = pci_default_setup,
2d47b716 2426 .exit = pci_plx9050_exit,
add7b58e 2427 },
1da177e4
LT		 2428 {
2429 .vendor = PCI_VENDOR_ID_PLX,
2430 .device = PCI_DEVICE_ID_PLX_9050,
2431 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2432 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2433 .init = pci_plx9050_init,
2434 .setup = pci_default_setup,
2d47b716 2435 .exit = pci_plx9050_exit,
1da177e4
LT		 2436 },
2437 {
2438 .vendor = PCI_VENDOR_ID_PLX,
2439 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2440 .subvendor = PCI_VENDOR_ID_PLX,
2441 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2442 .init = pci_plx9050_init,
2443 .setup = pci_default_setup,
2d47b716 2444 .exit = pci_plx9050_exit,
1da177e4
LT		 2445 },
2446 /*
2447 * SBS Technologies, Inc., PMC-OCTALPRO 232
2448 */
2449 {
2450 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2451 .device = PCI_DEVICE_ID_OCTPRO,
2452 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2453 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2454 .init = sbs_init,
2455 .setup = sbs_setup,
2d47b716 2456 .exit = sbs_exit,
1da177e4
LT		 2457 },
2458 /*
2459 * SBS Technologies, Inc., PMC-OCTALPRO 422
2460 */
2461 {
2462 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2463 .device = PCI_DEVICE_ID_OCTPRO,
2464 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2465 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2466 .init = sbs_init,
2467 .setup = sbs_setup,
2d47b716 2468 .exit = sbs_exit,
1da177e4
LT		 2469 },
2470 /*
2471 * SBS Technologies, Inc., P-Octal 232
2472 */
2473 {
2474 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2475 .device = PCI_DEVICE_ID_OCTPRO,
2476 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2477 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2478 .init = sbs_init,
2479 .setup = sbs_setup,
2d47b716 2480 .exit = sbs_exit,
1da177e4
LT		 2481 },
2482 /*
2483 * SBS Technologies, Inc., P-Octal 422
2484 */
2485 {
2486 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2487 .device = PCI_DEVICE_ID_OCTPRO,
2488 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2489 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2490 .init = sbs_init,
2491 .setup = sbs_setup,
2d47b716 2492 .exit = sbs_exit,
1da177e4 2493 },
1da177e4 2494 /*
61a116ef 2495 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2496 */
2497 {
2498 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2499 .device = PCI_ANY_ID,
1da177e4
LT		 2500 .subvendor = PCI_ANY_ID,
2501 .subdevice = PCI_ANY_ID,
67d74b87 2502 .init = pci_siig_init,
3ec9c594 2503 .setup = pci_siig_setup,
1da177e4
LT		 2504 },
2505 /*
2506 * Titan cards
2507 */
2508 {
2509 .vendor = PCI_VENDOR_ID_TITAN,
2510 .device = PCI_DEVICE_ID_TITAN_400L,
2511 .subvendor = PCI_ANY_ID,
2512 .subdevice = PCI_ANY_ID,
2513 .setup = titan_400l_800l_setup,
2514 },
2515 {
2516 .vendor = PCI_VENDOR_ID_TITAN,
2517 .device = PCI_DEVICE_ID_TITAN_800L,
2518 .subvendor = PCI_ANY_ID,
2519 .subdevice = PCI_ANY_ID,
2520 .setup = titan_400l_800l_setup,
2521 },
2522 /*
2523 * Timedia cards
2524 */
2525 {
2526 .vendor = PCI_VENDOR_ID_TIMEDIA,
2527 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2528 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2529 .subdevice = PCI_ANY_ID,
b9b24558 2530 .probe = pci_timedia_probe,
1da177e4
LT		 2531 .init = pci_timedia_init,
2532 .setup = pci_timedia_setup,
2533 },
2534 {
2535 .vendor = PCI_VENDOR_ID_TIMEDIA,
2536 .device = PCI_ANY_ID,
2537 .subvendor = PCI_ANY_ID,
2538 .subdevice = PCI_ANY_ID,
2539 .setup = pci_timedia_setup,
2540 },
abd7baca
SC		 2541 /*
2542 * SUNIX (Timedia) cards
2543 * Do not "probe" for these cards as there is at least one combination
2544 * card that should be handled by parport_pc that doesn't match the
2545 * rule in pci_timedia_probe.
2546 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2547 * There are some boards with part number SER5037AL that report
2548 * subdevice ID 0x0002.
2549 */
2550 {
2551 .vendor = PCI_VENDOR_ID_SUNIX,
2552 .device = PCI_DEVICE_ID_SUNIX_1999,
2553 .subvendor = PCI_VENDOR_ID_SUNIX,
2554 .subdevice = PCI_ANY_ID,
2555 .init = pci_timedia_init,
2556 .setup = pci_timedia_setup,
2557 },
06315348
SH		 2558 /*
2559 * Exar cards
2560 */
2561 {
2562 .vendor = PCI_VENDOR_ID_EXAR,
2563 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2564 .subvendor = PCI_ANY_ID,
2565 .subdevice = PCI_ANY_ID,
2566 .setup = pci_xr17c154_setup,
2567 },
2568 {
2569 .vendor = PCI_VENDOR_ID_EXAR,
2570 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2571 .subvendor = PCI_ANY_ID,
2572 .subdevice = PCI_ANY_ID,
2573 .setup = pci_xr17c154_setup,
2574 },
2575 {
2576 .vendor = PCI_VENDOR_ID_EXAR,
2577 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2578 .subvendor = PCI_ANY_ID,
2579 .subdevice = PCI_ANY_ID,
2580 .setup = pci_xr17c154_setup,
2581 },
dc96efb7
MS		 2582 {
2583 .vendor = PCI_VENDOR_ID_EXAR,
2584 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2585 .subvendor = PCI_ANY_ID,
2586 .subdevice = PCI_ANY_ID,
2587 .setup = pci_xr17v35x_setup,
2588 },
2589 {
2590 .vendor = PCI_VENDOR_ID_EXAR,
2591 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2592 .subvendor = PCI_ANY_ID,
2593 .subdevice = PCI_ANY_ID,
2594 .setup = pci_xr17v35x_setup,
2595 },
2596 {
2597 .vendor = PCI_VENDOR_ID_EXAR,
2598 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2599 .subvendor = PCI_ANY_ID,
2600 .subdevice = PCI_ANY_ID,
2601 .setup = pci_xr17v35x_setup,
2602 },
be32c0cf
SG		 2603 {
2604 .vendor = PCI_VENDOR_ID_EXAR,
2605 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2606 .subvendor = PCI_ANY_ID,
2607 .subdevice = PCI_ANY_ID,
2608 .setup = pci_xr17v35x_setup,
2609 },
96a5d18b
SG		 2610 {
2611 .vendor = PCI_VENDOR_ID_EXAR,
2612 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2613 .subvendor = PCI_ANY_ID,
2614 .subdevice = PCI_ANY_ID,
2615 .setup = pci_xr17v35x_setup,
2616 },
1da177e4
LT		 2617 /*
2618 * Xircom cards
2619 */
2620 {
2621 .vendor = PCI_VENDOR_ID_XIRCOM,
2622 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2623 .subvendor = PCI_ANY_ID,
2624 .subdevice = PCI_ANY_ID,
2625 .init = pci_xircom_init,
2626 .setup = pci_default_setup,
2627 },
2628 /*
61a116ef 2629 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2630 */
2631 {
2632 .vendor = PCI_VENDOR_ID_NETMOS,
2633 .device = PCI_ANY_ID,
2634 .subvendor = PCI_ANY_ID,
2635 .subdevice = PCI_ANY_ID,
2636 .init = pci_netmos_init,
7808edcd 2637 .setup = pci_netmos_9900_setup,
1da177e4 2638 },
1bc8cde4
MS		 2639 /*
2640 * EndRun Technologies
2641 */
2642 {
2643 .vendor = PCI_VENDOR_ID_ENDRUN,
2644 .device = PCI_ANY_ID,
2645 .subvendor = PCI_ANY_ID,
2646 .subdevice = PCI_ANY_ID,
2647 .init = pci_endrun_init,
2648 .setup = pci_default_setup,
2649 },
9f2a036a 2650 /*
aa273ae5 2651 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2652 */
2653 {
2654 .vendor = PCI_VENDOR_ID_OXSEMI,
2655 .device = PCI_ANY_ID,
2656 .subvendor = PCI_ANY_ID,
2657 .subdevice = PCI_ANY_ID,
2658 .init = pci_oxsemi_tornado_init,
2659 .setup = pci_default_setup,
2660 },
2661 {
2662 .vendor = PCI_VENDOR_ID_MAINPINE,
2663 .device = PCI_ANY_ID,
2664 .subvendor = PCI_ANY_ID,
2665 .subdevice = PCI_ANY_ID,
2666 .init = pci_oxsemi_tornado_init,
2667 .setup = pci_default_setup,
2668 },
aa273ae5
SK		 2669 {
2670 .vendor = PCI_VENDOR_ID_DIGI,
2671 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2672 .subvendor = PCI_SUBVENDOR_ID_IBM,
2673 .subdevice = PCI_ANY_ID,
2674 .init = pci_oxsemi_tornado_init,
2675 .setup = pci_default_setup,
2676 },
eb7073db
TM		 2677 {
2678 .vendor = PCI_VENDOR_ID_INTEL,
2679 .device = 0x8811,
aaa10eb1
AP		 2680 .subvendor = PCI_ANY_ID,
2681 .subdevice = PCI_ANY_ID,
eb7073db 2682 .init = pci_eg20t_init,
64d91cfa 2683 .setup = pci_default_setup,
eb7073db
TM		 2684 },
2685 {
2686 .vendor = PCI_VENDOR_ID_INTEL,
2687 .device = 0x8812,
aaa10eb1
AP		 2688 .subvendor = PCI_ANY_ID,
2689 .subdevice = PCI_ANY_ID,
eb7073db 2690 .init = pci_eg20t_init,
64d91cfa 2691 .setup = pci_default_setup,
eb7073db
TM		 2692 },
2693 {
2694 .vendor = PCI_VENDOR_ID_INTEL,
2695 .device = 0x8813,
aaa10eb1
AP		 2696 .subvendor = PCI_ANY_ID,
2697 .subdevice = PCI_ANY_ID,
eb7073db 2698 .init = pci_eg20t_init,
64d91cfa 2699 .setup = pci_default_setup,
eb7073db
TM		 2700 },
2701 {
2702 .vendor = PCI_VENDOR_ID_INTEL,
2703 .device = 0x8814,
aaa10eb1
AP		 2704 .subvendor = PCI_ANY_ID,
2705 .subdevice = PCI_ANY_ID,
eb7073db 2706 .init = pci_eg20t_init,
64d91cfa 2707 .setup = pci_default_setup,
eb7073db
TM		 2708 },
2709 {
2710 .vendor = 0x10DB,
2711 .device = 0x8027,
aaa10eb1
AP		 2712 .subvendor = PCI_ANY_ID,
2713 .subdevice = PCI_ANY_ID,
eb7073db 2714 .init = pci_eg20t_init,
64d91cfa 2715 .setup = pci_default_setup,
eb7073db
TM		 2716 },
2717 {
2718 .vendor = 0x10DB,
2719 .device = 0x8028,
aaa10eb1
AP		 2720 .subvendor = PCI_ANY_ID,
2721 .subdevice = PCI_ANY_ID,
eb7073db 2722 .init = pci_eg20t_init,
64d91cfa 2723 .setup = pci_default_setup,
eb7073db
TM		 2724 },
2725 {
2726 .vendor = 0x10DB,
2727 .device = 0x8029,
aaa10eb1
AP		 2728 .subvendor = PCI_ANY_ID,
2729 .subdevice = PCI_ANY_ID,
eb7073db 2730 .init = pci_eg20t_init,
64d91cfa 2731 .setup = pci_default_setup,
eb7073db
TM		 2732 },
2733 {
2734 .vendor = 0x10DB,
2735 .device = 0x800C,
aaa10eb1
AP		 2736 .subvendor = PCI_ANY_ID,
2737 .subdevice = PCI_ANY_ID,
eb7073db 2738 .init = pci_eg20t_init,
64d91cfa 2739 .setup = pci_default_setup,
eb7073db
TM		 2740 },
2741 {
2742 .vendor = 0x10DB,
2743 .device = 0x800D,
aaa10eb1
AP		 2744 .subvendor = PCI_ANY_ID,
2745 .subdevice = PCI_ANY_ID,
eb7073db 2746 .init = pci_eg20t_init,
64d91cfa 2747 .setup = pci_default_setup,
eb7073db 2748 },
d9a0fbfd
AP		 2749 /*
2750 * Cronyx Omega PCI (PLX-chip based)
2751 */
2752 {
2753 .vendor = PCI_VENDOR_ID_PLX,
2754 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2755 .subvendor = PCI_ANY_ID,
2756 .subdevice = PCI_ANY_ID,
2757 .setup = pci_omegapci_setup,
eb26dfe8 2758 },
feb58142
EG		 2759 /* WCH CH353 1S1P card (16550 clone) */
2760 {
2761 .vendor = PCI_VENDOR_ID_WCH,
2762 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2763 .subvendor = PCI_ANY_ID,
2764 .subdevice = PCI_ANY_ID,
2765 .setup = pci_wch_ch353_setup,
2766 },
6971c635
GA		 2767 /* WCH CH353 2S1P card (16550 clone) */
2768 {
27788c5f
AC		 2769 .vendor = PCI_VENDOR_ID_WCH,
2770 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2771 .subvendor = PCI_ANY_ID,
2772 .subdevice = PCI_ANY_ID,
2773 .setup = pci_wch_ch353_setup,
2774 },
2775 /* WCH CH353 4S card (16550 clone) */
2776 {
2777 .vendor = PCI_VENDOR_ID_WCH,
2778 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2779 .subvendor = PCI_ANY_ID,
2780 .subdevice = PCI_ANY_ID,
2781 .setup = pci_wch_ch353_setup,
2782 },
2783 /* WCH CH353 2S1PF card (16550 clone) */
2784 {
2785 .vendor = PCI_VENDOR_ID_WCH,
2786 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2787 .subvendor = PCI_ANY_ID,
2788 .subdevice = PCI_ANY_ID,
6971c635
GA		 2789 .setup = pci_wch_ch353_setup,
2790 },
8b5c913f
WY		 2791 /* WCH CH352 2S card (16550 clone) */
2792 {
2793 .vendor = PCI_VENDOR_ID_WCH,
2794 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2795 .subvendor = PCI_ANY_ID,
2796 .subdevice = PCI_ANY_ID,
2797 .setup = pci_wch_ch353_setup,
2798 },
72a3c0e4 2799 /* WCH CH382 2S1P card (16850 clone) */
2fdd8c8c
SP		 2800 {
2801 .vendor = PCIE_VENDOR_ID_WCH,
2802 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2803 .subvendor = PCI_ANY_ID,
2804 .subdevice = PCI_ANY_ID,
72a3c0e4
SP		 2805 .setup = pci_wch_ch38x_setup,
2806 },
2807 /* WCH CH384 4S card (16850 clone) */
2808 {
2809 .vendor = PCIE_VENDOR_ID_WCH,
2810 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2811 .subvendor = PCI_ANY_ID,
2812 .subdevice = PCI_ANY_ID,
2813 .setup = pci_wch_ch38x_setup,
2fdd8c8c 2814 },
eb26dfe8
AC		 2815 /*
2816 * ASIX devices with FIFO bug
2817 */
2818 {
2819 .vendor = PCI_VENDOR_ID_ASIX,
2820 .device = PCI_ANY_ID,
2821 .subvendor = PCI_ANY_ID,
2822 .subdevice = PCI_ANY_ID,
2823 .setup = pci_asix_setup,
2824 },
14faa8cc
MS		 2825 /*
2826 * Commtech, Inc. Fastcom adapters
2827 *
2828 */
2829 {
2830 .vendor = PCI_VENDOR_ID_COMMTECH,
2831 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2832 .subvendor = PCI_ANY_ID,
2833 .subdevice = PCI_ANY_ID,
2834 .setup = pci_fastcom335_setup,
2835 },
2836 {
2837 .vendor = PCI_VENDOR_ID_COMMTECH,
2838 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2839 .subvendor = PCI_ANY_ID,
2840 .subdevice = PCI_ANY_ID,
2841 .setup = pci_fastcom335_setup,
2842 },
2843 {
2844 .vendor = PCI_VENDOR_ID_COMMTECH,
2845 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2846 .subvendor = PCI_ANY_ID,
2847 .subdevice = PCI_ANY_ID,
2848 .setup = pci_fastcom335_setup,
2849 },
2850 {
2851 .vendor = PCI_VENDOR_ID_COMMTECH,
2852 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2853 .subvendor = PCI_ANY_ID,
2854 .subdevice = PCI_ANY_ID,
2855 .setup = pci_fastcom335_setup,
2856 },
2857 {
2858 .vendor = PCI_VENDOR_ID_COMMTECH,
2859 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2860 .subvendor = PCI_ANY_ID,
2861 .subdevice = PCI_ANY_ID,
2862 .setup = pci_xr17v35x_setup,
2863 },
2864 {
2865 .vendor = PCI_VENDOR_ID_COMMTECH,
2866 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2867 .subvendor = PCI_ANY_ID,
2868 .subdevice = PCI_ANY_ID,
2869 .setup = pci_xr17v35x_setup,
2870 },
2871 {
2872 .vendor = PCI_VENDOR_ID_COMMTECH,
2873 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2874 .subvendor = PCI_ANY_ID,
2875 .subdevice = PCI_ANY_ID,
2876 .setup = pci_xr17v35x_setup,
2877 },
ebebd49a
SH		 2878 /*
2879 * Broadcom TruManage (NetXtreme)
2880 */
2881 {
2882 .vendor = PCI_VENDOR_ID_BROADCOM,
2883 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2884 .subvendor = PCI_ANY_ID,
2885 .subdevice = PCI_ANY_ID,
2886 .setup = pci_brcm_trumanage_setup,
2887 },
2c62a3c8
GKH		 2888 {
2889 .vendor = 0x1c29,
2890 .device = 0x1104,
2891 .subvendor = PCI_ANY_ID,
2892 .subdevice = PCI_ANY_ID,
2893 .setup = pci_fintek_setup,
6a8bc239 2894 .init = pci_fintek_init,
2c62a3c8
GKH		 2895 },
2896 {
2897 .vendor = 0x1c29,
2898 .device = 0x1108,
2899 .subvendor = PCI_ANY_ID,
2900 .subdevice = PCI_ANY_ID,
2901 .setup = pci_fintek_setup,
6a8bc239 2902 .init = pci_fintek_init,
2c62a3c8
GKH		 2903 },
2904 {
2905 .vendor = 0x1c29,
2906 .device = 0x1112,
2907 .subvendor = PCI_ANY_ID,
2908 .subdevice = PCI_ANY_ID,
2909 .setup = pci_fintek_setup,
6a8bc239 2910 .init = pci_fintek_init,
2c62a3c8 2911 },
ebebd49a 2912
1da177e4
LT		 2913 /*
2914 * Default "match everything" terminator entry
2915 */
2916 {
2917 .vendor = PCI_ANY_ID,
2918 .device = PCI_ANY_ID,
2919 .subvendor = PCI_ANY_ID,
2920 .subdevice = PCI_ANY_ID,
2921 .setup = pci_default_setup,
2922 }
2923};
2924
2925static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2926{
2927 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2928}
2929
2930static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2931{
2932 struct pci_serial_quirk *quirk;
2933
2934 for (quirk = pci_serial_quirks; ; quirk++)
2935 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2936 quirk_id_matches(quirk->device, dev->device) &&
2937 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2938 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2939 break;
1da177e4
LT		 2940 return quirk;
2941}
2942
dd68e88c 2943static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2944 const struct pciserial_board *board)
1da177e4
LT		 2945{
2946 if (board->flags & FL_NOIRQ)
2947 return 0;
2948 else
2949 return dev->irq;
2950}
2951
2952/*
2953 * This is the configuration table for all of the PCI serial boards
2954 * which we support. It is directly indexed by the pci_board_num_t enum
2955 * value, which is encoded in the pci_device_id PCI probe table's
2956 * driver_data member.
2957 *
2958 * The makeup of these names are:
26e92861 2959 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2960 *
26e92861
GH		 2961 * bn = PCI BAR number
2962 * bt = Index using PCI BARs
2963 * n = number of serial ports
2964 * baud = baud rate
2965 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2966 *
26e92861 2967 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2968 *
1da177e4
LT		 2969 * Please note: in theory if n = 1, _bt infix should make no difference.
2970 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2971 */
2972enum pci_board_num_t {
2973 pbn_default = 0,
2974
2975 pbn_b0_1_115200,
2976 pbn_b0_2_115200,
2977 pbn_b0_4_115200,
2978 pbn_b0_5_115200,
bf0df636 2979 pbn_b0_8_115200,
1da177e4
LT		 2980
2981 pbn_b0_1_921600,
2982 pbn_b0_2_921600,
2983 pbn_b0_4_921600,
2984
db1de159
DR		 2985 pbn_b0_2_1130000,
2986
fbc0dc0d
AP		 2987 pbn_b0_4_1152000,
2988
14faa8cc
MS		 2989 pbn_b0_2_1152000_200,
2990 pbn_b0_4_1152000_200,
2991 pbn_b0_8_1152000_200,
2992
26e92861
GH		 2993 pbn_b0_2_1843200,
2994 pbn_b0_4_1843200,
2995
2996 pbn_b0_2_1843200_200,
2997 pbn_b0_4_1843200_200,
2998 pbn_b0_8_1843200_200,
2999
7106b4e3
LH		 3000 pbn_b0_1_4000000,
3001
1da177e4
LT		 3002 pbn_b0_bt_1_115200,
3003 pbn_b0_bt_2_115200,
ac6ec5b1 3004 pbn_b0_bt_4_115200,
1da177e4
LT		 3005 pbn_b0_bt_8_115200,
3006
3007 pbn_b0_bt_1_460800,
3008 pbn_b0_bt_2_460800,
3009 pbn_b0_bt_4_460800,
3010
3011 pbn_b0_bt_1_921600,
3012 pbn_b0_bt_2_921600,
3013 pbn_b0_bt_4_921600,
3014 pbn_b0_bt_8_921600,
3015
3016 pbn_b1_1_115200,
3017 pbn_b1_2_115200,
3018 pbn_b1_4_115200,
3019 pbn_b1_8_115200,
04bf7e74 3020 pbn_b1_16_115200,
1da177e4
LT		 3021
3022 pbn_b1_1_921600,
3023 pbn_b1_2_921600,
3024 pbn_b1_4_921600,
3025 pbn_b1_8_921600,
3026
26e92861
GH		 3027 pbn_b1_2_1250000,
3028
84f8c6fc 3029 pbn_b1_bt_1_115200,
04bf7e74
WP		 3030 pbn_b1_bt_2_115200,
3031 pbn_b1_bt_4_115200,
3032
1da177e4
LT		 3033 pbn_b1_bt_2_921600,
3034
3035 pbn_b1_1_1382400,
3036 pbn_b1_2_1382400,
3037 pbn_b1_4_1382400,
3038 pbn_b1_8_1382400,
3039
3040 pbn_b2_1_115200,
737c1756 3041 pbn_b2_2_115200,
a9cccd34 3042 pbn_b2_4_115200,
1da177e4
LT		 3043 pbn_b2_8_115200,
3044
3045 pbn_b2_1_460800,
3046 pbn_b2_4_460800,
3047 pbn_b2_8_460800,
3048 pbn_b2_16_460800,
3049
3050 pbn_b2_1_921600,
3051 pbn_b2_4_921600,
3052 pbn_b2_8_921600,
3053
e847003f
LB		 3054 pbn_b2_8_1152000,
3055
1da177e4
LT		 3056 pbn_b2_bt_1_115200,
3057 pbn_b2_bt_2_115200,
3058 pbn_b2_bt_4_115200,
3059
3060 pbn_b2_bt_2_921600,
3061 pbn_b2_bt_4_921600,
3062
d9004eb4 3063 pbn_b3_2_115200,
1da177e4
LT		 3064 pbn_b3_4_115200,
3065 pbn_b3_8_115200,
3066
66169ad1
YY		 3067 pbn_b4_bt_2_921600,
3068 pbn_b4_bt_4_921600,
3069 pbn_b4_bt_8_921600,
3070
1da177e4
LT		 3071 /*
3072 * Board-specific versions.
3073 */
3074 pbn_panacom,
3075 pbn_panacom2,
3076 pbn_panacom4,
3077 pbn_plx_romulus,
1bc8cde4 3078 pbn_endrun_2_4000000,
1da177e4 3079 pbn_oxsemi,
7106b4e3
LH		 3080 pbn_oxsemi_1_4000000,
3081 pbn_oxsemi_2_4000000,
3082 pbn_oxsemi_4_4000000,
3083 pbn_oxsemi_8_4000000,
1da177e4
LT		 3084 pbn_intel_i960,
3085 pbn_sgi_ioc3,
1da177e4
LT		 3086 pbn_computone_4,
3087 pbn_computone_6,
3088 pbn_computone_8,
3089 pbn_sbsxrsio,
3090 pbn_exar_XR17C152,
3091 pbn_exar_XR17C154,
3092 pbn_exar_XR17C158,
dc96efb7
MS		 3093 pbn_exar_XR17V352,
3094 pbn_exar_XR17V354,
3095 pbn_exar_XR17V358,
be32c0cf 3096 pbn_exar_XR17V4358,
96a5d18b 3097 pbn_exar_XR17V8358,
c68d2b15 3098 pbn_exar_ibm_saturn,
aa798505 3099 pbn_pasemi_1682M,
46a0fac9
SB		 3100 pbn_ni8430_2,
3101 pbn_ni8430_4,
3102 pbn_ni8430_8,
3103 pbn_ni8430_16,
1b62cbf2
KJ		 3104 pbn_ADDIDATA_PCIe_1_3906250,
3105 pbn_ADDIDATA_PCIe_2_3906250,
3106 pbn_ADDIDATA_PCIe_4_3906250,
3107 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 3108 pbn_ce4100_1_115200,
b15e5691 3109 pbn_byt,
f549e94e 3110 pbn_pnw,
90b9aacf 3111 pbn_tng,
1ede7dcc 3112 pbn_qrk,
d9a0fbfd 3113 pbn_omegapci,
7808edcd 3114 pbn_NETMOS9900_2s_115200,
ebebd49a 3115 pbn_brcm_trumanage,
2c62a3c8
GKH		 3116 pbn_fintek_4,
3117 pbn_fintek_8,
3118 pbn_fintek_12,
72a3c0e4 3119 pbn_wch384_4,
1da177e4
LT		 3120};
3121
3122/*
3123 * uart_offset - the space between channels
3124 * reg_shift - describes how the UART registers are mapped
3125 * to PCI memory by the card.
3126 * For example IER register on SBS, Inc. PMC-OctPro is located at
3127 * offset 0x10 from the UART base, while UART_IER is defined as 1
3128 * in include/linux/serial_reg.h,
3129 * see first lines of serial_in() and serial_out() in 8250.c
3130*/
3131
de88b340 3132static struct pciserial_board pci_boards[] = {
1da177e4
LT		 3133 [pbn_default] = {
3134 .flags = FL_BASE0,
3135 .num_ports = 1,
3136 .base_baud = 115200,
3137 .uart_offset = 8,
3138 },
3139 [pbn_b0_1_115200] = {
3140 .flags = FL_BASE0,
3141 .num_ports = 1,
3142 .base_baud = 115200,
3143 .uart_offset = 8,
3144 },
3145 [pbn_b0_2_115200] = {
3146 .flags = FL_BASE0,
3147 .num_ports = 2,
3148 .base_baud = 115200,
3149 .uart_offset = 8,
3150 },
3151 [pbn_b0_4_115200] = {
3152 .flags = FL_BASE0,
3153 .num_ports = 4,
3154 .base_baud = 115200,
3155 .uart_offset = 8,
3156 },
3157 [pbn_b0_5_115200] = {
3158 .flags = FL_BASE0,
3159 .num_ports = 5,
3160 .base_baud = 115200,
3161 .uart_offset = 8,
3162 },
bf0df636
AC		 3163 [pbn_b0_8_115200] = {
3164 .flags = FL_BASE0,
3165 .num_ports = 8,
3166 .base_baud = 115200,
3167 .uart_offset = 8,
3168 },
1da177e4
LT		 3169 [pbn_b0_1_921600] = {
3170 .flags = FL_BASE0,
3171 .num_ports = 1,
3172 .base_baud = 921600,
3173 .uart_offset = 8,
3174 },
3175 [pbn_b0_2_921600] = {
3176 .flags = FL_BASE0,
3177 .num_ports = 2,
3178 .base_baud = 921600,
3179 .uart_offset = 8,
3180 },
3181 [pbn_b0_4_921600] = {
3182 .flags = FL_BASE0,
3183 .num_ports = 4,
3184 .base_baud = 921600,
3185 .uart_offset = 8,
3186 },
db1de159
DR		 3187
3188 [pbn_b0_2_1130000] = {
3189 .flags = FL_BASE0,
3190 .num_ports = 2,
3191 .base_baud = 1130000,
3192 .uart_offset = 8,
3193 },
3194
fbc0dc0d
AP		 3195 [pbn_b0_4_1152000] = {
3196 .flags = FL_BASE0,
3197 .num_ports = 4,
3198 .base_baud = 1152000,
3199 .uart_offset = 8,
3200 },
1da177e4 3201
14faa8cc
MS		 3202 [pbn_b0_2_1152000_200] = {
3203 .flags = FL_BASE0,
3204 .num_ports = 2,
3205 .base_baud = 1152000,
3206 .uart_offset = 0x200,
3207 },
3208
3209 [pbn_b0_4_1152000_200] = {
3210 .flags = FL_BASE0,
3211 .num_ports = 4,
3212 .base_baud = 1152000,
3213 .uart_offset = 0x200,
3214 },
3215
3216 [pbn_b0_8_1152000_200] = {
3217 .flags = FL_BASE0,
4f7d67d0 3218 .num_ports = 8,
14faa8cc
MS		 3219 .base_baud = 1152000,
3220 .uart_offset = 0x200,
3221 },
3222
26e92861
GH		 3223 [pbn_b0_2_1843200] = {
3224 .flags = FL_BASE0,
3225 .num_ports = 2,
3226 .base_baud = 1843200,
3227 .uart_offset = 8,
3228 },
3229 [pbn_b0_4_1843200] = {
3230 .flags = FL_BASE0,
3231 .num_ports = 4,
3232 .base_baud = 1843200,
3233 .uart_offset = 8,
3234 },
3235
3236 [pbn_b0_2_1843200_200] = {
3237 .flags = FL_BASE0,
3238 .num_ports = 2,
3239 .base_baud = 1843200,
3240 .uart_offset = 0x200,
3241 },
3242 [pbn_b0_4_1843200_200] = {
3243 .flags = FL_BASE0,
3244 .num_ports = 4,
3245 .base_baud = 1843200,
3246 .uart_offset = 0x200,
3247 },
3248 [pbn_b0_8_1843200_200] = {
3249 .flags = FL_BASE0,
3250 .num_ports = 8,
3251 .base_baud = 1843200,
3252 .uart_offset = 0x200,
3253 },
7106b4e3
LH		 3254 [pbn_b0_1_4000000] = {
3255 .flags = FL_BASE0,
3256 .num_ports = 1,
3257 .base_baud = 4000000,
3258 .uart_offset = 8,
3259 },
26e92861 3260
1da177e4
LT		 3261 [pbn_b0_bt_1_115200] = {
3262 .flags = FL_BASE0|FL_BASE_BARS,
3263 .num_ports = 1,
3264 .base_baud = 115200,
3265 .uart_offset = 8,
3266 },
3267 [pbn_b0_bt_2_115200] = {
3268 .flags = FL_BASE0|FL_BASE_BARS,
3269 .num_ports = 2,
3270 .base_baud = 115200,
3271 .uart_offset = 8,
3272 },
ac6ec5b1
IS		 3273 [pbn_b0_bt_4_115200] = {
3274 .flags = FL_BASE0|FL_BASE_BARS,
3275 .num_ports = 4,
3276 .base_baud = 115200,
3277 .uart_offset = 8,
3278 },
1da177e4
LT		 3279 [pbn_b0_bt_8_115200] = {
3280 .flags = FL_BASE0|FL_BASE_BARS,
3281 .num_ports = 8,
3282 .base_baud = 115200,
3283 .uart_offset = 8,
3284 },
3285
3286 [pbn_b0_bt_1_460800] = {
3287 .flags = FL_BASE0|FL_BASE_BARS,
3288 .num_ports = 1,
3289 .base_baud = 460800,
3290 .uart_offset = 8,
3291 },
3292 [pbn_b0_bt_2_460800] = {
3293 .flags = FL_BASE0|FL_BASE_BARS,
3294 .num_ports = 2,
3295 .base_baud = 460800,
3296 .uart_offset = 8,
3297 },
3298 [pbn_b0_bt_4_460800] = {
3299 .flags = FL_BASE0|FL_BASE_BARS,
3300 .num_ports = 4,
3301 .base_baud = 460800,
3302 .uart_offset = 8,
3303 },
3304
3305 [pbn_b0_bt_1_921600] = {
3306 .flags = FL_BASE0|FL_BASE_BARS,
3307 .num_ports = 1,
3308 .base_baud = 921600,
3309 .uart_offset = 8,
3310 },
3311 [pbn_b0_bt_2_921600] = {
3312 .flags = FL_BASE0|FL_BASE_BARS,
3313 .num_ports = 2,
3314 .base_baud = 921600,
3315 .uart_offset = 8,
3316 },
3317 [pbn_b0_bt_4_921600] = {
3318 .flags = FL_BASE0|FL_BASE_BARS,
3319 .num_ports = 4,
3320 .base_baud = 921600,
3321 .uart_offset = 8,
3322 },
3323 [pbn_b0_bt_8_921600] = {
3324 .flags = FL_BASE0|FL_BASE_BARS,
3325 .num_ports = 8,
3326 .base_baud = 921600,
3327 .uart_offset = 8,
3328 },
3329
3330 [pbn_b1_1_115200] = {
3331 .flags = FL_BASE1,
3332 .num_ports = 1,
3333 .base_baud = 115200,
3334 .uart_offset = 8,
3335 },
3336 [pbn_b1_2_115200] = {
3337 .flags = FL_BASE1,
3338 .num_ports = 2,
3339 .base_baud = 115200,
3340 .uart_offset = 8,
3341 },
3342 [pbn_b1_4_115200] = {
3343 .flags = FL_BASE1,
3344 .num_ports = 4,
3345 .base_baud = 115200,
3346 .uart_offset = 8,
3347 },
3348 [pbn_b1_8_115200] = {
3349 .flags = FL_BASE1,
3350 .num_ports = 8,
3351 .base_baud = 115200,
3352 .uart_offset = 8,
3353 },
04bf7e74
WP		 3354 [pbn_b1_16_115200] = {
3355 .flags = FL_BASE1,
3356 .num_ports = 16,
3357 .base_baud = 115200,
3358 .uart_offset = 8,
3359 },
1da177e4
LT		 3360
3361 [pbn_b1_1_921600] = {
3362 .flags = FL_BASE1,
3363 .num_ports = 1,
3364 .base_baud = 921600,
3365 .uart_offset = 8,
3366 },
3367 [pbn_b1_2_921600] = {
3368 .flags = FL_BASE1,
3369 .num_ports = 2,
3370 .base_baud = 921600,
3371 .uart_offset = 8,
3372 },
3373 [pbn_b1_4_921600] = {
3374 .flags = FL_BASE1,
3375 .num_ports = 4,
3376 .base_baud = 921600,
3377 .uart_offset = 8,
3378 },
3379 [pbn_b1_8_921600] = {
3380 .flags = FL_BASE1,
3381 .num_ports = 8,
3382 .base_baud = 921600,
3383 .uart_offset = 8,
3384 },
26e92861
GH		 3385 [pbn_b1_2_1250000] = {
3386 .flags = FL_BASE1,
3387 .num_ports = 2,
3388 .base_baud = 1250000,
3389 .uart_offset = 8,
3390 },
1da177e4 3391
84f8c6fc
NV		 3392 [pbn_b1_bt_1_115200] = {
3393 .flags = FL_BASE1|FL_BASE_BARS,
3394 .num_ports = 1,
3395 .base_baud = 115200,
3396 .uart_offset = 8,
3397 },
04bf7e74
WP		 3398 [pbn_b1_bt_2_115200] = {
3399 .flags = FL_BASE1|FL_BASE_BARS,
3400 .num_ports = 2,
3401 .base_baud = 115200,
3402 .uart_offset = 8,
3403 },
3404 [pbn_b1_bt_4_115200] = {
3405 .flags = FL_BASE1|FL_BASE_BARS,
3406 .num_ports = 4,
3407 .base_baud = 115200,
3408 .uart_offset = 8,
3409 },
84f8c6fc 3410
1da177e4
LT		 3411 [pbn_b1_bt_2_921600] = {
3412 .flags = FL_BASE1|FL_BASE_BARS,
3413 .num_ports = 2,
3414 .base_baud = 921600,
3415 .uart_offset = 8,
3416 },
3417
3418 [pbn_b1_1_1382400] = {
3419 .flags = FL_BASE1,
3420 .num_ports = 1,
3421 .base_baud = 1382400,
3422 .uart_offset = 8,
3423 },
3424 [pbn_b1_2_1382400] = {
3425 .flags = FL_BASE1,
3426 .num_ports = 2,
3427 .base_baud = 1382400,
3428 .uart_offset = 8,
3429 },
3430 [pbn_b1_4_1382400] = {
3431 .flags = FL_BASE1,
3432 .num_ports = 4,
3433 .base_baud = 1382400,
3434 .uart_offset = 8,
3435 },
3436 [pbn_b1_8_1382400] = {
3437 .flags = FL_BASE1,
3438 .num_ports = 8,
3439 .base_baud = 1382400,
3440 .uart_offset = 8,
3441 },
3442
3443 [pbn_b2_1_115200] = {
3444 .flags = FL_BASE2,
3445 .num_ports = 1,
3446 .base_baud = 115200,
3447 .uart_offset = 8,
3448 },
737c1756
PH		 3449 [pbn_b2_2_115200] = {
3450 .flags = FL_BASE2,
3451 .num_ports = 2,
3452 .base_baud = 115200,
3453 .uart_offset = 8,
3454 },
a9cccd34
MF		 3455 [pbn_b2_4_115200] = {
3456 .flags = FL_BASE2,
3457 .num_ports = 4,
3458 .base_baud = 115200,
3459 .uart_offset = 8,
3460 },
1da177e4
LT		 3461 [pbn_b2_8_115200] = {
3462 .flags = FL_BASE2,
3463 .num_ports = 8,
3464 .base_baud = 115200,
3465 .uart_offset = 8,
3466 },
3467
3468 [pbn_b2_1_460800] = {
3469 .flags = FL_BASE2,
3470 .num_ports = 1,
3471 .base_baud = 460800,
3472 .uart_offset = 8,
3473 },
3474 [pbn_b2_4_460800] = {
3475 .flags = FL_BASE2,
3476 .num_ports = 4,
3477 .base_baud = 460800,
3478 .uart_offset = 8,
3479 },
3480 [pbn_b2_8_460800] = {
3481 .flags = FL_BASE2,
3482 .num_ports = 8,
3483 .base_baud = 460800,
3484 .uart_offset = 8,
3485 },
3486 [pbn_b2_16_460800] = {
3487 .flags = FL_BASE2,
3488 .num_ports = 16,
3489 .base_baud = 460800,
3490 .uart_offset = 8,
3491 },
3492
3493 [pbn_b2_1_921600] = {
3494 .flags = FL_BASE2,
3495 .num_ports = 1,
3496 .base_baud = 921600,
3497 .uart_offset = 8,
3498 },
3499 [pbn_b2_4_921600] = {
3500 .flags = FL_BASE2,
3501 .num_ports = 4,
3502 .base_baud = 921600,
3503 .uart_offset = 8,
3504 },
3505 [pbn_b2_8_921600] = {
3506 .flags = FL_BASE2,
3507 .num_ports = 8,
3508 .base_baud = 921600,
3509 .uart_offset = 8,
3510 },
3511
e847003f
LB		 3512 [pbn_b2_8_1152000] = {
3513 .flags = FL_BASE2,
3514 .num_ports = 8,
3515 .base_baud = 1152000,
3516 .uart_offset = 8,
3517 },
3518
1da177e4
LT		 3519 [pbn_b2_bt_1_115200] = {
3520 .flags = FL_BASE2|FL_BASE_BARS,
3521 .num_ports = 1,
3522 .base_baud = 115200,
3523 .uart_offset = 8,
3524 },
3525 [pbn_b2_bt_2_115200] = {
3526 .flags = FL_BASE2|FL_BASE_BARS,
3527 .num_ports = 2,
3528 .base_baud = 115200,
3529 .uart_offset = 8,
3530 },
3531 [pbn_b2_bt_4_115200] = {
3532 .flags = FL_BASE2|FL_BASE_BARS,
3533 .num_ports = 4,
3534 .base_baud = 115200,
3535 .uart_offset = 8,
3536 },
3537
3538 [pbn_b2_bt_2_921600] = {
3539 .flags = FL_BASE2|FL_BASE_BARS,
3540 .num_ports = 2,
3541 .base_baud = 921600,
3542 .uart_offset = 8,
3543 },
3544 [pbn_b2_bt_4_921600] = {
3545 .flags = FL_BASE2|FL_BASE_BARS,
3546 .num_ports = 4,
3547 .base_baud = 921600,
3548 .uart_offset = 8,
3549 },
3550
d9004eb4
ABL		 3551 [pbn_b3_2_115200] = {
3552 .flags = FL_BASE3,
3553 .num_ports = 2,
3554 .base_baud = 115200,
3555 .uart_offset = 8,
3556 },
1da177e4
LT		 3557 [pbn_b3_4_115200] = {
3558 .flags = FL_BASE3,
3559 .num_ports = 4,
3560 .base_baud = 115200,
3561 .uart_offset = 8,
3562 },
3563 [pbn_b3_8_115200] = {
3564 .flags = FL_BASE3,
3565 .num_ports = 8,
3566 .base_baud = 115200,
3567 .uart_offset = 8,
3568 },
3569
66169ad1
YY		 3570 [pbn_b4_bt_2_921600] = {
3571 .flags = FL_BASE4,
3572 .num_ports = 2,
3573 .base_baud = 921600,
3574 .uart_offset = 8,
3575 },
3576 [pbn_b4_bt_4_921600] = {
3577 .flags = FL_BASE4,
3578 .num_ports = 4,
3579 .base_baud = 921600,
3580 .uart_offset = 8,
3581 },
3582 [pbn_b4_bt_8_921600] = {
3583 .flags = FL_BASE4,
3584 .num_ports = 8,
3585 .base_baud = 921600,
3586 .uart_offset = 8,
3587 },
3588
1da177e4
LT		 3589 /*
3590 * Entries following this are board-specific.
3591 */
3592
3593 /*
3594 * Panacom - IOMEM
3595 */
3596 [pbn_panacom] = {
3597 .flags = FL_BASE2,
3598 .num_ports = 2,
3599 .base_baud = 921600,
3600 .uart_offset = 0x400,
3601 .reg_shift = 7,
3602 },
3603 [pbn_panacom2] = {
3604 .flags = FL_BASE2|FL_BASE_BARS,
3605 .num_ports = 2,
3606 .base_baud = 921600,
3607 .uart_offset = 0x400,
3608 .reg_shift = 7,
3609 },
3610 [pbn_panacom4] = {
3611 .flags = FL_BASE2|FL_BASE_BARS,
3612 .num_ports = 4,
3613 .base_baud = 921600,
3614 .uart_offset = 0x400,
3615 .reg_shift = 7,
3616 },
3617
3618 /* I think this entry is broken - the first_offset looks wrong --rmk */
3619 [pbn_plx_romulus] = {
3620 .flags = FL_BASE2,
3621 .num_ports = 4,
3622 .base_baud = 921600,
3623 .uart_offset = 8 << 2,
3624 .reg_shift = 2,
3625 .first_offset = 0x03,
3626 },
3627
1bc8cde4
MS		 3628 /*
3629 * EndRun Technologies
3630 * Uses the size of PCI Base region 0 to
3631 * signal now many ports are available
3632 * 2 port 952 Uart support
3633 */
3634 [pbn_endrun_2_4000000] = {
3635 .flags = FL_BASE0,
3636 .num_ports = 2,
3637 .base_baud = 4000000,
3638 .uart_offset = 0x200,
3639 .first_offset = 0x1000,
3640 },
3641
1da177e4
LT		 3642 /*
3643 * This board uses the size of PCI Base region 0 to
3644 * signal now many ports are available
3645 */
3646 [pbn_oxsemi] = {
3647 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3648 .num_ports = 32,
3649 .base_baud = 115200,
3650 .uart_offset = 8,
3651 },
7106b4e3
LH		 3652 [pbn_oxsemi_1_4000000] = {
3653 .flags = FL_BASE0,
3654 .num_ports = 1,
3655 .base_baud = 4000000,
3656 .uart_offset = 0x200,
3657 .first_offset = 0x1000,
3658 },
3659 [pbn_oxsemi_2_4000000] = {
3660 .flags = FL_BASE0,
3661 .num_ports = 2,
3662 .base_baud = 4000000,
3663 .uart_offset = 0x200,
3664 .first_offset = 0x1000,
3665 },
3666 [pbn_oxsemi_4_4000000] = {
3667 .flags = FL_BASE0,
3668 .num_ports = 4,
3669 .base_baud = 4000000,
3670 .uart_offset = 0x200,
3671 .first_offset = 0x1000,
3672 },
3673 [pbn_oxsemi_8_4000000] = {
3674 .flags = FL_BASE0,
3675 .num_ports = 8,
3676 .base_baud = 4000000,
3677 .uart_offset = 0x200,
3678 .first_offset = 0x1000,
3679 },
3680
1da177e4
LT		 3681
3682 /*
3683 * EKF addition for i960 Boards form EKF with serial port.
3684 * Max 256 ports.
3685 */
3686 [pbn_intel_i960] = {
3687 .flags = FL_BASE0,
3688 .num_ports = 32,
3689 .base_baud = 921600,
3690 .uart_offset = 8 << 2,
3691 .reg_shift = 2,
3692 .first_offset = 0x10000,
3693 },
3694 [pbn_sgi_ioc3] = {
3695 .flags = FL_BASE0|FL_NOIRQ,
3696 .num_ports = 1,
3697 .base_baud = 458333,
3698 .uart_offset = 8,
3699 .reg_shift = 0,
3700 .first_offset = 0x20178,
3701 },
3702
1da177e4
LT		 3703 /*
3704 * Computone - uses IOMEM.
3705 */
3706 [pbn_computone_4] = {
3707 .flags = FL_BASE0,
3708 .num_ports = 4,
3709 .base_baud = 921600,
3710 .uart_offset = 0x40,
3711 .reg_shift = 2,
3712 .first_offset = 0x200,
3713 },
3714 [pbn_computone_6] = {
3715 .flags = FL_BASE0,
3716 .num_ports = 6,
3717 .base_baud = 921600,
3718 .uart_offset = 0x40,
3719 .reg_shift = 2,
3720 .first_offset = 0x200,
3721 },
3722 [pbn_computone_8] = {
3723 .flags = FL_BASE0,
3724 .num_ports = 8,
3725 .base_baud = 921600,
3726 .uart_offset = 0x40,
3727 .reg_shift = 2,
3728 .first_offset = 0x200,
3729 },
3730 [pbn_sbsxrsio] = {
3731 .flags = FL_BASE0,
3732 .num_ports = 8,
3733 .base_baud = 460800,
3734 .uart_offset = 256,
3735 .reg_shift = 4,
3736 },
3737 /*
3738 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3739 * Only basic 16550A support.
3740 * XR17C15[24] are not tested, but they should work.
3741 */
3742 [pbn_exar_XR17C152] = {
3743 .flags = FL_BASE0,
3744 .num_ports = 2,
3745 .base_baud = 921600,
3746 .uart_offset = 0x200,
3747 },
3748 [pbn_exar_XR17C154] = {
3749 .flags = FL_BASE0,
3750 .num_ports = 4,
3751 .base_baud = 921600,
3752 .uart_offset = 0x200,
3753 },
3754 [pbn_exar_XR17C158] = {
3755 .flags = FL_BASE0,
3756 .num_ports = 8,
3757 .base_baud = 921600,
3758 .uart_offset = 0x200,
3759 },
dc96efb7
MS		 3760 [pbn_exar_XR17V352] = {
3761 .flags = FL_BASE0,
3762 .num_ports = 2,
3763 .base_baud = 7812500,
3764 .uart_offset = 0x400,
3765 .reg_shift = 0,
3766 .first_offset = 0,
3767 },
3768 [pbn_exar_XR17V354] = {
3769 .flags = FL_BASE0,
3770 .num_ports = 4,
3771 .base_baud = 7812500,
3772 .uart_offset = 0x400,
3773 .reg_shift = 0,
3774 .first_offset = 0,
3775 },
3776 [pbn_exar_XR17V358] = {
3777 .flags = FL_BASE0,
3778 .num_ports = 8,
3779 .base_baud = 7812500,
3780 .uart_offset = 0x400,
3781 .reg_shift = 0,
3782 .first_offset = 0,
3783 },
be32c0cf
SG		 3784 [pbn_exar_XR17V4358] = {
3785 .flags = FL_BASE0,
3786 .num_ports = 12,
3787 .base_baud = 7812500,
3788 .uart_offset = 0x400,
3789 .reg_shift = 0,
3790 .first_offset = 0,
3791 },
96a5d18b
SG		 3792 [pbn_exar_XR17V8358] = {
3793 .flags = FL_BASE0,
3794 .num_ports = 16,
3795 .base_baud = 7812500,
3796 .uart_offset = 0x400,
3797 .reg_shift = 0,
3798 .first_offset = 0,
3799 },
c68d2b15
BH		 3800 [pbn_exar_ibm_saturn] = {
3801 .flags = FL_BASE0,
3802 .num_ports = 1,
3803 .base_baud = 921600,
3804 .uart_offset = 0x200,
3805 },
3806
aa798505
OJ		 3807 /*
3808 * PA Semi PWRficient PA6T-1682M on-chip UART
3809 */
3810 [pbn_pasemi_1682M] = {
3811 .flags = FL_BASE0,
3812 .num_ports = 1,
3813 .base_baud = 8333333,
3814 },
46a0fac9
SB		 3815 /*
3816 * National Instruments 843x
3817 */
3818 [pbn_ni8430_16] = {
3819 .flags = FL_BASE0,
3820 .num_ports = 16,
3821 .base_baud = 3686400,
3822 .uart_offset = 0x10,
3823 .first_offset = 0x800,
3824 },
3825 [pbn_ni8430_8] = {
3826 .flags = FL_BASE0,
3827 .num_ports = 8,
3828 .base_baud = 3686400,
3829 .uart_offset = 0x10,
3830 .first_offset = 0x800,
3831 },
3832 [pbn_ni8430_4] = {
3833 .flags = FL_BASE0,
3834 .num_ports = 4,
3835 .base_baud = 3686400,
3836 .uart_offset = 0x10,
3837 .first_offset = 0x800,
3838 },
3839 [pbn_ni8430_2] = {
3840 .flags = FL_BASE0,
3841 .num_ports = 2,
3842 .base_baud = 3686400,
3843 .uart_offset = 0x10,
3844 .first_offset = 0x800,
3845 },
1b62cbf2
KJ		 3846 /*
3847 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3848 */
3849 [pbn_ADDIDATA_PCIe_1_3906250] = {
3850 .flags = FL_BASE0,
3851 .num_ports = 1,
3852 .base_baud = 3906250,
3853 .uart_offset = 0x200,
3854 .first_offset = 0x1000,
3855 },
3856 [pbn_ADDIDATA_PCIe_2_3906250] = {
3857 .flags = FL_BASE0,
3858 .num_ports = 2,
3859 .base_baud = 3906250,
3860 .uart_offset = 0x200,
3861 .first_offset = 0x1000,
3862 },
3863 [pbn_ADDIDATA_PCIe_4_3906250] = {
3864 .flags = FL_BASE0,
3865 .num_ports = 4,
3866 .base_baud = 3906250,
3867 .uart_offset = 0x200,
3868 .first_offset = 0x1000,
3869 },
3870 [pbn_ADDIDATA_PCIe_8_3906250] = {
3871 .flags = FL_BASE0,
3872 .num_ports = 8,
3873 .base_baud = 3906250,
3874 .uart_offset = 0x200,
3875 .first_offset = 0x1000,
3876 },
095e24b0 3877 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3878 .flags = FL_BASE_BARS,
3879 .num_ports = 2,
095e24b0
DB		 3880 .base_baud = 921600,
3881 .reg_shift = 2,
3882 },
41d3f099
AS		 3883 /*
3884 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3885 * but is overridden by byt_set_termios.
3886 */
b15e5691
HK		 3887 [pbn_byt] = {
3888 .flags = FL_BASE0,
3889 .num_ports = 1,
3890 .base_baud = 2764800,
3891 .uart_offset = 0x80,
3892 .reg_shift = 2,
3893 },
f549e94e
AS		 3894 [pbn_pnw] = {
3895 .flags = FL_BASE0,
3896 .num_ports = 1,
3897 .base_baud = 115200,
3898 },
90b9aacf
AS		 3899 [pbn_tng] = {
3900 .flags = FL_BASE0,
3901 .num_ports = 1,
3902 .base_baud = 1843200,
3903 },
1ede7dcc
BD		 3904 [pbn_qrk] = {
3905 .flags = FL_BASE0,
3906 .num_ports = 1,
3907 .base_baud = 2764800,
3908 .reg_shift = 2,
3909 },
d9a0fbfd
AP		 3910 [pbn_omegapci] = {
3911 .flags = FL_BASE0,
3912 .num_ports = 8,
3913 .base_baud = 115200,
3914 .uart_offset = 0x200,
3915 },
7808edcd
NG		 3916 [pbn_NETMOS9900_2s_115200] = {
3917 .flags = FL_BASE0,
3918 .num_ports = 2,
3919 .base_baud = 115200,
3920 },
ebebd49a
SH		 3921 [pbn_brcm_trumanage] = {
3922 .flags = FL_BASE0,
3923 .num_ports = 1,
3924 .reg_shift = 2,
3925 .base_baud = 115200,
3926 },
2c62a3c8
GKH		 3927 [pbn_fintek_4] = {
3928 .num_ports = 4,
3929 .uart_offset = 8,
3930 .base_baud = 115200,
3931 .first_offset = 0x40,
3932 },
3933 [pbn_fintek_8] = {
3934 .num_ports = 8,
3935 .uart_offset = 8,
3936 .base_baud = 115200,
3937 .first_offset = 0x40,
3938 },
3939 [pbn_fintek_12] = {
3940 .num_ports = 12,
3941 .uart_offset = 8,
3942 .base_baud = 115200,
3943 .first_offset = 0x40,
3944 },
72a3c0e4
SP		 3945
3946 [pbn_wch384_4] = {
3947 .flags = FL_BASE0,
3948 .num_ports = 4,
3949 .base_baud = 115200,
3950 .uart_offset = 8,
3951 .first_offset = 0xC0,
3952 },
1da177e4
LT		 3953};
3954
6971c635
GA		 3955static const struct pci_device_id blacklist[] = {
3956 /* softmodems */
5756ee99 3957 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3958 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3959 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3960
3961 /* multi-io cards handled by parport_serial */
3962 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
feb58142 3963 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
2fdd8c8c 3964 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
72a3c0e4 3965 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
436bbd43
CS		 3966};
3967
1da177e4
LT		 3968/*
3969 * Given a complete unknown PCI device, try to use some heuristics to
3970 * guess what the configuration might be, based on the pitiful PCI
3971 * serial specs. Returns 0 on success, 1 on failure.
3972 */
9671f099 3973static int
1c7c1fe5 3974serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3975{
6971c635 3976 const struct pci_device_id *bldev;
1da177e4 3977 int num_iomem, num_port, first_port = -1, i;
5756ee99 3978
1da177e4
LT		 3979 /*
3980 * If it is not a communications device or the programming
3981 * interface is greater than 6, give up.
3982 *
3983 * (Should we try to make guesses for multiport serial devices
5756ee99 3984 * later?)
1da177e4
LT		 3985 */
3986 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3987 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3988 (dev->class & 0xff) > 6)
3989 return -ENODEV;
3990
436bbd43
CS		 3991 /*
3992 * Do not access blacklisted devices that are known not to
6971c635 3993 * feature serial ports or are handled by other modules.
436bbd43 3994 */
6971c635
GA		 3995 for (bldev = blacklist;
3996 bldev < blacklist + ARRAY_SIZE(blacklist);
3997 bldev++) {
3998 if (dev->vendor == bldev->vendor &&
3999 dev->device == bldev->device)
436bbd43
CS		 4000 return -ENODEV;
4001 }
4002
1da177e4
LT		 4003 num_iomem = num_port = 0;
4004 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4005 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4006 num_port++;
4007 if (first_port == -1)
4008 first_port = i;
4009 }
4010 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4011 num_iomem++;
4012 }
4013
4014 /*
4015 * If there is 1 or 0 iomem regions, and exactly one port,
4016 * use it. We guess the number of ports based on the IO
4017 * region size.
4018 */
4019 if (num_iomem <= 1 && num_port == 1) {
4020 board->flags = first_port;
4021 board->num_ports = pci_resource_len(dev, first_port) / 8;
4022 return 0;
4023 }
4024
4025 /*
4026 * Now guess if we've got a board which indexes by BARs.
4027 * Each IO BAR should be 8 bytes, and they should follow
4028 * consecutively.
4029 */
4030 first_port = -1;
4031 num_port = 0;
4032 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4033 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4034 pci_resource_len(dev, i) == 8 &&
4035 (first_port == -1 || (first_port + num_port) == i)) {
4036 num_port++;
4037 if (first_port == -1)
4038 first_port = i;
4039 }
4040 }
4041
4042 if (num_port > 1) {
4043 board->flags = first_port | FL_BASE_BARS;
4044 board->num_ports = num_port;
4045 return 0;
4046 }
4047
4048 return -ENODEV;
4049}
4050
4051static inline int
975a1a7d
RK		 4052serial_pci_matches(const struct pciserial_board *board,
4053 const struct pciserial_board *guessed)
1da177e4
LT		 4054{
4055 return
4056 board->num_ports == guessed->num_ports &&
4057 board->base_baud == guessed->base_baud &&
4058 board->uart_offset == guessed->uart_offset &&
4059 board->reg_shift == guessed->reg_shift &&
4060 board->first_offset == guessed->first_offset;
4061}
4062
241fc436 4063struct serial_private *
975a1a7d 4064pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 4065{
2655a2c7 4066 struct uart_8250_port uart;
1da177e4 4067 struct serial_private *priv;
1da177e4
LT		 4068 struct pci_serial_quirk *quirk;
4069 int rc, nr_ports, i;
4070
1da177e4
LT		 4071 nr_ports = board->num_ports;
4072
4073 /*
4074 * Find an init and setup quirks.
4075 */
4076 quirk = find_quirk(dev);
4077
4078 /*
4079 * Run the new-style initialization function.
4080 * The initialization function returns:
4081 * <0 - error
4082 * 0 - use board->num_ports
4083 * >0 - number of ports
4084 */
4085 if (quirk->init) {
4086 rc = quirk->init(dev);
241fc436
RK		 4087 if (rc < 0) {
4088 priv = ERR_PTR(rc);
4089 goto err_out;
4090 }
1da177e4
LT		 4091 if (rc)
4092 nr_ports = rc;
4093 }
4094
8f31bb39 4095 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 4096 sizeof(unsigned int) * nr_ports,
4097 GFP_KERNEL);
4098 if (!priv) {
241fc436
RK		 4099 priv = ERR_PTR(-ENOMEM);
4100 goto err_deinit;
1da177e4
LT		 4101 }
4102
70db3d91 4103 priv->dev = dev;
1da177e4 4104 priv->quirk = quirk;
1da177e4 4105
2655a2c7
AC		 4106 memset(&uart, 0, sizeof(uart));
4107 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4108 uart.port.uartclk = board->base_baud * 16;
4109 uart.port.irq = get_pci_irq(dev, board);
4110 uart.port.dev = &dev->dev;
72ce9a83 4111
1da177e4 4112 for (i = 0; i < nr_ports; i++) {
2655a2c7 4113 if (quirk->setup(priv, board, &uart, i))
1da177e4 4114 break;
72ce9a83 4115
af8c5b8d
GKH		 4116 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4117 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 4118
2655a2c7 4119 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 4120 if (priv->line[i] < 0) {
af8c5b8d
GKH		 4121 dev_err(&dev->dev,
4122 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4123 uart.port.iobase, uart.port.irq,
4124 uart.port.iotype, priv->line[i]);
1da177e4
LT		 4125 break;
4126 }
4127 }
1da177e4 4128 priv->nr = i;
241fc436 4129 return priv;
1da177e4 4130
5756ee99 4131err_deinit:
1da177e4
LT		 4132 if (quirk->exit)
4133 quirk->exit(dev);
5756ee99 4134err_out:
241fc436 4135 return priv;
1da177e4 4136}
241fc436 4137EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 4138
241fc436 4139void pciserial_remove_ports(struct serial_private *priv)
1da177e4 4140{
056a8763
RK		 4141 struct pci_serial_quirk *quirk;
4142 int i;
1da177e4 4143
056a8763
RK		 4144 for (i = 0; i < priv->nr; i++)
4145 serial8250_unregister_port(priv->line[i]);
1da177e4 4146
056a8763
RK		 4147 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4148 if (priv->remapped_bar[i])
4149 iounmap(priv->remapped_bar[i]);
4150 priv->remapped_bar[i] = NULL;
4151 }
1da177e4 4152
056a8763
RK		 4153 /*
4154 * Find the exit quirks.
4155 */
241fc436 4156 quirk = find_quirk(priv->dev);
056a8763 4157 if (quirk->exit)
241fc436
RK		 4158 quirk->exit(priv->dev);
4159
4160 kfree(priv);
4161}
4162EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4163
4164void pciserial_suspend_ports(struct serial_private *priv)
4165{
4166 int i;
4167
4168 for (i = 0; i < priv->nr; i++)
4169 if (priv->line[i] >= 0)
4170 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 4171
4172 /*
4173 * Ensure that every init quirk is properly torn down
4174 */
4175 if (priv->quirk->exit)
4176 priv->quirk->exit(priv->dev);
241fc436
RK		 4177}
4178EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4179
4180void pciserial_resume_ports(struct serial_private *priv)
4181{
4182 int i;
4183
4184 /*
4185 * Ensure that the board is correctly configured.
4186 */
4187 if (priv->quirk->init)
4188 priv->quirk->init(priv->dev);
4189
4190 for (i = 0; i < priv->nr; i++)
4191 if (priv->line[i] >= 0)
4192 serial8250_resume_port(priv->line[i]);
4193}
4194EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4195
4196/*
4197 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4198 * to the arrangement of serial ports on a PCI card.
4199 */
9671f099 4200static int
241fc436
RK		 4201pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4202{
5bf8f501 4203 struct pci_serial_quirk *quirk;
241fc436 4204 struct serial_private *priv;
975a1a7d
RK		 4205 const struct pciserial_board *board;
4206 struct pciserial_board tmp;
241fc436
RK		 4207 int rc;
4208
5bf8f501
FB		 4209 quirk = find_quirk(dev);
4210 if (quirk->probe) {
4211 rc = quirk->probe(dev);
4212 if (rc)
4213 return rc;
4214 }
4215
241fc436 4216 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 4217 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 4218 ent->driver_data);
4219 return -EINVAL;
4220 }
4221
4222 board = &pci_boards[ent->driver_data];
4223
4224 rc = pci_enable_device(dev);
2807190b 4225 pci_save_state(dev);
241fc436
RK		 4226 if (rc)
4227 return rc;
4228
4229 if (ent->driver_data == pbn_default) {
4230 /*
4231 * Use a copy of the pci_board entry for this;
4232 * avoid changing entries in the table.
4233 */
4234 memcpy(&tmp, board, sizeof(struct pciserial_board));
4235 board = &tmp;
4236
4237 /*
4238 * We matched one of our class entries. Try to
4239 * determine the parameters of this board.
4240 */
975a1a7d 4241 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 4242 if (rc)
4243 goto disable;
4244 } else {
4245 /*
4246 * We matched an explicit entry. If we are able to
4247 * detect this boards settings with our heuristic,
4248 * then we no longer need this entry.
4249 */
4250 memcpy(&tmp, &pci_boards[pbn_default],
4251 sizeof(struct pciserial_board));
4252 rc = serial_pci_guess_board(dev, &tmp);
4253 if (rc == 0 && serial_pci_matches(board, &tmp))
4254 moan_device("Redundant entry in serial pci_table.",
4255 dev);
4256 }
4257
4258 priv = pciserial_init_ports(dev, board);
4259 if (!IS_ERR(priv)) {
4260 pci_set_drvdata(dev, priv);
4261 return 0;
4262 }
4263
4264 rc = PTR_ERR(priv);
1da177e4 4265
241fc436 4266 disable:
056a8763 4267 pci_disable_device(dev);
241fc436
RK		 4268 return rc;
4269}
1da177e4 4270
ae8d8a14 4271static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 4272{
4273 struct serial_private *priv = pci_get_drvdata(dev);
4274
241fc436
RK		 4275 pciserial_remove_ports(priv);
4276
4277 pci_disable_device(dev);
1da177e4
LT		 4278}
4279
61702c3e
AS		 4280#ifdef CONFIG_PM_SLEEP
4281static int pciserial_suspend_one(struct device *dev)
1da177e4 4282{
61702c3e
AS		 4283 struct pci_dev *pdev = to_pci_dev(dev);
4284 struct serial_private *priv = pci_get_drvdata(pdev);
1da177e4 4285
241fc436
RK		 4286 if (priv)
4287 pciserial_suspend_ports(priv);
1da177e4 4288
1da177e4
LT		 4289 return 0;
4290}
4291
61702c3e 4292static int pciserial_resume_one(struct device *dev)
1da177e4 4293{
61702c3e
AS		 4294 struct pci_dev *pdev = to_pci_dev(dev);
4295 struct serial_private *priv = pci_get_drvdata(pdev);
ccb9d59e 4296 int err;
1da177e4
LT		 4297
4298 if (priv) {
1da177e4
LT		 4299 /*
4300 * The device may have been disabled. Re-enable it.
4301 */
61702c3e 4302 err = pci_enable_device(pdev);
40836c48 4303 /* FIXME: We cannot simply error out here */
ccb9d59e 4304 if (err)
61702c3e 4305 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 4306 pciserial_resume_ports(priv);
1da177e4
LT		 4307 }
4308 return 0;
4309}
1d5e7996 4310#endif
1da177e4 4311
61702c3e
AS		 4312static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4313 pciserial_resume_one);
4314
1da177e4 4315static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 4316 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4317 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4318 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4319 pbn_b2_8_921600 },
0c6d774c
TW		 4320 /* Advantech also use 0x3618 and 0xf618 */
4321 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4322 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4323 pbn_b0_4_921600 },
4324 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4325 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4326 pbn_b0_4_921600 },
1da177e4
LT		 4327 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4328 PCI_SUBVENDOR_ID_CONNECT_TECH,
4329 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4330 pbn_b1_8_1382400 },
4331 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4332 PCI_SUBVENDOR_ID_CONNECT_TECH,
4333 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4334 pbn_b1_4_1382400 },
4335 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4336 PCI_SUBVENDOR_ID_CONNECT_TECH,
4337 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4338 pbn_b1_2_1382400 },
4339 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4340 PCI_SUBVENDOR_ID_CONNECT_TECH,
4341 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4342 pbn_b1_8_1382400 },
4343 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4344 PCI_SUBVENDOR_ID_CONNECT_TECH,
4345 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4346 pbn_b1_4_1382400 },
4347 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4348 PCI_SUBVENDOR_ID_CONNECT_TECH,
4349 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4350 pbn_b1_2_1382400 },
4351 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4352 PCI_SUBVENDOR_ID_CONNECT_TECH,
4353 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4354 pbn_b1_8_921600 },
4355 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4356 PCI_SUBVENDOR_ID_CONNECT_TECH,
4357 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4358 pbn_b1_8_921600 },
4359 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4360 PCI_SUBVENDOR_ID_CONNECT_TECH,
4361 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4362 pbn_b1_4_921600 },
4363 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4364 PCI_SUBVENDOR_ID_CONNECT_TECH,
4365 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4366 pbn_b1_4_921600 },
4367 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4368 PCI_SUBVENDOR_ID_CONNECT_TECH,
4369 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4370 pbn_b1_2_921600 },
4371 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4372 PCI_SUBVENDOR_ID_CONNECT_TECH,
4373 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4374 pbn_b1_8_921600 },
4375 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4376 PCI_SUBVENDOR_ID_CONNECT_TECH,
4377 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4378 pbn_b1_8_921600 },
4379 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4380 PCI_SUBVENDOR_ID_CONNECT_TECH,
4381 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4382 pbn_b1_4_921600 },
26e92861
GH		 4383 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4384 PCI_SUBVENDOR_ID_CONNECT_TECH,
4385 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4386 pbn_b1_2_1250000 },
4387 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4388 PCI_SUBVENDOR_ID_CONNECT_TECH,
4389 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4390 pbn_b0_2_1843200 },
4391 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4392 PCI_SUBVENDOR_ID_CONNECT_TECH,
4393 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4394 pbn_b0_4_1843200 },
85d1494e
YY		 4395 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4396 PCI_VENDOR_ID_AFAVLAB,
4397 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4398 pbn_b0_4_1152000 },
26e92861
GH		 4399 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4400 PCI_SUBVENDOR_ID_CONNECT_TECH,
4401 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4402 pbn_b0_2_1843200_200 },
4403 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4404 PCI_SUBVENDOR_ID_CONNECT_TECH,
4405 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4406 pbn_b0_4_1843200_200 },
4407 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4408 PCI_SUBVENDOR_ID_CONNECT_TECH,
4409 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4410 pbn_b0_8_1843200_200 },
4411 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4412 PCI_SUBVENDOR_ID_CONNECT_TECH,
4413 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4414 pbn_b0_2_1843200_200 },
4415 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4416 PCI_SUBVENDOR_ID_CONNECT_TECH,
4417 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4418 pbn_b0_4_1843200_200 },
4419 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4420 PCI_SUBVENDOR_ID_CONNECT_TECH,
4421 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4422 pbn_b0_8_1843200_200 },
4423 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4424 PCI_SUBVENDOR_ID_CONNECT_TECH,
4425 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4426 pbn_b0_2_1843200_200 },
4427 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4428 PCI_SUBVENDOR_ID_CONNECT_TECH,
4429 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4430 pbn_b0_4_1843200_200 },
4431 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4432 PCI_SUBVENDOR_ID_CONNECT_TECH,
4433 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4434 pbn_b0_8_1843200_200 },
4435 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4436 PCI_SUBVENDOR_ID_CONNECT_TECH,
4437 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4438 pbn_b0_2_1843200_200 },
4439 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4440 PCI_SUBVENDOR_ID_CONNECT_TECH,
4441 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4442 pbn_b0_4_1843200_200 },
4443 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4444 PCI_SUBVENDOR_ID_CONNECT_TECH,
4445 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4446 pbn_b0_8_1843200_200 },
c68d2b15
BH		 4447 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4448 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4449 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 4450
4451 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4453 pbn_b2_bt_1_115200 },
4454 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4456 pbn_b2_bt_2_115200 },
4457 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4459 pbn_b2_bt_4_115200 },
4460 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4462 pbn_b2_bt_2_115200 },
4463 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4465 pbn_b2_bt_4_115200 },
4466 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4468 pbn_b2_8_115200 },
e65f0f82
FL		 4469 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_b2_8_460800 },
1da177e4
LT		 4472 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_b2_8_115200 },
4475
4476 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_b2_bt_2_115200 },
4479 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 pbn_b2_bt_2_921600 },
4482 /*
4483 * VScom SPCOM800, from sl@s.pl
4484 */
5756ee99
AC		 4485 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4487 pbn_b2_8_921600 },
4488 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4490 pbn_b2_4_921600 },
b76c5a07
CB		 4491 /* Unknown card - subdevice 0x1584 */
4492 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4493 PCI_VENDOR_ID_PLX,
4494 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 4495 pbn_b2_4_115200 },
4496 /* Unknown card - subdevice 0x1588 */
4497 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4498 PCI_VENDOR_ID_PLX,
4499 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4500 pbn_b2_8_115200 },
1da177e4
LT		 4501 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4502 PCI_SUBVENDOR_ID_KEYSPAN,
4503 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4504 pbn_panacom },
4505 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_panacom4 },
4508 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_panacom2 },
a9cccd34
MF		 4511 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4512 PCI_VENDOR_ID_ESDGMBH,
4513 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4514 pbn_b2_4_115200 },
1da177e4
LT		 4515 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4516 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4517 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4518 pbn_b2_4_460800 },
4519 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4520 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4521 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4522 pbn_b2_8_460800 },
4523 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4524 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4525 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4526 pbn_b2_16_460800 },
4527 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4528 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4529 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4530 pbn_b2_16_460800 },
4531 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4532 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4533 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4534 pbn_b2_4_460800 },
4535 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4536 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4537 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4538 pbn_b2_8_460800 },
add7b58e
BH		 4539 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4540 PCI_SUBVENDOR_ID_EXSYS,
4541 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4542 pbn_b2_4_115200 },
1da177e4
LT		 4543 /*
4544 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4545 * (Exoray@isys.ca)
4546 */
4547 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4548 0x10b5, 0x106a, 0, 0,
4549 pbn_plx_romulus },
1bc8cde4
MS		 4550 /*
4551 * EndRun Technologies. PCI express device range.
4552 * EndRun PTP/1588 has 2 Native UARTs.
4553 */
4554 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 pbn_endrun_2_4000000 },
55c7c0fd
AC		 4557 /*
4558 * Quatech cards. These actually have configurable clocks but for
4559 * now we just use the default.
4560 *
4561 * 100 series are RS232, 200 series RS422,
4562 */
1da177e4
LT		 4563 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565 pbn_b1_4_115200 },
4566 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_b1_2_115200 },
55c7c0fd
AC		 4569 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_b2_2_115200 },
4572 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_b1_2_115200 },
4575 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_b2_2_115200 },
4578 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_b1_4_115200 },
1da177e4
LT		 4581 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_b1_8_115200 },
4584 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_b1_8_115200 },
55c7c0fd
AC		 4587 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_b1_4_115200 },
4590 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b1_2_115200 },
4593 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b1_4_115200 },
4596 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_b1_2_115200 },
4599 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_b2_4_115200 },
4602 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_b2_2_115200 },
4605 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_b2_1_115200 },
4608 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_b2_4_115200 },
4611 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_b2_2_115200 },
4614 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_b2_1_115200 },
4617 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_b0_8_115200 },
4620
1da177e4 4621 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4622 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4623 0, 0,
1da177e4 4624 pbn_b0_4_921600 },
fbc0dc0d 4625 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4626 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4627 0, 0,
fbc0dc0d 4628 pbn_b0_4_1152000 },
c9bd9d01
MP		 4629 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_b0_bt_2_921600 },
db1de159
DR		 4632
4633 /*
4634 * The below card is a little controversial since it is the
4635 * subject of a PCI vendor/device ID clash. (See
4636 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4637 * For now just used the hex ID 0x950a.
4638 */
39aced68 4639 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4640 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4641 0, 0, pbn_b0_2_115200 },
4642 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4643 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4644 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4645 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_b0_2_1130000 },
70fd8fde
AP		 4648 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4649 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4650 pbn_b0_1_921600 },
1da177e4
LT		 4651 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_b0_4_115200 },
4654 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_b0_bt_2_921600 },
e847003f
LB		 4657 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4658 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4659 pbn_b2_8_1152000 },
1da177e4 4660
7106b4e3
LH		 4661 /*
4662 * Oxford Semiconductor Inc. Tornado PCI express device range.
4663 */
4664 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_b0_1_4000000 },
4667 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_b0_1_4000000 },
4670 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_oxsemi_1_4000000 },
4673 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_oxsemi_1_4000000 },
4676 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_b0_1_4000000 },
4679 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_b0_1_4000000 },
4682 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_oxsemi_1_4000000 },
4685 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_oxsemi_1_4000000 },
4688 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_b0_1_4000000 },
4691 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_b0_1_4000000 },
4694 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_b0_1_4000000 },
4697 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_b0_1_4000000 },
4700 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_oxsemi_2_4000000 },
4703 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_oxsemi_2_4000000 },
4706 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_oxsemi_4_4000000 },
4709 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_oxsemi_4_4000000 },
4712 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_oxsemi_8_4000000 },
4715 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_oxsemi_8_4000000 },
4718 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_oxsemi_1_4000000 },
4721 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_oxsemi_1_4000000 },
4724 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_oxsemi_1_4000000 },
4727 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 pbn_oxsemi_1_4000000 },
4730 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 pbn_oxsemi_1_4000000 },
4733 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 pbn_oxsemi_1_4000000 },
4736 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_oxsemi_1_4000000 },
4739 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 pbn_oxsemi_1_4000000 },
4742 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 pbn_oxsemi_1_4000000 },
4745 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 pbn_oxsemi_1_4000000 },
4748 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 pbn_oxsemi_1_4000000 },
4751 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 pbn_oxsemi_1_4000000 },
4754 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 pbn_oxsemi_1_4000000 },
4757 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 pbn_oxsemi_1_4000000 },
4760 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 pbn_oxsemi_1_4000000 },
4763 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 pbn_oxsemi_1_4000000 },
4766 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 pbn_oxsemi_1_4000000 },
4769 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 pbn_oxsemi_1_4000000 },
4772 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 pbn_oxsemi_1_4000000 },
4775 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 pbn_oxsemi_1_4000000 },
4778 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 pbn_oxsemi_1_4000000 },
4781 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 pbn_oxsemi_1_4000000 },
4784 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 pbn_oxsemi_1_4000000 },
4787 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 pbn_oxsemi_1_4000000 },
4790 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 pbn_oxsemi_1_4000000 },
4793 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 pbn_oxsemi_1_4000000 },
b80de369
LH		 4796 /*
4797 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4798 */
4799 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4800 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4801 pbn_oxsemi_1_4000000 },
4802 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4803 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4804 pbn_oxsemi_2_4000000 },
4805 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4806 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4807 pbn_oxsemi_4_4000000 },
4808 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4809 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4810 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4811
4812 /*
4813 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4814 */
4815 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4816 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4817 pbn_oxsemi_2_4000000 },
4818
1da177e4
LT		 4819 /*
4820 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4821 * from skokodyn@yahoo.com
4822 */
4823 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4824 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4825 pbn_sbsxrsio },
4826 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4827 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4828 pbn_sbsxrsio },
4829 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4830 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4831 pbn_sbsxrsio },
4832 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4833 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4834 pbn_sbsxrsio },
4835
4836 /*
4837 * Digitan DS560-558, from jimd@esoft.com
4838 */
4839 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4841 pbn_b1_1_115200 },
4842
4843 /*
4844 * Titan Electronic cards
4845 * The 400L and 800L have a custom setup quirk.
4846 */
4847 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4849 pbn_b0_1_921600 },
4850 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4852 pbn_b0_2_921600 },
4853 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4855 pbn_b0_4_921600 },
4856 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4858 pbn_b0_4_921600 },
4859 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861 pbn_b1_1_921600 },
4862 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864 pbn_b1_bt_2_921600 },
4865 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867 pbn_b0_bt_4_921600 },
4868 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870 pbn_b0_bt_8_921600 },
66169ad1
YY		 4871 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873 pbn_b4_bt_2_921600 },
4874 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876 pbn_b4_bt_4_921600 },
4877 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 pbn_b4_bt_8_921600 },
4880 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 pbn_b0_4_921600 },
4883 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 pbn_b0_4_921600 },
4886 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 pbn_b0_4_921600 },
4889 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_oxsemi_1_4000000 },
4892 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 pbn_oxsemi_2_4000000 },
4895 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 pbn_oxsemi_4_4000000 },
4898 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900 pbn_oxsemi_8_4000000 },
4901 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 pbn_oxsemi_2_4000000 },
4904 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906 pbn_oxsemi_2_4000000 },
48c0247d
YY		 4907 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4910 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 pbn_b0_4_921600 },
4913 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 pbn_b0_4_921600 },
4916 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 pbn_b0_4_921600 },
4919 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921 pbn_b0_4_921600 },
1da177e4
LT		 4922
4923 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4925 pbn_b2_1_460800 },
4926 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4928 pbn_b2_1_460800 },
4929 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931 pbn_b2_1_460800 },
4932 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934 pbn_b2_bt_2_921600 },
4935 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937 pbn_b2_bt_2_921600 },
4938 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940 pbn_b2_bt_2_921600 },
4941 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4943 pbn_b2_bt_4_921600 },
4944 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4946 pbn_b2_bt_4_921600 },
4947 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4949 pbn_b2_bt_4_921600 },
4950 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4952 pbn_b0_1_921600 },
4953 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4955 pbn_b0_1_921600 },
4956 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4958 pbn_b0_1_921600 },
4959 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4961 pbn_b0_bt_2_921600 },
4962 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4964 pbn_b0_bt_2_921600 },
4965 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4967 pbn_b0_bt_2_921600 },
4968 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4970 pbn_b0_bt_4_921600 },
4971 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4973 pbn_b0_bt_4_921600 },
4974 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4976 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4977 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4979 pbn_b0_bt_8_921600 },
4980 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4982 pbn_b0_bt_8_921600 },
4983 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985 pbn_b0_bt_8_921600 },
1da177e4
LT		 4986
4987 /*
4988 * Computone devices submitted by Doug McNash dmcnash@computone.com
4989 */
4990 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4991 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4992 0, 0, pbn_computone_4 },
4993 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4994 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4995 0, 0, pbn_computone_8 },
4996 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4997 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4998 0, 0, pbn_computone_6 },
4999
5000 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 pbn_oxsemi },
5003 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5004 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5005 pbn_b0_bt_1_921600 },
5006
abd7baca
SC		 5007 /*
5008 * SUNIX (TIMEDIA)
5009 */
5010 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5011 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
5012 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
5013 pbn_b0_bt_1_921600 },
5014
5015 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5016 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
5017 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5018 pbn_b0_bt_1_921600 },
5019
1da177e4
LT		 5020 /*
5021 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5022 */
5023 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5025 pbn_b0_bt_8_115200 },
5026 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5028 pbn_b0_bt_8_115200 },
5029
5030 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5032 pbn_b0_bt_2_115200 },
5033 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035 pbn_b0_bt_2_115200 },
5036 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 5039 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041 pbn_b0_bt_2_115200 },
5042 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044 pbn_b0_bt_2_115200 },
1da177e4
LT		 5045 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5047 pbn_b0_bt_4_460800 },
5048 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050 pbn_b0_bt_4_460800 },
5051 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053 pbn_b0_bt_2_460800 },
5054 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5056 pbn_b0_bt_2_460800 },
5057 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5059 pbn_b0_bt_2_460800 },
5060 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062 pbn_b0_bt_1_115200 },
5063 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065 pbn_b0_bt_1_460800 },
5066
1fb8cacc
RK		 5067 /*
5068 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5069 * Cards are identified by their subsystem vendor IDs, which
5070 * (in hex) match the model number.
5071 *
5072 * Note that JC140x are RS422/485 cards which require ox950
5073 * ACR = 0x10, and as such are not currently fully supported.
5074 */
5075 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5076 0x1204, 0x0004, 0, 0,
5077 pbn_b0_4_921600 },
5078 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5079 0x1208, 0x0004, 0, 0,
5080 pbn_b0_4_921600 },
5081/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5082 0x1402, 0x0002, 0, 0,
5083 pbn_b0_2_921600 }, */
5084/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5085 0x1404, 0x0004, 0, 0,
5086 pbn_b0_4_921600 }, */
5087 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5088 0x1208, 0x0004, 0, 0,
5089 pbn_b0_4_921600 },
5090
2a52fcb5
KY		 5091 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5092 0x1204, 0x0004, 0, 0,
5093 pbn_b0_4_921600 },
5094 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5095 0x1208, 0x0004, 0, 0,
5096 pbn_b0_4_921600 },
5097 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5098 0x1208, 0x0004, 0, 0,
5099 pbn_b0_4_921600 },
1da177e4
LT		 5100 /*
5101 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5102 */
5103 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5105 pbn_b1_1_1382400 },
5106
5107 /*
5108 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5109 */
5110 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5112 pbn_b1_1_1382400 },
5113
5114 /*
5115 * RAStel 2 port modem, gerg@moreton.com.au
5116 */
5117 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5119 pbn_b2_bt_2_115200 },
5120
5121 /*
5122 * EKF addition for i960 Boards form EKF with serial port
5123 */
5124 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5125 0xE4BF, PCI_ANY_ID, 0, 0,
5126 pbn_intel_i960 },
5127
5128 /*
5129 * Xircom Cardbus/Ethernet combos
5130 */
5131 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5133 pbn_b0_1_115200 },
5134 /*
5135 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5136 */
5137 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5139 pbn_b0_1_115200 },
5140
5141 /*
5142 * Untested PCI modems, sent in from various folks...
5143 */
5144
5145 /*
5146 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5147 */
5148 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5149 0x1048, 0x1500, 0, 0,
5150 pbn_b1_1_115200 },
5151
5152 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5153 0xFF00, 0, 0, 0,
5154 pbn_sgi_ioc3 },
5155
5156 /*
5157 * HP Diva card
5158 */
5159 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5160 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5161 pbn_b1_1_115200 },
5162 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5164 pbn_b0_5_115200 },
5165 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5167 pbn_b2_1_115200 },
5168
d9004eb4
ABL		 5169 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5171 pbn_b3_2_115200 },
1da177e4
LT		 5172 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5174 pbn_b3_4_115200 },
5175 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5177 pbn_b3_8_115200 },
5178
5179 /*
5180 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5181 */
5182 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5183 PCI_ANY_ID, PCI_ANY_ID,
5184 0,
5185 0, pbn_exar_XR17C152 },
5186 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5187 PCI_ANY_ID, PCI_ANY_ID,
5188 0,
5189 0, pbn_exar_XR17C154 },
5190 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5191 PCI_ANY_ID, PCI_ANY_ID,
5192 0,
5193 0, pbn_exar_XR17C158 },
dc96efb7 5194 /*
96a5d18b 5195 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
dc96efb7
MS		 5196 */
5197 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5198 PCI_ANY_ID, PCI_ANY_ID,
5199 0,
5200 0, pbn_exar_XR17V352 },
5201 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5202 PCI_ANY_ID, PCI_ANY_ID,
5203 0,
5204 0, pbn_exar_XR17V354 },
5205 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5206 PCI_ANY_ID, PCI_ANY_ID,
5207 0,
5208 0, pbn_exar_XR17V358 },
be32c0cf
SG		 5209 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5210 PCI_ANY_ID, PCI_ANY_ID,
5211 0,
5212 0, pbn_exar_XR17V4358 },
96a5d18b
SG		 5213 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5214 PCI_ANY_ID, PCI_ANY_ID,
5215 0,
5216 0, pbn_exar_XR17V8358 },
1da177e4
LT		 5217 /*
5218 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5219 */
5220 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5222 pbn_b0_1_115200 },
84f8c6fc
NV		 5223 /*
5224 * ITE
5225 */
5226 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5227 PCI_ANY_ID, PCI_ANY_ID,
5228 0, 0,
5229 pbn_b1_bt_1_115200 },
1da177e4 5230
737c1756
PH		 5231 /*
5232 * IntaShield IS-200
5233 */
5234 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5236 pbn_b2_2_115200 },
4b6f6ce9
IGP		 5237 /*
5238 * IntaShield IS-400
5239 */
5240 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5242 pbn_b2_4_115200 },
48212008
TH		 5243 /*
5244 * Perle PCI-RAS cards
5245 */
5246 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5247 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5248 0, 0, pbn_b2_4_921600 },
5249 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5250 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5251 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 5252
5253 /*
5254 * Mainpine series cards: Fairly standard layout but fools
5255 * parts of the autodetect in some cases and uses otherwise
5256 * unmatched communications subclasses in the PCI Express case
5257 */
5258
5259 { /* RockForceDUO */
5260 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5261 PCI_VENDOR_ID_MAINPINE, 0x0200,
5262 0, 0, pbn_b0_2_115200 },
5263 { /* RockForceQUATRO */
5264 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5265 PCI_VENDOR_ID_MAINPINE, 0x0300,
5266 0, 0, pbn_b0_4_115200 },
5267 { /* RockForceDUO+ */
5268 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5269 PCI_VENDOR_ID_MAINPINE, 0x0400,
5270 0, 0, pbn_b0_2_115200 },
5271 { /* RockForceQUATRO+ */
5272 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5273 PCI_VENDOR_ID_MAINPINE, 0x0500,
5274 0, 0, pbn_b0_4_115200 },
5275 { /* RockForce+ */
5276 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5277 PCI_VENDOR_ID_MAINPINE, 0x0600,
5278 0, 0, pbn_b0_2_115200 },
5279 { /* RockForce+ */
5280 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5281 PCI_VENDOR_ID_MAINPINE, 0x0700,
5282 0, 0, pbn_b0_4_115200 },
5283 { /* RockForceOCTO+ */
5284 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5285 PCI_VENDOR_ID_MAINPINE, 0x0800,
5286 0, 0, pbn_b0_8_115200 },
5287 { /* RockForceDUO+ */
5288 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5289 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5290 0, 0, pbn_b0_2_115200 },
5291 { /* RockForceQUARTRO+ */
5292 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5293 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5294 0, 0, pbn_b0_4_115200 },
5295 { /* RockForceOCTO+ */
5296 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5297 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5298 0, 0, pbn_b0_8_115200 },
5299 { /* RockForceD1 */
5300 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5301 PCI_VENDOR_ID_MAINPINE, 0x2000,
5302 0, 0, pbn_b0_1_115200 },
5303 { /* RockForceF1 */
5304 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5305 PCI_VENDOR_ID_MAINPINE, 0x2100,
5306 0, 0, pbn_b0_1_115200 },
5307 { /* RockForceD2 */
5308 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5309 PCI_VENDOR_ID_MAINPINE, 0x2200,
5310 0, 0, pbn_b0_2_115200 },
5311 { /* RockForceF2 */
5312 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5313 PCI_VENDOR_ID_MAINPINE, 0x2300,
5314 0, 0, pbn_b0_2_115200 },
5315 { /* RockForceD4 */
5316 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5317 PCI_VENDOR_ID_MAINPINE, 0x2400,
5318 0, 0, pbn_b0_4_115200 },
5319 { /* RockForceF4 */
5320 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5321 PCI_VENDOR_ID_MAINPINE, 0x2500,
5322 0, 0, pbn_b0_4_115200 },
5323 { /* RockForceD8 */
5324 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5325 PCI_VENDOR_ID_MAINPINE, 0x2600,
5326 0, 0, pbn_b0_8_115200 },
5327 { /* RockForceF8 */
5328 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5329 PCI_VENDOR_ID_MAINPINE, 0x2700,
5330 0, 0, pbn_b0_8_115200 },
5331 { /* IQ Express D1 */
5332 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5333 PCI_VENDOR_ID_MAINPINE, 0x3000,
5334 0, 0, pbn_b0_1_115200 },
5335 { /* IQ Express F1 */
5336 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5337 PCI_VENDOR_ID_MAINPINE, 0x3100,
5338 0, 0, pbn_b0_1_115200 },
5339 { /* IQ Express D2 */
5340 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5341 PCI_VENDOR_ID_MAINPINE, 0x3200,
5342 0, 0, pbn_b0_2_115200 },
5343 { /* IQ Express F2 */
5344 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5345 PCI_VENDOR_ID_MAINPINE, 0x3300,
5346 0, 0, pbn_b0_2_115200 },
5347 { /* IQ Express D4 */
5348 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5349 PCI_VENDOR_ID_MAINPINE, 0x3400,
5350 0, 0, pbn_b0_4_115200 },
5351 { /* IQ Express F4 */
5352 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5353 PCI_VENDOR_ID_MAINPINE, 0x3500,
5354 0, 0, pbn_b0_4_115200 },
5355 { /* IQ Express D8 */
5356 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5357 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5358 0, 0, pbn_b0_8_115200 },
5359 { /* IQ Express F8 */
5360 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5361 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5362 0, 0, pbn_b0_8_115200 },
5363
5364
aa798505
OJ		 5365 /*
5366 * PA Semi PA6T-1682M on-chip UART
5367 */
5368 { PCI_VENDOR_ID_PASEMI, 0xa004,
5369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5370 pbn_pasemi_1682M },
5371
46a0fac9
SB		 5372 /*
5373 * National Instruments
5374 */
04bf7e74
WP		 5375 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5377 pbn_b1_16_115200 },
5378 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5380 pbn_b1_8_115200 },
5381 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5383 pbn_b1_bt_4_115200 },
5384 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5386 pbn_b1_bt_2_115200 },
5387 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5389 pbn_b1_bt_4_115200 },
5390 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5392 pbn_b1_bt_2_115200 },
5393 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5395 pbn_b1_16_115200 },
5396 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5398 pbn_b1_8_115200 },
5399 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5401 pbn_b1_bt_4_115200 },
5402 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5404 pbn_b1_bt_2_115200 },
5405 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5407 pbn_b1_bt_4_115200 },
5408 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5410 pbn_b1_bt_2_115200 },
46a0fac9
SB		 5411 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5413 pbn_ni8430_2 },
5414 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5416 pbn_ni8430_2 },
5417 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5419 pbn_ni8430_4 },
5420 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5422 pbn_ni8430_4 },
5423 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5425 pbn_ni8430_8 },
5426 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5428 pbn_ni8430_8 },
5429 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5431 pbn_ni8430_16 },
5432 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5434 pbn_ni8430_16 },
5435 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5437 pbn_ni8430_2 },
5438 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5440 pbn_ni8430_2 },
5441 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5443 pbn_ni8430_4 },
5444 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5446 pbn_ni8430_4 },
5447
02c9b5cf
KJ		 5448 /*
5449 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5450 */
5451 { PCI_VENDOR_ID_ADDIDATA,
5452 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5453 PCI_ANY_ID,
5454 PCI_ANY_ID,
5455 0,
5456 0,
5457 pbn_b0_4_115200 },
5458
5459 { PCI_VENDOR_ID_ADDIDATA,
5460 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5461 PCI_ANY_ID,
5462 PCI_ANY_ID,
5463 0,
5464 0,
5465 pbn_b0_2_115200 },
5466
5467 { PCI_VENDOR_ID_ADDIDATA,
5468 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5469 PCI_ANY_ID,
5470 PCI_ANY_ID,
5471 0,
5472 0,
5473 pbn_b0_1_115200 },
5474
086231f7 5475 { PCI_VENDOR_ID_AMCC,
57c1f0e9 5476 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 5477 PCI_ANY_ID,
5478 PCI_ANY_ID,
5479 0,
5480 0,
5481 pbn_b1_8_115200 },
5482
5483 { PCI_VENDOR_ID_ADDIDATA,
5484 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5485 PCI_ANY_ID,
5486 PCI_ANY_ID,
5487 0,
5488 0,
5489 pbn_b0_4_115200 },
5490
5491 { PCI_VENDOR_ID_ADDIDATA,
5492 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5493 PCI_ANY_ID,
5494 PCI_ANY_ID,
5495 0,
5496 0,
5497 pbn_b0_2_115200 },
5498
5499 { PCI_VENDOR_ID_ADDIDATA,
5500 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5501 PCI_ANY_ID,
5502 PCI_ANY_ID,
5503 0,
5504 0,
5505 pbn_b0_1_115200 },
5506
5507 { PCI_VENDOR_ID_ADDIDATA,
5508 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5509 PCI_ANY_ID,
5510 PCI_ANY_ID,
5511 0,
5512 0,
5513 pbn_b0_4_115200 },
5514
5515 { PCI_VENDOR_ID_ADDIDATA,
5516 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5517 PCI_ANY_ID,
5518 PCI_ANY_ID,
5519 0,
5520 0,
5521 pbn_b0_2_115200 },
5522
5523 { PCI_VENDOR_ID_ADDIDATA,
5524 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5525 PCI_ANY_ID,
5526 PCI_ANY_ID,
5527 0,
5528 0,
5529 pbn_b0_1_115200 },
5530
5531 { PCI_VENDOR_ID_ADDIDATA,
5532 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5533 PCI_ANY_ID,
5534 PCI_ANY_ID,
5535 0,
5536 0,
5537 pbn_b0_8_115200 },
5538
1b62cbf2
KJ		 5539 { PCI_VENDOR_ID_ADDIDATA,
5540 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5541 PCI_ANY_ID,
5542 PCI_ANY_ID,
5543 0,
5544 0,
5545 pbn_ADDIDATA_PCIe_4_3906250 },
5546
5547 { PCI_VENDOR_ID_ADDIDATA,
5548 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5549 PCI_ANY_ID,
5550 PCI_ANY_ID,
5551 0,
5552 0,
5553 pbn_ADDIDATA_PCIe_2_3906250 },
5554
5555 { PCI_VENDOR_ID_ADDIDATA,
5556 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5557 PCI_ANY_ID,
5558 PCI_ANY_ID,
5559 0,
5560 0,
5561 pbn_ADDIDATA_PCIe_1_3906250 },
5562
5563 { PCI_VENDOR_ID_ADDIDATA,
5564 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5565 PCI_ANY_ID,
5566 PCI_ANY_ID,
5567 0,
5568 0,
5569 pbn_ADDIDATA_PCIe_8_3906250 },
5570
25cf9bc1
JS		 5571 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5572 PCI_VENDOR_ID_IBM, 0x0299,
5573 0, 0, pbn_b0_bt_2_115200 },
5574
972ce085
SS		 5575 /*
5576 * other NetMos 9835 devices are most likely handled by the
5577 * parport_serial driver, check drivers/parport/parport_serial.c
5578 * before adding them here.
5579 */
5580
c4285b47
MB		 5581 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5582 0xA000, 0x1000,
5583 0, 0, pbn_b0_1_115200 },
5584
7808edcd
NG		 5585 /* the 9901 is a rebranded 9912 */
5586 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5587 0xA000, 0x1000,
5588 0, 0, pbn_b0_1_115200 },
5589
5590 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5591 0xA000, 0x1000,
5592 0, 0, pbn_b0_1_115200 },
5593
5594 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5595 0xA000, 0x1000,
5596 0, 0, pbn_b0_1_115200 },
5597
5598 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5599 0xA000, 0x1000,
5600 0, 0, pbn_b0_1_115200 },
5601
5602 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5603 0xA000, 0x3002,
5604 0, 0, pbn_NETMOS9900_2s_115200 },
5605
ac6ec5b1 5606 /*
44178176 5607 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5608 */
5609
5610 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5611 0xA000, 0x1000,
5612 0, 0, pbn_b0_1_115200 },
5613
44178176
ES		 5614 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5615 0xA000, 0x3002,
5616 0, 0, pbn_b0_bt_2_115200 },
5617
ac6ec5b1
IS		 5618 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5619 0xA000, 0x3004,
5620 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5621 /* Intel CE4100 */
5622 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5624 pbn_ce4100_1_115200 },
b15e5691
HK		 5625 /* Intel BayTrail */
5626 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5627 PCI_ANY_ID, PCI_ANY_ID,
5628 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5629 pbn_byt },
5630 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5631 PCI_ANY_ID, PCI_ANY_ID,
5632 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5633 pbn_byt },
29897087
AC		 5634 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5635 PCI_ANY_ID, PCI_ANY_ID,
5636 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5637 pbn_byt },
5638 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
b15e5691
HK		 5639 PCI_ANY_ID, PCI_ANY_ID,
5640 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5641 pbn_byt },
095e24b0 5642
f549e94e
AS		 5643 /*
5644 * Intel Penwell
5645 */
5646 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
5647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5648 pbn_pnw},
5649 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
5650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5651 pbn_pnw},
5652 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
5653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5654 pbn_pnw},
5655
90b9aacf
AS		 5656 /*
5657 * Intel Tangier
5658 */
5659 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART,
5660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5661 pbn_tng},
5662
1ede7dcc
BD		 5663 /*
5664 * Intel Quark x1000
5665 */
5666 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5668 pbn_qrk },
d9a0fbfd
AP		 5669 /*
5670 * Cronyx Omega PCI
5671 */
5672 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5674 pbn_omegapci },
ac6ec5b1 5675
ebebd49a
SH		 5676 /*
5677 * Broadcom TruManage
5678 */
5679 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5681 pbn_brcm_trumanage },
5682
6683549e
AC		 5683 /*
5684 * AgeStar as-prs2-009
5685 */
5686 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5687 PCI_ANY_ID, PCI_ANY_ID,
5688 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5689
5690 /*
5691 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5692 * so not listed here.
5693 */
5694 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5695 PCI_ANY_ID, PCI_ANY_ID,
5696 0, 0, pbn_b0_bt_4_115200 },
5697
5698 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5699 PCI_ANY_ID, PCI_ANY_ID,
5700 0, 0, pbn_b0_bt_2_115200 },
5701
72a3c0e4
SP		 5702 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5703 PCI_ANY_ID, PCI_ANY_ID,
5704 0, 0, pbn_wch384_4 },
5705
14faa8cc
MS		 5706 /*
5707 * Commtech, Inc. Fastcom adapters
5708 */
5709 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5710 PCI_ANY_ID, PCI_ANY_ID,
5711 0,
5712 0, pbn_b0_2_1152000_200 },
5713 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5714 PCI_ANY_ID, PCI_ANY_ID,
5715 0,
5716 0, pbn_b0_4_1152000_200 },
5717 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5718 PCI_ANY_ID, PCI_ANY_ID,
5719 0,
5720 0, pbn_b0_4_1152000_200 },
5721 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5722 PCI_ANY_ID, PCI_ANY_ID,
5723 0,
5724 0, pbn_b0_8_1152000_200 },
5725 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5726 PCI_ANY_ID, PCI_ANY_ID,
5727 0,
5728 0, pbn_exar_XR17V352 },
5729 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5730 PCI_ANY_ID, PCI_ANY_ID,
5731 0,
5732 0, pbn_exar_XR17V354 },
5733 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5734 PCI_ANY_ID, PCI_ANY_ID,
5735 0,
5736 0, pbn_exar_XR17V358 },
5737
2c62a3c8
GKH		 5738 /* Fintek PCI serial cards */
5739 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5740 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5741 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5742
1da177e4
LT		 5743 /*
5744 * These entries match devices with class COMMUNICATION_SERIAL,
5745 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5746 */
5747 { PCI_ANY_ID, PCI_ANY_ID,
5748 PCI_ANY_ID, PCI_ANY_ID,
5749 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5750 0xffff00, pbn_default },
5751 { PCI_ANY_ID, PCI_ANY_ID,
5752 PCI_ANY_ID, PCI_ANY_ID,
5753 PCI_CLASS_COMMUNICATION_MODEM << 8,
5754 0xffff00, pbn_default },
5755 { PCI_ANY_ID, PCI_ANY_ID,
5756 PCI_ANY_ID, PCI_ANY_ID,
5757 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5758 0xffff00, pbn_default },
5759 { 0, }
5760};
5761
2807190b
MR		 5762static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5763 pci_channel_state_t state)
5764{
5765 struct serial_private *priv = pci_get_drvdata(dev);
5766
5767 if (state == pci_channel_io_perm_failure)
5768 return PCI_ERS_RESULT_DISCONNECT;
5769
5770 if (priv)
5771 pciserial_suspend_ports(priv);
5772
5773 pci_disable_device(dev);
5774
5775 return PCI_ERS_RESULT_NEED_RESET;
5776}
5777
5778static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5779{
5780 int rc;
5781
5782 rc = pci_enable_device(dev);
5783
5784 if (rc)
5785 return PCI_ERS_RESULT_DISCONNECT;
5786
5787 pci_restore_state(dev);
5788 pci_save_state(dev);
5789
5790 return PCI_ERS_RESULT_RECOVERED;
5791}
5792
5793static void serial8250_io_resume(struct pci_dev *dev)
5794{
5795 struct serial_private *priv = pci_get_drvdata(dev);
5796
5797 if (priv)
5798 pciserial_resume_ports(priv);
5799}
5800
1d352035 5801static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5802 .error_detected = serial8250_io_error_detected,
5803 .slot_reset = serial8250_io_slot_reset,
5804 .resume = serial8250_io_resume,
5805};
5806
1da177e4
LT		 5807static struct pci_driver serial_pci_driver = {
5808 .name = "serial",
5809 .probe = pciserial_init_one,
2d47b716 5810 .remove = pciserial_remove_one,
61702c3e
AS		 5811 .driver = {
5812 .pm = &pciserial_pm_ops,
5813 },
1da177e4 5814 .id_table = serial_pci_tbl,
2807190b 5815 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5816};
5817
15a12e83 5818module_pci_driver(serial_pci_driver);
1da177e4
LT		 5819
5820MODULE_LICENSE("GPL");
5821MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5822MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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