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serial: 8250: don't use slave_id of dma_slave_config
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4 13#include <linux/module.h>
1da177e4 14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
9a1870ce
AS		 28#include <linux/dmaengine.h>
29#include <linux/platform_data/dma-dw.h>
30
1da177e4
LT		 31#include "8250.h"
32
1da177e4
LT		 33/*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
5bf8f501 44 int (*probe)(struct pci_dev *dev);
1da177e4 45 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 46 int (*setup)(struct serial_private *,
47 const struct pciserial_board *,
2655a2c7 48 struct uart_8250_port *, int);
1da177e4
LT		 49 void (*exit)(struct pci_dev *dev);
50};
51
52#define PCI_NUM_BAR_RESOURCES 6
53
54struct serial_private {
70db3d91 55 struct pci_dev *dev;
1da177e4
LT		 56 unsigned int nr;
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
59 int line[0];
60};
61
7808edcd 62static int pci_default_setup(struct serial_private*,
2655a2c7 63 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 64
1da177e4
LT		 65static void moan_device(const char *str, struct pci_dev *dev)
66{
af8c5b8d 67 dev_err(&dev->dev,
ad361c98
JP		 68 "%s: %s\n"
69 "Please send the output of lspci -vv, this\n"
70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
71 "manufacturer and name of serial board or\n"
72 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 73 pci_name(dev), str, dev->vendor, dev->device,
74 dev->subsystem_vendor, dev->subsystem_device);
75}
76
77static int
2655a2c7 78setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 79 int bar, int offset, int regshift)
80{
70db3d91 81 struct pci_dev *dev = priv->dev;
1da177e4
LT		 82 unsigned long base, len;
83
84 if (bar >= PCI_NUM_BAR_RESOURCES)
85 return -EINVAL;
86
72ce9a83
RK		 87 base = pci_resource_start(dev, bar);
88
1da177e4 89 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 90 len = pci_resource_len(dev, bar);
91
92 if (!priv->remapped_bar[bar])
6f441fe9 93 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 94 if (!priv->remapped_bar[bar])
95 return -ENOMEM;
96
2655a2c7
AC		 97 port->port.iotype = UPIO_MEM;
98 port->port.iobase = 0;
99 port->port.mapbase = base + offset;
100 port->port.membase = priv->remapped_bar[bar] + offset;
101 port->port.regshift = regshift;
1da177e4 102 } else {
2655a2c7
AC		 103 port->port.iotype = UPIO_PORT;
104 port->port.iobase = base + offset;
105 port->port.mapbase = 0;
106 port->port.membase = NULL;
107 port->port.regshift = 0;
1da177e4
LT		 108 }
109 return 0;
110}
111
02c9b5cf
KJ		 112/*
113 * ADDI-DATA GmbH communication cards <info@addi-data.com>
114 */
115static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 116 const struct pciserial_board *board,
2655a2c7 117 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 118{
119 unsigned int bar = 0, offset = board->first_offset;
120 bar = FL_GET_BASE(board->flags);
121
122 if (idx < 2) {
123 offset += idx * board->uart_offset;
124 } else if ((idx >= 2) && (idx < 4)) {
125 bar += 1;
126 offset += ((idx - 2) * board->uart_offset);
127 } else if ((idx >= 4) && (idx < 6)) {
128 bar += 2;
129 offset += ((idx - 4) * board->uart_offset);
130 } else if (idx >= 6) {
131 bar += 3;
132 offset += ((idx - 6) * board->uart_offset);
133 }
134
135 return setup_port(priv, port, bar, offset, board->reg_shift);
136}
137
1da177e4
LT		 138/*
139 * AFAVLAB uses a different mixture of BARs and offsets
140 * Not that ugly ;) -- HW
141 */
142static int
975a1a7d 143afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 144 struct uart_8250_port *port, int idx)
1da177e4
LT		 145{
146 unsigned int bar, offset = board->first_offset;
5756ee99 147
1da177e4
LT		 148 bar = FL_GET_BASE(board->flags);
149 if (idx < 4)
150 bar += idx;
151 else {
152 bar = 4;
153 offset += (idx - 4) * board->uart_offset;
154 }
155
70db3d91 156 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 157}
158
159/*
160 * HP's Remote Management Console. The Diva chip came in several
161 * different versions. N-class, L2000 and A500 have two Diva chips, each
162 * with 3 UARTs (the third UART on the second chip is unused). Superdome
163 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
164 * one Diva chip, but it has been expanded to 5 UARTs.
165 */
61a116ef 166static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 167{
168 int rc = 0;
169
170 switch (dev->subsystem_device) {
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
172 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
173 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
174 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
175 rc = 3;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
178 rc = 2;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
181 rc = 4;
182 break;
183 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 184 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 185 rc = 1;
186 break;
187 }
188
189 return rc;
190}
191
192/*
193 * HP's Diva chip puts the 4th/5th serial port further out, and
194 * some serial ports are supposed to be hidden on certain models.
195 */
196static int
975a1a7d
RK		 197pci_hp_diva_setup(struct serial_private *priv,
198 const struct pciserial_board *board,
2655a2c7 199 struct uart_8250_port *port, int idx)
1da177e4
LT		 200{
201 unsigned int offset = board->first_offset;
202 unsigned int bar = FL_GET_BASE(board->flags);
203
70db3d91 204 switch (priv->dev->subsystem_device) {
1da177e4
LT		 205 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
206 if (idx == 3)
207 idx++;
208 break;
209 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
210 if (idx > 0)
211 idx++;
212 if (idx > 2)
213 idx++;
214 break;
215 }
216 if (idx > 2)
217 offset = 0x18;
218
219 offset += idx * board->uart_offset;
220
70db3d91 221 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 222}
223
224/*
225 * Added for EKF Intel i960 serial boards
226 */
61a116ef 227static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 228{
229 unsigned long oldval;
230
231 if (!(dev->subsystem_device & 0x1000))
232 return -ENODEV;
233
234 /* is firmware started? */
5756ee99
AC		 235 pci_read_config_dword(dev, 0x44, (void *)&oldval);
236 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 237 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 238 return -ENODEV;
239 }
240 return 0;
241}
242
243/*
244 * Some PCI serial cards using the PLX 9050 PCI interface chip require
245 * that the card interrupt be explicitly enabled or disabled. This
246 * seems to be mainly needed on card using the PLX which also use I/O
247 * mapped memory.
248 */
61a116ef 249static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 250{
251 u8 irq_config;
252 void __iomem *p;
253
254 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
255 moan_device("no memory in bar 0", dev);
256 return 0;
257 }
258
259 irq_config = 0x41;
add7b58e 260 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 261 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 262 irq_config = 0x43;
5756ee99 263
1da177e4 264 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 265 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 266 /*
267 * As the megawolf cards have the int pins active
268 * high, and have 2 UART chips, both ints must be
269 * enabled on the 9050. Also, the UARTS are set in
270 * 16450 mode by default, so we have to enable the
271 * 16C950 'enhanced' mode so that we can use the
272 * deep FIFOs
273 */
274 irq_config = 0x5b;
1da177e4
LT		 275 /*
276 * enable/disable interrupts
277 */
6f441fe9 278 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 279 if (p == NULL)
280 return -ENOMEM;
281 writel(irq_config, p + 0x4c);
282
283 /*
284 * Read the register back to ensure that it took effect.
285 */
286 readl(p + 0x4c);
287 iounmap(p);
288
289 return 0;
290}
291
ae8d8a14 292static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 293{
294 u8 __iomem *p;
295
296 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
297 return;
298
299 /*
300 * disable interrupts
301 */
6f441fe9 302 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 303 if (p != NULL) {
304 writel(0, p + 0x4c);
305
306 /*
307 * Read the register back to ensure that it took effect.
308 */
309 readl(p + 0x4c);
310 iounmap(p);
311 }
312}
313
04bf7e74
WP		 314#define NI8420_INT_ENABLE_REG 0x38
315#define NI8420_INT_ENABLE_BIT 0x2000
316
ae8d8a14 317static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 318{
319 void __iomem *p;
320 unsigned long base, len;
321 unsigned int bar = 0;
322
323 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
324 moan_device("no memory in bar", dev);
325 return;
326 }
327
328 base = pci_resource_start(dev, bar);
329 len = pci_resource_len(dev, bar);
330 p = ioremap_nocache(base, len);
331 if (p == NULL)
332 return;
333
334 /* Disable the CPU Interrupt */
335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
336 p + NI8420_INT_ENABLE_REG);
337 iounmap(p);
338}
339
340
46a0fac9
SB		 341/* MITE registers */
342#define MITE_IOWBSR1 0xc4
343#define MITE_IOWCR1 0xf4
344#define MITE_LCIMR1 0x08
345#define MITE_LCIMR2 0x10
346
347#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
348
ae8d8a14 349static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 350{
351 void __iomem *p;
352 unsigned long base, len;
353 unsigned int bar = 0;
354
355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
356 moan_device("no memory in bar", dev);
357 return;
358 }
359
360 base = pci_resource_start(dev, bar);
361 len = pci_resource_len(dev, bar);
362 p = ioremap_nocache(base, len);
363 if (p == NULL)
364 return;
365
366 /* Disable the CPU Interrupt */
367 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
368 iounmap(p);
369}
370
1da177e4
LT		 371/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
372static int
975a1a7d 373sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 374 struct uart_8250_port *port, int idx)
1da177e4
LT		 375{
376 unsigned int bar, offset = board->first_offset;
377
378 bar = 0;
379
380 if (idx < 4) {
381 /* first four channels map to 0, 0x100, 0x200, 0x300 */
382 offset += idx * board->uart_offset;
383 } else if (idx < 8) {
384 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
385 offset += idx * board->uart_offset + 0xC00;
386 } else /* we have only 8 ports on PMC-OCTALPRO */
387 return 1;
388
70db3d91 389 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 390}
391
392/*
393* This does initialization for PMC OCTALPRO cards:
394* maps the device memory, resets the UARTs (needed, bc
395* if the module is removed and inserted again, the card
396* is in the sleep mode) and enables global interrupt.
397*/
398
399/* global control register offset for SBS PMC-OctalPro */
400#define OCT_REG_CR_OFF 0x500
401
61a116ef 402static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 403{
404 u8 __iomem *p;
405
24ed3aba 406 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 407
408 if (p == NULL)
409 return -ENOMEM;
410 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 411 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 412 udelay(50);
5756ee99 413 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 414
415 /* Set bit-2 (INTENABLE) of Control Register */
416 writeb(0x4, p + OCT_REG_CR_OFF);
417 iounmap(p);
418
419 return 0;
420}
421
422/*
423 * Disables the global interrupt of PMC-OctalPro
424 */
425
ae8d8a14 426static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 427{
428 u8 __iomem *p;
429
24ed3aba 430 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 431 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
432 if (p != NULL)
1da177e4 433 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 434 iounmap(p);
435}
436
437/*
438 * SIIG serial cards have an PCI interface chip which also controls
439 * the UART clocking frequency. Each UART can be clocked independently
25985edc 440 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 441 * are stored in the EEPROM chip. It can cause problems because this
442 * version of serial driver doesn't support differently clocked UART's
443 * on single PCI card. To prevent this, initialization functions set
444 * high frequency clocking for all UART's on given card. It is safe (I
445 * hope) because it doesn't touch EEPROM settings to prevent conflicts
446 * with other OSes (like M$ DOS).
447 *
448 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 449 *
1da177e4
LT		 450 * There is two family of SIIG serial cards with different PCI
451 * interface chip and different configuration methods:
452 * - 10x cards have control registers in IO and/or memory space;
453 * - 20x cards have control registers in standard PCI configuration space.
454 *
67d74b87
RK		 455 * Note: all 10x cards have PCI device ids 0x10..
456 * all 20x cards have PCI device ids 0x20..
457 *
fbc0dc0d
AP		 458 * There are also Quartet Serial cards which use Oxford Semiconductor
459 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
460 *
1da177e4
LT		 461 * Note: some SIIG cards are probed by the parport_serial object.
462 */
463
464#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
465#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
466
467static int pci_siig10x_init(struct pci_dev *dev)
468{
469 u16 data;
470 void __iomem *p;
471
472 switch (dev->device & 0xfff8) {
473 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
474 data = 0xffdf;
475 break;
476 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
477 data = 0xf7ff;
478 break;
479 default: /* 1S1P, 4S */
480 data = 0xfffb;
481 break;
482 }
483
6f441fe9 484 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 485 if (p == NULL)
486 return -ENOMEM;
487
488 writew(readw(p + 0x28) & data, p + 0x28);
489 readw(p + 0x28);
490 iounmap(p);
491 return 0;
492}
493
494#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
495#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
496
497static int pci_siig20x_init(struct pci_dev *dev)
498{
499 u8 data;
500
501 /* Change clock frequency for the first UART. */
502 pci_read_config_byte(dev, 0x6f, &data);
503 pci_write_config_byte(dev, 0x6f, data & 0xef);
504
505 /* If this card has 2 UART, we have to do the same with second UART. */
506 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
507 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
508 pci_read_config_byte(dev, 0x73, &data);
509 pci_write_config_byte(dev, 0x73, data & 0xef);
510 }
511 return 0;
512}
513
67d74b87
RK		 514static int pci_siig_init(struct pci_dev *dev)
515{
516 unsigned int type = dev->device & 0xff00;
517
518 if (type == 0x1000)
519 return pci_siig10x_init(dev);
520 else if (type == 0x2000)
521 return pci_siig20x_init(dev);
522
523 moan_device("Unknown SIIG card", dev);
524 return -ENODEV;
525}
526
3ec9c594 527static int pci_siig_setup(struct serial_private *priv,
975a1a7d 528 const struct pciserial_board *board,
2655a2c7 529 struct uart_8250_port *port, int idx)
3ec9c594
AP		 530{
531 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
532
533 if (idx > 3) {
534 bar = 4;
535 offset = (idx - 4) * 8;
536 }
537
538 return setup_port(priv, port, bar, offset, 0);
539}
540
1da177e4
LT		 541/*
542 * Timedia has an explosion of boards, and to avoid the PCI table from
543 * growing *huge*, we use this function to collapse some 70 entries
544 * in the PCI table into one, for sanity's and compactness's sake.
545 */
e9422e09 546static const unsigned short timedia_single_port[] = {
1da177e4
LT		 547 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
548};
549
e9422e09 550static const unsigned short timedia_dual_port[] = {
1da177e4 551 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 552 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
553 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 554 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
555 0xD079, 0
556};
557
e9422e09 558static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 559 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
560 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 561 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
562 0xB157, 0
563};
564
e9422e09 565static const unsigned short timedia_eight_port[] = {
5756ee99 566 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 567 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
568};
569
cb3592be 570static const struct timedia_struct {
1da177e4 571 int num;
e9422e09 572 const unsigned short *ids;
1da177e4
LT		 573} timedia_data[] = {
574 { 1, timedia_single_port },
575 { 2, timedia_dual_port },
576 { 4, timedia_quad_port },
e9422e09 577 { 8, timedia_eight_port }
1da177e4
LT		 578};
579
b9b24558
FB		 580/*
581 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
582 * listing them individually, this driver merely grabs them all with
583 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
584 * and should be left free to be claimed by parport_serial instead.
585 */
586static int pci_timedia_probe(struct pci_dev *dev)
587{
588 /*
589 * Check the third digit of the subdevice ID
590 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
591 */
592 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
593 dev_info(&dev->dev,
594 "ignoring Timedia subdevice %04x for parport_serial\n",
595 dev->subsystem_device);
596 return -ENODEV;
597 }
598
599 return 0;
600}
601
61a116ef 602static int pci_timedia_init(struct pci_dev *dev)
1da177e4 603{
e9422e09 604 const unsigned short *ids;
1da177e4
LT		 605 int i, j;
606
e9422e09 607 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 608 ids = timedia_data[i].ids;
609 for (j = 0; ids[j]; j++)
610 if (dev->subsystem_device == ids[j])
611 return timedia_data[i].num;
612 }
613 return 0;
614}
615
616/*
617 * Timedia/SUNIX uses a mixture of BARs and offsets
618 * Ugh, this is ugly as all hell --- TYT
619 */
620static int
975a1a7d
RK		 621pci_timedia_setup(struct serial_private *priv,
622 const struct pciserial_board *board,
2655a2c7 623 struct uart_8250_port *port, int idx)
1da177e4
LT		 624{
625 unsigned int bar = 0, offset = board->first_offset;
626
627 switch (idx) {
628 case 0:
629 bar = 0;
630 break;
631 case 1:
632 offset = board->uart_offset;
633 bar = 0;
634 break;
635 case 2:
636 bar = 1;
637 break;
638 case 3:
639 offset = board->uart_offset;
c2cd6d3c 640 /* FALLTHROUGH */
1da177e4
LT		 641 case 4: /* BAR 2 */
642 case 5: /* BAR 3 */
643 case 6: /* BAR 4 */
644 case 7: /* BAR 5 */
645 bar = idx - 2;
646 }
647
70db3d91 648 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 649}
650
651/*
652 * Some Titan cards are also a little weird
653 */
654static int
70db3d91 655titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 656 const struct pciserial_board *board,
2655a2c7 657 struct uart_8250_port *port, int idx)
1da177e4
LT		 658{
659 unsigned int bar, offset = board->first_offset;
660
661 switch (idx) {
662 case 0:
663 bar = 1;
664 break;
665 case 1:
666 bar = 2;
667 break;
668 default:
669 bar = 4;
670 offset = (idx - 2) * board->uart_offset;
671 }
672
70db3d91 673 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 674}
675
61a116ef 676static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 677{
678 msleep(100);
679 return 0;
680}
681
04bf7e74
WP		 682static int pci_ni8420_init(struct pci_dev *dev)
683{
684 void __iomem *p;
685 unsigned long base, len;
686 unsigned int bar = 0;
687
688 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
689 moan_device("no memory in bar", dev);
690 return 0;
691 }
692
693 base = pci_resource_start(dev, bar);
694 len = pci_resource_len(dev, bar);
695 p = ioremap_nocache(base, len);
696 if (p == NULL)
697 return -ENOMEM;
698
699 /* Enable CPU Interrupt */
700 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
701 p + NI8420_INT_ENABLE_REG);
702
703 iounmap(p);
704 return 0;
705}
706
46a0fac9
SB		 707#define MITE_IOWBSR1_WSIZE 0xa
708#define MITE_IOWBSR1_WIN_OFFSET 0x800
709#define MITE_IOWBSR1_WENAB (1 << 7)
710#define MITE_LCIMR1_IO_IE_0 (1 << 24)
711#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
712#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
713
714static int pci_ni8430_init(struct pci_dev *dev)
715{
716 void __iomem *p;
717 unsigned long base, len;
718 u32 device_window;
719 unsigned int bar = 0;
720
721 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
722 moan_device("no memory in bar", dev);
723 return 0;
724 }
725
726 base = pci_resource_start(dev, bar);
727 len = pci_resource_len(dev, bar);
728 p = ioremap_nocache(base, len);
729 if (p == NULL)
730 return -ENOMEM;
731
732 /* Set device window address and size in BAR0 */
733 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
734 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
735 writel(device_window, p + MITE_IOWBSR1);
736
737 /* Set window access to go to RAMSEL IO address space */
738 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
739 p + MITE_IOWCR1);
740
741 /* Enable IO Bus Interrupt 0 */
742 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
743
744 /* Enable CPU Interrupt */
745 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
746
747 iounmap(p);
748 return 0;
749}
750
751/* UART Port Control Register */
752#define NI8430_PORTCON 0x0f
753#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
754
755static int
bf538fe4
AC		 756pci_ni8430_setup(struct serial_private *priv,
757 const struct pciserial_board *board,
2655a2c7 758 struct uart_8250_port *port, int idx)
46a0fac9
SB		 759{
760 void __iomem *p;
761 unsigned long base, len;
762 unsigned int bar, offset = board->first_offset;
763
764 if (idx >= board->num_ports)
765 return 1;
766
767 bar = FL_GET_BASE(board->flags);
768 offset += idx * board->uart_offset;
769
770 base = pci_resource_start(priv->dev, bar);
771 len = pci_resource_len(priv->dev, bar);
772 p = ioremap_nocache(base, len);
773
7c9d440e 774 /* enable the transceiver */
46a0fac9
SB		 775 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
776 p + offset + NI8430_PORTCON);
777
778 iounmap(p);
779
780 return setup_port(priv, port, bar, offset, board->reg_shift);
781}
782
7808edcd
NG		 783static int pci_netmos_9900_setup(struct serial_private *priv,
784 const struct pciserial_board *board,
2655a2c7 785 struct uart_8250_port *port, int idx)
7808edcd
NG		 786{
787 unsigned int bar;
788
333c085e
DES		 789 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
790 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
7808edcd
NG		 791 /* netmos apparently orders BARs by datasheet layout, so serial
792 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
793 */
794 bar = 3 * idx;
795
796 return setup_port(priv, port, bar, 0, board->reg_shift);
797 } else {
798 return pci_default_setup(priv, board, port, idx);
799 }
800}
801
802/* the 99xx series comes with a range of device IDs and a variety
803 * of capabilities:
804 *
805 * 9900 has varying capabilities and can cascade to sub-controllers
806 * (cascading should be purely internal)
807 * 9904 is hardwired with 4 serial ports
808 * 9912 and 9922 are hardwired with 2 serial ports
809 */
810static int pci_netmos_9900_numports(struct pci_dev *dev)
811{
812 unsigned int c = dev->class;
813 unsigned int pi;
814 unsigned short sub_serports;
815
816 pi = (c & 0xff);
817
818 if (pi == 2) {
819 return 1;
820 } else if ((pi == 0) &&
821 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
822 /* two possibilities: 0x30ps encodes number of parallel and
823 * serial ports, or 0x1000 indicates *something*. This is not
824 * immediately obvious, since the 2s1p+4s configuration seems
825 * to offer all functionality on functions 0..2, while still
826 * advertising the same function 3 as the 4s+2s1p config.
827 */
828 sub_serports = dev->subsystem_device & 0xf;
829 if (sub_serports > 0) {
830 return sub_serports;
831 } else {
af8c5b8d 832 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
7808edcd
NG		 833 return 0;
834 }
835 }
836
837 moan_device("unknown NetMos/Mostech program interface", dev);
838 return 0;
839}
46a0fac9 840
61a116ef 841static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 842{
843 /* subdevice 0x00PS means <P> parallel, <S> serial */
844 unsigned int num_serial = dev->subsystem_device & 0xf;
845
ac6ec5b1
IS		 846 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
847 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 848 return 0;
7808edcd 849
25cf9bc1
JS		 850 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
851 dev->subsystem_device == 0x0299)
852 return 0;
853
7808edcd
NG		 854 switch (dev->device) { /* FALLTHROUGH on all */
855 case PCI_DEVICE_ID_NETMOS_9904:
856 case PCI_DEVICE_ID_NETMOS_9912:
857 case PCI_DEVICE_ID_NETMOS_9922:
858 case PCI_DEVICE_ID_NETMOS_9900:
859 num_serial = pci_netmos_9900_numports(dev);
860 break;
861
862 default:
863 if (num_serial == 0 ) {
864 moan_device("unknown NetMos/Mostech device", dev);
865 }
866 }
867
1da177e4
LT		 868 if (num_serial == 0)
869 return -ENODEV;
7808edcd 870
1da177e4
LT		 871 return num_serial;
872}
873
84f8c6fc 874/*
84f8c6fc
NV		 875 * These chips are available with optionally one parallel port and up to
876 * two serial ports. Unfortunately they all have the same product id.
877 *
878 * Basic configuration is done over a region of 32 I/O ports. The base
879 * ioport is called INTA or INTC, depending on docs/other drivers.
880 *
881 * The region of the 32 I/O ports is configured in POSIO0R...
882 */
883
884/* registers */
885#define ITE_887x_MISCR 0x9c
886#define ITE_887x_INTCBAR 0x78
887#define ITE_887x_UARTBAR 0x7c
888#define ITE_887x_PS0BAR 0x10
889#define ITE_887x_POSIO0 0x60
890
891/* I/O space size */
892#define ITE_887x_IOSIZE 32
893/* I/O space size (bits 26-24; 8 bytes = 011b) */
894#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
895/* I/O space size (bits 26-24; 32 bytes = 101b) */
896#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
897/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
898#define ITE_887x_POSIO_SPEED (3 << 29)
899/* enable IO_Space bit */
900#define ITE_887x_POSIO_ENABLE (1 << 31)
901
f79abb82 902static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 903{
904 /* inta_addr are the configuration addresses of the ITE */
905 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
906 0x200, 0x280, 0 };
907 int ret, i, type;
908 struct resource *iobase = NULL;
909 u32 miscr, uartbar, ioport;
910
911 /* search for the base-ioport */
912 i = 0;
913 while (inta_addr[i] && iobase == NULL) {
914 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
915 "ite887x");
916 if (iobase != NULL) {
917 /* write POSIO0R - speed | size | ioport */
918 pci_write_config_dword(dev, ITE_887x_POSIO0,
919 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
920 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
921 /* write INTCBAR - ioport */
5756ee99
AC		 922 pci_write_config_dword(dev, ITE_887x_INTCBAR,
923 inta_addr[i]);
84f8c6fc
NV		 924 ret = inb(inta_addr[i]);
925 if (ret != 0xff) {
926 /* ioport connected */
927 break;
928 }
929 release_region(iobase->start, ITE_887x_IOSIZE);
930 iobase = NULL;
931 }
932 i++;
933 }
934
935 if (!inta_addr[i]) {
af8c5b8d 936 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 937 return -ENODEV;
938 }
939
940 /* start of undocumented type checking (see parport_pc.c) */
941 type = inb(iobase->start + 0x18) & 0x0f;
942
943 switch (type) {
944 case 0x2: /* ITE8871 (1P) */
945 case 0xa: /* ITE8875 (1P) */
946 ret = 0;
947 break;
948 case 0xe: /* ITE8872 (2S1P) */
949 ret = 2;
950 break;
951 case 0x6: /* ITE8873 (1S) */
952 ret = 1;
953 break;
954 case 0x8: /* ITE8874 (2S) */
955 ret = 2;
956 break;
957 default:
958 moan_device("Unknown ITE887x", dev);
959 ret = -ENODEV;
960 }
961
962 /* configure all serial ports */
963 for (i = 0; i < ret; i++) {
964 /* read the I/O port from the device */
965 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
966 &ioport);
967 ioport &= 0x0000FF00; /* the actual base address */
968 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
969 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
970 ITE_887x_POSIO_IOSIZE_8 | ioport);
971
972 /* write the ioport to the UARTBAR */
973 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
974 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
975 uartbar |= (ioport << (16 * i)); /* set the ioport */
976 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
977
978 /* get current config */
979 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
980 /* disable interrupts (UARTx_Routing[3:0]) */
981 miscr &= ~(0xf << (12 - 4 * i));
982 /* activate the UART (UARTx_En) */
983 miscr |= 1 << (23 - i);
984 /* write new config with activated UART */
985 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
986 }
987
988 if (ret <= 0) {
989 /* the device has no UARTs if we get here */
990 release_region(iobase->start, ITE_887x_IOSIZE);
991 }
992
993 return ret;
994}
995
ae8d8a14 996static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 997{
998 u32 ioport;
999 /* the ioport is bit 0-15 in POSIO0R */
1000 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1001 ioport &= 0xffff;
1002 release_region(ioport, ITE_887x_IOSIZE);
1003}
1004
9f2a036a
RK		 1005/*
1006 * Oxford Semiconductor Inc.
1007 * Check that device is part of the Tornado range of devices, then determine
1008 * the number of ports available on the device.
1009 */
1010static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1011{
1012 u8 __iomem *p;
1013 unsigned long deviceID;
1014 unsigned int number_uarts = 0;
1015
1016 /* OxSemi Tornado devices are all 0xCxxx */
1017 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1018 (dev->device & 0xF000) != 0xC000)
1019 return 0;
1020
1021 p = pci_iomap(dev, 0, 5);
1022 if (p == NULL)
1023 return -ENOMEM;
1024
1025 deviceID = ioread32(p);
1026 /* Tornado device */
1027 if (deviceID == 0x07000200) {
1028 number_uarts = ioread8(p + 4);
af8c5b8d 1029 dev_dbg(&dev->dev,
9f2a036a 1030 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1031 number_uarts);
9f2a036a
RK		 1032 }
1033 pci_iounmap(dev, p);
1034 return number_uarts;
1035}
1036
eb26dfe8
AC		 1037static int pci_asix_setup(struct serial_private *priv,
1038 const struct pciserial_board *board,
1039 struct uart_8250_port *port, int idx)
1040{
1041 port->bugs |= UART_BUG_PARITY;
1042 return pci_default_setup(priv, board, port, idx);
1043}
1044
55c7c0fd
AC		 1045/* Quatech devices have their own extra interface features */
1046
1047struct quatech_feature {
1048 u16 devid;
1049 bool amcc;
1050};
1051
1052#define QPCR_TEST_FOR1 0x3F
1053#define QPCR_TEST_GET1 0x00
1054#define QPCR_TEST_FOR2 0x40
1055#define QPCR_TEST_GET2 0x40
1056#define QPCR_TEST_FOR3 0x80
1057#define QPCR_TEST_GET3 0x40
1058#define QPCR_TEST_FOR4 0xC0
1059#define QPCR_TEST_GET4 0x80
1060
1061#define QOPR_CLOCK_X1 0x0000
1062#define QOPR_CLOCK_X2 0x0001
1063#define QOPR_CLOCK_X4 0x0002
1064#define QOPR_CLOCK_X8 0x0003
1065#define QOPR_CLOCK_RATE_MASK 0x0003
1066
1067
1068static struct quatech_feature quatech_cards[] = {
1069 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1070 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1071 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1072 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1073 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1074 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1075 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1076 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1077 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1078 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1079 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1080 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1083 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1084 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1085 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1086 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1087 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1088 { 0, }
1089};
1090
1091static int pci_quatech_amcc(u16 devid)
1092{
1093 struct quatech_feature *qf = &quatech_cards[0];
1094 while (qf->devid) {
1095 if (qf->devid == devid)
1096 return qf->amcc;
1097 qf++;
1098 }
1099 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1100 return 0;
1101};
1102
1103static int pci_quatech_rqopr(struct uart_8250_port *port)
1104{
1105 unsigned long base = port->port.iobase;
1106 u8 LCR, val;
1107
1108 LCR = inb(base + UART_LCR);
1109 outb(0xBF, base + UART_LCR);
1110 val = inb(base + UART_SCR);
1111 outb(LCR, base + UART_LCR);
1112 return val;
1113}
1114
1115static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1116{
1117 unsigned long base = port->port.iobase;
1118 u8 LCR, val;
1119
1120 LCR = inb(base + UART_LCR);
1121 outb(0xBF, base + UART_LCR);
1122 val = inb(base + UART_SCR);
1123 outb(qopr, base + UART_SCR);
1124 outb(LCR, base + UART_LCR);
1125}
1126
1127static int pci_quatech_rqmcr(struct uart_8250_port *port)
1128{
1129 unsigned long base = port->port.iobase;
1130 u8 LCR, val, qmcr;
1131
1132 LCR = inb(base + UART_LCR);
1133 outb(0xBF, base + UART_LCR);
1134 val = inb(base + UART_SCR);
1135 outb(val | 0x10, base + UART_SCR);
1136 qmcr = inb(base + UART_MCR);
1137 outb(val, base + UART_SCR);
1138 outb(LCR, base + UART_LCR);
1139
1140 return qmcr;
1141}
1142
1143static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1144{
1145 unsigned long base = port->port.iobase;
1146 u8 LCR, val;
1147
1148 LCR = inb(base + UART_LCR);
1149 outb(0xBF, base + UART_LCR);
1150 val = inb(base + UART_SCR);
1151 outb(val | 0x10, base + UART_SCR);
1152 outb(qmcr, base + UART_MCR);
1153 outb(val, base + UART_SCR);
1154 outb(LCR, base + UART_LCR);
1155}
1156
1157static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1158{
1159 unsigned long base = port->port.iobase;
1160 u8 LCR, val;
1161
1162 LCR = inb(base + UART_LCR);
1163 outb(0xBF, base + UART_LCR);
1164 val = inb(base + UART_SCR);
1165 if (val & 0x20) {
1166 outb(0x80, UART_LCR);
1167 if (!(inb(UART_SCR) & 0x20)) {
1168 outb(LCR, base + UART_LCR);
1169 return 1;
1170 }
1171 }
1172 return 0;
1173}
1174
1175static int pci_quatech_test(struct uart_8250_port *port)
1176{
1177 u8 reg;
1178 u8 qopr = pci_quatech_rqopr(port);
1179 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1180 reg = pci_quatech_rqopr(port) & 0xC0;
1181 if (reg != QPCR_TEST_GET1)
1182 return -EINVAL;
1183 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1184 reg = pci_quatech_rqopr(port) & 0xC0;
1185 if (reg != QPCR_TEST_GET2)
1186 return -EINVAL;
1187 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1188 reg = pci_quatech_rqopr(port) & 0xC0;
1189 if (reg != QPCR_TEST_GET3)
1190 return -EINVAL;
1191 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1192 reg = pci_quatech_rqopr(port) & 0xC0;
1193 if (reg != QPCR_TEST_GET4)
1194 return -EINVAL;
1195
1196 pci_quatech_wqopr(port, qopr);
1197 return 0;
1198}
1199
1200static int pci_quatech_clock(struct uart_8250_port *port)
1201{
1202 u8 qopr, reg, set;
1203 unsigned long clock;
1204
1205 if (pci_quatech_test(port) < 0)
1206 return 1843200;
1207
1208 qopr = pci_quatech_rqopr(port);
1209
1210 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1211 reg = pci_quatech_rqopr(port);
1212 if (reg & QOPR_CLOCK_X8) {
1213 clock = 1843200;
1214 goto out;
1215 }
1216 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1217 reg = pci_quatech_rqopr(port);
1218 if (!(reg & QOPR_CLOCK_X8)) {
1219 clock = 1843200;
1220 goto out;
1221 }
1222 reg &= QOPR_CLOCK_X8;
1223 if (reg == QOPR_CLOCK_X2) {
1224 clock = 3685400;
1225 set = QOPR_CLOCK_X2;
1226 } else if (reg == QOPR_CLOCK_X4) {
1227 clock = 7372800;
1228 set = QOPR_CLOCK_X4;
1229 } else if (reg == QOPR_CLOCK_X8) {
1230 clock = 14745600;
1231 set = QOPR_CLOCK_X8;
1232 } else {
1233 clock = 1843200;
1234 set = QOPR_CLOCK_X1;
1235 }
1236 qopr &= ~QOPR_CLOCK_RATE_MASK;
1237 qopr |= set;
1238
1239out:
1240 pci_quatech_wqopr(port, qopr);
1241 return clock;
1242}
1243
1244static int pci_quatech_rs422(struct uart_8250_port *port)
1245{
1246 u8 qmcr;
1247 int rs422 = 0;
1248
1249 if (!pci_quatech_has_qmcr(port))
1250 return 0;
1251 qmcr = pci_quatech_rqmcr(port);
1252 pci_quatech_wqmcr(port, 0xFF);
1253 if (pci_quatech_rqmcr(port))
1254 rs422 = 1;
1255 pci_quatech_wqmcr(port, qmcr);
1256 return rs422;
1257}
1258
1259static int pci_quatech_init(struct pci_dev *dev)
1260{
1261 if (pci_quatech_amcc(dev->device)) {
1262 unsigned long base = pci_resource_start(dev, 0);
1263 if (base) {
1264 u32 tmp;
9c5320f8 1265 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1266 tmp = inl(base + 0x3c);
1267 outl(tmp | 0x01000000, base + 0x3c);
9c5320f8 1268 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1269 }
1270 }
1271 return 0;
1272}
1273
1274static int pci_quatech_setup(struct serial_private *priv,
1275 const struct pciserial_board *board,
1276 struct uart_8250_port *port, int idx)
1277{
1278 /* Needed by pci_quatech calls below */
1279 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1280 /* Set up the clocking */
1281 port->port.uartclk = pci_quatech_clock(port);
1282 /* For now just warn about RS422 */
1283 if (pci_quatech_rs422(port))
1284 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1285 return pci_default_setup(priv, board, port, idx);
1286}
1287
d73dfc6a 1288static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1289{
1290}
1291
eb26dfe8 1292static int pci_default_setup(struct serial_private *priv,
975a1a7d 1293 const struct pciserial_board *board,
2655a2c7 1294 struct uart_8250_port *port, int idx)
1da177e4
LT		 1295{
1296 unsigned int bar, offset = board->first_offset, maxnr;
1297
1298 bar = FL_GET_BASE(board->flags);
1299 if (board->flags & FL_BASE_BARS)
1300 bar += idx;
1301 else
1302 offset += idx * board->uart_offset;
1303
2427ddd8
GKH		 1304 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1305 (board->reg_shift + 3);
1da177e4
LT		 1306
1307 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1308 return 1;
5756ee99 1309
70db3d91 1310 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1311}
1312
94341475
AB		 1313static int pci_pericom_setup(struct serial_private *priv,
1314 const struct pciserial_board *board,
1315 struct uart_8250_port *port, int idx)
1316{
1317 unsigned int bar, offset = board->first_offset, maxnr;
1318
1319 bar = FL_GET_BASE(board->flags);
1320 if (board->flags & FL_BASE_BARS)
1321 bar += idx;
1322 else
1323 offset += idx * board->uart_offset;
1324
1325 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1326 (board->reg_shift + 3);
1327
1328 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1329 return 1;
1330
1331 port->port.uartclk = 14745600;
1332
1333 return setup_port(priv, port, bar, offset, board->reg_shift);
1334}
1335
095e24b0
DB		 1336static int
1337ce4100_serial_setup(struct serial_private *priv,
1338 const struct pciserial_board *board,
2655a2c7 1339 struct uart_8250_port *port, int idx)
095e24b0
DB		 1340{
1341 int ret;
1342
08ec212c 1343 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1344 port->port.iotype = UPIO_MEM32;
1345 port->port.type = PORT_XSCALE;
1346 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1347 port->port.regshift = 2;
095e24b0
DB		 1348
1349 return ret;
1350}
1351
b15e5691
HK		 1352#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1353#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1354
1355#define BYT_PRV_CLK 0x800
1356#define BYT_PRV_CLK_EN (1 << 0)
1357#define BYT_PRV_CLK_M_VAL_SHIFT 1
1358#define BYT_PRV_CLK_N_VAL_SHIFT 16
1359#define BYT_PRV_CLK_UPDATE (1 << 31)
1360
1361#define BYT_GENERAL_REG 0x808
1362#define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3)
1363
1364#define BYT_TX_OVF_INT 0x820
1365#define BYT_TX_OVF_INT_MASK (1 << 1)
1366
1367static void
1368byt_set_termios(struct uart_port *p, struct ktermios *termios,
1369 struct ktermios *old)
1370{
1371 unsigned int baud = tty_termios_baud_rate(termios);
50825c57 1372 unsigned int m, n;
b15e5691
HK		 1373 u32 reg;
1374
50825c57
AS		 1375 /*
1376 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1377 * dividers must be adjusted.
1378 *
1379 * uartclk = (m / n) * 100 MHz, where m <= n
1380 */
1381 switch (baud) {
1382 case 500000:
1383 case 1000000:
1384 case 2000000:
1385 case 4000000:
b15e5691
HK		 1386 m = 64;
1387 n = 100;
b15e5691 1388 p->uartclk = 64000000;
50825c57
AS		 1389 break;
1390 case 3500000:
1391 m = 56;
1392 n = 100;
1393 p->uartclk = 56000000;
1394 break;
1395 case 1500000:
1396 case 3000000:
b15e5691
HK		 1397 m = 48;
1398 n = 100;
b15e5691 1399 p->uartclk = 48000000;
50825c57
AS		 1400 break;
1401 case 2500000:
1402 m = 40;
1403 n = 100;
1404 p->uartclk = 40000000;
1405 break;
1406 default:
41d3f099
AS		 1407 m = 2304;
1408 n = 3125;
1409 p->uartclk = 73728000;
b15e5691
HK		 1410 }
1411
1412 /* Reset the clock */
1413 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1414 writel(reg, p->membase + BYT_PRV_CLK);
1415 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1416 writel(reg, p->membase + BYT_PRV_CLK);
1417
1418 /*
1419 * If auto-handshake mechanism is not enabled,
1420 * disable rts_n override
1421 */
1422 reg = readl(p->membase + BYT_GENERAL_REG);
1423 reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1424 if (termios->c_cflag & CRTSCTS)
1425 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1426 writel(reg, p->membase + BYT_GENERAL_REG);
1427
1428 serial8250_do_set_termios(p, termios, old);
1429}
1430
1431static bool byt_dma_filter(struct dma_chan *chan, void *param)
1432{
9a1870ce
AS		 1433 struct dw_dma_slave *dws = param;
1434
1435 if (dws->dma_dev != chan->device->dev)
1436 return false;
1437
1438 chan->private = dws;
1439 return true;
b15e5691
HK		 1440}
1441
1442static int
1443byt_serial_setup(struct serial_private *priv,
1444 const struct pciserial_board *board,
1445 struct uart_8250_port *port, int idx)
1446{
9a1870ce
AS		 1447 struct pci_dev *pdev = priv->dev;
1448 struct device *dev = port->port.dev;
b15e5691 1449 struct uart_8250_dma *dma;
9a1870ce
AS		 1450 struct dw_dma_slave *tx_param, *rx_param;
1451 struct pci_dev *dma_dev;
b15e5691
HK		 1452 int ret;
1453
9a1870ce 1454 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
b15e5691
HK		 1455 if (!dma)
1456 return -ENOMEM;
1457
9a1870ce
AS		 1458 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1459 if (!tx_param)
1460 return -ENOMEM;
1461
1462 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1463 if (!rx_param)
1464 return -ENOMEM;
1465
1466 switch (pdev->device) {
b15e5691 1467 case PCI_DEVICE_ID_INTEL_BYT_UART1:
9a1870ce
AS		 1468 rx_param->src_id = 3;
1469 tx_param->dst_id = 2;
b15e5691
HK		 1470 break;
1471 case PCI_DEVICE_ID_INTEL_BYT_UART2:
9a1870ce
AS		 1472 rx_param->src_id = 5;
1473 tx_param->dst_id = 4;
b15e5691
HK		 1474 break;
1475 default:
1476 return -EINVAL;
1477 }
1478
9a1870ce
AS		 1479 rx_param->src_master = 1;
1480 rx_param->dst_master = 0;
1481
b15e5691
HK		 1482 dma->rxconf.src_maxburst = 16;
1483
9a1870ce
AS		 1484 tx_param->src_master = 1;
1485 tx_param->dst_master = 0;
1486
b15e5691
HK		 1487 dma->txconf.dst_maxburst = 16;
1488
9a1870ce
AS		 1489 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1490 rx_param->dma_dev = &dma_dev->dev;
1491 tx_param->dma_dev = &dma_dev->dev;
1492
b15e5691 1493 dma->fn = byt_dma_filter;
9a1870ce
AS		 1494 dma->rx_param = rx_param;
1495 dma->tx_param = tx_param;
b15e5691
HK		 1496
1497 ret = pci_default_setup(priv, board, port, idx);
1498 port->port.iotype = UPIO_MEM;
1499 port->port.type = PORT_16550A;
1500 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1501 port->port.set_termios = byt_set_termios;
1502 port->port.fifosize = 64;
1503 port->tx_loadsz = 64;
1504 port->dma = dma;
1505 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1506
1507 /* Disable Tx counter interrupts */
1508 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1509
1510 return ret;
1511}
1512
d9a0fbfd
AP		 1513static int
1514pci_omegapci_setup(struct serial_private *priv,
1798ca13 1515 const struct pciserial_board *board,
2655a2c7 1516 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1517{
1518 return setup_port(priv, port, 2, idx * 8, 0);
1519}
1520
ebebd49a
SH		 1521static int
1522pci_brcm_trumanage_setup(struct serial_private *priv,
1523 const struct pciserial_board *board,
1524 struct uart_8250_port *port, int idx)
1525{
1526 int ret = pci_default_setup(priv, board, port, idx);
1527
1528 port->port.type = PORT_BRCM_TRUMANAGE;
1529 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1530 return ret;
1531}
1532
2c62a3c8
GKH		 1533static int pci_fintek_setup(struct serial_private *priv,
1534 const struct pciserial_board *board,
1535 struct uart_8250_port *port, int idx)
1536{
1537 struct pci_dev *pdev = priv->dev;
1538 unsigned long base;
1539 unsigned long iobase;
1540 unsigned long ciobase = 0;
1541 u8 config_base;
1542
1543 /*
1544 * We are supposed to be able to read these from the PCI config space,
1545 * but the values there don't seem to match what we need to use, so
1546 * just use these hard-coded values for now, as they are correct.
1547 */
1548 switch (idx) {
1549 case 0: iobase = 0xe000; config_base = 0x40; break;
1550 case 1: iobase = 0xe008; config_base = 0x48; break;
1551 case 2: iobase = 0xe010; config_base = 0x50; break;
1552 case 3: iobase = 0xe018; config_base = 0x58; break;
1553 case 4: iobase = 0xe020; config_base = 0x60; break;
1554 case 5: iobase = 0xe028; config_base = 0x68; break;
1555 case 6: iobase = 0xe030; config_base = 0x70; break;
1556 case 7: iobase = 0xe038; config_base = 0x78; break;
1557 case 8: iobase = 0xe040; config_base = 0x80; break;
1558 case 9: iobase = 0xe048; config_base = 0x88; break;
1559 case 10: iobase = 0xe050; config_base = 0x90; break;
1560 case 11: iobase = 0xe058; config_base = 0x98; break;
1561 default:
1562 /* Unknown number of ports, get out of here */
1563 return -EINVAL;
1564 }
1565
1566 if (idx < 4) {
1567 base = pci_resource_start(priv->dev, 3);
1568 ciobase = (int)(base + (0x8 * idx));
1569 }
1570
1571 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1572 __func__, idx, iobase, ciobase, config_base);
1573
1574 /* Enable UART I/O port */
1575 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1576
1577 /* Select 128-byte FIFO and 8x FIFO threshold */
1578 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1579
1580 /* LSB UART */
1581 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1582
1583 /* MSB UART */
1584 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1585
1586 /* irq number, this usually fails, but the spec says to do it anyway. */
1587 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1588
1589 port->port.iotype = UPIO_PORT;
1590 port->port.iobase = iobase;
1591 port->port.mapbase = 0;
1592 port->port.membase = NULL;
1593 port->port.regshift = 0;
1594
1595 return 0;
1596}
1597
b6adea33
MCC		 1598static int skip_tx_en_setup(struct serial_private *priv,
1599 const struct pciserial_board *board,
2655a2c7 1600 struct uart_8250_port *port, int idx)
b6adea33 1601{
2655a2c7 1602 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1603 dev_dbg(&priv->dev->dev,
1604 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1605 priv->dev->vendor, priv->dev->device,
1606 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1607
1608 return pci_default_setup(priv, board, port, idx);
1609}
1610
0ad372b9
SM		 1611static void kt_handle_break(struct uart_port *p)
1612{
b1261c86 1613 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1614 /*
1615 * On receipt of a BI, serial device in Intel ME (Intel
1616 * management engine) needs to have its fifos cleared for sane
1617 * SOL (Serial Over Lan) output.
1618 */
1619 serial8250_clear_and_reinit_fifos(up);
1620}
1621
1622static unsigned int kt_serial_in(struct uart_port *p, int offset)
1623{
b1261c86 1624 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1625 unsigned int val;
1626
1627 /*
1628 * When the Intel ME (management engine) gets reset its serial
1629 * port registers could return 0 momentarily. Functions like
1630 * serial8250_console_write, read and save the IER, perform
1631 * some operation and then restore it. In order to avoid
1632 * setting IER register inadvertently to 0, if the value read
1633 * is 0, double check with ier value in uart_8250_port and use
1634 * that instead. up->ier should be the same value as what is
1635 * currently configured.
1636 */
1637 val = inb(p->iobase + offset);
1638 if (offset == UART_IER) {
1639 if (val == 0)
1640 val = up->ier;
1641 }
1642 return val;
1643}
1644
bc02d15a
DW		 1645static int kt_serial_setup(struct serial_private *priv,
1646 const struct pciserial_board *board,
2655a2c7 1647 struct uart_8250_port *port, int idx)
bc02d15a 1648{
2655a2c7
AC		 1649 port->port.flags |= UPF_BUG_THRE;
1650 port->port.serial_in = kt_serial_in;
1651 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1652 return skip_tx_en_setup(priv, board, port, idx);
1653}
1654
eb7073db
TM		 1655static int pci_eg20t_init(struct pci_dev *dev)
1656{
1657#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1658 return -ENODEV;
1659#else
1660 return 0;
1661#endif
1662}
1663
06315348
SH		 1664static int
1665pci_xr17c154_setup(struct serial_private *priv,
1666 const struct pciserial_board *board,
2655a2c7 1667 struct uart_8250_port *port, int idx)
06315348 1668{
2655a2c7 1669 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1670 return pci_default_setup(priv, board, port, idx);
1671}
1672
dc96efb7
MS		 1673static int
1674pci_xr17v35x_setup(struct serial_private *priv,
1675 const struct pciserial_board *board,
1676 struct uart_8250_port *port, int idx)
1677{
1678 u8 __iomem *p;
1679
1680 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1681 if (p == NULL)
1682 return -ENOMEM;
dc96efb7
MS		 1683
1684 port->port.flags |= UPF_EXAR_EFR;
1685
1686 /*
1687 * Setup Multipurpose Input/Output pins.
1688 */
1689 if (idx == 0) {
1690 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1691 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1692 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1693 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1694 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1695 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1696 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1697 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1698 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1699 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1700 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1701 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1702 }
f965b9c4
MS		 1703 writeb(0x00, p + UART_EXAR_8XMODE);
1704 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1705 writeb(128, p + UART_EXAR_TXTRG);
1706 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1707 iounmap(p);
1708
1709 return pci_default_setup(priv, board, port, idx);
1710}
1711
14faa8cc
MS		 1712#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1713#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1714#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1715#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1716
1717static int
1718pci_fastcom335_setup(struct serial_private *priv,
1719 const struct pciserial_board *board,
1720 struct uart_8250_port *port, int idx)
1721{
1722 u8 __iomem *p;
1723
1724 p = pci_ioremap_bar(priv->dev, 0);
1725 if (p == NULL)
1726 return -ENOMEM;
1727
1728 port->port.flags |= UPF_EXAR_EFR;
1729
1730 /*
1731 * Setup Multipurpose Input/Output pins.
1732 */
1733 if (idx == 0) {
1734 switch (priv->dev->device) {
1735 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1736 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1737 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1738 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1739 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1740 break;
1741 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1742 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1743 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1744 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1745 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1746 break;
1747 }
1748 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1749 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1750 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1751 }
1752 writeb(0x00, p + UART_EXAR_8XMODE);
1753 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1754 writeb(32, p + UART_EXAR_TXTRG);
1755 writeb(32, p + UART_EXAR_RXTRG);
1756 iounmap(p);
1757
1758 return pci_default_setup(priv, board, port, idx);
1759}
1760
6971c635
GA		 1761static int
1762pci_wch_ch353_setup(struct serial_private *priv,
1763 const struct pciserial_board *board,
1764 struct uart_8250_port *port, int idx)
1765{
1766 port->port.flags |= UPF_FIXED_TYPE;
1767 port->port.type = PORT_16550A;
06315348
SH		 1768 return pci_default_setup(priv, board, port, idx);
1769}
1770
1da177e4
LT		 1771#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1772#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1773#define PCI_DEVICE_ID_OCTPRO 0x0001
1774#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1775#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1776#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1777#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1778#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1779#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1780#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1781#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1782#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
0c6d774c
TW		 1783#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1784#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
66169ad1
YY		 1785#define PCI_DEVICE_ID_TITAN_200I 0x8028
1786#define PCI_DEVICE_ID_TITAN_400I 0x8048
1787#define PCI_DEVICE_ID_TITAN_800I 0x8088
1788#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1789#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1790#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1791#define PCI_DEVICE_ID_TITAN_100E 0xA010
1792#define PCI_DEVICE_ID_TITAN_200E 0xA012
1793#define PCI_DEVICE_ID_TITAN_400E 0xA013
1794#define PCI_DEVICE_ID_TITAN_800E 0xA014
1795#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1796#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
48c0247d 1797#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 1798#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1799#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1800#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1801#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1802#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1803#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1804#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1805#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1806#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1807#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1808#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1809#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
feb58142 1810#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
27788c5f 1811#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 1812#define PCI_VENDOR_ID_AGESTAR 0x5372
1813#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1814#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 1815#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1816#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 1817#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 1818#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 1819#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
14faa8cc 1820
abd7baca
SC		 1821#define PCI_VENDOR_ID_SUNIX 0x1fd4
1822#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1823
1da177e4 1824
b76c5a07
CB		 1825/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1826#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 1827#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 1828
1da177e4
LT		 1829/*
1830 * Master list of serial port init/setup/exit quirks.
1831 * This does not describe the general nature of the port.
1832 * (ie, baud base, number and location of ports, etc)
1833 *
1834 * This list is ordered alphabetically by vendor then device.
1835 * Specific entries must come before more generic entries.
1836 */
7a63ce5a 1837static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1838 /*
1839 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1840 */
1841 {
086231f7 1842 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 1843 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 1844 .subvendor = PCI_ANY_ID,
1845 .subdevice = PCI_ANY_ID,
1846 .setup = addidata_apci7800_setup,
1847 },
1da177e4 1848 /*
61a116ef 1849 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1850 * It is not clear whether this applies to all products.
1851 */
1852 {
1853 .vendor = PCI_VENDOR_ID_AFAVLAB,
1854 .device = PCI_ANY_ID,
1855 .subvendor = PCI_ANY_ID,
1856 .subdevice = PCI_ANY_ID,
1857 .setup = afavlab_setup,
1858 },
1859 /*
1860 * HP Diva
1861 */
1862 {
1863 .vendor = PCI_VENDOR_ID_HP,
1864 .device = PCI_DEVICE_ID_HP_DIVA,
1865 .subvendor = PCI_ANY_ID,
1866 .subdevice = PCI_ANY_ID,
1867 .init = pci_hp_diva_init,
1868 .setup = pci_hp_diva_setup,
1869 },
1870 /*
1871 * Intel
1872 */
1873 {
1874 .vendor = PCI_VENDOR_ID_INTEL,
1875 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1876 .subvendor = 0xe4bf,
1877 .subdevice = PCI_ANY_ID,
1878 .init = pci_inteli960ni_init,
1879 .setup = pci_default_setup,
1880 },
b6adea33
MCC		 1881 {
1882 .vendor = PCI_VENDOR_ID_INTEL,
1883 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1884 .subvendor = PCI_ANY_ID,
1885 .subdevice = PCI_ANY_ID,
1886 .setup = skip_tx_en_setup,
1887 },
1888 {
1889 .vendor = PCI_VENDOR_ID_INTEL,
1890 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1891 .subvendor = PCI_ANY_ID,
1892 .subdevice = PCI_ANY_ID,
1893 .setup = skip_tx_en_setup,
1894 },
1895 {
1896 .vendor = PCI_VENDOR_ID_INTEL,
1897 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1898 .subvendor = PCI_ANY_ID,
1899 .subdevice = PCI_ANY_ID,
1900 .setup = skip_tx_en_setup,
1901 },
095e24b0
DB		 1902 {
1903 .vendor = PCI_VENDOR_ID_INTEL,
1904 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1905 .subvendor = PCI_ANY_ID,
1906 .subdevice = PCI_ANY_ID,
1907 .setup = ce4100_serial_setup,
1908 },
bc02d15a
DW		 1909 {
1910 .vendor = PCI_VENDOR_ID_INTEL,
1911 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1912 .subvendor = PCI_ANY_ID,
1913 .subdevice = PCI_ANY_ID,
1914 .setup = kt_serial_setup,
1915 },
b15e5691
HK		 1916 {
1917 .vendor = PCI_VENDOR_ID_INTEL,
1918 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1919 .subvendor = PCI_ANY_ID,
1920 .subdevice = PCI_ANY_ID,
1921 .setup = byt_serial_setup,
1922 },
1923 {
1924 .vendor = PCI_VENDOR_ID_INTEL,
1925 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1926 .subvendor = PCI_ANY_ID,
1927 .subdevice = PCI_ANY_ID,
1928 .setup = byt_serial_setup,
1929 },
84f8c6fc
NV		 1930 /*
1931 * ITE
1932 */
1933 {
1934 .vendor = PCI_VENDOR_ID_ITE,
1935 .device = PCI_DEVICE_ID_ITE_8872,
1936 .subvendor = PCI_ANY_ID,
1937 .subdevice = PCI_ANY_ID,
1938 .init = pci_ite887x_init,
1939 .setup = pci_default_setup,
2d47b716 1940 .exit = pci_ite887x_exit,
84f8c6fc 1941 },
46a0fac9
SB		 1942 /*
1943 * National Instruments
1944 */
04bf7e74
WP		 1945 {
1946 .vendor = PCI_VENDOR_ID_NI,
1947 .device = PCI_DEVICE_ID_NI_PCI23216,
1948 .subvendor = PCI_ANY_ID,
1949 .subdevice = PCI_ANY_ID,
1950 .init = pci_ni8420_init,
1951 .setup = pci_default_setup,
2d47b716 1952 .exit = pci_ni8420_exit,
04bf7e74
WP		 1953 },
1954 {
1955 .vendor = PCI_VENDOR_ID_NI,
1956 .device = PCI_DEVICE_ID_NI_PCI2328,
1957 .subvendor = PCI_ANY_ID,
1958 .subdevice = PCI_ANY_ID,
1959 .init = pci_ni8420_init,
1960 .setup = pci_default_setup,
2d47b716 1961 .exit = pci_ni8420_exit,
04bf7e74
WP		 1962 },
1963 {
1964 .vendor = PCI_VENDOR_ID_NI,
1965 .device = PCI_DEVICE_ID_NI_PCI2324,
1966 .subvendor = PCI_ANY_ID,
1967 .subdevice = PCI_ANY_ID,
1968 .init = pci_ni8420_init,
1969 .setup = pci_default_setup,
2d47b716 1970 .exit = pci_ni8420_exit,
04bf7e74
WP		 1971 },
1972 {
1973 .vendor = PCI_VENDOR_ID_NI,
1974 .device = PCI_DEVICE_ID_NI_PCI2322,
1975 .subvendor = PCI_ANY_ID,
1976 .subdevice = PCI_ANY_ID,
1977 .init = pci_ni8420_init,
1978 .setup = pci_default_setup,
2d47b716 1979 .exit = pci_ni8420_exit,
04bf7e74
WP		 1980 },
1981 {
1982 .vendor = PCI_VENDOR_ID_NI,
1983 .device = PCI_DEVICE_ID_NI_PCI2324I,
1984 .subvendor = PCI_ANY_ID,
1985 .subdevice = PCI_ANY_ID,
1986 .init = pci_ni8420_init,
1987 .setup = pci_default_setup,
2d47b716 1988 .exit = pci_ni8420_exit,
04bf7e74
WP		 1989 },
1990 {
1991 .vendor = PCI_VENDOR_ID_NI,
1992 .device = PCI_DEVICE_ID_NI_PCI2322I,
1993 .subvendor = PCI_ANY_ID,
1994 .subdevice = PCI_ANY_ID,
1995 .init = pci_ni8420_init,
1996 .setup = pci_default_setup,
2d47b716 1997 .exit = pci_ni8420_exit,
04bf7e74
WP		 1998 },
1999 {
2000 .vendor = PCI_VENDOR_ID_NI,
2001 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2002 .subvendor = PCI_ANY_ID,
2003 .subdevice = PCI_ANY_ID,
2004 .init = pci_ni8420_init,
2005 .setup = pci_default_setup,
2d47b716 2006 .exit = pci_ni8420_exit,
04bf7e74
WP		 2007 },
2008 {
2009 .vendor = PCI_VENDOR_ID_NI,
2010 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2011 .subvendor = PCI_ANY_ID,
2012 .subdevice = PCI_ANY_ID,
2013 .init = pci_ni8420_init,
2014 .setup = pci_default_setup,
2d47b716 2015 .exit = pci_ni8420_exit,
04bf7e74
WP		 2016 },
2017 {
2018 .vendor = PCI_VENDOR_ID_NI,
2019 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2020 .subvendor = PCI_ANY_ID,
2021 .subdevice = PCI_ANY_ID,
2022 .init = pci_ni8420_init,
2023 .setup = pci_default_setup,
2d47b716 2024 .exit = pci_ni8420_exit,
04bf7e74
WP		 2025 },
2026 {
2027 .vendor = PCI_VENDOR_ID_NI,
2028 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2029 .subvendor = PCI_ANY_ID,
2030 .subdevice = PCI_ANY_ID,
2031 .init = pci_ni8420_init,
2032 .setup = pci_default_setup,
2d47b716 2033 .exit = pci_ni8420_exit,
04bf7e74
WP		 2034 },
2035 {
2036 .vendor = PCI_VENDOR_ID_NI,
2037 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2038 .subvendor = PCI_ANY_ID,
2039 .subdevice = PCI_ANY_ID,
2040 .init = pci_ni8420_init,
2041 .setup = pci_default_setup,
2d47b716 2042 .exit = pci_ni8420_exit,
04bf7e74
WP		 2043 },
2044 {
2045 .vendor = PCI_VENDOR_ID_NI,
2046 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2047 .subvendor = PCI_ANY_ID,
2048 .subdevice = PCI_ANY_ID,
2049 .init = pci_ni8420_init,
2050 .setup = pci_default_setup,
2d47b716 2051 .exit = pci_ni8420_exit,
04bf7e74 2052 },
46a0fac9
SB		 2053 {
2054 .vendor = PCI_VENDOR_ID_NI,
2055 .device = PCI_ANY_ID,
2056 .subvendor = PCI_ANY_ID,
2057 .subdevice = PCI_ANY_ID,
2058 .init = pci_ni8430_init,
2059 .setup = pci_ni8430_setup,
2d47b716 2060 .exit = pci_ni8430_exit,
46a0fac9 2061 },
55c7c0fd
AC		 2062 /* Quatech */
2063 {
2064 .vendor = PCI_VENDOR_ID_QUATECH,
2065 .device = PCI_ANY_ID,
2066 .subvendor = PCI_ANY_ID,
2067 .subdevice = PCI_ANY_ID,
2068 .init = pci_quatech_init,
2069 .setup = pci_quatech_setup,
d73dfc6a 2070 .exit = pci_quatech_exit,
55c7c0fd 2071 },
1da177e4
LT		 2072 /*
2073 * Panacom
2074 */
2075 {
2076 .vendor = PCI_VENDOR_ID_PANACOM,
2077 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2078 .subvendor = PCI_ANY_ID,
2079 .subdevice = PCI_ANY_ID,
2080 .init = pci_plx9050_init,
2081 .setup = pci_default_setup,
2d47b716 2082 .exit = pci_plx9050_exit,
5756ee99 2083 },
1da177e4
LT		 2084 {
2085 .vendor = PCI_VENDOR_ID_PANACOM,
2086 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2087 .subvendor = PCI_ANY_ID,
2088 .subdevice = PCI_ANY_ID,
2089 .init = pci_plx9050_init,
2090 .setup = pci_default_setup,
2d47b716 2091 .exit = pci_plx9050_exit,
1da177e4 2092 },
94341475
AB		 2093 /*
2094 * Pericom
2095 */
2096 {
2097 .vendor = 0x12d8,
2098 .device = 0x7952,
2099 .subvendor = PCI_ANY_ID,
2100 .subdevice = PCI_ANY_ID,
2101 .setup = pci_pericom_setup,
2102 },
2103 {
2104 .vendor = 0x12d8,
2105 .device = 0x7954,
2106 .subvendor = PCI_ANY_ID,
2107 .subdevice = PCI_ANY_ID,
2108 .setup = pci_pericom_setup,
2109 },
2110 {
2111 .vendor = 0x12d8,
2112 .device = 0x7958,
2113 .subvendor = PCI_ANY_ID,
2114 .subdevice = PCI_ANY_ID,
2115 .setup = pci_pericom_setup,
2116 },
2117
1da177e4
LT		 2118 /*
2119 * PLX
2120 */
48212008
TH		 2121 {
2122 .vendor = PCI_VENDOR_ID_PLX,
2123 .device = PCI_DEVICE_ID_PLX_9030,
2124 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2125 .subdevice = PCI_ANY_ID,
2126 .setup = pci_default_setup,
2127 },
add7b58e
BH		 2128 {
2129 .vendor = PCI_VENDOR_ID_PLX,
2130 .device = PCI_DEVICE_ID_PLX_9050,
2131 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2132 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2133 .init = pci_plx9050_init,
2134 .setup = pci_default_setup,
2d47b716 2135 .exit = pci_plx9050_exit,
add7b58e 2136 },
1da177e4
LT		 2137 {
2138 .vendor = PCI_VENDOR_ID_PLX,
2139 .device = PCI_DEVICE_ID_PLX_9050,
2140 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2141 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2142 .init = pci_plx9050_init,
2143 .setup = pci_default_setup,
2d47b716 2144 .exit = pci_plx9050_exit,
1da177e4
LT		 2145 },
2146 {
2147 .vendor = PCI_VENDOR_ID_PLX,
2148 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2149 .subvendor = PCI_VENDOR_ID_PLX,
2150 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2151 .init = pci_plx9050_init,
2152 .setup = pci_default_setup,
2d47b716 2153 .exit = pci_plx9050_exit,
1da177e4
LT		 2154 },
2155 /*
2156 * SBS Technologies, Inc., PMC-OCTALPRO 232
2157 */
2158 {
2159 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2160 .device = PCI_DEVICE_ID_OCTPRO,
2161 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2162 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2163 .init = sbs_init,
2164 .setup = sbs_setup,
2d47b716 2165 .exit = sbs_exit,
1da177e4
LT		 2166 },
2167 /*
2168 * SBS Technologies, Inc., PMC-OCTALPRO 422
2169 */
2170 {
2171 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2172 .device = PCI_DEVICE_ID_OCTPRO,
2173 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2174 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2175 .init = sbs_init,
2176 .setup = sbs_setup,
2d47b716 2177 .exit = sbs_exit,
1da177e4
LT		 2178 },
2179 /*
2180 * SBS Technologies, Inc., P-Octal 232
2181 */
2182 {
2183 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2184 .device = PCI_DEVICE_ID_OCTPRO,
2185 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2186 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2187 .init = sbs_init,
2188 .setup = sbs_setup,
2d47b716 2189 .exit = sbs_exit,
1da177e4
LT		 2190 },
2191 /*
2192 * SBS Technologies, Inc., P-Octal 422
2193 */
2194 {
2195 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2196 .device = PCI_DEVICE_ID_OCTPRO,
2197 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2198 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2199 .init = sbs_init,
2200 .setup = sbs_setup,
2d47b716 2201 .exit = sbs_exit,
1da177e4 2202 },
1da177e4 2203 /*
61a116ef 2204 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2205 */
2206 {
2207 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2208 .device = PCI_ANY_ID,
1da177e4
LT		 2209 .subvendor = PCI_ANY_ID,
2210 .subdevice = PCI_ANY_ID,
67d74b87 2211 .init = pci_siig_init,
3ec9c594 2212 .setup = pci_siig_setup,
1da177e4
LT		 2213 },
2214 /*
2215 * Titan cards
2216 */
2217 {
2218 .vendor = PCI_VENDOR_ID_TITAN,
2219 .device = PCI_DEVICE_ID_TITAN_400L,
2220 .subvendor = PCI_ANY_ID,
2221 .subdevice = PCI_ANY_ID,
2222 .setup = titan_400l_800l_setup,
2223 },
2224 {
2225 .vendor = PCI_VENDOR_ID_TITAN,
2226 .device = PCI_DEVICE_ID_TITAN_800L,
2227 .subvendor = PCI_ANY_ID,
2228 .subdevice = PCI_ANY_ID,
2229 .setup = titan_400l_800l_setup,
2230 },
2231 /*
2232 * Timedia cards
2233 */
2234 {
2235 .vendor = PCI_VENDOR_ID_TIMEDIA,
2236 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2237 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2238 .subdevice = PCI_ANY_ID,
b9b24558 2239 .probe = pci_timedia_probe,
1da177e4
LT		 2240 .init = pci_timedia_init,
2241 .setup = pci_timedia_setup,
2242 },
2243 {
2244 .vendor = PCI_VENDOR_ID_TIMEDIA,
2245 .device = PCI_ANY_ID,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .setup = pci_timedia_setup,
2249 },
abd7baca
SC		 2250 /*
2251 * SUNIX (Timedia) cards
2252 * Do not "probe" for these cards as there is at least one combination
2253 * card that should be handled by parport_pc that doesn't match the
2254 * rule in pci_timedia_probe.
2255 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2256 * There are some boards with part number SER5037AL that report
2257 * subdevice ID 0x0002.
2258 */
2259 {
2260 .vendor = PCI_VENDOR_ID_SUNIX,
2261 .device = PCI_DEVICE_ID_SUNIX_1999,
2262 .subvendor = PCI_VENDOR_ID_SUNIX,
2263 .subdevice = PCI_ANY_ID,
2264 .init = pci_timedia_init,
2265 .setup = pci_timedia_setup,
2266 },
06315348
SH		 2267 /*
2268 * Exar cards
2269 */
2270 {
2271 .vendor = PCI_VENDOR_ID_EXAR,
2272 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2273 .subvendor = PCI_ANY_ID,
2274 .subdevice = PCI_ANY_ID,
2275 .setup = pci_xr17c154_setup,
2276 },
2277 {
2278 .vendor = PCI_VENDOR_ID_EXAR,
2279 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2280 .subvendor = PCI_ANY_ID,
2281 .subdevice = PCI_ANY_ID,
2282 .setup = pci_xr17c154_setup,
2283 },
2284 {
2285 .vendor = PCI_VENDOR_ID_EXAR,
2286 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2287 .subvendor = PCI_ANY_ID,
2288 .subdevice = PCI_ANY_ID,
2289 .setup = pci_xr17c154_setup,
2290 },
dc96efb7
MS		 2291 {
2292 .vendor = PCI_VENDOR_ID_EXAR,
2293 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2294 .subvendor = PCI_ANY_ID,
2295 .subdevice = PCI_ANY_ID,
2296 .setup = pci_xr17v35x_setup,
2297 },
2298 {
2299 .vendor = PCI_VENDOR_ID_EXAR,
2300 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2301 .subvendor = PCI_ANY_ID,
2302 .subdevice = PCI_ANY_ID,
2303 .setup = pci_xr17v35x_setup,
2304 },
2305 {
2306 .vendor = PCI_VENDOR_ID_EXAR,
2307 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2308 .subvendor = PCI_ANY_ID,
2309 .subdevice = PCI_ANY_ID,
2310 .setup = pci_xr17v35x_setup,
2311 },
1da177e4
LT		 2312 /*
2313 * Xircom cards
2314 */
2315 {
2316 .vendor = PCI_VENDOR_ID_XIRCOM,
2317 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2318 .subvendor = PCI_ANY_ID,
2319 .subdevice = PCI_ANY_ID,
2320 .init = pci_xircom_init,
2321 .setup = pci_default_setup,
2322 },
2323 /*
61a116ef 2324 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2325 */
2326 {
2327 .vendor = PCI_VENDOR_ID_NETMOS,
2328 .device = PCI_ANY_ID,
2329 .subvendor = PCI_ANY_ID,
2330 .subdevice = PCI_ANY_ID,
2331 .init = pci_netmos_init,
7808edcd 2332 .setup = pci_netmos_9900_setup,
1da177e4 2333 },
9f2a036a 2334 /*
aa273ae5 2335 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2336 */
2337 {
2338 .vendor = PCI_VENDOR_ID_OXSEMI,
2339 .device = PCI_ANY_ID,
2340 .subvendor = PCI_ANY_ID,
2341 .subdevice = PCI_ANY_ID,
2342 .init = pci_oxsemi_tornado_init,
2343 .setup = pci_default_setup,
2344 },
2345 {
2346 .vendor = PCI_VENDOR_ID_MAINPINE,
2347 .device = PCI_ANY_ID,
2348 .subvendor = PCI_ANY_ID,
2349 .subdevice = PCI_ANY_ID,
2350 .init = pci_oxsemi_tornado_init,
2351 .setup = pci_default_setup,
2352 },
aa273ae5
SK		 2353 {
2354 .vendor = PCI_VENDOR_ID_DIGI,
2355 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2356 .subvendor = PCI_SUBVENDOR_ID_IBM,
2357 .subdevice = PCI_ANY_ID,
2358 .init = pci_oxsemi_tornado_init,
2359 .setup = pci_default_setup,
2360 },
eb7073db
TM		 2361 {
2362 .vendor = PCI_VENDOR_ID_INTEL,
2363 .device = 0x8811,
aaa10eb1
AP		 2364 .subvendor = PCI_ANY_ID,
2365 .subdevice = PCI_ANY_ID,
eb7073db 2366 .init = pci_eg20t_init,
64d91cfa 2367 .setup = pci_default_setup,
eb7073db
TM		 2368 },
2369 {
2370 .vendor = PCI_VENDOR_ID_INTEL,
2371 .device = 0x8812,
aaa10eb1
AP		 2372 .subvendor = PCI_ANY_ID,
2373 .subdevice = PCI_ANY_ID,
eb7073db 2374 .init = pci_eg20t_init,
64d91cfa 2375 .setup = pci_default_setup,
eb7073db
TM		 2376 },
2377 {
2378 .vendor = PCI_VENDOR_ID_INTEL,
2379 .device = 0x8813,
aaa10eb1
AP		 2380 .subvendor = PCI_ANY_ID,
2381 .subdevice = PCI_ANY_ID,
eb7073db 2382 .init = pci_eg20t_init,
64d91cfa 2383 .setup = pci_default_setup,
eb7073db
TM		 2384 },
2385 {
2386 .vendor = PCI_VENDOR_ID_INTEL,
2387 .device = 0x8814,
aaa10eb1
AP		 2388 .subvendor = PCI_ANY_ID,
2389 .subdevice = PCI_ANY_ID,
eb7073db 2390 .init = pci_eg20t_init,
64d91cfa 2391 .setup = pci_default_setup,
eb7073db
TM		 2392 },
2393 {
2394 .vendor = 0x10DB,
2395 .device = 0x8027,
aaa10eb1
AP		 2396 .subvendor = PCI_ANY_ID,
2397 .subdevice = PCI_ANY_ID,
eb7073db 2398 .init = pci_eg20t_init,
64d91cfa 2399 .setup = pci_default_setup,
eb7073db
TM		 2400 },
2401 {
2402 .vendor = 0x10DB,
2403 .device = 0x8028,
aaa10eb1
AP		 2404 .subvendor = PCI_ANY_ID,
2405 .subdevice = PCI_ANY_ID,
eb7073db 2406 .init = pci_eg20t_init,
64d91cfa 2407 .setup = pci_default_setup,
eb7073db
TM		 2408 },
2409 {
2410 .vendor = 0x10DB,
2411 .device = 0x8029,
aaa10eb1
AP		 2412 .subvendor = PCI_ANY_ID,
2413 .subdevice = PCI_ANY_ID,
eb7073db 2414 .init = pci_eg20t_init,
64d91cfa 2415 .setup = pci_default_setup,
eb7073db
TM		 2416 },
2417 {
2418 .vendor = 0x10DB,
2419 .device = 0x800C,
aaa10eb1
AP		 2420 .subvendor = PCI_ANY_ID,
2421 .subdevice = PCI_ANY_ID,
eb7073db 2422 .init = pci_eg20t_init,
64d91cfa 2423 .setup = pci_default_setup,
eb7073db
TM		 2424 },
2425 {
2426 .vendor = 0x10DB,
2427 .device = 0x800D,
aaa10eb1
AP		 2428 .subvendor = PCI_ANY_ID,
2429 .subdevice = PCI_ANY_ID,
eb7073db 2430 .init = pci_eg20t_init,
64d91cfa 2431 .setup = pci_default_setup,
eb7073db 2432 },
d9a0fbfd
AP		 2433 /*
2434 * Cronyx Omega PCI (PLX-chip based)
2435 */
2436 {
2437 .vendor = PCI_VENDOR_ID_PLX,
2438 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2439 .subvendor = PCI_ANY_ID,
2440 .subdevice = PCI_ANY_ID,
2441 .setup = pci_omegapci_setup,
eb26dfe8 2442 },
feb58142
EG		 2443 /* WCH CH353 1S1P card (16550 clone) */
2444 {
2445 .vendor = PCI_VENDOR_ID_WCH,
2446 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2447 .subvendor = PCI_ANY_ID,
2448 .subdevice = PCI_ANY_ID,
2449 .setup = pci_wch_ch353_setup,
2450 },
6971c635
GA		 2451 /* WCH CH353 2S1P card (16550 clone) */
2452 {
27788c5f
AC		 2453 .vendor = PCI_VENDOR_ID_WCH,
2454 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2455 .subvendor = PCI_ANY_ID,
2456 .subdevice = PCI_ANY_ID,
2457 .setup = pci_wch_ch353_setup,
2458 },
2459 /* WCH CH353 4S card (16550 clone) */
2460 {
2461 .vendor = PCI_VENDOR_ID_WCH,
2462 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2463 .subvendor = PCI_ANY_ID,
2464 .subdevice = PCI_ANY_ID,
2465 .setup = pci_wch_ch353_setup,
2466 },
2467 /* WCH CH353 2S1PF card (16550 clone) */
2468 {
2469 .vendor = PCI_VENDOR_ID_WCH,
2470 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2471 .subvendor = PCI_ANY_ID,
2472 .subdevice = PCI_ANY_ID,
6971c635
GA		 2473 .setup = pci_wch_ch353_setup,
2474 },
8b5c913f
WY		 2475 /* WCH CH352 2S card (16550 clone) */
2476 {
2477 .vendor = PCI_VENDOR_ID_WCH,
2478 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2479 .subvendor = PCI_ANY_ID,
2480 .subdevice = PCI_ANY_ID,
2481 .setup = pci_wch_ch353_setup,
2482 },
eb26dfe8
AC		 2483 /*
2484 * ASIX devices with FIFO bug
2485 */
2486 {
2487 .vendor = PCI_VENDOR_ID_ASIX,
2488 .device = PCI_ANY_ID,
2489 .subvendor = PCI_ANY_ID,
2490 .subdevice = PCI_ANY_ID,
2491 .setup = pci_asix_setup,
2492 },
14faa8cc
MS		 2493 /*
2494 * Commtech, Inc. Fastcom adapters
2495 *
2496 */
2497 {
2498 .vendor = PCI_VENDOR_ID_COMMTECH,
2499 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2500 .subvendor = PCI_ANY_ID,
2501 .subdevice = PCI_ANY_ID,
2502 .setup = pci_fastcom335_setup,
2503 },
2504 {
2505 .vendor = PCI_VENDOR_ID_COMMTECH,
2506 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2507 .subvendor = PCI_ANY_ID,
2508 .subdevice = PCI_ANY_ID,
2509 .setup = pci_fastcom335_setup,
2510 },
2511 {
2512 .vendor = PCI_VENDOR_ID_COMMTECH,
2513 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2514 .subvendor = PCI_ANY_ID,
2515 .subdevice = PCI_ANY_ID,
2516 .setup = pci_fastcom335_setup,
2517 },
2518 {
2519 .vendor = PCI_VENDOR_ID_COMMTECH,
2520 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2521 .subvendor = PCI_ANY_ID,
2522 .subdevice = PCI_ANY_ID,
2523 .setup = pci_fastcom335_setup,
2524 },
2525 {
2526 .vendor = PCI_VENDOR_ID_COMMTECH,
2527 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2528 .subvendor = PCI_ANY_ID,
2529 .subdevice = PCI_ANY_ID,
2530 .setup = pci_xr17v35x_setup,
2531 },
2532 {
2533 .vendor = PCI_VENDOR_ID_COMMTECH,
2534 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2535 .subvendor = PCI_ANY_ID,
2536 .subdevice = PCI_ANY_ID,
2537 .setup = pci_xr17v35x_setup,
2538 },
2539 {
2540 .vendor = PCI_VENDOR_ID_COMMTECH,
2541 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2542 .subvendor = PCI_ANY_ID,
2543 .subdevice = PCI_ANY_ID,
2544 .setup = pci_xr17v35x_setup,
2545 },
ebebd49a
SH		 2546 /*
2547 * Broadcom TruManage (NetXtreme)
2548 */
2549 {
2550 .vendor = PCI_VENDOR_ID_BROADCOM,
2551 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2552 .subvendor = PCI_ANY_ID,
2553 .subdevice = PCI_ANY_ID,
2554 .setup = pci_brcm_trumanage_setup,
2555 },
2c62a3c8
GKH		 2556 {
2557 .vendor = 0x1c29,
2558 .device = 0x1104,
2559 .subvendor = PCI_ANY_ID,
2560 .subdevice = PCI_ANY_ID,
2561 .setup = pci_fintek_setup,
2562 },
2563 {
2564 .vendor = 0x1c29,
2565 .device = 0x1108,
2566 .subvendor = PCI_ANY_ID,
2567 .subdevice = PCI_ANY_ID,
2568 .setup = pci_fintek_setup,
2569 },
2570 {
2571 .vendor = 0x1c29,
2572 .device = 0x1112,
2573 .subvendor = PCI_ANY_ID,
2574 .subdevice = PCI_ANY_ID,
2575 .setup = pci_fintek_setup,
2576 },
ebebd49a 2577
1da177e4
LT		 2578 /*
2579 * Default "match everything" terminator entry
2580 */
2581 {
2582 .vendor = PCI_ANY_ID,
2583 .device = PCI_ANY_ID,
2584 .subvendor = PCI_ANY_ID,
2585 .subdevice = PCI_ANY_ID,
2586 .setup = pci_default_setup,
2587 }
2588};
2589
2590static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2591{
2592 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2593}
2594
2595static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2596{
2597 struct pci_serial_quirk *quirk;
2598
2599 for (quirk = pci_serial_quirks; ; quirk++)
2600 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2601 quirk_id_matches(quirk->device, dev->device) &&
2602 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2603 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2604 break;
1da177e4
LT		 2605 return quirk;
2606}
2607
dd68e88c 2608static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2609 const struct pciserial_board *board)
1da177e4
LT		 2610{
2611 if (board->flags & FL_NOIRQ)
2612 return 0;
2613 else
2614 return dev->irq;
2615}
2616
2617/*
2618 * This is the configuration table for all of the PCI serial boards
2619 * which we support. It is directly indexed by the pci_board_num_t enum
2620 * value, which is encoded in the pci_device_id PCI probe table's
2621 * driver_data member.
2622 *
2623 * The makeup of these names are:
26e92861 2624 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2625 *
26e92861
GH		 2626 * bn = PCI BAR number
2627 * bt = Index using PCI BARs
2628 * n = number of serial ports
2629 * baud = baud rate
2630 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2631 *
26e92861 2632 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2633 *
1da177e4
LT		 2634 * Please note: in theory if n = 1, _bt infix should make no difference.
2635 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2636 */
2637enum pci_board_num_t {
2638 pbn_default = 0,
2639
2640 pbn_b0_1_115200,
2641 pbn_b0_2_115200,
2642 pbn_b0_4_115200,
2643 pbn_b0_5_115200,
bf0df636 2644 pbn_b0_8_115200,
1da177e4
LT		 2645
2646 pbn_b0_1_921600,
2647 pbn_b0_2_921600,
2648 pbn_b0_4_921600,
2649
db1de159
DR		 2650 pbn_b0_2_1130000,
2651
fbc0dc0d
AP		 2652 pbn_b0_4_1152000,
2653
14faa8cc
MS		 2654 pbn_b0_2_1152000_200,
2655 pbn_b0_4_1152000_200,
2656 pbn_b0_8_1152000_200,
2657
26e92861
GH		 2658 pbn_b0_2_1843200,
2659 pbn_b0_4_1843200,
2660
2661 pbn_b0_2_1843200_200,
2662 pbn_b0_4_1843200_200,
2663 pbn_b0_8_1843200_200,
2664
7106b4e3
LH		 2665 pbn_b0_1_4000000,
2666
1da177e4
LT		 2667 pbn_b0_bt_1_115200,
2668 pbn_b0_bt_2_115200,
ac6ec5b1 2669 pbn_b0_bt_4_115200,
1da177e4
LT		 2670 pbn_b0_bt_8_115200,
2671
2672 pbn_b0_bt_1_460800,
2673 pbn_b0_bt_2_460800,
2674 pbn_b0_bt_4_460800,
2675
2676 pbn_b0_bt_1_921600,
2677 pbn_b0_bt_2_921600,
2678 pbn_b0_bt_4_921600,
2679 pbn_b0_bt_8_921600,
2680
2681 pbn_b1_1_115200,
2682 pbn_b1_2_115200,
2683 pbn_b1_4_115200,
2684 pbn_b1_8_115200,
04bf7e74 2685 pbn_b1_16_115200,
1da177e4
LT		 2686
2687 pbn_b1_1_921600,
2688 pbn_b1_2_921600,
2689 pbn_b1_4_921600,
2690 pbn_b1_8_921600,
2691
26e92861
GH		 2692 pbn_b1_2_1250000,
2693
84f8c6fc 2694 pbn_b1_bt_1_115200,
04bf7e74
WP		 2695 pbn_b1_bt_2_115200,
2696 pbn_b1_bt_4_115200,
2697
1da177e4
LT		 2698 pbn_b1_bt_2_921600,
2699
2700 pbn_b1_1_1382400,
2701 pbn_b1_2_1382400,
2702 pbn_b1_4_1382400,
2703 pbn_b1_8_1382400,
2704
2705 pbn_b2_1_115200,
737c1756 2706 pbn_b2_2_115200,
a9cccd34 2707 pbn_b2_4_115200,
1da177e4
LT		 2708 pbn_b2_8_115200,
2709
2710 pbn_b2_1_460800,
2711 pbn_b2_4_460800,
2712 pbn_b2_8_460800,
2713 pbn_b2_16_460800,
2714
2715 pbn_b2_1_921600,
2716 pbn_b2_4_921600,
2717 pbn_b2_8_921600,
2718
e847003f
LB		 2719 pbn_b2_8_1152000,
2720
1da177e4
LT		 2721 pbn_b2_bt_1_115200,
2722 pbn_b2_bt_2_115200,
2723 pbn_b2_bt_4_115200,
2724
2725 pbn_b2_bt_2_921600,
2726 pbn_b2_bt_4_921600,
2727
d9004eb4 2728 pbn_b3_2_115200,
1da177e4
LT		 2729 pbn_b3_4_115200,
2730 pbn_b3_8_115200,
2731
66169ad1
YY		 2732 pbn_b4_bt_2_921600,
2733 pbn_b4_bt_4_921600,
2734 pbn_b4_bt_8_921600,
2735
1da177e4
LT		 2736 /*
2737 * Board-specific versions.
2738 */
2739 pbn_panacom,
2740 pbn_panacom2,
2741 pbn_panacom4,
2742 pbn_plx_romulus,
2743 pbn_oxsemi,
7106b4e3
LH		 2744 pbn_oxsemi_1_4000000,
2745 pbn_oxsemi_2_4000000,
2746 pbn_oxsemi_4_4000000,
2747 pbn_oxsemi_8_4000000,
1da177e4
LT		 2748 pbn_intel_i960,
2749 pbn_sgi_ioc3,
1da177e4
LT		 2750 pbn_computone_4,
2751 pbn_computone_6,
2752 pbn_computone_8,
2753 pbn_sbsxrsio,
2754 pbn_exar_XR17C152,
2755 pbn_exar_XR17C154,
2756 pbn_exar_XR17C158,
dc96efb7
MS		 2757 pbn_exar_XR17V352,
2758 pbn_exar_XR17V354,
2759 pbn_exar_XR17V358,
c68d2b15 2760 pbn_exar_ibm_saturn,
aa798505 2761 pbn_pasemi_1682M,
46a0fac9
SB		 2762 pbn_ni8430_2,
2763 pbn_ni8430_4,
2764 pbn_ni8430_8,
2765 pbn_ni8430_16,
1b62cbf2
KJ		 2766 pbn_ADDIDATA_PCIe_1_3906250,
2767 pbn_ADDIDATA_PCIe_2_3906250,
2768 pbn_ADDIDATA_PCIe_4_3906250,
2769 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2770 pbn_ce4100_1_115200,
b15e5691 2771 pbn_byt,
d9a0fbfd 2772 pbn_omegapci,
7808edcd 2773 pbn_NETMOS9900_2s_115200,
ebebd49a 2774 pbn_brcm_trumanage,
2c62a3c8
GKH		 2775 pbn_fintek_4,
2776 pbn_fintek_8,
2777 pbn_fintek_12,
1da177e4
LT		 2778};
2779
2780/*
2781 * uart_offset - the space between channels
2782 * reg_shift - describes how the UART registers are mapped
2783 * to PCI memory by the card.
2784 * For example IER register on SBS, Inc. PMC-OctPro is located at
2785 * offset 0x10 from the UART base, while UART_IER is defined as 1
2786 * in include/linux/serial_reg.h,
2787 * see first lines of serial_in() and serial_out() in 8250.c
2788*/
2789
de88b340 2790static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2791 [pbn_default] = {
2792 .flags = FL_BASE0,
2793 .num_ports = 1,
2794 .base_baud = 115200,
2795 .uart_offset = 8,
2796 },
2797 [pbn_b0_1_115200] = {
2798 .flags = FL_BASE0,
2799 .num_ports = 1,
2800 .base_baud = 115200,
2801 .uart_offset = 8,
2802 },
2803 [pbn_b0_2_115200] = {
2804 .flags = FL_BASE0,
2805 .num_ports = 2,
2806 .base_baud = 115200,
2807 .uart_offset = 8,
2808 },
2809 [pbn_b0_4_115200] = {
2810 .flags = FL_BASE0,
2811 .num_ports = 4,
2812 .base_baud = 115200,
2813 .uart_offset = 8,
2814 },
2815 [pbn_b0_5_115200] = {
2816 .flags = FL_BASE0,
2817 .num_ports = 5,
2818 .base_baud = 115200,
2819 .uart_offset = 8,
2820 },
bf0df636
AC		 2821 [pbn_b0_8_115200] = {
2822 .flags = FL_BASE0,
2823 .num_ports = 8,
2824 .base_baud = 115200,
2825 .uart_offset = 8,
2826 },
1da177e4
LT		 2827 [pbn_b0_1_921600] = {
2828 .flags = FL_BASE0,
2829 .num_ports = 1,
2830 .base_baud = 921600,
2831 .uart_offset = 8,
2832 },
2833 [pbn_b0_2_921600] = {
2834 .flags = FL_BASE0,
2835 .num_ports = 2,
2836 .base_baud = 921600,
2837 .uart_offset = 8,
2838 },
2839 [pbn_b0_4_921600] = {
2840 .flags = FL_BASE0,
2841 .num_ports = 4,
2842 .base_baud = 921600,
2843 .uart_offset = 8,
2844 },
db1de159
DR		 2845
2846 [pbn_b0_2_1130000] = {
2847 .flags = FL_BASE0,
2848 .num_ports = 2,
2849 .base_baud = 1130000,
2850 .uart_offset = 8,
2851 },
2852
fbc0dc0d
AP		 2853 [pbn_b0_4_1152000] = {
2854 .flags = FL_BASE0,
2855 .num_ports = 4,
2856 .base_baud = 1152000,
2857 .uart_offset = 8,
2858 },
1da177e4 2859
14faa8cc
MS		 2860 [pbn_b0_2_1152000_200] = {
2861 .flags = FL_BASE0,
2862 .num_ports = 2,
2863 .base_baud = 1152000,
2864 .uart_offset = 0x200,
2865 },
2866
2867 [pbn_b0_4_1152000_200] = {
2868 .flags = FL_BASE0,
2869 .num_ports = 4,
2870 .base_baud = 1152000,
2871 .uart_offset = 0x200,
2872 },
2873
2874 [pbn_b0_8_1152000_200] = {
2875 .flags = FL_BASE0,
4f7d67d0 2876 .num_ports = 8,
14faa8cc
MS		 2877 .base_baud = 1152000,
2878 .uart_offset = 0x200,
2879 },
2880
26e92861
GH		 2881 [pbn_b0_2_1843200] = {
2882 .flags = FL_BASE0,
2883 .num_ports = 2,
2884 .base_baud = 1843200,
2885 .uart_offset = 8,
2886 },
2887 [pbn_b0_4_1843200] = {
2888 .flags = FL_BASE0,
2889 .num_ports = 4,
2890 .base_baud = 1843200,
2891 .uart_offset = 8,
2892 },
2893
2894 [pbn_b0_2_1843200_200] = {
2895 .flags = FL_BASE0,
2896 .num_ports = 2,
2897 .base_baud = 1843200,
2898 .uart_offset = 0x200,
2899 },
2900 [pbn_b0_4_1843200_200] = {
2901 .flags = FL_BASE0,
2902 .num_ports = 4,
2903 .base_baud = 1843200,
2904 .uart_offset = 0x200,
2905 },
2906 [pbn_b0_8_1843200_200] = {
2907 .flags = FL_BASE0,
2908 .num_ports = 8,
2909 .base_baud = 1843200,
2910 .uart_offset = 0x200,
2911 },
7106b4e3
LH		 2912 [pbn_b0_1_4000000] = {
2913 .flags = FL_BASE0,
2914 .num_ports = 1,
2915 .base_baud = 4000000,
2916 .uart_offset = 8,
2917 },
26e92861 2918
1da177e4
LT		 2919 [pbn_b0_bt_1_115200] = {
2920 .flags = FL_BASE0|FL_BASE_BARS,
2921 .num_ports = 1,
2922 .base_baud = 115200,
2923 .uart_offset = 8,
2924 },
2925 [pbn_b0_bt_2_115200] = {
2926 .flags = FL_BASE0|FL_BASE_BARS,
2927 .num_ports = 2,
2928 .base_baud = 115200,
2929 .uart_offset = 8,
2930 },
ac6ec5b1
IS		 2931 [pbn_b0_bt_4_115200] = {
2932 .flags = FL_BASE0|FL_BASE_BARS,
2933 .num_ports = 4,
2934 .base_baud = 115200,
2935 .uart_offset = 8,
2936 },
1da177e4
LT		 2937 [pbn_b0_bt_8_115200] = {
2938 .flags = FL_BASE0|FL_BASE_BARS,
2939 .num_ports = 8,
2940 .base_baud = 115200,
2941 .uart_offset = 8,
2942 },
2943
2944 [pbn_b0_bt_1_460800] = {
2945 .flags = FL_BASE0|FL_BASE_BARS,
2946 .num_ports = 1,
2947 .base_baud = 460800,
2948 .uart_offset = 8,
2949 },
2950 [pbn_b0_bt_2_460800] = {
2951 .flags = FL_BASE0|FL_BASE_BARS,
2952 .num_ports = 2,
2953 .base_baud = 460800,
2954 .uart_offset = 8,
2955 },
2956 [pbn_b0_bt_4_460800] = {
2957 .flags = FL_BASE0|FL_BASE_BARS,
2958 .num_ports = 4,
2959 .base_baud = 460800,
2960 .uart_offset = 8,
2961 },
2962
2963 [pbn_b0_bt_1_921600] = {
2964 .flags = FL_BASE0|FL_BASE_BARS,
2965 .num_ports = 1,
2966 .base_baud = 921600,
2967 .uart_offset = 8,
2968 },
2969 [pbn_b0_bt_2_921600] = {
2970 .flags = FL_BASE0|FL_BASE_BARS,
2971 .num_ports = 2,
2972 .base_baud = 921600,
2973 .uart_offset = 8,
2974 },
2975 [pbn_b0_bt_4_921600] = {
2976 .flags = FL_BASE0|FL_BASE_BARS,
2977 .num_ports = 4,
2978 .base_baud = 921600,
2979 .uart_offset = 8,
2980 },
2981 [pbn_b0_bt_8_921600] = {
2982 .flags = FL_BASE0|FL_BASE_BARS,
2983 .num_ports = 8,
2984 .base_baud = 921600,
2985 .uart_offset = 8,
2986 },
2987
2988 [pbn_b1_1_115200] = {
2989 .flags = FL_BASE1,
2990 .num_ports = 1,
2991 .base_baud = 115200,
2992 .uart_offset = 8,
2993 },
2994 [pbn_b1_2_115200] = {
2995 .flags = FL_BASE1,
2996 .num_ports = 2,
2997 .base_baud = 115200,
2998 .uart_offset = 8,
2999 },
3000 [pbn_b1_4_115200] = {
3001 .flags = FL_BASE1,
3002 .num_ports = 4,
3003 .base_baud = 115200,
3004 .uart_offset = 8,
3005 },
3006 [pbn_b1_8_115200] = {
3007 .flags = FL_BASE1,
3008 .num_ports = 8,
3009 .base_baud = 115200,
3010 .uart_offset = 8,
3011 },
04bf7e74
WP		 3012 [pbn_b1_16_115200] = {
3013 .flags = FL_BASE1,
3014 .num_ports = 16,
3015 .base_baud = 115200,
3016 .uart_offset = 8,
3017 },
1da177e4
LT		 3018
3019 [pbn_b1_1_921600] = {
3020 .flags = FL_BASE1,
3021 .num_ports = 1,
3022 .base_baud = 921600,
3023 .uart_offset = 8,
3024 },
3025 [pbn_b1_2_921600] = {
3026 .flags = FL_BASE1,
3027 .num_ports = 2,
3028 .base_baud = 921600,
3029 .uart_offset = 8,
3030 },
3031 [pbn_b1_4_921600] = {
3032 .flags = FL_BASE1,
3033 .num_ports = 4,
3034 .base_baud = 921600,
3035 .uart_offset = 8,
3036 },
3037 [pbn_b1_8_921600] = {
3038 .flags = FL_BASE1,
3039 .num_ports = 8,
3040 .base_baud = 921600,
3041 .uart_offset = 8,
3042 },
26e92861
GH		 3043 [pbn_b1_2_1250000] = {
3044 .flags = FL_BASE1,
3045 .num_ports = 2,
3046 .base_baud = 1250000,
3047 .uart_offset = 8,
3048 },
1da177e4 3049
84f8c6fc
NV		 3050 [pbn_b1_bt_1_115200] = {
3051 .flags = FL_BASE1|FL_BASE_BARS,
3052 .num_ports = 1,
3053 .base_baud = 115200,
3054 .uart_offset = 8,
3055 },
04bf7e74
WP		 3056 [pbn_b1_bt_2_115200] = {
3057 .flags = FL_BASE1|FL_BASE_BARS,
3058 .num_ports = 2,
3059 .base_baud = 115200,
3060 .uart_offset = 8,
3061 },
3062 [pbn_b1_bt_4_115200] = {
3063 .flags = FL_BASE1|FL_BASE_BARS,
3064 .num_ports = 4,
3065 .base_baud = 115200,
3066 .uart_offset = 8,
3067 },
84f8c6fc 3068
1da177e4
LT		 3069 [pbn_b1_bt_2_921600] = {
3070 .flags = FL_BASE1|FL_BASE_BARS,
3071 .num_ports = 2,
3072 .base_baud = 921600,
3073 .uart_offset = 8,
3074 },
3075
3076 [pbn_b1_1_1382400] = {
3077 .flags = FL_BASE1,
3078 .num_ports = 1,
3079 .base_baud = 1382400,
3080 .uart_offset = 8,
3081 },
3082 [pbn_b1_2_1382400] = {
3083 .flags = FL_BASE1,
3084 .num_ports = 2,
3085 .base_baud = 1382400,
3086 .uart_offset = 8,
3087 },
3088 [pbn_b1_4_1382400] = {
3089 .flags = FL_BASE1,
3090 .num_ports = 4,
3091 .base_baud = 1382400,
3092 .uart_offset = 8,
3093 },
3094 [pbn_b1_8_1382400] = {
3095 .flags = FL_BASE1,
3096 .num_ports = 8,
3097 .base_baud = 1382400,
3098 .uart_offset = 8,
3099 },
3100
3101 [pbn_b2_1_115200] = {
3102 .flags = FL_BASE2,
3103 .num_ports = 1,
3104 .base_baud = 115200,
3105 .uart_offset = 8,
3106 },
737c1756
PH		 3107 [pbn_b2_2_115200] = {
3108 .flags = FL_BASE2,
3109 .num_ports = 2,
3110 .base_baud = 115200,
3111 .uart_offset = 8,
3112 },
a9cccd34
MF		 3113 [pbn_b2_4_115200] = {
3114 .flags = FL_BASE2,
3115 .num_ports = 4,
3116 .base_baud = 115200,
3117 .uart_offset = 8,
3118 },
1da177e4
LT		 3119 [pbn_b2_8_115200] = {
3120 .flags = FL_BASE2,
3121 .num_ports = 8,
3122 .base_baud = 115200,
3123 .uart_offset = 8,
3124 },
3125
3126 [pbn_b2_1_460800] = {
3127 .flags = FL_BASE2,
3128 .num_ports = 1,
3129 .base_baud = 460800,
3130 .uart_offset = 8,
3131 },
3132 [pbn_b2_4_460800] = {
3133 .flags = FL_BASE2,
3134 .num_ports = 4,
3135 .base_baud = 460800,
3136 .uart_offset = 8,
3137 },
3138 [pbn_b2_8_460800] = {
3139 .flags = FL_BASE2,
3140 .num_ports = 8,
3141 .base_baud = 460800,
3142 .uart_offset = 8,
3143 },
3144 [pbn_b2_16_460800] = {
3145 .flags = FL_BASE2,
3146 .num_ports = 16,
3147 .base_baud = 460800,
3148 .uart_offset = 8,
3149 },
3150
3151 [pbn_b2_1_921600] = {
3152 .flags = FL_BASE2,
3153 .num_ports = 1,
3154 .base_baud = 921600,
3155 .uart_offset = 8,
3156 },
3157 [pbn_b2_4_921600] = {
3158 .flags = FL_BASE2,
3159 .num_ports = 4,
3160 .base_baud = 921600,
3161 .uart_offset = 8,
3162 },
3163 [pbn_b2_8_921600] = {
3164 .flags = FL_BASE2,
3165 .num_ports = 8,
3166 .base_baud = 921600,
3167 .uart_offset = 8,
3168 },
3169
e847003f
LB		 3170 [pbn_b2_8_1152000] = {
3171 .flags = FL_BASE2,
3172 .num_ports = 8,
3173 .base_baud = 1152000,
3174 .uart_offset = 8,
3175 },
3176
1da177e4
LT		 3177 [pbn_b2_bt_1_115200] = {
3178 .flags = FL_BASE2|FL_BASE_BARS,
3179 .num_ports = 1,
3180 .base_baud = 115200,
3181 .uart_offset = 8,
3182 },
3183 [pbn_b2_bt_2_115200] = {
3184 .flags = FL_BASE2|FL_BASE_BARS,
3185 .num_ports = 2,
3186 .base_baud = 115200,
3187 .uart_offset = 8,
3188 },
3189 [pbn_b2_bt_4_115200] = {
3190 .flags = FL_BASE2|FL_BASE_BARS,
3191 .num_ports = 4,
3192 .base_baud = 115200,
3193 .uart_offset = 8,
3194 },
3195
3196 [pbn_b2_bt_2_921600] = {
3197 .flags = FL_BASE2|FL_BASE_BARS,
3198 .num_ports = 2,
3199 .base_baud = 921600,
3200 .uart_offset = 8,
3201 },
3202 [pbn_b2_bt_4_921600] = {
3203 .flags = FL_BASE2|FL_BASE_BARS,
3204 .num_ports = 4,
3205 .base_baud = 921600,
3206 .uart_offset = 8,
3207 },
3208
d9004eb4
ABL		 3209 [pbn_b3_2_115200] = {
3210 .flags = FL_BASE3,
3211 .num_ports = 2,
3212 .base_baud = 115200,
3213 .uart_offset = 8,
3214 },
1da177e4
LT		 3215 [pbn_b3_4_115200] = {
3216 .flags = FL_BASE3,
3217 .num_ports = 4,
3218 .base_baud = 115200,
3219 .uart_offset = 8,
3220 },
3221 [pbn_b3_8_115200] = {
3222 .flags = FL_BASE3,
3223 .num_ports = 8,
3224 .base_baud = 115200,
3225 .uart_offset = 8,
3226 },
3227
66169ad1
YY		 3228 [pbn_b4_bt_2_921600] = {
3229 .flags = FL_BASE4,
3230 .num_ports = 2,
3231 .base_baud = 921600,
3232 .uart_offset = 8,
3233 },
3234 [pbn_b4_bt_4_921600] = {
3235 .flags = FL_BASE4,
3236 .num_ports = 4,
3237 .base_baud = 921600,
3238 .uart_offset = 8,
3239 },
3240 [pbn_b4_bt_8_921600] = {
3241 .flags = FL_BASE4,
3242 .num_ports = 8,
3243 .base_baud = 921600,
3244 .uart_offset = 8,
3245 },
3246
1da177e4
LT		 3247 /*
3248 * Entries following this are board-specific.
3249 */
3250
3251 /*
3252 * Panacom - IOMEM
3253 */
3254 [pbn_panacom] = {
3255 .flags = FL_BASE2,
3256 .num_ports = 2,
3257 .base_baud = 921600,
3258 .uart_offset = 0x400,
3259 .reg_shift = 7,
3260 },
3261 [pbn_panacom2] = {
3262 .flags = FL_BASE2|FL_BASE_BARS,
3263 .num_ports = 2,
3264 .base_baud = 921600,
3265 .uart_offset = 0x400,
3266 .reg_shift = 7,
3267 },
3268 [pbn_panacom4] = {
3269 .flags = FL_BASE2|FL_BASE_BARS,
3270 .num_ports = 4,
3271 .base_baud = 921600,
3272 .uart_offset = 0x400,
3273 .reg_shift = 7,
3274 },
3275
3276 /* I think this entry is broken - the first_offset looks wrong --rmk */
3277 [pbn_plx_romulus] = {
3278 .flags = FL_BASE2,
3279 .num_ports = 4,
3280 .base_baud = 921600,
3281 .uart_offset = 8 << 2,
3282 .reg_shift = 2,
3283 .first_offset = 0x03,
3284 },
3285
3286 /*
3287 * This board uses the size of PCI Base region 0 to
3288 * signal now many ports are available
3289 */
3290 [pbn_oxsemi] = {
3291 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3292 .num_ports = 32,
3293 .base_baud = 115200,
3294 .uart_offset = 8,
3295 },
7106b4e3
LH		 3296 [pbn_oxsemi_1_4000000] = {
3297 .flags = FL_BASE0,
3298 .num_ports = 1,
3299 .base_baud = 4000000,
3300 .uart_offset = 0x200,
3301 .first_offset = 0x1000,
3302 },
3303 [pbn_oxsemi_2_4000000] = {
3304 .flags = FL_BASE0,
3305 .num_ports = 2,
3306 .base_baud = 4000000,
3307 .uart_offset = 0x200,
3308 .first_offset = 0x1000,
3309 },
3310 [pbn_oxsemi_4_4000000] = {
3311 .flags = FL_BASE0,
3312 .num_ports = 4,
3313 .base_baud = 4000000,
3314 .uart_offset = 0x200,
3315 .first_offset = 0x1000,
3316 },
3317 [pbn_oxsemi_8_4000000] = {
3318 .flags = FL_BASE0,
3319 .num_ports = 8,
3320 .base_baud = 4000000,
3321 .uart_offset = 0x200,
3322 .first_offset = 0x1000,
3323 },
3324
1da177e4
LT		 3325
3326 /*
3327 * EKF addition for i960 Boards form EKF with serial port.
3328 * Max 256 ports.
3329 */
3330 [pbn_intel_i960] = {
3331 .flags = FL_BASE0,
3332 .num_ports = 32,
3333 .base_baud = 921600,
3334 .uart_offset = 8 << 2,
3335 .reg_shift = 2,
3336 .first_offset = 0x10000,
3337 },
3338 [pbn_sgi_ioc3] = {
3339 .flags = FL_BASE0|FL_NOIRQ,
3340 .num_ports = 1,
3341 .base_baud = 458333,
3342 .uart_offset = 8,
3343 .reg_shift = 0,
3344 .first_offset = 0x20178,
3345 },
3346
1da177e4
LT		 3347 /*
3348 * Computone - uses IOMEM.
3349 */
3350 [pbn_computone_4] = {
3351 .flags = FL_BASE0,
3352 .num_ports = 4,
3353 .base_baud = 921600,
3354 .uart_offset = 0x40,
3355 .reg_shift = 2,
3356 .first_offset = 0x200,
3357 },
3358 [pbn_computone_6] = {
3359 .flags = FL_BASE0,
3360 .num_ports = 6,
3361 .base_baud = 921600,
3362 .uart_offset = 0x40,
3363 .reg_shift = 2,
3364 .first_offset = 0x200,
3365 },
3366 [pbn_computone_8] = {
3367 .flags = FL_BASE0,
3368 .num_ports = 8,
3369 .base_baud = 921600,
3370 .uart_offset = 0x40,
3371 .reg_shift = 2,
3372 .first_offset = 0x200,
3373 },
3374 [pbn_sbsxrsio] = {
3375 .flags = FL_BASE0,
3376 .num_ports = 8,
3377 .base_baud = 460800,
3378 .uart_offset = 256,
3379 .reg_shift = 4,
3380 },
3381 /*
3382 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3383 * Only basic 16550A support.
3384 * XR17C15[24] are not tested, but they should work.
3385 */
3386 [pbn_exar_XR17C152] = {
3387 .flags = FL_BASE0,
3388 .num_ports = 2,
3389 .base_baud = 921600,
3390 .uart_offset = 0x200,
3391 },
3392 [pbn_exar_XR17C154] = {
3393 .flags = FL_BASE0,
3394 .num_ports = 4,
3395 .base_baud = 921600,
3396 .uart_offset = 0x200,
3397 },
3398 [pbn_exar_XR17C158] = {
3399 .flags = FL_BASE0,
3400 .num_ports = 8,
3401 .base_baud = 921600,
3402 .uart_offset = 0x200,
3403 },
dc96efb7
MS		 3404 [pbn_exar_XR17V352] = {
3405 .flags = FL_BASE0,
3406 .num_ports = 2,
3407 .base_baud = 7812500,
3408 .uart_offset = 0x400,
3409 .reg_shift = 0,
3410 .first_offset = 0,
3411 },
3412 [pbn_exar_XR17V354] = {
3413 .flags = FL_BASE0,
3414 .num_ports = 4,
3415 .base_baud = 7812500,
3416 .uart_offset = 0x400,
3417 .reg_shift = 0,
3418 .first_offset = 0,
3419 },
3420 [pbn_exar_XR17V358] = {
3421 .flags = FL_BASE0,
3422 .num_ports = 8,
3423 .base_baud = 7812500,
3424 .uart_offset = 0x400,
3425 .reg_shift = 0,
3426 .first_offset = 0,
3427 },
c68d2b15
BH		 3428 [pbn_exar_ibm_saturn] = {
3429 .flags = FL_BASE0,
3430 .num_ports = 1,
3431 .base_baud = 921600,
3432 .uart_offset = 0x200,
3433 },
3434
aa798505
OJ		 3435 /*
3436 * PA Semi PWRficient PA6T-1682M on-chip UART
3437 */
3438 [pbn_pasemi_1682M] = {
3439 .flags = FL_BASE0,
3440 .num_ports = 1,
3441 .base_baud = 8333333,
3442 },
46a0fac9
SB		 3443 /*
3444 * National Instruments 843x
3445 */
3446 [pbn_ni8430_16] = {
3447 .flags = FL_BASE0,
3448 .num_ports = 16,
3449 .base_baud = 3686400,
3450 .uart_offset = 0x10,
3451 .first_offset = 0x800,
3452 },
3453 [pbn_ni8430_8] = {
3454 .flags = FL_BASE0,
3455 .num_ports = 8,
3456 .base_baud = 3686400,
3457 .uart_offset = 0x10,
3458 .first_offset = 0x800,
3459 },
3460 [pbn_ni8430_4] = {
3461 .flags = FL_BASE0,
3462 .num_ports = 4,
3463 .base_baud = 3686400,
3464 .uart_offset = 0x10,
3465 .first_offset = 0x800,
3466 },
3467 [pbn_ni8430_2] = {
3468 .flags = FL_BASE0,
3469 .num_ports = 2,
3470 .base_baud = 3686400,
3471 .uart_offset = 0x10,
3472 .first_offset = 0x800,
3473 },
1b62cbf2
KJ		 3474 /*
3475 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3476 */
3477 [pbn_ADDIDATA_PCIe_1_3906250] = {
3478 .flags = FL_BASE0,
3479 .num_ports = 1,
3480 .base_baud = 3906250,
3481 .uart_offset = 0x200,
3482 .first_offset = 0x1000,
3483 },
3484 [pbn_ADDIDATA_PCIe_2_3906250] = {
3485 .flags = FL_BASE0,
3486 .num_ports = 2,
3487 .base_baud = 3906250,
3488 .uart_offset = 0x200,
3489 .first_offset = 0x1000,
3490 },
3491 [pbn_ADDIDATA_PCIe_4_3906250] = {
3492 .flags = FL_BASE0,
3493 .num_ports = 4,
3494 .base_baud = 3906250,
3495 .uart_offset = 0x200,
3496 .first_offset = 0x1000,
3497 },
3498 [pbn_ADDIDATA_PCIe_8_3906250] = {
3499 .flags = FL_BASE0,
3500 .num_ports = 8,
3501 .base_baud = 3906250,
3502 .uart_offset = 0x200,
3503 .first_offset = 0x1000,
3504 },
095e24b0 3505 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3506 .flags = FL_BASE_BARS,
3507 .num_ports = 2,
095e24b0
DB		 3508 .base_baud = 921600,
3509 .reg_shift = 2,
3510 },
41d3f099
AS		 3511 /*
3512 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3513 * but is overridden by byt_set_termios.
3514 */
b15e5691
HK		 3515 [pbn_byt] = {
3516 .flags = FL_BASE0,
3517 .num_ports = 1,
3518 .base_baud = 2764800,
3519 .uart_offset = 0x80,
3520 .reg_shift = 2,
3521 },
d9a0fbfd
AP		 3522 [pbn_omegapci] = {
3523 .flags = FL_BASE0,
3524 .num_ports = 8,
3525 .base_baud = 115200,
3526 .uart_offset = 0x200,
3527 },
7808edcd
NG		 3528 [pbn_NETMOS9900_2s_115200] = {
3529 .flags = FL_BASE0,
3530 .num_ports = 2,
3531 .base_baud = 115200,
3532 },
ebebd49a
SH		 3533 [pbn_brcm_trumanage] = {
3534 .flags = FL_BASE0,
3535 .num_ports = 1,
3536 .reg_shift = 2,
3537 .base_baud = 115200,
3538 },
2c62a3c8
GKH		 3539 [pbn_fintek_4] = {
3540 .num_ports = 4,
3541 .uart_offset = 8,
3542 .base_baud = 115200,
3543 .first_offset = 0x40,
3544 },
3545 [pbn_fintek_8] = {
3546 .num_ports = 8,
3547 .uart_offset = 8,
3548 .base_baud = 115200,
3549 .first_offset = 0x40,
3550 },
3551 [pbn_fintek_12] = {
3552 .num_ports = 12,
3553 .uart_offset = 8,
3554 .base_baud = 115200,
3555 .first_offset = 0x40,
3556 },
1da177e4
LT		 3557};
3558
6971c635
GA		 3559static const struct pci_device_id blacklist[] = {
3560 /* softmodems */
5756ee99 3561 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3562 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3563 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3564
3565 /* multi-io cards handled by parport_serial */
3566 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
feb58142 3567 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
436bbd43
CS		 3568};
3569
1da177e4
LT		 3570/*
3571 * Given a complete unknown PCI device, try to use some heuristics to
3572 * guess what the configuration might be, based on the pitiful PCI
3573 * serial specs. Returns 0 on success, 1 on failure.
3574 */
9671f099 3575static int
1c7c1fe5 3576serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3577{
6971c635 3578 const struct pci_device_id *bldev;
1da177e4 3579 int num_iomem, num_port, first_port = -1, i;
5756ee99 3580
1da177e4
LT		 3581 /*
3582 * If it is not a communications device or the programming
3583 * interface is greater than 6, give up.
3584 *
3585 * (Should we try to make guesses for multiport serial devices
5756ee99 3586 * later?)
1da177e4
LT		 3587 */
3588 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3589 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3590 (dev->class & 0xff) > 6)
3591 return -ENODEV;
3592
436bbd43
CS		 3593 /*
3594 * Do not access blacklisted devices that are known not to
6971c635 3595 * feature serial ports or are handled by other modules.
436bbd43 3596 */
6971c635
GA		 3597 for (bldev = blacklist;
3598 bldev < blacklist + ARRAY_SIZE(blacklist);
3599 bldev++) {
3600 if (dev->vendor == bldev->vendor &&
3601 dev->device == bldev->device)
436bbd43
CS		 3602 return -ENODEV;
3603 }
3604
1da177e4
LT		 3605 num_iomem = num_port = 0;
3606 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3607 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3608 num_port++;
3609 if (first_port == -1)
3610 first_port = i;
3611 }
3612 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3613 num_iomem++;
3614 }
3615
3616 /*
3617 * If there is 1 or 0 iomem regions, and exactly one port,
3618 * use it. We guess the number of ports based on the IO
3619 * region size.
3620 */
3621 if (num_iomem <= 1 && num_port == 1) {
3622 board->flags = first_port;
3623 board->num_ports = pci_resource_len(dev, first_port) / 8;
3624 return 0;
3625 }
3626
3627 /*
3628 * Now guess if we've got a board which indexes by BARs.
3629 * Each IO BAR should be 8 bytes, and they should follow
3630 * consecutively.
3631 */
3632 first_port = -1;
3633 num_port = 0;
3634 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3635 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3636 pci_resource_len(dev, i) == 8 &&
3637 (first_port == -1 || (first_port + num_port) == i)) {
3638 num_port++;
3639 if (first_port == -1)
3640 first_port = i;
3641 }
3642 }
3643
3644 if (num_port > 1) {
3645 board->flags = first_port | FL_BASE_BARS;
3646 board->num_ports = num_port;
3647 return 0;
3648 }
3649
3650 return -ENODEV;
3651}
3652
3653static inline int
975a1a7d
RK		 3654serial_pci_matches(const struct pciserial_board *board,
3655 const struct pciserial_board *guessed)
1da177e4
LT		 3656{
3657 return
3658 board->num_ports == guessed->num_ports &&
3659 board->base_baud == guessed->base_baud &&
3660 board->uart_offset == guessed->uart_offset &&
3661 board->reg_shift == guessed->reg_shift &&
3662 board->first_offset == guessed->first_offset;
3663}
3664
241fc436 3665struct serial_private *
975a1a7d 3666pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3667{
2655a2c7 3668 struct uart_8250_port uart;
1da177e4 3669 struct serial_private *priv;
1da177e4
LT		 3670 struct pci_serial_quirk *quirk;
3671 int rc, nr_ports, i;
3672
1da177e4
LT		 3673 nr_ports = board->num_ports;
3674
3675 /*
3676 * Find an init and setup quirks.
3677 */
3678 quirk = find_quirk(dev);
3679
3680 /*
3681 * Run the new-style initialization function.
3682 * The initialization function returns:
3683 * <0 - error
3684 * 0 - use board->num_ports
3685 * >0 - number of ports
3686 */
3687 if (quirk->init) {
3688 rc = quirk->init(dev);
241fc436
RK		 3689 if (rc < 0) {
3690 priv = ERR_PTR(rc);
3691 goto err_out;
3692 }
1da177e4
LT		 3693 if (rc)
3694 nr_ports = rc;
3695 }
3696
8f31bb39 3697 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3698 sizeof(unsigned int) * nr_ports,
3699 GFP_KERNEL);
3700 if (!priv) {
241fc436
RK		 3701 priv = ERR_PTR(-ENOMEM);
3702 goto err_deinit;
1da177e4
LT		 3703 }
3704
70db3d91 3705 priv->dev = dev;
1da177e4 3706 priv->quirk = quirk;
1da177e4 3707
2655a2c7
AC		 3708 memset(&uart, 0, sizeof(uart));
3709 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3710 uart.port.uartclk = board->base_baud * 16;
3711 uart.port.irq = get_pci_irq(dev, board);
3712 uart.port.dev = &dev->dev;
72ce9a83 3713
1da177e4 3714 for (i = 0; i < nr_ports; i++) {
2655a2c7 3715 if (quirk->setup(priv, board, &uart, i))
1da177e4 3716 break;
72ce9a83 3717
af8c5b8d
GKH		 3718 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3719 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 3720
2655a2c7 3721 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 3722 if (priv->line[i] < 0) {
af8c5b8d
GKH		 3723 dev_err(&dev->dev,
3724 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3725 uart.port.iobase, uart.port.irq,
3726 uart.port.iotype, priv->line[i]);
1da177e4
LT		 3727 break;
3728 }
3729 }
1da177e4 3730 priv->nr = i;
241fc436 3731 return priv;
1da177e4 3732
5756ee99 3733err_deinit:
1da177e4
LT		 3734 if (quirk->exit)
3735 quirk->exit(dev);
5756ee99 3736err_out:
241fc436 3737 return priv;
1da177e4 3738}
241fc436 3739EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 3740
241fc436 3741void pciserial_remove_ports(struct serial_private *priv)
1da177e4 3742{
056a8763
RK		 3743 struct pci_serial_quirk *quirk;
3744 int i;
1da177e4 3745
056a8763
RK		 3746 for (i = 0; i < priv->nr; i++)
3747 serial8250_unregister_port(priv->line[i]);
1da177e4 3748
056a8763
RK		 3749 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3750 if (priv->remapped_bar[i])
3751 iounmap(priv->remapped_bar[i]);
3752 priv->remapped_bar[i] = NULL;
3753 }
1da177e4 3754
056a8763
RK		 3755 /*
3756 * Find the exit quirks.
3757 */
241fc436 3758 quirk = find_quirk(priv->dev);
056a8763 3759 if (quirk->exit)
241fc436
RK		 3760 quirk->exit(priv->dev);
3761
3762 kfree(priv);
3763}
3764EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3765
3766void pciserial_suspend_ports(struct serial_private *priv)
3767{
3768 int i;
3769
3770 for (i = 0; i < priv->nr; i++)
3771 if (priv->line[i] >= 0)
3772 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 3773
3774 /*
3775 * Ensure that every init quirk is properly torn down
3776 */
3777 if (priv->quirk->exit)
3778 priv->quirk->exit(priv->dev);
241fc436
RK		 3779}
3780EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3781
3782void pciserial_resume_ports(struct serial_private *priv)
3783{
3784 int i;
3785
3786 /*
3787 * Ensure that the board is correctly configured.
3788 */
3789 if (priv->quirk->init)
3790 priv->quirk->init(priv->dev);
3791
3792 for (i = 0; i < priv->nr; i++)
3793 if (priv->line[i] >= 0)
3794 serial8250_resume_port(priv->line[i]);
3795}
3796EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3797
3798/*
3799 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3800 * to the arrangement of serial ports on a PCI card.
3801 */
9671f099 3802static int
241fc436
RK		 3803pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3804{
5bf8f501 3805 struct pci_serial_quirk *quirk;
241fc436 3806 struct serial_private *priv;
975a1a7d
RK		 3807 const struct pciserial_board *board;
3808 struct pciserial_board tmp;
241fc436
RK		 3809 int rc;
3810
5bf8f501
FB		 3811 quirk = find_quirk(dev);
3812 if (quirk->probe) {
3813 rc = quirk->probe(dev);
3814 if (rc)
3815 return rc;
3816 }
3817
241fc436 3818 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 3819 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 3820 ent->driver_data);
3821 return -EINVAL;
3822 }
3823
3824 board = &pci_boards[ent->driver_data];
3825
3826 rc = pci_enable_device(dev);
2807190b 3827 pci_save_state(dev);
241fc436
RK		 3828 if (rc)
3829 return rc;
3830
3831 if (ent->driver_data == pbn_default) {
3832 /*
3833 * Use a copy of the pci_board entry for this;
3834 * avoid changing entries in the table.
3835 */
3836 memcpy(&tmp, board, sizeof(struct pciserial_board));
3837 board = &tmp;
3838
3839 /*
3840 * We matched one of our class entries. Try to
3841 * determine the parameters of this board.
3842 */
975a1a7d 3843 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 3844 if (rc)
3845 goto disable;
3846 } else {
3847 /*
3848 * We matched an explicit entry. If we are able to
3849 * detect this boards settings with our heuristic,
3850 * then we no longer need this entry.
3851 */
3852 memcpy(&tmp, &pci_boards[pbn_default],
3853 sizeof(struct pciserial_board));
3854 rc = serial_pci_guess_board(dev, &tmp);
3855 if (rc == 0 && serial_pci_matches(board, &tmp))
3856 moan_device("Redundant entry in serial pci_table.",
3857 dev);
3858 }
3859
3860 priv = pciserial_init_ports(dev, board);
3861 if (!IS_ERR(priv)) {
3862 pci_set_drvdata(dev, priv);
3863 return 0;
3864 }
3865
3866 rc = PTR_ERR(priv);
1da177e4 3867
241fc436 3868 disable:
056a8763 3869 pci_disable_device(dev);
241fc436
RK		 3870 return rc;
3871}
1da177e4 3872
ae8d8a14 3873static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3874{
3875 struct serial_private *priv = pci_get_drvdata(dev);
3876
241fc436
RK		 3877 pciserial_remove_ports(priv);
3878
3879 pci_disable_device(dev);
1da177e4
LT		 3880}
3881
1d5e7996 3882#ifdef CONFIG_PM
1da177e4
LT		 3883static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3884{
3885 struct serial_private *priv = pci_get_drvdata(dev);
3886
241fc436
RK		 3887 if (priv)
3888 pciserial_suspend_ports(priv);
1da177e4 3889
1da177e4
LT		 3890 pci_save_state(dev);
3891 pci_set_power_state(dev, pci_choose_state(dev, state));
3892 return 0;
3893}
3894
3895static int pciserial_resume_one(struct pci_dev *dev)
3896{
ccb9d59e 3897 int err;
1da177e4
LT		 3898 struct serial_private *priv = pci_get_drvdata(dev);
3899
3900 pci_set_power_state(dev, PCI_D0);
3901 pci_restore_state(dev);
3902
3903 if (priv) {
1da177e4
LT		 3904 /*
3905 * The device may have been disabled. Re-enable it.
3906 */
ccb9d59e 3907 err = pci_enable_device(dev);
40836c48 3908 /* FIXME: We cannot simply error out here */
ccb9d59e 3909 if (err)
af8c5b8d 3910 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 3911 pciserial_resume_ports(priv);
1da177e4
LT		 3912 }
3913 return 0;
3914}
1d5e7996 3915#endif
1da177e4
LT		 3916
3917static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3918 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3919 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3920 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3921 pbn_b2_8_921600 },
0c6d774c
TW		 3922 /* Advantech also use 0x3618 and 0xf618 */
3923 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3924 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3925 pbn_b0_4_921600 },
3926 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3927 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3928 pbn_b0_4_921600 },
1da177e4
LT		 3929 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3930 PCI_SUBVENDOR_ID_CONNECT_TECH,
3931 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3932 pbn_b1_8_1382400 },
3933 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3934 PCI_SUBVENDOR_ID_CONNECT_TECH,
3935 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3936 pbn_b1_4_1382400 },
3937 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3938 PCI_SUBVENDOR_ID_CONNECT_TECH,
3939 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3940 pbn_b1_2_1382400 },
3941 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3942 PCI_SUBVENDOR_ID_CONNECT_TECH,
3943 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3944 pbn_b1_8_1382400 },
3945 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3946 PCI_SUBVENDOR_ID_CONNECT_TECH,
3947 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3948 pbn_b1_4_1382400 },
3949 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3950 PCI_SUBVENDOR_ID_CONNECT_TECH,
3951 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3952 pbn_b1_2_1382400 },
3953 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3954 PCI_SUBVENDOR_ID_CONNECT_TECH,
3955 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3956 pbn_b1_8_921600 },
3957 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3958 PCI_SUBVENDOR_ID_CONNECT_TECH,
3959 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3960 pbn_b1_8_921600 },
3961 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3962 PCI_SUBVENDOR_ID_CONNECT_TECH,
3963 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3964 pbn_b1_4_921600 },
3965 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3966 PCI_SUBVENDOR_ID_CONNECT_TECH,
3967 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3968 pbn_b1_4_921600 },
3969 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3970 PCI_SUBVENDOR_ID_CONNECT_TECH,
3971 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3972 pbn_b1_2_921600 },
3973 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3974 PCI_SUBVENDOR_ID_CONNECT_TECH,
3975 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3976 pbn_b1_8_921600 },
3977 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3978 PCI_SUBVENDOR_ID_CONNECT_TECH,
3979 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3980 pbn_b1_8_921600 },
3981 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3982 PCI_SUBVENDOR_ID_CONNECT_TECH,
3983 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3984 pbn_b1_4_921600 },
26e92861
GH		 3985 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3986 PCI_SUBVENDOR_ID_CONNECT_TECH,
3987 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3988 pbn_b1_2_1250000 },
3989 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3990 PCI_SUBVENDOR_ID_CONNECT_TECH,
3991 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3992 pbn_b0_2_1843200 },
3993 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3994 PCI_SUBVENDOR_ID_CONNECT_TECH,
3995 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3996 pbn_b0_4_1843200 },
85d1494e
YY		 3997 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3998 PCI_VENDOR_ID_AFAVLAB,
3999 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4000 pbn_b0_4_1152000 },
26e92861
GH		 4001 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4002 PCI_SUBVENDOR_ID_CONNECT_TECH,
4003 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4004 pbn_b0_2_1843200_200 },
4005 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4006 PCI_SUBVENDOR_ID_CONNECT_TECH,
4007 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4008 pbn_b0_4_1843200_200 },
4009 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4010 PCI_SUBVENDOR_ID_CONNECT_TECH,
4011 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4012 pbn_b0_8_1843200_200 },
4013 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4014 PCI_SUBVENDOR_ID_CONNECT_TECH,
4015 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4016 pbn_b0_2_1843200_200 },
4017 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4018 PCI_SUBVENDOR_ID_CONNECT_TECH,
4019 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4020 pbn_b0_4_1843200_200 },
4021 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4022 PCI_SUBVENDOR_ID_CONNECT_TECH,
4023 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4024 pbn_b0_8_1843200_200 },
4025 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4026 PCI_SUBVENDOR_ID_CONNECT_TECH,
4027 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4028 pbn_b0_2_1843200_200 },
4029 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4030 PCI_SUBVENDOR_ID_CONNECT_TECH,
4031 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4032 pbn_b0_4_1843200_200 },
4033 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4034 PCI_SUBVENDOR_ID_CONNECT_TECH,
4035 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4036 pbn_b0_8_1843200_200 },
4037 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4038 PCI_SUBVENDOR_ID_CONNECT_TECH,
4039 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4040 pbn_b0_2_1843200_200 },
4041 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4042 PCI_SUBVENDOR_ID_CONNECT_TECH,
4043 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4044 pbn_b0_4_1843200_200 },
4045 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4046 PCI_SUBVENDOR_ID_CONNECT_TECH,
4047 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4048 pbn_b0_8_1843200_200 },
c68d2b15
BH		 4049 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4050 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4051 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 4052
4053 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 4054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4055 pbn_b2_bt_1_115200 },
4056 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 4057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4058 pbn_b2_bt_2_115200 },
4059 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 4060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4061 pbn_b2_bt_4_115200 },
4062 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 4063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4064 pbn_b2_bt_2_115200 },
4065 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 4066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4067 pbn_b2_bt_4_115200 },
4068 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4070 pbn_b2_8_115200 },
e65f0f82
FL		 4071 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4073 pbn_b2_8_460800 },
1da177e4
LT		 4074 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4076 pbn_b2_8_115200 },
4077
4078 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4080 pbn_b2_bt_2_115200 },
4081 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4083 pbn_b2_bt_2_921600 },
4084 /*
4085 * VScom SPCOM800, from sl@s.pl
4086 */
5756ee99
AC		 4087 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4089 pbn_b2_8_921600 },
4090 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 4091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4092 pbn_b2_4_921600 },
b76c5a07
CB		 4093 /* Unknown card - subdevice 0x1584 */
4094 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4095 PCI_VENDOR_ID_PLX,
4096 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 4097 pbn_b2_4_115200 },
4098 /* Unknown card - subdevice 0x1588 */
4099 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4100 PCI_VENDOR_ID_PLX,
4101 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4102 pbn_b2_8_115200 },
1da177e4
LT		 4103 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4104 PCI_SUBVENDOR_ID_KEYSPAN,
4105 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4106 pbn_panacom },
4107 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4109 pbn_panacom4 },
4110 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4112 pbn_panacom2 },
a9cccd34
MF		 4113 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4114 PCI_VENDOR_ID_ESDGMBH,
4115 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4116 pbn_b2_4_115200 },
1da177e4
LT		 4117 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4118 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4119 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4120 pbn_b2_4_460800 },
4121 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4122 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4123 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4124 pbn_b2_8_460800 },
4125 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4126 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4127 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4128 pbn_b2_16_460800 },
4129 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4130 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4131 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4132 pbn_b2_16_460800 },
4133 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4134 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4135 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4136 pbn_b2_4_460800 },
4137 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4138 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4139 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4140 pbn_b2_8_460800 },
add7b58e
BH		 4141 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4142 PCI_SUBVENDOR_ID_EXSYS,
4143 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4144 pbn_b2_4_115200 },
1da177e4
LT		 4145 /*
4146 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4147 * (Exoray@isys.ca)
4148 */
4149 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4150 0x10b5, 0x106a, 0, 0,
4151 pbn_plx_romulus },
55c7c0fd
AC		 4152 /*
4153 * Quatech cards. These actually have configurable clocks but for
4154 * now we just use the default.
4155 *
4156 * 100 series are RS232, 200 series RS422,
4157 */
1da177e4
LT		 4158 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4160 pbn_b1_4_115200 },
4161 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4163 pbn_b1_2_115200 },
55c7c0fd
AC		 4164 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4166 pbn_b2_2_115200 },
4167 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4169 pbn_b1_2_115200 },
4170 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4172 pbn_b2_2_115200 },
4173 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4175 pbn_b1_4_115200 },
1da177e4
LT		 4176 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4178 pbn_b1_8_115200 },
4179 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4181 pbn_b1_8_115200 },
55c7c0fd
AC		 4182 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4184 pbn_b1_4_115200 },
4185 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4187 pbn_b1_2_115200 },
4188 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4190 pbn_b1_4_115200 },
4191 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4193 pbn_b1_2_115200 },
4194 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4196 pbn_b2_4_115200 },
4197 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4199 pbn_b2_2_115200 },
4200 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4202 pbn_b2_1_115200 },
4203 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4205 pbn_b2_4_115200 },
4206 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4208 pbn_b2_2_115200 },
4209 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4211 pbn_b2_1_115200 },
4212 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4214 pbn_b0_8_115200 },
4215
1da177e4 4216 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4217 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4218 0, 0,
1da177e4 4219 pbn_b0_4_921600 },
fbc0dc0d 4220 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4221 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4222 0, 0,
fbc0dc0d 4223 pbn_b0_4_1152000 },
c9bd9d01
MP		 4224 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4226 pbn_b0_bt_2_921600 },
db1de159
DR		 4227
4228 /*
4229 * The below card is a little controversial since it is the
4230 * subject of a PCI vendor/device ID clash. (See
4231 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4232 * For now just used the hex ID 0x950a.
4233 */
39aced68 4234 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4235 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4236 0, 0, pbn_b0_2_115200 },
4237 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4238 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4239 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4240 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4242 pbn_b0_2_1130000 },
70fd8fde
AP		 4243 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4244 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4245 pbn_b0_1_921600 },
1da177e4
LT		 4246 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4248 pbn_b0_4_115200 },
4249 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251 pbn_b0_bt_2_921600 },
e847003f
LB		 4252 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4253 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4254 pbn_b2_8_1152000 },
1da177e4 4255
7106b4e3
LH		 4256 /*
4257 * Oxford Semiconductor Inc. Tornado PCI express device range.
4258 */
4259 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_b0_1_4000000 },
4262 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_b0_1_4000000 },
4265 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_oxsemi_1_4000000 },
4268 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_oxsemi_1_4000000 },
4271 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_b0_1_4000000 },
4274 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_b0_1_4000000 },
4277 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_oxsemi_1_4000000 },
4280 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282 pbn_oxsemi_1_4000000 },
4283 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_b0_1_4000000 },
4286 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288 pbn_b0_1_4000000 },
4289 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291 pbn_b0_1_4000000 },
4292 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294 pbn_b0_1_4000000 },
4295 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297 pbn_oxsemi_2_4000000 },
4298 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300 pbn_oxsemi_2_4000000 },
4301 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 pbn_oxsemi_4_4000000 },
4304 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 pbn_oxsemi_4_4000000 },
4307 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 pbn_oxsemi_8_4000000 },
4310 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_oxsemi_8_4000000 },
4313 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 pbn_oxsemi_1_4000000 },
4316 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 pbn_oxsemi_1_4000000 },
4319 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 pbn_oxsemi_1_4000000 },
4322 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 pbn_oxsemi_1_4000000 },
4325 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 pbn_oxsemi_1_4000000 },
4328 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 pbn_oxsemi_1_4000000 },
4331 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_oxsemi_1_4000000 },
4334 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_oxsemi_1_4000000 },
4337 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_oxsemi_1_4000000 },
4340 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_oxsemi_1_4000000 },
4343 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_oxsemi_1_4000000 },
4346 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_oxsemi_1_4000000 },
4349 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_oxsemi_1_4000000 },
4352 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_oxsemi_1_4000000 },
4355 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_oxsemi_1_4000000 },
4358 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_oxsemi_1_4000000 },
4361 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 pbn_oxsemi_1_4000000 },
4364 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366 pbn_oxsemi_1_4000000 },
4367 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369 pbn_oxsemi_1_4000000 },
4370 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 pbn_oxsemi_1_4000000 },
4373 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375 pbn_oxsemi_1_4000000 },
4376 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378 pbn_oxsemi_1_4000000 },
4379 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381 pbn_oxsemi_1_4000000 },
4382 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384 pbn_oxsemi_1_4000000 },
4385 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387 pbn_oxsemi_1_4000000 },
4388 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390 pbn_oxsemi_1_4000000 },
b80de369
LH		 4391 /*
4392 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4393 */
4394 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4395 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4396 pbn_oxsemi_1_4000000 },
4397 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4398 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4399 pbn_oxsemi_2_4000000 },
4400 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4401 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4402 pbn_oxsemi_4_4000000 },
4403 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4404 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4405 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4406
4407 /*
4408 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4409 */
4410 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4411 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4412 pbn_oxsemi_2_4000000 },
4413
1da177e4
LT		 4414 /*
4415 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4416 * from skokodyn@yahoo.com
4417 */
4418 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4419 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4420 pbn_sbsxrsio },
4421 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4422 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4423 pbn_sbsxrsio },
4424 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4425 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4426 pbn_sbsxrsio },
4427 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4428 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4429 pbn_sbsxrsio },
4430
4431 /*
4432 * Digitan DS560-558, from jimd@esoft.com
4433 */
4434 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4436 pbn_b1_1_115200 },
4437
4438 /*
4439 * Titan Electronic cards
4440 * The 400L and 800L have a custom setup quirk.
4441 */
4442 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4444 pbn_b0_1_921600 },
4445 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4447 pbn_b0_2_921600 },
4448 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4450 pbn_b0_4_921600 },
4451 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4453 pbn_b0_4_921600 },
4454 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 pbn_b1_1_921600 },
4457 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 pbn_b1_bt_2_921600 },
4460 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 pbn_b0_bt_4_921600 },
4463 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_b0_bt_8_921600 },
66169ad1
YY		 4466 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 pbn_b4_bt_2_921600 },
4469 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_b4_bt_4_921600 },
4472 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_b4_bt_8_921600 },
4475 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_b0_4_921600 },
4478 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_b0_4_921600 },
4481 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 pbn_b0_4_921600 },
4484 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 pbn_oxsemi_1_4000000 },
4487 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_oxsemi_2_4000000 },
4490 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 pbn_oxsemi_4_4000000 },
4493 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 pbn_oxsemi_8_4000000 },
4496 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498 pbn_oxsemi_2_4000000 },
4499 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 pbn_oxsemi_2_4000000 },
48c0247d
YY		 4502 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4505 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_b0_4_921600 },
4508 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b0_4_921600 },
4511 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 pbn_b0_4_921600 },
4514 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_b0_4_921600 },
1da177e4
LT		 4517
4518 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 pbn_b2_1_460800 },
4521 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_b2_1_460800 },
4524 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_b2_1_460800 },
4527 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529 pbn_b2_bt_2_921600 },
4530 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_b2_bt_2_921600 },
4533 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_b2_bt_2_921600 },
4536 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_b2_bt_4_921600 },
4539 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_b2_bt_4_921600 },
4542 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 pbn_b2_bt_4_921600 },
4545 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 pbn_b0_1_921600 },
4548 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 pbn_b0_1_921600 },
4551 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 pbn_b0_1_921600 },
4554 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 pbn_b0_bt_2_921600 },
4557 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559 pbn_b0_bt_2_921600 },
4560 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562 pbn_b0_bt_2_921600 },
4563 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565 pbn_b0_bt_4_921600 },
4566 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_b0_bt_4_921600 },
4569 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4572 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_b0_bt_8_921600 },
4575 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_b0_bt_8_921600 },
4578 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_b0_bt_8_921600 },
1da177e4
LT		 4581
4582 /*
4583 * Computone devices submitted by Doug McNash dmcnash@computone.com
4584 */
4585 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4586 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4587 0, 0, pbn_computone_4 },
4588 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4589 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4590 0, 0, pbn_computone_8 },
4591 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4592 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4593 0, 0, pbn_computone_6 },
4594
4595 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597 pbn_oxsemi },
4598 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4599 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4600 pbn_b0_bt_1_921600 },
4601
abd7baca
SC		 4602 /*
4603 * SUNIX (TIMEDIA)
4604 */
4605 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4606 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4607 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4608 pbn_b0_bt_1_921600 },
4609
4610 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4611 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4612 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4613 pbn_b0_bt_1_921600 },
4614
1da177e4
LT		 4615 /*
4616 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4617 */
4618 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b0_bt_8_115200 },
4621 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b0_bt_8_115200 },
4624
4625 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_b0_bt_2_115200 },
4628 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_b0_bt_2_115200 },
4631 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4634 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_b0_bt_2_115200 },
4637 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_b0_bt_2_115200 },
1da177e4
LT		 4640 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_b0_bt_4_460800 },
4643 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_b0_bt_4_460800 },
4646 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_b0_bt_2_460800 },
4649 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_b0_bt_2_460800 },
4652 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_b0_bt_2_460800 },
4655 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_b0_bt_1_115200 },
4658 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_b0_bt_1_460800 },
4661
1fb8cacc
RK		 4662 /*
4663 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4664 * Cards are identified by their subsystem vendor IDs, which
4665 * (in hex) match the model number.
4666 *
4667 * Note that JC140x are RS422/485 cards which require ox950
4668 * ACR = 0x10, and as such are not currently fully supported.
4669 */
4670 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4671 0x1204, 0x0004, 0, 0,
4672 pbn_b0_4_921600 },
4673 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4674 0x1208, 0x0004, 0, 0,
4675 pbn_b0_4_921600 },
4676/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4677 0x1402, 0x0002, 0, 0,
4678 pbn_b0_2_921600 }, */
4679/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4680 0x1404, 0x0004, 0, 0,
4681 pbn_b0_4_921600 }, */
4682 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4683 0x1208, 0x0004, 0, 0,
4684 pbn_b0_4_921600 },
4685
2a52fcb5
KY		 4686 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4687 0x1204, 0x0004, 0, 0,
4688 pbn_b0_4_921600 },
4689 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4690 0x1208, 0x0004, 0, 0,
4691 pbn_b0_4_921600 },
4692 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4693 0x1208, 0x0004, 0, 0,
4694 pbn_b0_4_921600 },
1da177e4
LT		 4695 /*
4696 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4697 */
4698 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_b1_1_1382400 },
4701
4702 /*
4703 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4704 */
4705 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_b1_1_1382400 },
4708
4709 /*
4710 * RAStel 2 port modem, gerg@moreton.com.au
4711 */
4712 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_b2_bt_2_115200 },
4715
4716 /*
4717 * EKF addition for i960 Boards form EKF with serial port
4718 */
4719 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4720 0xE4BF, PCI_ANY_ID, 0, 0,
4721 pbn_intel_i960 },
4722
4723 /*
4724 * Xircom Cardbus/Ethernet combos
4725 */
4726 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_b0_1_115200 },
4729 /*
4730 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4731 */
4732 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_b0_1_115200 },
4735
4736 /*
4737 * Untested PCI modems, sent in from various folks...
4738 */
4739
4740 /*
4741 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4742 */
4743 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4744 0x1048, 0x1500, 0, 0,
4745 pbn_b1_1_115200 },
4746
4747 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4748 0xFF00, 0, 0, 0,
4749 pbn_sgi_ioc3 },
4750
4751 /*
4752 * HP Diva card
4753 */
4754 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4755 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4756 pbn_b1_1_115200 },
4757 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 pbn_b0_5_115200 },
4760 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 pbn_b2_1_115200 },
4763
d9004eb4
ABL		 4764 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_b3_2_115200 },
1da177e4
LT		 4767 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_b3_4_115200 },
4770 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_b3_8_115200 },
4773
4774 /*
4775 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4776 */
4777 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4778 PCI_ANY_ID, PCI_ANY_ID,
4779 0,
4780 0, pbn_exar_XR17C152 },
4781 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4782 PCI_ANY_ID, PCI_ANY_ID,
4783 0,
4784 0, pbn_exar_XR17C154 },
4785 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4786 PCI_ANY_ID, PCI_ANY_ID,
4787 0,
4788 0, pbn_exar_XR17C158 },
dc96efb7
MS		 4789 /*
4790 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4791 */
4792 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4793 PCI_ANY_ID, PCI_ANY_ID,
4794 0,
4795 0, pbn_exar_XR17V352 },
4796 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4797 PCI_ANY_ID, PCI_ANY_ID,
4798 0,
4799 0, pbn_exar_XR17V354 },
4800 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4801 PCI_ANY_ID, PCI_ANY_ID,
4802 0,
4803 0, pbn_exar_XR17V358 },
1da177e4
LT		 4804
4805 /*
4806 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4807 */
4808 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 pbn_b0_1_115200 },
84f8c6fc
NV		 4811 /*
4812 * ITE
4813 */
4814 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4815 PCI_ANY_ID, PCI_ANY_ID,
4816 0, 0,
4817 pbn_b1_bt_1_115200 },
1da177e4 4818
737c1756
PH		 4819 /*
4820 * IntaShield IS-200
4821 */
4822 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4824 pbn_b2_2_115200 },
4b6f6ce9
IGP		 4825 /*
4826 * IntaShield IS-400
4827 */
4828 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4830 pbn_b2_4_115200 },
48212008
TH		 4831 /*
4832 * Perle PCI-RAS cards
4833 */
4834 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4835 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4836 0, 0, pbn_b2_4_921600 },
4837 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4838 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4839 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 4840
4841 /*
4842 * Mainpine series cards: Fairly standard layout but fools
4843 * parts of the autodetect in some cases and uses otherwise
4844 * unmatched communications subclasses in the PCI Express case
4845 */
4846
4847 { /* RockForceDUO */
4848 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4849 PCI_VENDOR_ID_MAINPINE, 0x0200,
4850 0, 0, pbn_b0_2_115200 },
4851 { /* RockForceQUATRO */
4852 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4853 PCI_VENDOR_ID_MAINPINE, 0x0300,
4854 0, 0, pbn_b0_4_115200 },
4855 { /* RockForceDUO+ */
4856 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4857 PCI_VENDOR_ID_MAINPINE, 0x0400,
4858 0, 0, pbn_b0_2_115200 },
4859 { /* RockForceQUATRO+ */
4860 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4861 PCI_VENDOR_ID_MAINPINE, 0x0500,
4862 0, 0, pbn_b0_4_115200 },
4863 { /* RockForce+ */
4864 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4865 PCI_VENDOR_ID_MAINPINE, 0x0600,
4866 0, 0, pbn_b0_2_115200 },
4867 { /* RockForce+ */
4868 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4869 PCI_VENDOR_ID_MAINPINE, 0x0700,
4870 0, 0, pbn_b0_4_115200 },
4871 { /* RockForceOCTO+ */
4872 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4873 PCI_VENDOR_ID_MAINPINE, 0x0800,
4874 0, 0, pbn_b0_8_115200 },
4875 { /* RockForceDUO+ */
4876 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4877 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4878 0, 0, pbn_b0_2_115200 },
4879 { /* RockForceQUARTRO+ */
4880 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4881 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4882 0, 0, pbn_b0_4_115200 },
4883 { /* RockForceOCTO+ */
4884 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4885 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4886 0, 0, pbn_b0_8_115200 },
4887 { /* RockForceD1 */
4888 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4889 PCI_VENDOR_ID_MAINPINE, 0x2000,
4890 0, 0, pbn_b0_1_115200 },
4891 { /* RockForceF1 */
4892 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4893 PCI_VENDOR_ID_MAINPINE, 0x2100,
4894 0, 0, pbn_b0_1_115200 },
4895 { /* RockForceD2 */
4896 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4897 PCI_VENDOR_ID_MAINPINE, 0x2200,
4898 0, 0, pbn_b0_2_115200 },
4899 { /* RockForceF2 */
4900 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4901 PCI_VENDOR_ID_MAINPINE, 0x2300,
4902 0, 0, pbn_b0_2_115200 },
4903 { /* RockForceD4 */
4904 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4905 PCI_VENDOR_ID_MAINPINE, 0x2400,
4906 0, 0, pbn_b0_4_115200 },
4907 { /* RockForceF4 */
4908 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4909 PCI_VENDOR_ID_MAINPINE, 0x2500,
4910 0, 0, pbn_b0_4_115200 },
4911 { /* RockForceD8 */
4912 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4913 PCI_VENDOR_ID_MAINPINE, 0x2600,
4914 0, 0, pbn_b0_8_115200 },
4915 { /* RockForceF8 */
4916 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4917 PCI_VENDOR_ID_MAINPINE, 0x2700,
4918 0, 0, pbn_b0_8_115200 },
4919 { /* IQ Express D1 */
4920 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4921 PCI_VENDOR_ID_MAINPINE, 0x3000,
4922 0, 0, pbn_b0_1_115200 },
4923 { /* IQ Express F1 */
4924 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4925 PCI_VENDOR_ID_MAINPINE, 0x3100,
4926 0, 0, pbn_b0_1_115200 },
4927 { /* IQ Express D2 */
4928 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4929 PCI_VENDOR_ID_MAINPINE, 0x3200,
4930 0, 0, pbn_b0_2_115200 },
4931 { /* IQ Express F2 */
4932 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4933 PCI_VENDOR_ID_MAINPINE, 0x3300,
4934 0, 0, pbn_b0_2_115200 },
4935 { /* IQ Express D4 */
4936 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4937 PCI_VENDOR_ID_MAINPINE, 0x3400,
4938 0, 0, pbn_b0_4_115200 },
4939 { /* IQ Express F4 */
4940 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4941 PCI_VENDOR_ID_MAINPINE, 0x3500,
4942 0, 0, pbn_b0_4_115200 },
4943 { /* IQ Express D8 */
4944 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4945 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4946 0, 0, pbn_b0_8_115200 },
4947 { /* IQ Express F8 */
4948 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4949 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4950 0, 0, pbn_b0_8_115200 },
4951
4952
aa798505
OJ		 4953 /*
4954 * PA Semi PA6T-1682M on-chip UART
4955 */
4956 { PCI_VENDOR_ID_PASEMI, 0xa004,
4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4958 pbn_pasemi_1682M },
4959
46a0fac9
SB		 4960 /*
4961 * National Instruments
4962 */
04bf7e74
WP		 4963 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b1_16_115200 },
4966 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 pbn_b1_8_115200 },
4969 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b1_bt_4_115200 },
4972 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 pbn_b1_bt_2_115200 },
4975 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977 pbn_b1_bt_4_115200 },
4978 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 pbn_b1_bt_2_115200 },
4981 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983 pbn_b1_16_115200 },
4984 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 pbn_b1_8_115200 },
4987 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 pbn_b1_bt_4_115200 },
4990 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 pbn_b1_bt_2_115200 },
4993 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995 pbn_b1_bt_4_115200 },
4996 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998 pbn_b1_bt_2_115200 },
46a0fac9
SB		 4999 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001 pbn_ni8430_2 },
5002 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 pbn_ni8430_2 },
5005 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007 pbn_ni8430_4 },
5008 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5010 pbn_ni8430_4 },
5011 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5013 pbn_ni8430_8 },
5014 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5016 pbn_ni8430_8 },
5017 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5019 pbn_ni8430_16 },
5020 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5022 pbn_ni8430_16 },
5023 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5025 pbn_ni8430_2 },
5026 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5028 pbn_ni8430_2 },
5029 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5031 pbn_ni8430_4 },
5032 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5034 pbn_ni8430_4 },
5035
02c9b5cf
KJ		 5036 /*
5037 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5038 */
5039 { PCI_VENDOR_ID_ADDIDATA,
5040 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5041 PCI_ANY_ID,
5042 PCI_ANY_ID,
5043 0,
5044 0,
5045 pbn_b0_4_115200 },
5046
5047 { PCI_VENDOR_ID_ADDIDATA,
5048 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5049 PCI_ANY_ID,
5050 PCI_ANY_ID,
5051 0,
5052 0,
5053 pbn_b0_2_115200 },
5054
5055 { PCI_VENDOR_ID_ADDIDATA,
5056 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5057 PCI_ANY_ID,
5058 PCI_ANY_ID,
5059 0,
5060 0,
5061 pbn_b0_1_115200 },
5062
086231f7 5063 { PCI_VENDOR_ID_AMCC,
57c1f0e9 5064 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 5065 PCI_ANY_ID,
5066 PCI_ANY_ID,
5067 0,
5068 0,
5069 pbn_b1_8_115200 },
5070
5071 { PCI_VENDOR_ID_ADDIDATA,
5072 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5073 PCI_ANY_ID,
5074 PCI_ANY_ID,
5075 0,
5076 0,
5077 pbn_b0_4_115200 },
5078
5079 { PCI_VENDOR_ID_ADDIDATA,
5080 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5081 PCI_ANY_ID,
5082 PCI_ANY_ID,
5083 0,
5084 0,
5085 pbn_b0_2_115200 },
5086
5087 { PCI_VENDOR_ID_ADDIDATA,
5088 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5089 PCI_ANY_ID,
5090 PCI_ANY_ID,
5091 0,
5092 0,
5093 pbn_b0_1_115200 },
5094
5095 { PCI_VENDOR_ID_ADDIDATA,
5096 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5097 PCI_ANY_ID,
5098 PCI_ANY_ID,
5099 0,
5100 0,
5101 pbn_b0_4_115200 },
5102
5103 { PCI_VENDOR_ID_ADDIDATA,
5104 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5105 PCI_ANY_ID,
5106 PCI_ANY_ID,
5107 0,
5108 0,
5109 pbn_b0_2_115200 },
5110
5111 { PCI_VENDOR_ID_ADDIDATA,
5112 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5113 PCI_ANY_ID,
5114 PCI_ANY_ID,
5115 0,
5116 0,
5117 pbn_b0_1_115200 },
5118
5119 { PCI_VENDOR_ID_ADDIDATA,
5120 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5121 PCI_ANY_ID,
5122 PCI_ANY_ID,
5123 0,
5124 0,
5125 pbn_b0_8_115200 },
5126
1b62cbf2
KJ		 5127 { PCI_VENDOR_ID_ADDIDATA,
5128 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5129 PCI_ANY_ID,
5130 PCI_ANY_ID,
5131 0,
5132 0,
5133 pbn_ADDIDATA_PCIe_4_3906250 },
5134
5135 { PCI_VENDOR_ID_ADDIDATA,
5136 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5137 PCI_ANY_ID,
5138 PCI_ANY_ID,
5139 0,
5140 0,
5141 pbn_ADDIDATA_PCIe_2_3906250 },
5142
5143 { PCI_VENDOR_ID_ADDIDATA,
5144 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5145 PCI_ANY_ID,
5146 PCI_ANY_ID,
5147 0,
5148 0,
5149 pbn_ADDIDATA_PCIe_1_3906250 },
5150
5151 { PCI_VENDOR_ID_ADDIDATA,
5152 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5153 PCI_ANY_ID,
5154 PCI_ANY_ID,
5155 0,
5156 0,
5157 pbn_ADDIDATA_PCIe_8_3906250 },
5158
25cf9bc1
JS		 5159 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5160 PCI_VENDOR_ID_IBM, 0x0299,
5161 0, 0, pbn_b0_bt_2_115200 },
5162
972ce085
SS		 5163 /*
5164 * other NetMos 9835 devices are most likely handled by the
5165 * parport_serial driver, check drivers/parport/parport_serial.c
5166 * before adding them here.
5167 */
5168
c4285b47
MB		 5169 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5170 0xA000, 0x1000,
5171 0, 0, pbn_b0_1_115200 },
5172
7808edcd
NG		 5173 /* the 9901 is a rebranded 9912 */
5174 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5175 0xA000, 0x1000,
5176 0, 0, pbn_b0_1_115200 },
5177
5178 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5179 0xA000, 0x1000,
5180 0, 0, pbn_b0_1_115200 },
5181
5182 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5183 0xA000, 0x1000,
5184 0, 0, pbn_b0_1_115200 },
5185
5186 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5187 0xA000, 0x1000,
5188 0, 0, pbn_b0_1_115200 },
5189
5190 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5191 0xA000, 0x3002,
5192 0, 0, pbn_NETMOS9900_2s_115200 },
5193
ac6ec5b1 5194 /*
44178176 5195 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5196 */
5197
5198 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5199 0xA000, 0x1000,
5200 0, 0, pbn_b0_1_115200 },
5201
44178176
ES		 5202 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5203 0xA000, 0x3002,
5204 0, 0, pbn_b0_bt_2_115200 },
5205
ac6ec5b1
IS		 5206 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5207 0xA000, 0x3004,
5208 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5209 /* Intel CE4100 */
5210 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5212 pbn_ce4100_1_115200 },
b15e5691
HK		 5213 /* Intel BayTrail */
5214 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5215 PCI_ANY_ID, PCI_ANY_ID,
5216 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5217 pbn_byt },
5218 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5219 PCI_ANY_ID, PCI_ANY_ID,
5220 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5221 pbn_byt },
095e24b0 5222
d9a0fbfd
AP		 5223 /*
5224 * Cronyx Omega PCI
5225 */
5226 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5228 pbn_omegapci },
ac6ec5b1 5229
ebebd49a
SH		 5230 /*
5231 * Broadcom TruManage
5232 */
5233 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5235 pbn_brcm_trumanage },
5236
6683549e
AC		 5237 /*
5238 * AgeStar as-prs2-009
5239 */
5240 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5241 PCI_ANY_ID, PCI_ANY_ID,
5242 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5243
5244 /*
5245 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5246 * so not listed here.
5247 */
5248 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5249 PCI_ANY_ID, PCI_ANY_ID,
5250 0, 0, pbn_b0_bt_4_115200 },
5251
5252 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5253 PCI_ANY_ID, PCI_ANY_ID,
5254 0, 0, pbn_b0_bt_2_115200 },
5255
8b5c913f
WY		 5256 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5257 PCI_ANY_ID, PCI_ANY_ID,
5258 0, 0, pbn_b0_bt_2_115200 },
5259
14faa8cc
MS		 5260 /*
5261 * Commtech, Inc. Fastcom adapters
5262 */
5263 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5264 PCI_ANY_ID, PCI_ANY_ID,
5265 0,
5266 0, pbn_b0_2_1152000_200 },
5267 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5268 PCI_ANY_ID, PCI_ANY_ID,
5269 0,
5270 0, pbn_b0_4_1152000_200 },
5271 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5272 PCI_ANY_ID, PCI_ANY_ID,
5273 0,
5274 0, pbn_b0_4_1152000_200 },
5275 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5276 PCI_ANY_ID, PCI_ANY_ID,
5277 0,
5278 0, pbn_b0_8_1152000_200 },
5279 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5280 PCI_ANY_ID, PCI_ANY_ID,
5281 0,
5282 0, pbn_exar_XR17V352 },
5283 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5284 PCI_ANY_ID, PCI_ANY_ID,
5285 0,
5286 0, pbn_exar_XR17V354 },
5287 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5288 PCI_ANY_ID, PCI_ANY_ID,
5289 0,
5290 0, pbn_exar_XR17V358 },
5291
2c62a3c8
GKH		 5292 /* Fintek PCI serial cards */
5293 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5294 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5295 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5296
1da177e4
LT		 5297 /*
5298 * These entries match devices with class COMMUNICATION_SERIAL,
5299 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5300 */
5301 { PCI_ANY_ID, PCI_ANY_ID,
5302 PCI_ANY_ID, PCI_ANY_ID,
5303 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5304 0xffff00, pbn_default },
5305 { PCI_ANY_ID, PCI_ANY_ID,
5306 PCI_ANY_ID, PCI_ANY_ID,
5307 PCI_CLASS_COMMUNICATION_MODEM << 8,
5308 0xffff00, pbn_default },
5309 { PCI_ANY_ID, PCI_ANY_ID,
5310 PCI_ANY_ID, PCI_ANY_ID,
5311 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5312 0xffff00, pbn_default },
5313 { 0, }
5314};
5315
2807190b
MR		 5316static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5317 pci_channel_state_t state)
5318{
5319 struct serial_private *priv = pci_get_drvdata(dev);
5320
5321 if (state == pci_channel_io_perm_failure)
5322 return PCI_ERS_RESULT_DISCONNECT;
5323
5324 if (priv)
5325 pciserial_suspend_ports(priv);
5326
5327 pci_disable_device(dev);
5328
5329 return PCI_ERS_RESULT_NEED_RESET;
5330}
5331
5332static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5333{
5334 int rc;
5335
5336 rc = pci_enable_device(dev);
5337
5338 if (rc)
5339 return PCI_ERS_RESULT_DISCONNECT;
5340
5341 pci_restore_state(dev);
5342 pci_save_state(dev);
5343
5344 return PCI_ERS_RESULT_RECOVERED;
5345}
5346
5347static void serial8250_io_resume(struct pci_dev *dev)
5348{
5349 struct serial_private *priv = pci_get_drvdata(dev);
5350
5351 if (priv)
5352 pciserial_resume_ports(priv);
5353}
5354
1d352035 5355static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5356 .error_detected = serial8250_io_error_detected,
5357 .slot_reset = serial8250_io_slot_reset,
5358 .resume = serial8250_io_resume,
5359};
5360
1da177e4
LT		 5361static struct pci_driver serial_pci_driver = {
5362 .name = "serial",
5363 .probe = pciserial_init_one,
2d47b716 5364 .remove = pciserial_remove_one,
1d5e7996 5365#ifdef CONFIG_PM
1da177e4
LT		 5366 .suspend = pciserial_suspend_one,
5367 .resume = pciserial_resume_one,
1d5e7996 5368#endif
1da177e4 5369 .id_table = serial_pci_tbl,
2807190b 5370 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5371};
5372
15a12e83 5373module_pci_driver(serial_pci_driver);
1da177e4
LT		 5374
5375MODULE_LICENSE("GPL");
5376MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5377MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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