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tty: serial: Add missing module license for 8250_base.ko
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_port.c
CommitLineData
b6830f6d
PH		 1/*
2 * Base port operations for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * A note about mapbase / membase
13 *
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
16 */
17
18#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/ioport.h>
25#include <linux/init.h>
26#include <linux/console.h>
27#include <linux/sysrq.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/tty.h>
31#include <linux/ratelimit.h>
32#include <linux/tty_flip.h>
33#include <linux/serial.h>
34#include <linux/serial_8250.h>
35#include <linux/nmi.h>
36#include <linux/mutex.h>
37#include <linux/slab.h>
38#include <linux/uaccess.h>
39#include <linux/pm_runtime.h>
40
41#include <asm/io.h>
42#include <asm/irq.h>
43
44#include "8250.h"
45
46/*
47 * Debugging.
48 */
49#if 0
50#define DEBUG_AUTOCONF(fmt...) printk(fmt)
51#else
52#define DEBUG_AUTOCONF(fmt...) do { } while (0)
53#endif
54
55#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
56
57/*
58 * Here we define the default xmit fifo size used for each type of UART.
59 */
60static const struct serial8250_config uart_config[] = {
61 [PORT_UNKNOWN] = {
62 .name = "unknown",
63 .fifo_size = 1,
64 .tx_loadsz = 1,
65 },
66 [PORT_8250] = {
67 .name = "8250",
68 .fifo_size = 1,
69 .tx_loadsz = 1,
70 },
71 [PORT_16450] = {
72 .name = "16450",
73 .fifo_size = 1,
74 .tx_loadsz = 1,
75 },
76 [PORT_16550] = {
77 .name = "16550",
78 .fifo_size = 1,
79 .tx_loadsz = 1,
80 },
81 [PORT_16550A] = {
82 .name = "16550A",
83 .fifo_size = 16,
84 .tx_loadsz = 16,
85 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
86 .rxtrig_bytes = {1, 4, 8, 14},
87 .flags = UART_CAP_FIFO,
88 },
89 [PORT_CIRRUS] = {
90 .name = "Cirrus",
91 .fifo_size = 1,
92 .tx_loadsz = 1,
93 },
94 [PORT_16650] = {
95 .name = "ST16650",
96 .fifo_size = 1,
97 .tx_loadsz = 1,
98 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
99 },
100 [PORT_16650V2] = {
101 .name = "ST16650V2",
102 .fifo_size = 32,
103 .tx_loadsz = 16,
104 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
105 UART_FCR_T_TRIG_00,
106 .rxtrig_bytes = {8, 16, 24, 28},
107 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
108 },
109 [PORT_16750] = {
110 .name = "TI16750",
111 .fifo_size = 64,
112 .tx_loadsz = 64,
113 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
114 UART_FCR7_64BYTE,
115 .rxtrig_bytes = {1, 16, 32, 56},
116 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
117 },
118 [PORT_STARTECH] = {
119 .name = "Startech",
120 .fifo_size = 1,
121 .tx_loadsz = 1,
122 },
123 [PORT_16C950] = {
124 .name = "16C950/954",
125 .fifo_size = 128,
126 .tx_loadsz = 128,
127 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
128 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
129 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
130 },
131 [PORT_16654] = {
132 .name = "ST16654",
133 .fifo_size = 64,
134 .tx_loadsz = 32,
135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
136 UART_FCR_T_TRIG_10,
137 .rxtrig_bytes = {8, 16, 56, 60},
138 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
139 },
140 [PORT_16850] = {
141 .name = "XR16850",
142 .fifo_size = 128,
143 .tx_loadsz = 128,
144 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
145 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
146 },
147 [PORT_RSA] = {
148 .name = "RSA",
149 .fifo_size = 2048,
150 .tx_loadsz = 2048,
151 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
152 .flags = UART_CAP_FIFO,
153 },
154 [PORT_NS16550A] = {
155 .name = "NS16550A",
156 .fifo_size = 16,
157 .tx_loadsz = 16,
158 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
159 .flags = UART_CAP_FIFO | UART_NATSEMI,
160 },
161 [PORT_XSCALE] = {
162 .name = "XScale",
163 .fifo_size = 32,
164 .tx_loadsz = 32,
165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
166 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
167 },
168 [PORT_OCTEON] = {
169 .name = "OCTEON",
170 .fifo_size = 64,
171 .tx_loadsz = 64,
172 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
173 .flags = UART_CAP_FIFO,
174 },
175 [PORT_AR7] = {
176 .name = "AR7",
177 .fifo_size = 16,
178 .tx_loadsz = 16,
179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
180 .flags = UART_CAP_FIFO | UART_CAP_AFE,
181 },
182 [PORT_U6_16550A] = {
183 .name = "U6_16550A",
184 .fifo_size = 64,
185 .tx_loadsz = 64,
186 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
187 .flags = UART_CAP_FIFO | UART_CAP_AFE,
188 },
189 [PORT_TEGRA] = {
190 .name = "Tegra",
191 .fifo_size = 32,
192 .tx_loadsz = 8,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
194 UART_FCR_T_TRIG_01,
195 .rxtrig_bytes = {1, 4, 8, 14},
196 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
197 },
198 [PORT_XR17D15X] = {
199 .name = "XR17D15X",
200 .fifo_size = 64,
201 .tx_loadsz = 64,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
204 UART_CAP_SLEEP,
205 },
206 [PORT_XR17V35X] = {
207 .name = "XR17V35X",
208 .fifo_size = 256,
209 .tx_loadsz = 256,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
211 UART_FCR_T_TRIG_11,
212 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
213 UART_CAP_SLEEP,
214 },
215 [PORT_LPC3220] = {
216 .name = "LPC3220",
217 .fifo_size = 64,
218 .tx_loadsz = 32,
219 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
220 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
221 .flags = UART_CAP_FIFO,
222 },
223 [PORT_BRCM_TRUMANAGE] = {
224 .name = "TruManage",
225 .fifo_size = 1,
226 .tx_loadsz = 1024,
227 .flags = UART_CAP_HFIFO,
228 },
229 [PORT_8250_CIR] = {
230 .name = "CIR port"
231 },
232 [PORT_ALTR_16550_F32] = {
233 .name = "Altera 16550 FIFO32",
234 .fifo_size = 32,
235 .tx_loadsz = 32,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
238 },
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
241 .fifo_size = 64,
242 .tx_loadsz = 64,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_CAP_AFE,
245 },
246 [PORT_ALTR_16550_F128] = {
247 .name = "Altera 16550 FIFO128",
248 .fifo_size = 128,
249 .tx_loadsz = 128,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
252 },
253/* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
254workaround of errata A-008006 which states that tx_loadsz should be
255configured less than Maximum supported fifo bytes */
256 [PORT_16550A_FSL64] = {
257 .name = "16550A_FSL64",
258 .fifo_size = 64,
259 .tx_loadsz = 63,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
261 UART_FCR7_64BYTE,
262 .flags = UART_CAP_FIFO,
263 },
264};
265
266/* Uart divisor latch read */
267static int default_serial_dl_read(struct uart_8250_port *up)
268{
269 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
270}
271
272/* Uart divisor latch write */
273static void default_serial_dl_write(struct uart_8250_port *up, int value)
274{
275 serial_out(up, UART_DLL, value & 0xff);
276 serial_out(up, UART_DLM, value >> 8 & 0xff);
277}
278
279#if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
280
281/* Au1x00/RT288x UART hardware has a weird register layout */
282static const s8 au_io_in_map[8] = {
283 0, /* UART_RX */
284 2, /* UART_IER */
285 3, /* UART_IIR */
286 5, /* UART_LCR */
287 6, /* UART_MCR */
288 7, /* UART_LSR */
289 8, /* UART_MSR */
290 -1, /* UART_SCR (unmapped) */
291};
292
293static const s8 au_io_out_map[8] = {
294 1, /* UART_TX */
295 2, /* UART_IER */
296 4, /* UART_FCR */
297 5, /* UART_LCR */
298 6, /* UART_MCR */
299 -1, /* UART_LSR (unmapped) */
300 -1, /* UART_MSR (unmapped) */
301 -1, /* UART_SCR (unmapped) */
302};
303
304static unsigned int au_serial_in(struct uart_port *p, int offset)
305{
306 if (offset >= ARRAY_SIZE(au_io_in_map))
307 return UINT_MAX;
308 offset = au_io_in_map[offset];
309 if (offset < 0)
310 return UINT_MAX;
311 return __raw_readl(p->membase + (offset << p->regshift));
312}
313
314static void au_serial_out(struct uart_port *p, int offset, int value)
315{
316 if (offset >= ARRAY_SIZE(au_io_out_map))
317 return;
318 offset = au_io_out_map[offset];
319 if (offset < 0)
320 return;
321 __raw_writel(value, p->membase + (offset << p->regshift));
322}
323
324/* Au1x00 haven't got a standard divisor latch */
325static int au_serial_dl_read(struct uart_8250_port *up)
326{
327 return __raw_readl(up->port.membase + 0x28);
328}
329
330static void au_serial_dl_write(struct uart_8250_port *up, int value)
331{
332 __raw_writel(value, up->port.membase + 0x28);
333}
334
335#endif
336
337static unsigned int hub6_serial_in(struct uart_port *p, int offset)
338{
339 offset = offset << p->regshift;
340 outb(p->hub6 - 1 + offset, p->iobase);
341 return inb(p->iobase + 1);
342}
343
344static void hub6_serial_out(struct uart_port *p, int offset, int value)
345{
346 offset = offset << p->regshift;
347 outb(p->hub6 - 1 + offset, p->iobase);
348 outb(value, p->iobase + 1);
349}
350
351static unsigned int mem_serial_in(struct uart_port *p, int offset)
352{
353 offset = offset << p->regshift;
354 return readb(p->membase + offset);
355}
356
357static void mem_serial_out(struct uart_port *p, int offset, int value)
358{
359 offset = offset << p->regshift;
360 writeb(value, p->membase + offset);
361}
362
363static void mem32_serial_out(struct uart_port *p, int offset, int value)
364{
365 offset = offset << p->regshift;
366 writel(value, p->membase + offset);
367}
368
369static unsigned int mem32_serial_in(struct uart_port *p, int offset)
370{
371 offset = offset << p->regshift;
372 return readl(p->membase + offset);
373}
374
375static void mem32be_serial_out(struct uart_port *p, int offset, int value)
376{
377 offset = offset << p->regshift;
378 iowrite32be(value, p->membase + offset);
379}
380
381static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
382{
383 offset = offset << p->regshift;
384 return ioread32be(p->membase + offset);
385}
386
387static unsigned int io_serial_in(struct uart_port *p, int offset)
388{
389 offset = offset << p->regshift;
390 return inb(p->iobase + offset);
391}
392
393static void io_serial_out(struct uart_port *p, int offset, int value)
394{
395 offset = offset << p->regshift;
396 outb(value, p->iobase + offset);
397}
398
399static int serial8250_default_handle_irq(struct uart_port *port);
400static int exar_handle_irq(struct uart_port *port);
401
402static void set_io_from_upio(struct uart_port *p)
403{
404 struct uart_8250_port *up = up_to_u8250p(p);
405
406 up->dl_read = default_serial_dl_read;
407 up->dl_write = default_serial_dl_write;
408
409 switch (p->iotype) {
410 case UPIO_HUB6:
411 p->serial_in = hub6_serial_in;
412 p->serial_out = hub6_serial_out;
413 break;
414
415 case UPIO_MEM:
416 p->serial_in = mem_serial_in;
417 p->serial_out = mem_serial_out;
418 break;
419
420 case UPIO_MEM32:
421 p->serial_in = mem32_serial_in;
422 p->serial_out = mem32_serial_out;
423 break;
424
425 case UPIO_MEM32BE:
426 p->serial_in = mem32be_serial_in;
427 p->serial_out = mem32be_serial_out;
428 break;
429
430#if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
431 case UPIO_AU:
432 p->serial_in = au_serial_in;
433 p->serial_out = au_serial_out;
434 up->dl_read = au_serial_dl_read;
435 up->dl_write = au_serial_dl_write;
436 break;
437#endif
438
439 default:
440 p->serial_in = io_serial_in;
441 p->serial_out = io_serial_out;
442 break;
443 }
444 /* Remember loaded iotype */
445 up->cur_iotype = p->iotype;
446 p->handle_irq = serial8250_default_handle_irq;
447}
448
449static void
450serial_port_out_sync(struct uart_port *p, int offset, int value)
451{
452 switch (p->iotype) {
453 case UPIO_MEM:
454 case UPIO_MEM32:
455 case UPIO_MEM32BE:
456 case UPIO_AU:
457 p->serial_out(p, offset, value);
458 p->serial_in(p, UART_LCR); /* safe, no side-effects */
459 break;
460 default:
461 p->serial_out(p, offset, value);
462 }
463}
464
465/*
466 * For the 16C950
467 */
468static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
469{
470 serial_out(up, UART_SCR, offset);
471 serial_out(up, UART_ICR, value);
472}
473
474static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
475{
476 unsigned int value;
477
478 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
479 serial_out(up, UART_SCR, offset);
480 value = serial_in(up, UART_ICR);
481 serial_icr_write(up, UART_ACR, up->acr);
482
483 return value;
484}
485
486/*
487 * FIFO support.
488 */
489static void serial8250_clear_fifos(struct uart_8250_port *p)
490{
491 if (p->capabilities & UART_CAP_FIFO) {
492 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
493 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
494 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
495 serial_out(p, UART_FCR, 0);
496 }
497}
498
499void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
500{
501 serial8250_clear_fifos(p);
502 serial_out(p, UART_FCR, p->fcr);
503}
504EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
505
506void serial8250_rpm_get(struct uart_8250_port *p)
507{
508 if (!(p->capabilities & UART_CAP_RPM))
509 return;
510 pm_runtime_get_sync(p->port.dev);
511}
512EXPORT_SYMBOL_GPL(serial8250_rpm_get);
513
514void serial8250_rpm_put(struct uart_8250_port *p)
515{
516 if (!(p->capabilities & UART_CAP_RPM))
517 return;
518 pm_runtime_mark_last_busy(p->port.dev);
519 pm_runtime_put_autosuspend(p->port.dev);
520}
521EXPORT_SYMBOL_GPL(serial8250_rpm_put);
522
523/*
524 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
525 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
526 * empty and the HW can idle again.
527 */
528static void serial8250_rpm_get_tx(struct uart_8250_port *p)
529{
530 unsigned char rpm_active;
531
532 if (!(p->capabilities & UART_CAP_RPM))
533 return;
534
535 rpm_active = xchg(&p->rpm_tx_active, 1);
536 if (rpm_active)
537 return;
538 pm_runtime_get_sync(p->port.dev);
539}
540
541static void serial8250_rpm_put_tx(struct uart_8250_port *p)
542{
543 unsigned char rpm_active;
544
545 if (!(p->capabilities & UART_CAP_RPM))
546 return;
547
548 rpm_active = xchg(&p->rpm_tx_active, 0);
549 if (!rpm_active)
550 return;
551 pm_runtime_mark_last_busy(p->port.dev);
552 pm_runtime_put_autosuspend(p->port.dev);
553}
554
555/*
556 * IER sleep support. UARTs which have EFRs need the "extended
557 * capability" bit enabled. Note that on XR16C850s, we need to
558 * reset LCR to write to IER.
559 */
560static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
561{
562 unsigned char lcr = 0, efr = 0;
563 /*
564 * Exar UARTs have a SLEEP register that enables or disables
565 * each UART to enter sleep mode separately. On the XR17V35x the
566 * register is accessible to each UART at the UART_EXAR_SLEEP
567 * offset but the UART channel may only write to the corresponding
568 * bit.
569 */
570 serial8250_rpm_get(p);
571 if ((p->port.type == PORT_XR17V35X) ||
572 (p->port.type == PORT_XR17D15X)) {
573 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
574 goto out;
575 }
576
577 if (p->capabilities & UART_CAP_SLEEP) {
578 if (p->capabilities & UART_CAP_EFR) {
579 lcr = serial_in(p, UART_LCR);
580 efr = serial_in(p, UART_EFR);
581 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
582 serial_out(p, UART_EFR, UART_EFR_ECB);
583 serial_out(p, UART_LCR, 0);
584 }
585 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
586 if (p->capabilities & UART_CAP_EFR) {
587 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
588 serial_out(p, UART_EFR, efr);
589 serial_out(p, UART_LCR, lcr);
590 }
591 }
592out:
593 serial8250_rpm_put(p);
594}
595
596#ifdef CONFIG_SERIAL_8250_RSA
597/*
598 * Attempts to turn on the RSA FIFO. Returns zero on failure.
599 * We set the port uart clock rate if we succeed.
600 */
601static int __enable_rsa(struct uart_8250_port *up)
602{
603 unsigned char mode;
604 int result;
605
606 mode = serial_in(up, UART_RSA_MSR);
607 result = mode & UART_RSA_MSR_FIFO;
608
609 if (!result) {
610 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
611 mode = serial_in(up, UART_RSA_MSR);
612 result = mode & UART_RSA_MSR_FIFO;
613 }
614
615 if (result)
616 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
617
618 return result;
619}
620
621static void enable_rsa(struct uart_8250_port *up)
622{
623 if (up->port.type == PORT_RSA) {
624 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
625 spin_lock_irq(&up->port.lock);
626 __enable_rsa(up);
627 spin_unlock_irq(&up->port.lock);
628 }
629 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
630 serial_out(up, UART_RSA_FRR, 0);
631 }
632}
633
634/*
635 * Attempts to turn off the RSA FIFO. Returns zero on failure.
636 * It is unknown why interrupts were disabled in here. However,
637 * the caller is expected to preserve this behaviour by grabbing
638 * the spinlock before calling this function.
639 */
640static void disable_rsa(struct uart_8250_port *up)
641{
642 unsigned char mode;
643 int result;
644
645 if (up->port.type == PORT_RSA &&
646 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
647 spin_lock_irq(&up->port.lock);
648
649 mode = serial_in(up, UART_RSA_MSR);
650 result = !(mode & UART_RSA_MSR_FIFO);
651
652 if (!result) {
653 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
654 mode = serial_in(up, UART_RSA_MSR);
655 result = !(mode & UART_RSA_MSR_FIFO);
656 }
657
658 if (result)
659 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
660 spin_unlock_irq(&up->port.lock);
661 }
662}
663#endif /* CONFIG_SERIAL_8250_RSA */
664
665/*
666 * This is a quickie test to see how big the FIFO is.
667 * It doesn't work at all the time, more's the pity.
668 */
669static int size_fifo(struct uart_8250_port *up)
670{
671 unsigned char old_fcr, old_mcr, old_lcr;
672 unsigned short old_dl;
673 int count;
674
675 old_lcr = serial_in(up, UART_LCR);
676 serial_out(up, UART_LCR, 0);
677 old_fcr = serial_in(up, UART_FCR);
678 old_mcr = serial_in(up, UART_MCR);
679 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
680 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
681 serial_out(up, UART_MCR, UART_MCR_LOOP);
682 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
683 old_dl = serial_dl_read(up);
684 serial_dl_write(up, 0x0001);
685 serial_out(up, UART_LCR, 0x03);
686 for (count = 0; count < 256; count++)
687 serial_out(up, UART_TX, count);
688 mdelay(20);/* FIXME - schedule_timeout */
689 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
690 (count < 256); count++)
691 serial_in(up, UART_RX);
692 serial_out(up, UART_FCR, old_fcr);
693 serial_out(up, UART_MCR, old_mcr);
694 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
695 serial_dl_write(up, old_dl);
696 serial_out(up, UART_LCR, old_lcr);
697
698 return count;
699}
700
701/*
702 * Read UART ID using the divisor method - set DLL and DLM to zero
703 * and the revision will be in DLL and device type in DLM. We
704 * preserve the device state across this.
705 */
706static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
707{
708 unsigned char old_dll, old_dlm, old_lcr;
709 unsigned int id;
710
711 old_lcr = serial_in(p, UART_LCR);
712 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
713
714 old_dll = serial_in(p, UART_DLL);
715 old_dlm = serial_in(p, UART_DLM);
716
717 serial_out(p, UART_DLL, 0);
718 serial_out(p, UART_DLM, 0);
719
720 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
721
722 serial_out(p, UART_DLL, old_dll);
723 serial_out(p, UART_DLM, old_dlm);
724 serial_out(p, UART_LCR, old_lcr);
725
726 return id;
727}
728
729/*
730 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
731 * When this function is called we know it is at least a StarTech
732 * 16650 V2, but it might be one of several StarTech UARTs, or one of
733 * its clones. (We treat the broken original StarTech 16650 V1 as a
734 * 16550, and why not? Startech doesn't seem to even acknowledge its
735 * existence.)
736 *
737 * What evil have men's minds wrought...
738 */
739static void autoconfig_has_efr(struct uart_8250_port *up)
740{
741 unsigned int id1, id2, id3, rev;
742
743 /*
744 * Everything with an EFR has SLEEP
745 */
746 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
747
748 /*
749 * First we check to see if it's an Oxford Semiconductor UART.
750 *
751 * If we have to do this here because some non-National
752 * Semiconductor clone chips lock up if you try writing to the
753 * LSR register (which serial_icr_read does)
754 */
755
756 /*
757 * Check for Oxford Semiconductor 16C950.
758 *
759 * EFR [4] must be set else this test fails.
760 *
761 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
762 * claims that it's needed for 952 dual UART's (which are not
763 * recommended for new designs).
764 */
765 up->acr = 0;
766 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
767 serial_out(up, UART_EFR, UART_EFR_ECB);
768 serial_out(up, UART_LCR, 0x00);
769 id1 = serial_icr_read(up, UART_ID1);
770 id2 = serial_icr_read(up, UART_ID2);
771 id3 = serial_icr_read(up, UART_ID3);
772 rev = serial_icr_read(up, UART_REV);
773
774 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
775
776 if (id1 == 0x16 && id2 == 0xC9 &&
777 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
778 up->port.type = PORT_16C950;
779
780 /*
781 * Enable work around for the Oxford Semiconductor 952 rev B
782 * chip which causes it to seriously miscalculate baud rates
783 * when DLL is 0.
784 */
785 if (id3 == 0x52 && rev == 0x01)
786 up->bugs |= UART_BUG_QUOT;
787 return;
788 }
789
790 /*
791 * We check for a XR16C850 by setting DLL and DLM to 0, and then
792 * reading back DLL and DLM. The chip type depends on the DLM
793 * value read back:
794 * 0x10 - XR16C850 and the DLL contains the chip revision.
795 * 0x12 - XR16C2850.
796 * 0x14 - XR16C854.
797 */
798 id1 = autoconfig_read_divisor_id(up);
799 DEBUG_AUTOCONF("850id=%04x ", id1);
800
801 id2 = id1 >> 8;
802 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
803 up->port.type = PORT_16850;
804 return;
805 }
806
807 /*
808 * It wasn't an XR16C850.
809 *
810 * We distinguish between the '654 and the '650 by counting
811 * how many bytes are in the FIFO. I'm using this for now,
812 * since that's the technique that was sent to me in the
813 * serial driver update, but I'm not convinced this works.
814 * I've had problems doing this in the past. -TYT
815 */
816 if (size_fifo(up) == 64)
817 up->port.type = PORT_16654;
818 else
819 up->port.type = PORT_16650V2;
820}
821
822/*
823 * We detected a chip without a FIFO. Only two fall into
824 * this category - the original 8250 and the 16450. The
825 * 16450 has a scratch register (accessible with LCR=0)
826 */
827static void autoconfig_8250(struct uart_8250_port *up)
828{
829 unsigned char scratch, status1, status2;
830
831 up->port.type = PORT_8250;
832
833 scratch = serial_in(up, UART_SCR);
834 serial_out(up, UART_SCR, 0xa5);
835 status1 = serial_in(up, UART_SCR);
836 serial_out(up, UART_SCR, 0x5a);
837 status2 = serial_in(up, UART_SCR);
838 serial_out(up, UART_SCR, scratch);
839
840 if (status1 == 0xa5 && status2 == 0x5a)
841 up->port.type = PORT_16450;
842}
843
844static int broken_efr(struct uart_8250_port *up)
845{
846 /*
847 * Exar ST16C2550 "A2" devices incorrectly detect as
848 * having an EFR, and report an ID of 0x0201. See
849 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
850 */
851 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
852 return 1;
853
854 return 0;
855}
856
857/*
858 * We know that the chip has FIFOs. Does it have an EFR? The
859 * EFR is located in the same register position as the IIR and
860 * we know the top two bits of the IIR are currently set. The
861 * EFR should contain zero. Try to read the EFR.
862 */
863static void autoconfig_16550a(struct uart_8250_port *up)
864{
865 unsigned char status1, status2;
866 unsigned int iersave;
867
868 up->port.type = PORT_16550A;
869 up->capabilities |= UART_CAP_FIFO;
870
871 /*
872 * XR17V35x UARTs have an extra divisor register, DLD
873 * that gets enabled with when DLAB is set which will
874 * cause the device to incorrectly match and assign
875 * port type to PORT_16650. The EFR for this UART is
876 * found at offset 0x09. Instead check the Deice ID (DVID)
877 * register for a 2, 4 or 8 port UART.
878 */
879 if (up->port.flags & UPF_EXAR_EFR) {
880 status1 = serial_in(up, UART_EXAR_DVID);
881 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
882 DEBUG_AUTOCONF("Exar XR17V35x ");
883 up->port.type = PORT_XR17V35X;
884 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
885 UART_CAP_SLEEP;
886
887 return;
888 }
889
890 }
891
892 /*
893 * Check for presence of the EFR when DLAB is set.
894 * Only ST16C650V1 UARTs pass this test.
895 */
896 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
897 if (serial_in(up, UART_EFR) == 0) {
898 serial_out(up, UART_EFR, 0xA8);
899 if (serial_in(up, UART_EFR) != 0) {
900 DEBUG_AUTOCONF("EFRv1 ");
901 up->port.type = PORT_16650;
902 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
903 } else {
904 serial_out(up, UART_LCR, 0);
905 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
906 UART_FCR7_64BYTE);
907 status1 = serial_in(up, UART_IIR) >> 5;
908 serial_out(up, UART_FCR, 0);
909 serial_out(up, UART_LCR, 0);
910
911 if (status1 == 7)
912 up->port.type = PORT_16550A_FSL64;
913 else
914 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
915 }
916 serial_out(up, UART_EFR, 0);
917 return;
918 }
919
920 /*
921 * Maybe it requires 0xbf to be written to the LCR.
922 * (other ST16C650V2 UARTs, TI16C752A, etc)
923 */
924 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
925 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
926 DEBUG_AUTOCONF("EFRv2 ");
927 autoconfig_has_efr(up);
928 return;
929 }
930
931 /*
932 * Check for a National Semiconductor SuperIO chip.
933 * Attempt to switch to bank 2, read the value of the LOOP bit
934 * from EXCR1. Switch back to bank 0, change it in MCR. Then
935 * switch back to bank 2, read it from EXCR1 again and check
936 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
937 */
938 serial_out(up, UART_LCR, 0);
939 status1 = serial_in(up, UART_MCR);
940 serial_out(up, UART_LCR, 0xE0);
941 status2 = serial_in(up, 0x02); /* EXCR1 */
942
943 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
944 serial_out(up, UART_LCR, 0);
945 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
946 serial_out(up, UART_LCR, 0xE0);
947 status2 = serial_in(up, 0x02); /* EXCR1 */
948 serial_out(up, UART_LCR, 0);
949 serial_out(up, UART_MCR, status1);
950
951 if ((status2 ^ status1) & UART_MCR_LOOP) {
952 unsigned short quot;
953
954 serial_out(up, UART_LCR, 0xE0);
955
956 quot = serial_dl_read(up);
957 quot <<= 3;
958
959 if (ns16550a_goto_highspeed(up))
960 serial_dl_write(up, quot);
961
962 serial_out(up, UART_LCR, 0);
963
964 up->port.uartclk = 921600*16;
965 up->port.type = PORT_NS16550A;
966 up->capabilities |= UART_NATSEMI;
967 return;
968 }
969 }
970
971 /*
972 * No EFR. Try to detect a TI16750, which only sets bit 5 of
973 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
974 * Try setting it with and without DLAB set. Cheap clones
975 * set bit 5 without DLAB set.
976 */
977 serial_out(up, UART_LCR, 0);
978 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
979 status1 = serial_in(up, UART_IIR) >> 5;
980 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
981 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
982 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
983 status2 = serial_in(up, UART_IIR) >> 5;
984 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
985 serial_out(up, UART_LCR, 0);
986
987 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
988
989 if (status1 == 6 && status2 == 7) {
990 up->port.type = PORT_16750;
991 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
992 return;
993 }
994
995 /*
996 * Try writing and reading the UART_IER_UUE bit (b6).
997 * If it works, this is probably one of the Xscale platform's
998 * internal UARTs.
999 * We're going to explicitly set the UUE bit to 0 before
1000 * trying to write and read a 1 just to make sure it's not
1001 * already a 1 and maybe locked there before we even start start.
1002 */
1003 iersave = serial_in(up, UART_IER);
1004 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1005 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1006 /*
1007 * OK it's in a known zero state, try writing and reading
1008 * without disturbing the current state of the other bits.
1009 */
1010 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1011 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1012 /*
1013 * It's an Xscale.
1014 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1015 */
1016 DEBUG_AUTOCONF("Xscale ");
1017 up->port.type = PORT_XSCALE;
1018 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1019 return;
1020 }
1021 } else {
1022 /*
1023 * If we got here we couldn't force the IER_UUE bit to 0.
1024 * Log it and continue.
1025 */
1026 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1027 }
1028 serial_out(up, UART_IER, iersave);
1029
1030 /*
1031 * Exar uarts have EFR in a weird location
1032 */
1033 if (up->port.flags & UPF_EXAR_EFR) {
1034 DEBUG_AUTOCONF("Exar XR17D15x ");
1035 up->port.type = PORT_XR17D15X;
1036 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1037 UART_CAP_SLEEP;
1038
1039 return;
1040 }
1041
1042 /*
1043 * We distinguish between 16550A and U6 16550A by counting
1044 * how many bytes are in the FIFO.
1045 */
1046 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1047 up->port.type = PORT_U6_16550A;
1048 up->capabilities |= UART_CAP_AFE;
1049 }
1050}
1051
1052/*
1053 * This routine is called by rs_init() to initialize a specific serial
1054 * port. It determines what type of UART chip this serial port is
1055 * using: 8250, 16450, 16550, 16550A. The important question is
1056 * whether or not this UART is a 16550A or not, since this will
1057 * determine whether or not we can use its FIFO features or not.
1058 */
1059static void autoconfig(struct uart_8250_port *up)
1060{
1061 unsigned char status1, scratch, scratch2, scratch3;
1062 unsigned char save_lcr, save_mcr;
1063 struct uart_port *port = &up->port;
1064 unsigned long flags;
1065 unsigned int old_capabilities;
1066
1067 if (!port->iobase && !port->mapbase && !port->membase)
1068 return;
1069
1070 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1071 serial_index(port), port->iobase, port->membase);
1072
1073 /*
1074 * We really do need global IRQs disabled here - we're going to
1075 * be frobbing the chips IRQ enable register to see if it exists.
1076 */
1077 spin_lock_irqsave(&port->lock, flags);
1078
1079 up->capabilities = 0;
1080 up->bugs = 0;
1081
1082 if (!(port->flags & UPF_BUGGY_UART)) {
1083 /*
1084 * Do a simple existence test first; if we fail this,
1085 * there's no point trying anything else.
1086 *
1087 * 0x80 is used as a nonsense port to prevent against
1088 * false positives due to ISA bus float. The
1089 * assumption is that 0x80 is a non-existent port;
1090 * which should be safe since include/asm/io.h also
1091 * makes this assumption.
1092 *
1093 * Note: this is safe as long as MCR bit 4 is clear
1094 * and the device is in "PC" mode.
1095 */
1096 scratch = serial_in(up, UART_IER);
1097 serial_out(up, UART_IER, 0);
1098#ifdef __i386__
1099 outb(0xff, 0x080);
1100#endif
1101 /*
1102 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1103 * 16C754B) allow only to modify them if an EFR bit is set.
1104 */
1105 scratch2 = serial_in(up, UART_IER) & 0x0f;
1106 serial_out(up, UART_IER, 0x0F);
1107#ifdef __i386__
1108 outb(0, 0x080);
1109#endif
1110 scratch3 = serial_in(up, UART_IER) & 0x0f;
1111 serial_out(up, UART_IER, scratch);
1112 if (scratch2 != 0 || scratch3 != 0x0F) {
1113 /*
1114 * We failed; there's nothing here
1115 */
1116 spin_unlock_irqrestore(&port->lock, flags);
1117 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1118 scratch2, scratch3);
1119 goto out;
1120 }
1121 }
1122
1123 save_mcr = serial_in(up, UART_MCR);
1124 save_lcr = serial_in(up, UART_LCR);
1125
1126 /*
1127 * Check to see if a UART is really there. Certain broken
1128 * internal modems based on the Rockwell chipset fail this
1129 * test, because they apparently don't implement the loopback
1130 * test mode. So this test is skipped on the COM 1 through
1131 * COM 4 ports. This *should* be safe, since no board
1132 * manufacturer would be stupid enough to design a board
1133 * that conflicts with COM 1-4 --- we hope!
1134 */
1135 if (!(port->flags & UPF_SKIP_TEST)) {
1136 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1137 status1 = serial_in(up, UART_MSR) & 0xF0;
1138 serial_out(up, UART_MCR, save_mcr);
1139 if (status1 != 0x90) {
1140 spin_unlock_irqrestore(&port->lock, flags);
1141 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1142 status1);
1143 goto out;
1144 }
1145 }
1146
1147 /*
1148 * We're pretty sure there's a port here. Lets find out what
1149 * type of port it is. The IIR top two bits allows us to find
1150 * out if it's 8250 or 16450, 16550, 16550A or later. This
1151 * determines what we test for next.
1152 *
1153 * We also initialise the EFR (if any) to zero for later. The
1154 * EFR occupies the same register location as the FCR and IIR.
1155 */
1156 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1157 serial_out(up, UART_EFR, 0);
1158 serial_out(up, UART_LCR, 0);
1159
1160 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1161 scratch = serial_in(up, UART_IIR) >> 6;
1162
1163 switch (scratch) {
1164 case 0:
1165 autoconfig_8250(up);
1166 break;
1167 case 1:
1168 port->type = PORT_UNKNOWN;
1169 break;
1170 case 2:
1171 port->type = PORT_16550;
1172 break;
1173 case 3:
1174 autoconfig_16550a(up);
1175 break;
1176 }
1177
1178#ifdef CONFIG_SERIAL_8250_RSA
1179 /*
1180 * Only probe for RSA ports if we got the region.
1181 */
1182 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1183 __enable_rsa(up))
1184 port->type = PORT_RSA;
1185#endif
1186
1187 serial_out(up, UART_LCR, save_lcr);
1188
1189 port->fifosize = uart_config[up->port.type].fifo_size;
1190 old_capabilities = up->capabilities;
1191 up->capabilities = uart_config[port->type].flags;
1192 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1193
1194 if (port->type == PORT_UNKNOWN)
1195 goto out_lock;
1196
1197 /*
1198 * Reset the UART.
1199 */
1200#ifdef CONFIG_SERIAL_8250_RSA
1201 if (port->type == PORT_RSA)
1202 serial_out(up, UART_RSA_FRR, 0);
1203#endif
1204 serial_out(up, UART_MCR, save_mcr);
1205 serial8250_clear_fifos(up);
1206 serial_in(up, UART_RX);
1207 if (up->capabilities & UART_CAP_UUE)
1208 serial_out(up, UART_IER, UART_IER_UUE);
1209 else
1210 serial_out(up, UART_IER, 0);
1211
1212out_lock:
1213 spin_unlock_irqrestore(&port->lock, flags);
1214 if (up->capabilities != old_capabilities) {
1215 printk(KERN_WARNING
1216 "ttyS%d: detected caps %08x should be %08x\n",
1217 serial_index(port), old_capabilities,
1218 up->capabilities);
1219 }
1220out:
1221 DEBUG_AUTOCONF("iir=%d ", scratch);
1222 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1223}
1224
1225static void autoconfig_irq(struct uart_8250_port *up)
1226{
1227 struct uart_port *port = &up->port;
1228 unsigned char save_mcr, save_ier;
1229 unsigned char save_ICP = 0;
1230 unsigned int ICP = 0;
1231 unsigned long irqs;
1232 int irq;
1233
1234 if (port->flags & UPF_FOURPORT) {
1235 ICP = (port->iobase & 0xfe0) | 0x1f;
1236 save_ICP = inb_p(ICP);
1237 outb_p(0x80, ICP);
1238 inb_p(ICP);
1239 }
1240
1241 /* forget possible initially masked and pending IRQ */
1242 probe_irq_off(probe_irq_on());
1243 save_mcr = serial_in(up, UART_MCR);
1244 save_ier = serial_in(up, UART_IER);
1245 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1246
1247 irqs = probe_irq_on();
1248 serial_out(up, UART_MCR, 0);
1249 udelay(10);
1250 if (port->flags & UPF_FOURPORT) {
1251 serial_out(up, UART_MCR,
1252 UART_MCR_DTR | UART_MCR_RTS);
1253 } else {
1254 serial_out(up, UART_MCR,
1255 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1256 }
1257 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1258 serial_in(up, UART_LSR);
1259 serial_in(up, UART_RX);
1260 serial_in(up, UART_IIR);
1261 serial_in(up, UART_MSR);
1262 serial_out(up, UART_TX, 0xFF);
1263 udelay(20);
1264 irq = probe_irq_off(irqs);
1265
1266 serial_out(up, UART_MCR, save_mcr);
1267 serial_out(up, UART_IER, save_ier);
1268
1269 if (port->flags & UPF_FOURPORT)
1270 outb_p(save_ICP, ICP);
1271
1272 port->irq = (irq > 0) ? irq : 0;
1273}
1274
1275static inline void __stop_tx(struct uart_8250_port *p)
1276{
1277 if (p->ier & UART_IER_THRI) {
1278 p->ier &= ~UART_IER_THRI;
1279 serial_out(p, UART_IER, p->ier);
1280 serial8250_rpm_put_tx(p);
1281 }
1282}
1283
1284static void serial8250_stop_tx(struct uart_port *port)
1285{
1286 struct uart_8250_port *up = up_to_u8250p(port);
1287
1288 serial8250_rpm_get(up);
1289 __stop_tx(up);
1290
1291 /*
1292 * We really want to stop the transmitter from sending.
1293 */
1294 if (port->type == PORT_16C950) {
1295 up->acr |= UART_ACR_TXDIS;
1296 serial_icr_write(up, UART_ACR, up->acr);
1297 }
1298 serial8250_rpm_put(up);
1299}
1300
1301static void serial8250_start_tx(struct uart_port *port)
1302{
1303 struct uart_8250_port *up = up_to_u8250p(port);
1304
1305 serial8250_rpm_get_tx(up);
1306
1307 if (up->dma && !up->dma->tx_dma(up))
1308 return;
1309
1310 if (!(up->ier & UART_IER_THRI)) {
1311 up->ier |= UART_IER_THRI;
1312 serial_port_out(port, UART_IER, up->ier);
1313
1314 if (up->bugs & UART_BUG_TXEN) {
1315 unsigned char lsr;
1316 lsr = serial_in(up, UART_LSR);
1317 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1318 if (lsr & UART_LSR_THRE)
1319 serial8250_tx_chars(up);
1320 }
1321 }
1322
1323 /*
1324 * Re-enable the transmitter if we disabled it.
1325 */
1326 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1327 up->acr &= ~UART_ACR_TXDIS;
1328 serial_icr_write(up, UART_ACR, up->acr);
1329 }
1330}
1331
1332static void serial8250_throttle(struct uart_port *port)
1333{
1334 port->throttle(port);
1335}
1336
1337static void serial8250_unthrottle(struct uart_port *port)
1338{
1339 port->unthrottle(port);
1340}
1341
1342static void serial8250_stop_rx(struct uart_port *port)
1343{
1344 struct uart_8250_port *up = up_to_u8250p(port);
1345
1346 serial8250_rpm_get(up);
1347
1348 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1349 up->port.read_status_mask &= ~UART_LSR_DR;
1350 serial_port_out(port, UART_IER, up->ier);
1351
1352 serial8250_rpm_put(up);
1353}
1354
1355static void serial8250_disable_ms(struct uart_port *port)
1356{
1357 struct uart_8250_port *up =
1358 container_of(port, struct uart_8250_port, port);
1359
1360 /* no MSR capabilities */
1361 if (up->bugs & UART_BUG_NOMSR)
1362 return;
1363
1364 up->ier &= ~UART_IER_MSI;
1365 serial_port_out(port, UART_IER, up->ier);
1366}
1367
1368static void serial8250_enable_ms(struct uart_port *port)
1369{
1370 struct uart_8250_port *up = up_to_u8250p(port);
1371
1372 /* no MSR capabilities */
1373 if (up->bugs & UART_BUG_NOMSR)
1374 return;
1375
1376 up->ier |= UART_IER_MSI;
1377
1378 serial8250_rpm_get(up);
1379 serial_port_out(port, UART_IER, up->ier);
1380 serial8250_rpm_put(up);
1381}
1382
1383/*
1384 * serial8250_rx_chars: processes according to the passed in LSR
1385 * value, and returns the remaining LSR bits not handled
1386 * by this Rx routine.
1387 */
1388unsigned char
1389serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1390{
1391 struct uart_port *port = &up->port;
1392 unsigned char ch;
1393 int max_count = 256;
1394 char flag;
1395
1396 do {
1397 if (likely(lsr & UART_LSR_DR))
1398 ch = serial_in(up, UART_RX);
1399 else
1400 /*
1401 * Intel 82571 has a Serial Over Lan device that will
1402 * set UART_LSR_BI without setting UART_LSR_DR when
1403 * it receives a break. To avoid reading from the
1404 * receive buffer without UART_LSR_DR bit set, we
1405 * just force the read character to be 0
1406 */
1407 ch = 0;
1408
1409 flag = TTY_NORMAL;
1410 port->icount.rx++;
1411
1412 lsr |= up->lsr_saved_flags;
1413 up->lsr_saved_flags = 0;
1414
1415 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1416 if (lsr & UART_LSR_BI) {
1417 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1418 port->icount.brk++;
1419 /*
1420 * We do the SysRQ and SAK checking
1421 * here because otherwise the break
1422 * may get masked by ignore_status_mask
1423 * or read_status_mask.
1424 */
1425 if (uart_handle_break(port))
1426 goto ignore_char;
1427 } else if (lsr & UART_LSR_PE)
1428 port->icount.parity++;
1429 else if (lsr & UART_LSR_FE)
1430 port->icount.frame++;
1431 if (lsr & UART_LSR_OE)
1432 port->icount.overrun++;
1433
1434 /*
1435 * Mask off conditions which should be ignored.
1436 */
1437 lsr &= port->read_status_mask;
1438
1439 if (lsr & UART_LSR_BI) {
1440 DEBUG_INTR("handling break....");
1441 flag = TTY_BREAK;
1442 } else if (lsr & UART_LSR_PE)
1443 flag = TTY_PARITY;
1444 else if (lsr & UART_LSR_FE)
1445 flag = TTY_FRAME;
1446 }
1447 if (uart_handle_sysrq_char(port, ch))
1448 goto ignore_char;
1449
1450 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1451
1452ignore_char:
1453 lsr = serial_in(up, UART_LSR);
1454 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0));
1455 spin_unlock(&port->lock);
1456 tty_flip_buffer_push(&port->state->port);
1457 spin_lock(&port->lock);
1458 return lsr;
1459}
1460EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1461
1462void serial8250_tx_chars(struct uart_8250_port *up)
1463{
1464 struct uart_port *port = &up->port;
1465 struct circ_buf *xmit = &port->state->xmit;
1466 int count;
1467
1468 if (port->x_char) {
1469 serial_out(up, UART_TX, port->x_char);
1470 port->icount.tx++;
1471 port->x_char = 0;
1472 return;
1473 }
1474 if (uart_tx_stopped(port)) {
1475 serial8250_stop_tx(port);
1476 return;
1477 }
1478 if (uart_circ_empty(xmit)) {
1479 __stop_tx(up);
1480 return;
1481 }
1482
1483 count = up->tx_loadsz;
1484 do {
1485 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1486 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1487 port->icount.tx++;
1488 if (uart_circ_empty(xmit))
1489 break;
1490 if (up->capabilities & UART_CAP_HFIFO) {
1491 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1492 BOTH_EMPTY)
1493 break;
1494 }
1495 } while (--count > 0);
1496
1497 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1498 uart_write_wakeup(port);
1499
1500 DEBUG_INTR("THRE...");
1501
1502 /*
1503 * With RPM enabled, we have to wait until the FIFO is empty before the
1504 * HW can go idle. So we get here once again with empty FIFO and disable
1505 * the interrupt and RPM in __stop_tx()
1506 */
1507 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1508 __stop_tx(up);
1509}
1510EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1511
1512/* Caller holds uart port lock */
1513unsigned int serial8250_modem_status(struct uart_8250_port *up)
1514{
1515 struct uart_port *port = &up->port;
1516 unsigned int status = serial_in(up, UART_MSR);
1517
1518 status |= up->msr_saved_flags;
1519 up->msr_saved_flags = 0;
1520 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1521 port->state != NULL) {
1522 if (status & UART_MSR_TERI)
1523 port->icount.rng++;
1524 if (status & UART_MSR_DDSR)
1525 port->icount.dsr++;
1526 if (status & UART_MSR_DDCD)
1527 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1528 if (status & UART_MSR_DCTS)
1529 uart_handle_cts_change(port, status & UART_MSR_CTS);
1530
1531 wake_up_interruptible(&port->state->port.delta_msr_wait);
1532 }
1533
1534 return status;
1535}
1536EXPORT_SYMBOL_GPL(serial8250_modem_status);
1537
1538/*
1539 * This handles the interrupt from one port.
1540 */
1541int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1542{
1543 unsigned char status;
1544 unsigned long flags;
1545 struct uart_8250_port *up = up_to_u8250p(port);
1546 int dma_err = 0;
1547
1548 if (iir & UART_IIR_NO_INT)
1549 return 0;
1550
1551 spin_lock_irqsave(&port->lock, flags);
1552
1553 status = serial_port_in(port, UART_LSR);
1554
1555 DEBUG_INTR("status = %x...", status);
1556
1557 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1558 if (up->dma)
1559 dma_err = up->dma->rx_dma(up, iir);
1560
1561 if (!up->dma || dma_err)
1562 status = serial8250_rx_chars(up, status);
1563 }
1564 serial8250_modem_status(up);
1565 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1566 (status & UART_LSR_THRE))
1567 serial8250_tx_chars(up);
1568
1569 spin_unlock_irqrestore(&port->lock, flags);
1570 return 1;
1571}
1572EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1573
1574static int serial8250_default_handle_irq(struct uart_port *port)
1575{
1576 struct uart_8250_port *up = up_to_u8250p(port);
1577 unsigned int iir;
1578 int ret;
1579
1580 serial8250_rpm_get(up);
1581
1582 iir = serial_port_in(port, UART_IIR);
1583 ret = serial8250_handle_irq(port, iir);
1584
1585 serial8250_rpm_put(up);
1586 return ret;
1587}
1588
1589/*
1590 * These Exar UARTs have an extra interrupt indicator that could
1591 * fire for a few unimplemented interrupts. One of which is a
1592 * wakeup event when coming out of sleep. Put this here just
1593 * to be on the safe side that these interrupts don't go unhandled.
1594 */
1595static int exar_handle_irq(struct uart_port *port)
1596{
1597 unsigned char int0, int1, int2, int3;
1598 unsigned int iir = serial_port_in(port, UART_IIR);
1599 int ret;
1600
1601 ret = serial8250_handle_irq(port, iir);
1602
1603 if ((port->type == PORT_XR17V35X) ||
1604 (port->type == PORT_XR17D15X)) {
1605 int0 = serial_port_in(port, 0x80);
1606 int1 = serial_port_in(port, 0x81);
1607 int2 = serial_port_in(port, 0x82);
1608 int3 = serial_port_in(port, 0x83);
1609 }
1610
1611 return ret;
1612}
1613
1614static unsigned int serial8250_tx_empty(struct uart_port *port)
1615{
1616 struct uart_8250_port *up = up_to_u8250p(port);
1617 unsigned long flags;
1618 unsigned int lsr;
1619
1620 serial8250_rpm_get(up);
1621
1622 spin_lock_irqsave(&port->lock, flags);
1623 lsr = serial_port_in(port, UART_LSR);
1624 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1625 spin_unlock_irqrestore(&port->lock, flags);
1626
1627 serial8250_rpm_put(up);
1628
1629 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1630}
1631
1632static unsigned int serial8250_get_mctrl(struct uart_port *port)
1633{
1634 struct uart_8250_port *up = up_to_u8250p(port);
1635 unsigned int status;
1636 unsigned int ret;
1637
1638 serial8250_rpm_get(up);
1639 status = serial8250_modem_status(up);
1640 serial8250_rpm_put(up);
1641
1642 ret = 0;
1643 if (status & UART_MSR_DCD)
1644 ret |= TIOCM_CAR;
1645 if (status & UART_MSR_RI)
1646 ret |= TIOCM_RNG;
1647 if (status & UART_MSR_DSR)
1648 ret |= TIOCM_DSR;
1649 if (status & UART_MSR_CTS)
1650 ret |= TIOCM_CTS;
1651 return ret;
1652}
1653
1654void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1655{
1656 struct uart_8250_port *up = up_to_u8250p(port);
1657 unsigned char mcr = 0;
1658
1659 if (mctrl & TIOCM_RTS)
1660 mcr |= UART_MCR_RTS;
1661 if (mctrl & TIOCM_DTR)
1662 mcr |= UART_MCR_DTR;
1663 if (mctrl & TIOCM_OUT1)
1664 mcr |= UART_MCR_OUT1;
1665 if (mctrl & TIOCM_OUT2)
1666 mcr |= UART_MCR_OUT2;
1667 if (mctrl & TIOCM_LOOP)
1668 mcr |= UART_MCR_LOOP;
1669
1670 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1671
1672 serial_port_out(port, UART_MCR, mcr);
1673}
1674EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1675
1676static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1677{
1678 if (port->set_mctrl)
1679 port->set_mctrl(port, mctrl);
1680 else
1681 serial8250_do_set_mctrl(port, mctrl);
1682}
1683
1684static void serial8250_break_ctl(struct uart_port *port, int break_state)
1685{
1686 struct uart_8250_port *up = up_to_u8250p(port);
1687 unsigned long flags;
1688
1689 serial8250_rpm_get(up);
1690 spin_lock_irqsave(&port->lock, flags);
1691 if (break_state == -1)
1692 up->lcr |= UART_LCR_SBC;
1693 else
1694 up->lcr &= ~UART_LCR_SBC;
1695 serial_port_out(port, UART_LCR, up->lcr);
1696 spin_unlock_irqrestore(&port->lock, flags);
1697 serial8250_rpm_put(up);
1698}
1699
1700/*
1701 * Wait for transmitter & holding register to empty
1702 */
1703static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1704{
1705 unsigned int status, tmout = 10000;
1706
1707 /* Wait up to 10ms for the character(s) to be sent. */
1708 for (;;) {
1709 status = serial_in(up, UART_LSR);
1710
1711 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1712
1713 if ((status & bits) == bits)
1714 break;
1715 if (--tmout == 0)
1716 break;
1717 udelay(1);
1718 }
1719
1720 /* Wait up to 1s for flow control if necessary */
1721 if (up->port.flags & UPF_CONS_FLOW) {
1722 unsigned int tmout;
1723 for (tmout = 1000000; tmout; tmout--) {
1724 unsigned int msr = serial_in(up, UART_MSR);
1725 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1726 if (msr & UART_MSR_CTS)
1727 break;
1728 udelay(1);
1729 touch_nmi_watchdog();
1730 }
1731 }
1732}
1733
1734#ifdef CONFIG_CONSOLE_POLL
1735/*
1736 * Console polling routines for writing and reading from the uart while
1737 * in an interrupt or debug context.
1738 */
1739
1740static int serial8250_get_poll_char(struct uart_port *port)
1741{
1742 struct uart_8250_port *up = up_to_u8250p(port);
1743 unsigned char lsr;
1744 int status;
1745
1746 serial8250_rpm_get(up);
1747
1748 lsr = serial_port_in(port, UART_LSR);
1749
1750 if (!(lsr & UART_LSR_DR)) {
1751 status = NO_POLL_CHAR;
1752 goto out;
1753 }
1754
1755 status = serial_port_in(port, UART_RX);
1756out:
1757 serial8250_rpm_put(up);
1758 return status;
1759}
1760
1761
1762static void serial8250_put_poll_char(struct uart_port *port,
1763 unsigned char c)
1764{
1765 unsigned int ier;
1766 struct uart_8250_port *up = up_to_u8250p(port);
1767
1768 serial8250_rpm_get(up);
1769 /*
1770 * First save the IER then disable the interrupts
1771 */
1772 ier = serial_port_in(port, UART_IER);
1773 if (up->capabilities & UART_CAP_UUE)
1774 serial_port_out(port, UART_IER, UART_IER_UUE);
1775 else
1776 serial_port_out(port, UART_IER, 0);
1777
1778 wait_for_xmitr(up, BOTH_EMPTY);
1779 /*
1780 * Send the character out.
1781 */
1782 serial_port_out(port, UART_TX, c);
1783
1784 /*
1785 * Finally, wait for transmitter to become empty
1786 * and restore the IER
1787 */
1788 wait_for_xmitr(up, BOTH_EMPTY);
1789 serial_port_out(port, UART_IER, ier);
1790 serial8250_rpm_put(up);
1791}
1792
1793#endif /* CONFIG_CONSOLE_POLL */
1794
1795int serial8250_do_startup(struct uart_port *port)
1796{
1797 struct uart_8250_port *up = up_to_u8250p(port);
1798 unsigned long flags;
1799 unsigned char lsr, iir;
1800 int retval;
1801
1802 if (port->type == PORT_8250_CIR)
1803 return -ENODEV;
1804
1805 if (!port->fifosize)
1806 port->fifosize = uart_config[port->type].fifo_size;
1807 if (!up->tx_loadsz)
1808 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1809 if (!up->capabilities)
1810 up->capabilities = uart_config[port->type].flags;
1811 up->mcr = 0;
1812
1813 if (port->iotype != up->cur_iotype)
1814 set_io_from_upio(port);
1815
1816 serial8250_rpm_get(up);
1817 if (port->type == PORT_16C950) {
1818 /* Wake up and initialize UART */
1819 up->acr = 0;
1820 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1821 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1822 serial_port_out(port, UART_IER, 0);
1823 serial_port_out(port, UART_LCR, 0);
1824 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1825 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1826 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1827 serial_port_out(port, UART_LCR, 0);
1828 }
1829
1830#ifdef CONFIG_SERIAL_8250_RSA
1831 /*
1832 * If this is an RSA port, see if we can kick it up to the
1833 * higher speed clock.
1834 */
1835 enable_rsa(up);
1836#endif
da891641
JR		 1837
1838 if (port->type == PORT_XR17V35X) {
1839 /*
1840 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
1841 * MCR [7:5] and MSR [7:0]
1842 */
1843 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
1844
1845 /*
1846 * Make sure all interrups are masked until initialization is
1847 * complete and the FIFOs are cleared
1848 */
1849 serial_port_out(port, UART_IER, 0);
1850 }
1851
b6830f6d
PH		 1852 /*
1853 * Clear the FIFO buffers and disable them.
1854 * (they will be reenabled in set_termios())
1855 */
1856 serial8250_clear_fifos(up);
1857
1858 /*
1859 * Clear the interrupt registers.
1860 */
1861 serial_port_in(port, UART_LSR);
1862 serial_port_in(port, UART_RX);
1863 serial_port_in(port, UART_IIR);
1864 serial_port_in(port, UART_MSR);
1865
1866 /*
1867 * At this point, there's no way the LSR could still be 0xff;
1868 * if it is, then bail out, because there's likely no UART
1869 * here.
1870 */
1871 if (!(port->flags & UPF_BUGGY_UART) &&
1872 (serial_port_in(port, UART_LSR) == 0xff)) {
1873 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1874 serial_index(port));
1875 retval = -ENODEV;
1876 goto out;
1877 }
1878
1879 /*
1880 * For a XR16C850, we need to set the trigger levels
1881 */
1882 if (port->type == PORT_16850) {
1883 unsigned char fctr;
1884
1885 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1886
1887 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1888 serial_port_out(port, UART_FCTR,
1889 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1890 serial_port_out(port, UART_TRG, UART_TRG_96);
1891 serial_port_out(port, UART_FCTR,
1892 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1893 serial_port_out(port, UART_TRG, UART_TRG_96);
1894
1895 serial_port_out(port, UART_LCR, 0);
1896 }
1897
1898 if (port->irq) {
1899 unsigned char iir1;
1900 /*
1901 * Test for UARTs that do not reassert THRE when the
1902 * transmitter is idle and the interrupt has already
1903 * been cleared. Real 16550s should always reassert
1904 * this interrupt whenever the transmitter is idle and
1905 * the interrupt is enabled. Delays are necessary to
1906 * allow register changes to become visible.
1907 */
1908 spin_lock_irqsave(&port->lock, flags);
1909 if (up->port.irqflags & IRQF_SHARED)
1910 disable_irq_nosync(port->irq);
1911
1912 wait_for_xmitr(up, UART_LSR_THRE);
1913 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1914 udelay(1); /* allow THRE to set */
1915 iir1 = serial_port_in(port, UART_IIR);
1916 serial_port_out(port, UART_IER, 0);
1917 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1918 udelay(1); /* allow a working UART time to re-assert THRE */
1919 iir = serial_port_in(port, UART_IIR);
1920 serial_port_out(port, UART_IER, 0);
1921
1922 if (port->irqflags & IRQF_SHARED)
1923 enable_irq(port->irq);
1924 spin_unlock_irqrestore(&port->lock, flags);
1925
1926 /*
1927 * If the interrupt is not reasserted, or we otherwise
1928 * don't trust the iir, setup a timer to kick the UART
1929 * on a regular basis.
1930 */
1931 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
1932 up->port.flags & UPF_BUG_THRE) {
1933 up->bugs |= UART_BUG_THRE;
1934 }
1935 }
1936
1937 retval = up->ops->setup_irq(up);
1938 if (retval)
1939 goto out;
1940
1941 /*
1942 * Now, initialize the UART
1943 */
1944 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1945
1946 spin_lock_irqsave(&port->lock, flags);
1947 if (up->port.flags & UPF_FOURPORT) {
1948 if (!up->port.irq)
1949 up->port.mctrl |= TIOCM_OUT1;
1950 } else
1951 /*
1952 * Most PC uarts need OUT2 raised to enable interrupts.
1953 */
1954 if (port->irq)
1955 up->port.mctrl |= TIOCM_OUT2;
1956
1957 serial8250_set_mctrl(port, port->mctrl);
1958
1959 /* Serial over Lan (SoL) hack:
1960 Intel 8257x Gigabit ethernet chips have a
1961 16550 emulation, to be used for Serial Over Lan.
1962 Those chips take a longer time than a normal
1963 serial device to signalize that a transmission
1964 data was queued. Due to that, the above test generally
1965 fails. One solution would be to delay the reading of
1966 iir. However, this is not reliable, since the timeout
1967 is variable. So, let's just don't test if we receive
1968 TX irq. This way, we'll never enable UART_BUG_TXEN.
1969 */
1970 if (up->port.flags & UPF_NO_TXEN_TEST)
1971 goto dont_test_tx_en;
1972
1973 /*
1974 * Do a quick test to see if we receive an
1975 * interrupt when we enable the TX irq.
1976 */
1977 serial_port_out(port, UART_IER, UART_IER_THRI);
1978 lsr = serial_port_in(port, UART_LSR);
1979 iir = serial_port_in(port, UART_IIR);
1980 serial_port_out(port, UART_IER, 0);
1981
1982 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1983 if (!(up->bugs & UART_BUG_TXEN)) {
1984 up->bugs |= UART_BUG_TXEN;
1985 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1986 serial_index(port));
1987 }
1988 } else {
1989 up->bugs &= ~UART_BUG_TXEN;
1990 }
1991
1992dont_test_tx_en:
1993 spin_unlock_irqrestore(&port->lock, flags);
1994
1995 /*
1996 * Clear the interrupt registers again for luck, and clear the
1997 * saved flags to avoid getting false values from polling
1998 * routines or the previous session.
1999 */
2000 serial_port_in(port, UART_LSR);
2001 serial_port_in(port, UART_RX);
2002 serial_port_in(port, UART_IIR);
2003 serial_port_in(port, UART_MSR);
2004 up->lsr_saved_flags = 0;
2005 up->msr_saved_flags = 0;
2006
2007 /*
2008 * Request DMA channels for both RX and TX.
2009 */
2010 if (up->dma) {
2011 retval = serial8250_request_dma(up);
2012 if (retval) {
2013 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2014 serial_index(port));
2015 up->dma = NULL;
2016 }
2017 }
2018
2019 /*
ee3ad90b
PH		 2020 * Set the IER shadow for rx interrupts but defer actual interrupt
2021 * enable until after the FIFOs are enabled; otherwise, an already-
2022 * active sender can swamp the interrupt handler with "too much work".
b6830f6d
PH		 2023 */
2024 up->ier = UART_IER_RLSI | UART_IER_RDI;
b6830f6d
PH		 2025
2026 if (port->flags & UPF_FOURPORT) {
2027 unsigned int icp;
2028 /*
2029 * Enable interrupts on the AST Fourport board
2030 */
2031 icp = (port->iobase & 0xfe0) | 0x01f;
2032 outb_p(0x80, icp);
2033 inb_p(icp);
2034 }
2035 retval = 0;
2036out:
2037 serial8250_rpm_put(up);
2038 return retval;
2039}
2040EXPORT_SYMBOL_GPL(serial8250_do_startup);
2041
2042static int serial8250_startup(struct uart_port *port)
2043{
2044 if (port->startup)
2045 return port->startup(port);
2046 return serial8250_do_startup(port);
2047}
2048
2049void serial8250_do_shutdown(struct uart_port *port)
2050{
2051 struct uart_8250_port *up = up_to_u8250p(port);
2052 unsigned long flags;
2053
2054 serial8250_rpm_get(up);
2055 /*
2056 * Disable interrupts from this port
2057 */
2058 up->ier = 0;
2059 serial_port_out(port, UART_IER, 0);
2060
2061 if (up->dma)
2062 serial8250_release_dma(up);
2063
2064 spin_lock_irqsave(&port->lock, flags);
2065 if (port->flags & UPF_FOURPORT) {
2066 /* reset interrupts on the AST Fourport board */
2067 inb((port->iobase & 0xfe0) | 0x1f);
2068 port->mctrl |= TIOCM_OUT1;
2069 } else
2070 port->mctrl &= ~TIOCM_OUT2;
2071
2072 serial8250_set_mctrl(port, port->mctrl);
2073 spin_unlock_irqrestore(&port->lock, flags);
2074
2075 /*
2076 * Disable break condition and FIFOs
2077 */
2078 serial_port_out(port, UART_LCR,
2079 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2080 serial8250_clear_fifos(up);
2081
2082#ifdef CONFIG_SERIAL_8250_RSA
2083 /*
2084 * Reset the RSA board back to 115kbps compat mode.
2085 */
2086 disable_rsa(up);
2087#endif
2088
2089 /*
2090 * Read data port to reset things, and then unlink from
2091 * the IRQ chain.
2092 */
2093 serial_port_in(port, UART_RX);
2094 serial8250_rpm_put(up);
2095
2096 up->ops->release_irq(up);
2097}
2098EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2099
2100static void serial8250_shutdown(struct uart_port *port)
2101{
2102 if (port->shutdown)
2103 port->shutdown(port);
2104 else
2105 serial8250_do_shutdown(port);
2106}
2107
2108/*
2109 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2110 * Calculate divisor with extra 4-bit fractional portion
2111 */
2112static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2113 unsigned int baud,
2114 unsigned int *frac)
2115{
2116 struct uart_port *port = &up->port;
2117 unsigned int quot_16;
2118
2119 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2120 *frac = quot_16 & 0x0f;
2121
2122 return quot_16 >> 4;
2123}
2124
2125static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2126 unsigned int baud,
2127 unsigned int *frac)
2128{
2129 struct uart_port *port = &up->port;
2130 unsigned int quot;
2131
2132 /*
2133 * Handle magic divisors for baud rates above baud_base on
2134 * SMSC SuperIO chips.
2135 *
2136 */
2137 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2138 baud == (port->uartclk/4))
2139 quot = 0x8001;
2140 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2141 baud == (port->uartclk/8))
2142 quot = 0x8002;
2143 else if (up->port.type == PORT_XR17V35X)
2144 quot = xr17v35x_get_divisor(up, baud, frac);
2145 else
2146 quot = uart_get_divisor(port, baud);
2147
2148 /*
2149 * Oxford Semi 952 rev B workaround
2150 */
2151 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2152 quot++;
2153
2154 return quot;
2155}
2156
2157static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2158 tcflag_t c_cflag)
2159{
2160 unsigned char cval;
2161
2162 switch (c_cflag & CSIZE) {
2163 case CS5:
2164 cval = UART_LCR_WLEN5;
2165 break;
2166 case CS6:
2167 cval = UART_LCR_WLEN6;
2168 break;
2169 case CS7:
2170 cval = UART_LCR_WLEN7;
2171 break;
2172 default:
2173 case CS8:
2174 cval = UART_LCR_WLEN8;
2175 break;
2176 }
2177
2178 if (c_cflag & CSTOPB)
2179 cval |= UART_LCR_STOP;
2180 if (c_cflag & PARENB) {
2181 cval |= UART_LCR_PARITY;
2182 if (up->bugs & UART_BUG_PARITY)
2183 up->fifo_bug = true;
2184 }
2185 if (!(c_cflag & PARODD))
2186 cval |= UART_LCR_EPAR;
2187#ifdef CMSPAR
2188 if (c_cflag & CMSPAR)
2189 cval |= UART_LCR_SPAR;
2190#endif
2191
2192 return cval;
2193}
2194
2195static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2196 unsigned int quot, unsigned int quot_frac)
2197{
2198 struct uart_8250_port *up = up_to_u8250p(port);
2199
2200 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2201 if (is_omap1510_8250(up)) {
2202 if (baud == 115200) {
2203 quot = 1;
2204 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2205 } else
2206 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2207 }
2208
2209 /*
2210 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2211 * otherwise just set DLAB
2212 */
2213 if (up->capabilities & UART_NATSEMI)
2214 serial_port_out(port, UART_LCR, 0xe0);
2215 else
2216 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2217
2218 serial_dl_write(up, quot);
2219
2220 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2221 if (up->port.type == PORT_XR17V35X)
2222 serial_port_out(port, 0x2, quot_frac);
2223}
2224
2225void
2226serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2227 struct ktermios *old)
2228{
2229 struct uart_8250_port *up = up_to_u8250p(port);
2230 unsigned char cval;
2231 unsigned long flags;
2232 unsigned int baud, quot, frac = 0;
2233
2234 cval = serial8250_compute_lcr(up, termios->c_cflag);
2235
2236 /*
2237 * Ask the core to calculate the divisor for us.
2238 */
2239 baud = uart_get_baud_rate(port, termios, old,
2240 port->uartclk / 16 / 0xffff,
2241 port->uartclk / 16);
2242 quot = serial8250_get_divisor(up, baud, &frac);
2243
2244 /*
2245 * Ok, we're now changing the port state. Do it with
2246 * interrupts disabled.
2247 */
2248 serial8250_rpm_get(up);
2249 spin_lock_irqsave(&port->lock, flags);
2250
2251 up->lcr = cval; /* Save computed LCR */
2252
2253 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2254 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2255 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2256 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2257 up->fcr |= UART_FCR_TRIGGER_1;
2258 }
2259 }
2260
2261 /*
2262 * MCR-based auto flow control. When AFE is enabled, RTS will be
2263 * deasserted when the receive FIFO contains more characters than
2264 * the trigger, or the MCR RTS bit is cleared. In the case where
2265 * the remote UART is not using CTS auto flow control, we must
2266 * have sufficient FIFO entries for the latency of the remote
2267 * UART to respond. IOW, at least 32 bytes of FIFO.
2268 */
2269 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2270 up->mcr &= ~UART_MCR_AFE;
2271 if (termios->c_cflag & CRTSCTS)
2272 up->mcr |= UART_MCR_AFE;
2273 }
2274
2275 /*
2276 * Update the per-port timeout.
2277 */
2278 uart_update_timeout(port, termios->c_cflag, baud);
2279
2280 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2281 if (termios->c_iflag & INPCK)
2282 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2283 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2284 port->read_status_mask |= UART_LSR_BI;
2285
2286 /*
2287 * Characteres to ignore
2288 */
2289 port->ignore_status_mask = 0;
2290 if (termios->c_iflag & IGNPAR)
2291 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2292 if (termios->c_iflag & IGNBRK) {
2293 port->ignore_status_mask |= UART_LSR_BI;
2294 /*
2295 * If we're ignoring parity and break indicators,
2296 * ignore overruns too (for real raw support).
2297 */
2298 if (termios->c_iflag & IGNPAR)
2299 port->ignore_status_mask |= UART_LSR_OE;
2300 }
2301
2302 /*
2303 * ignore all characters if CREAD is not set
2304 */
2305 if ((termios->c_cflag & CREAD) == 0)
2306 port->ignore_status_mask |= UART_LSR_DR;
2307
2308 /*
2309 * CTS flow control flag and modem status interrupts
2310 */
2311 up->ier &= ~UART_IER_MSI;
2312 if (!(up->bugs & UART_BUG_NOMSR) &&
2313 UART_ENABLE_MS(&up->port, termios->c_cflag))
2314 up->ier |= UART_IER_MSI;
2315 if (up->capabilities & UART_CAP_UUE)
2316 up->ier |= UART_IER_UUE;
2317 if (up->capabilities & UART_CAP_RTOIE)
2318 up->ier |= UART_IER_RTOIE;
2319
2320 serial_port_out(port, UART_IER, up->ier);
2321
2322 if (up->capabilities & UART_CAP_EFR) {
2323 unsigned char efr = 0;
2324 /*
2325 * TI16C752/Startech hardware flow control. FIXME:
2326 * - TI16C752 requires control thresholds to be set.
2327 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2328 */
2329 if (termios->c_cflag & CRTSCTS)
2330 efr |= UART_EFR_CTS;
2331
2332 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2333 if (port->flags & UPF_EXAR_EFR)
2334 serial_port_out(port, UART_XR_EFR, efr);
2335 else
2336 serial_port_out(port, UART_EFR, efr);
2337 }
2338
2339 serial8250_set_divisor(port, baud, quot, frac);
2340
2341 /*
2342 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2343 * is written without DLAB set, this mode will be disabled.
2344 */
2345 if (port->type == PORT_16750)
2346 serial_port_out(port, UART_FCR, up->fcr);
2347
2348 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2349 if (port->type != PORT_16750) {
2350 /* emulated UARTs (Lucent Venus 167x) need two steps */
2351 if (up->fcr & UART_FCR_ENABLE_FIFO)
2352 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2353 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2354 }
2355 serial8250_set_mctrl(port, port->mctrl);
2356 spin_unlock_irqrestore(&port->lock, flags);
2357 serial8250_rpm_put(up);
2358
2359 /* Don't rewrite B0 */
2360 if (tty_termios_baud_rate(termios))
2361 tty_termios_encode_baud_rate(termios, baud, baud);
2362}
2363EXPORT_SYMBOL(serial8250_do_set_termios);
2364
2365static void
2366serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2367 struct ktermios *old)
2368{
2369 if (port->set_termios)
2370 port->set_termios(port, termios, old);
2371 else
2372 serial8250_do_set_termios(port, termios, old);
2373}
2374
2375static void
2376serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2377{
2378 if (termios->c_line == N_PPS) {
2379 port->flags |= UPF_HARDPPS_CD;
2380 spin_lock_irq(&port->lock);
2381 serial8250_enable_ms(port);
2382 spin_unlock_irq(&port->lock);
2383 } else {
2384 port->flags &= ~UPF_HARDPPS_CD;
2385 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2386 spin_lock_irq(&port->lock);
2387 serial8250_disable_ms(port);
2388 spin_unlock_irq(&port->lock);
2389 }
2390 }
2391}
2392
2393
2394void serial8250_do_pm(struct uart_port *port, unsigned int state,
2395 unsigned int oldstate)
2396{
2397 struct uart_8250_port *p = up_to_u8250p(port);
2398
2399 serial8250_set_sleep(p, state != 0);
2400}
2401EXPORT_SYMBOL(serial8250_do_pm);
2402
2403static void
2404serial8250_pm(struct uart_port *port, unsigned int state,
2405 unsigned int oldstate)
2406{
2407 if (port->pm)
2408 port->pm(port, state, oldstate);
2409 else
2410 serial8250_do_pm(port, state, oldstate);
2411}
2412
2413static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2414{
2415 if (pt->port.mapsize)
2416 return pt->port.mapsize;
2417 if (pt->port.iotype == UPIO_AU) {
2418 if (pt->port.type == PORT_RT2880)
2419 return 0x100;
2420 return 0x1000;
2421 }
2422 if (is_omap1_8250(pt))
2423 return 0x16 << pt->port.regshift;
2424
2425 return 8 << pt->port.regshift;
2426}
2427
2428/*
2429 * Resource handling.
2430 */
2431static int serial8250_request_std_resource(struct uart_8250_port *up)
2432{
2433 unsigned int size = serial8250_port_size(up);
2434 struct uart_port *port = &up->port;
2435 int ret = 0;
2436
2437 switch (port->iotype) {
2438 case UPIO_AU:
2439 case UPIO_TSI:
2440 case UPIO_MEM32:
2441 case UPIO_MEM32BE:
2442 case UPIO_MEM:
2443 if (!port->mapbase)
2444 break;
2445
2446 if (!request_mem_region(port->mapbase, size, "serial")) {
2447 ret = -EBUSY;
2448 break;
2449 }
2450
2451 if (port->flags & UPF_IOREMAP) {
2452 port->membase = ioremap_nocache(port->mapbase, size);
2453 if (!port->membase) {
2454 release_mem_region(port->mapbase, size);
2455 ret = -ENOMEM;
2456 }
2457 }
2458 break;
2459
2460 case UPIO_HUB6:
2461 case UPIO_PORT:
2462 if (!request_region(port->iobase, size, "serial"))
2463 ret = -EBUSY;
2464 break;
2465 }
2466 return ret;
2467}
2468
2469static void serial8250_release_std_resource(struct uart_8250_port *up)
2470{
2471 unsigned int size = serial8250_port_size(up);
2472 struct uart_port *port = &up->port;
2473
2474 switch (port->iotype) {
2475 case UPIO_AU:
2476 case UPIO_TSI:
2477 case UPIO_MEM32:
2478 case UPIO_MEM32BE:
2479 case UPIO_MEM:
2480 if (!port->mapbase)
2481 break;
2482
2483 if (port->flags & UPF_IOREMAP) {
2484 iounmap(port->membase);
2485 port->membase = NULL;
2486 }
2487
2488 release_mem_region(port->mapbase, size);
2489 break;
2490
2491 case UPIO_HUB6:
2492 case UPIO_PORT:
2493 release_region(port->iobase, size);
2494 break;
2495 }
2496}
2497
2498static void serial8250_release_port(struct uart_port *port)
2499{
2500 struct uart_8250_port *up = up_to_u8250p(port);
2501
2502 serial8250_release_std_resource(up);
2503}
2504
2505static int serial8250_request_port(struct uart_port *port)
2506{
2507 struct uart_8250_port *up = up_to_u8250p(port);
2508 int ret;
2509
2510 if (port->type == PORT_8250_CIR)
2511 return -ENODEV;
2512
2513 ret = serial8250_request_std_resource(up);
2514
2515 return ret;
2516}
2517
2518static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2519{
2520 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2521 unsigned char bytes;
2522
2523 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2524
2525 return bytes ? bytes : -EOPNOTSUPP;
2526}
2527
2528static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2529{
2530 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2531 int i;
2532
2533 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2534 return -EOPNOTSUPP;
2535
2536 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2537 if (bytes < conf_type->rxtrig_bytes[i])
2538 /* Use the nearest lower value */
2539 return (--i) << UART_FCR_R_TRIG_SHIFT;
2540 }
2541
2542 return UART_FCR_R_TRIG_11;
2543}
2544
2545static int do_get_rxtrig(struct tty_port *port)
2546{
2547 struct uart_state *state = container_of(port, struct uart_state, port);
2548 struct uart_port *uport = state->uart_port;
2549 struct uart_8250_port *up =
2550 container_of(uport, struct uart_8250_port, port);
2551
2552 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2553 return -EINVAL;
2554
2555 return fcr_get_rxtrig_bytes(up);
2556}
2557
2558static int do_serial8250_get_rxtrig(struct tty_port *port)
2559{
2560 int rxtrig_bytes;
2561
2562 mutex_lock(&port->mutex);
2563 rxtrig_bytes = do_get_rxtrig(port);
2564 mutex_unlock(&port->mutex);
2565
2566 return rxtrig_bytes;
2567}
2568
2569static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2570 struct device_attribute *attr, char *buf)
2571{
2572 struct tty_port *port = dev_get_drvdata(dev);
2573 int rxtrig_bytes;
2574
2575 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2576 if (rxtrig_bytes < 0)
2577 return rxtrig_bytes;
2578
2579 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2580}
2581
2582static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2583{
2584 struct uart_state *state = container_of(port, struct uart_state, port);
2585 struct uart_port *uport = state->uart_port;
2586 struct uart_8250_port *up =
2587 container_of(uport, struct uart_8250_port, port);
2588 int rxtrig;
2589
2590 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2591 up->fifo_bug)
2592 return -EINVAL;
2593
2594 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2595 if (rxtrig < 0)
2596 return rxtrig;
2597
2598 serial8250_clear_fifos(up);
2599 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2600 up->fcr |= (unsigned char)rxtrig;
2601 serial_out(up, UART_FCR, up->fcr);
2602 return 0;
2603}
2604
2605static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2606{
2607 int ret;
2608
2609 mutex_lock(&port->mutex);
2610 ret = do_set_rxtrig(port, bytes);
2611 mutex_unlock(&port->mutex);
2612
2613 return ret;
2614}
2615
2616static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2617 struct device_attribute *attr, const char *buf, size_t count)
2618{
2619 struct tty_port *port = dev_get_drvdata(dev);
2620 unsigned char bytes;
2621 int ret;
2622
2623 if (!count)
2624 return -EINVAL;
2625
2626 ret = kstrtou8(buf, 10, &bytes);
2627 if (ret < 0)
2628 return ret;
2629
2630 ret = do_serial8250_set_rxtrig(port, bytes);
2631 if (ret < 0)
2632 return ret;
2633
2634 return count;
2635}
2636
2637static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2638 serial8250_get_attr_rx_trig_bytes,
2639 serial8250_set_attr_rx_trig_bytes);
2640
2641static struct attribute *serial8250_dev_attrs[] = {
2642 &dev_attr_rx_trig_bytes.attr,
2643 NULL,
2644 };
2645
2646static struct attribute_group serial8250_dev_attr_group = {
2647 .attrs = serial8250_dev_attrs,
2648 };
2649
2650static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2651{
2652 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2653
2654 if (conf_type->rxtrig_bytes[0])
2655 up->port.attr_group = &serial8250_dev_attr_group;
2656}
2657
2658static void serial8250_config_port(struct uart_port *port, int flags)
2659{
2660 struct uart_8250_port *up = up_to_u8250p(port);
2661 int ret;
2662
2663 if (port->type == PORT_8250_CIR)
2664 return;
2665
2666 /*
2667 * Find the region that we can probe for. This in turn
2668 * tells us whether we can probe for the type of port.
2669 */
2670 ret = serial8250_request_std_resource(up);
2671 if (ret < 0)
2672 return;
2673
2674 if (port->iotype != up->cur_iotype)
2675 set_io_from_upio(port);
2676
2677 if (flags & UART_CONFIG_TYPE)
2678 autoconfig(up);
2679
2680 /* if access method is AU, it is a 16550 with a quirk */
2681 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2682 up->bugs |= UART_BUG_NOMSR;
2683
2684 /* HW bugs may trigger IRQ while IIR == NO_INT */
2685 if (port->type == PORT_TEGRA)
2686 up->bugs |= UART_BUG_NOMSR;
2687
2688 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2689 autoconfig_irq(up);
2690
2691 if (port->type == PORT_UNKNOWN)
2692 serial8250_release_std_resource(up);
2693
2694 /* Fixme: probably not the best place for this */
2695 if ((port->type == PORT_XR17V35X) ||
2696 (port->type == PORT_XR17D15X))
2697 port->handle_irq = exar_handle_irq;
2698
2699 register_dev_spec_attr_grp(up);
2700 up->fcr = uart_config[up->port.type].fcr;
2701}
2702
2703static int
2704serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2705{
2706 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2707 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2708 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2709 ser->type == PORT_STARTECH)
2710 return -EINVAL;
2711 return 0;
2712}
2713
2714static const char *
2715serial8250_type(struct uart_port *port)
2716{
2717 int type = port->type;
2718
2719 if (type >= ARRAY_SIZE(uart_config))
2720 type = 0;
2721 return uart_config[type].name;
2722}
2723
2724static const struct uart_ops serial8250_pops = {
2725 .tx_empty = serial8250_tx_empty,
2726 .set_mctrl = serial8250_set_mctrl,
2727 .get_mctrl = serial8250_get_mctrl,
2728 .stop_tx = serial8250_stop_tx,
2729 .start_tx = serial8250_start_tx,
2730 .throttle = serial8250_throttle,
2731 .unthrottle = serial8250_unthrottle,
2732 .stop_rx = serial8250_stop_rx,
2733 .enable_ms = serial8250_enable_ms,
2734 .break_ctl = serial8250_break_ctl,
2735 .startup = serial8250_startup,
2736 .shutdown = serial8250_shutdown,
2737 .set_termios = serial8250_set_termios,
2738 .set_ldisc = serial8250_set_ldisc,
2739 .pm = serial8250_pm,
2740 .type = serial8250_type,
2741 .release_port = serial8250_release_port,
2742 .request_port = serial8250_request_port,
2743 .config_port = serial8250_config_port,
2744 .verify_port = serial8250_verify_port,
2745#ifdef CONFIG_CONSOLE_POLL
2746 .poll_get_char = serial8250_get_poll_char,
2747 .poll_put_char = serial8250_put_poll_char,
2748#endif
2749};
2750
2751void serial8250_init_port(struct uart_8250_port *up)
2752{
2753 struct uart_port *port = &up->port;
2754
2755 spin_lock_init(&port->lock);
2756 port->ops = &serial8250_pops;
2757
2758 up->cur_iotype = 0xFF;
2759}
2760EXPORT_SYMBOL_GPL(serial8250_init_port);
2761
2762void serial8250_set_defaults(struct uart_8250_port *up)
2763{
2764 struct uart_port *port = &up->port;
2765
2766 if (up->port.flags & UPF_FIXED_TYPE) {
2767 unsigned int type = up->port.type;
2768
2769 if (!up->port.fifosize)
2770 up->port.fifosize = uart_config[type].fifo_size;
2771 if (!up->tx_loadsz)
2772 up->tx_loadsz = uart_config[type].tx_loadsz;
2773 if (!up->capabilities)
2774 up->capabilities = uart_config[type].flags;
2775 }
2776
2777 set_io_from_upio(port);
2778
2779 /* default dma handlers */
2780 if (up->dma) {
2781 if (!up->dma->tx_dma)
2782 up->dma->tx_dma = serial8250_tx_dma;
2783 if (!up->dma->rx_dma)
2784 up->dma->rx_dma = serial8250_rx_dma;
2785 }
2786}
2787EXPORT_SYMBOL_GPL(serial8250_set_defaults);
2788
2789#ifdef CONFIG_SERIAL_8250_CONSOLE
2790
2791static void serial8250_console_putchar(struct uart_port *port, int ch)
2792{
2793 struct uart_8250_port *up = up_to_u8250p(port);
2794
2795 wait_for_xmitr(up, UART_LSR_THRE);
2796 serial_port_out(port, UART_TX, ch);
2797}
2798
2799/*
2800 * Print a string to the serial port trying not to disturb
2801 * any possible real use of the port...
2802 *
2803 * The console_lock must be held when we get here.
2804 */
2805void serial8250_console_write(struct uart_8250_port *up, const char *s,
2806 unsigned int count)
2807{
2808 struct uart_port *port = &up->port;
2809 unsigned long flags;
2810 unsigned int ier;
2811 int locked = 1;
2812
2813 touch_nmi_watchdog();
2814
2815 serial8250_rpm_get(up);
2816
2817 if (port->sysrq)
2818 locked = 0;
2819 else if (oops_in_progress)
2820 locked = spin_trylock_irqsave(&port->lock, flags);
2821 else
2822 spin_lock_irqsave(&port->lock, flags);
2823
2824 /*
2825 * First save the IER then disable the interrupts
2826 */
2827 ier = serial_port_in(port, UART_IER);
2828
2829 if (up->capabilities & UART_CAP_UUE)
2830 serial_port_out(port, UART_IER, UART_IER_UUE);
2831 else
2832 serial_port_out(port, UART_IER, 0);
2833
2834 /* check scratch reg to see if port powered off during system sleep */
2835 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
2836 struct ktermios termios;
2837 unsigned int baud, quot, frac = 0;
2838
2839 termios.c_cflag = port->cons->cflag;
2840 if (port->state->port.tty && termios.c_cflag == 0)
2841 termios.c_cflag = port->state->port.tty->termios.c_cflag;
2842
2843 baud = uart_get_baud_rate(port, &termios, NULL,
2844 port->uartclk / 16 / 0xffff,
2845 port->uartclk / 16);
2846 quot = serial8250_get_divisor(up, baud, &frac);
2847
2848 serial8250_set_divisor(port, baud, quot, frac);
2849 serial_port_out(port, UART_LCR, up->lcr);
2850 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
2851
2852 up->canary = 0;
2853 }
2854
2855 uart_console_write(port, s, count, serial8250_console_putchar);
2856
2857 /*
2858 * Finally, wait for transmitter to become empty
2859 * and restore the IER
2860 */
2861 wait_for_xmitr(up, BOTH_EMPTY);
2862 serial_port_out(port, UART_IER, ier);
2863
2864 /*
2865 * The receive handling will happen properly because the
2866 * receive ready bit will still be set; it is not cleared
2867 * on read. However, modem control will not, we must
2868 * call it if we have saved something in the saved flags
2869 * while processing with interrupts off.
2870 */
2871 if (up->msr_saved_flags)
2872 serial8250_modem_status(up);
2873
2874 if (locked)
2875 spin_unlock_irqrestore(&port->lock, flags);
2876 serial8250_rpm_put(up);
2877}
2878
2879static unsigned int probe_baud(struct uart_port *port)
2880{
2881 unsigned char lcr, dll, dlm;
2882 unsigned int quot;
2883
2884 lcr = serial_port_in(port, UART_LCR);
2885 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
2886 dll = serial_port_in(port, UART_DLL);
2887 dlm = serial_port_in(port, UART_DLM);
2888 serial_port_out(port, UART_LCR, lcr);
2889
2890 quot = (dlm << 8) | dll;
2891 return (port->uartclk / 16) / quot;
2892}
2893
2894int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
2895{
2896 int baud = 9600;
2897 int bits = 8;
2898 int parity = 'n';
2899 int flow = 'n';
2900
2901 if (!port->iobase && !port->membase)
2902 return -ENODEV;
2903
2904 if (options)
2905 uart_parse_options(options, &baud, &parity, &bits, &flow);
2906 else if (probe)
2907 baud = probe_baud(port);
2908
2909 return uart_set_options(port, port->cons, baud, parity, bits, flow);
2910}
2911
2912#endif /* CONFIG_SERIAL_8250_CONSOLE */
f7a7651f
JM		 2913
2914MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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