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serial/8250_pci: setup-quirk workaround for the kt serial controller
[deliverable/linux.git] / drivers / tty / serial / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <linux/8250_pci.h>
22#include <linux/bitops.h>
23
24#include <asm/byteorder.h>
25#include <asm/io.h>
26
27#include "8250.h"
28
29#undef SERIAL_DEBUG_PCI
30
1da177e4
LT		 31/*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
5bf8f501 42 int (*probe)(struct pci_dev *dev);
1da177e4 43 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 44 int (*setup)(struct serial_private *,
45 const struct pciserial_board *,
05caac58 46 struct uart_port *, int);
1da177e4
LT		 47 void (*exit)(struct pci_dev *dev);
48};
49
50#define PCI_NUM_BAR_RESOURCES 6
51
52struct serial_private {
70db3d91 53 struct pci_dev *dev;
1da177e4
LT		 54 unsigned int nr;
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
57 int line[0];
58};
59
7808edcd
NG		 60static int pci_default_setup(struct serial_private*,
61 const struct pciserial_board*, struct uart_port*, int);
62
1da177e4
LT		 63static void moan_device(const char *str, struct pci_dev *dev)
64{
ad361c98
JP		 65 printk(KERN_WARNING
66 "%s: %s\n"
67 "Please send the output of lspci -vv, this\n"
68 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69 "manufacturer and name of serial board or\n"
70 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 71 pci_name(dev), str, dev->vendor, dev->device,
72 dev->subsystem_vendor, dev->subsystem_device);
73}
74
75static int
70db3d91 76setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 77 int bar, int offset, int regshift)
78{
70db3d91 79 struct pci_dev *dev = priv->dev;
1da177e4
LT		 80 unsigned long base, len;
81
82 if (bar >= PCI_NUM_BAR_RESOURCES)
83 return -EINVAL;
84
72ce9a83
RK		 85 base = pci_resource_start(dev, bar);
86
1da177e4 87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 88 len = pci_resource_len(dev, bar);
89
90 if (!priv->remapped_bar[bar])
6f441fe9 91 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 92 if (!priv->remapped_bar[bar])
93 return -ENOMEM;
94
95 port->iotype = UPIO_MEM;
72ce9a83 96 port->iobase = 0;
1da177e4
LT		 97 port->mapbase = base + offset;
98 port->membase = priv->remapped_bar[bar] + offset;
99 port->regshift = regshift;
100 } else {
1da177e4 101 port->iotype = UPIO_PORT;
72ce9a83
RK		 102 port->iobase = base + offset;
103 port->mapbase = 0;
104 port->membase = NULL;
105 port->regshift = 0;
1da177e4
LT		 106 }
107 return 0;
108}
109
02c9b5cf
KJ		 110/*
111 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 */
113static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 114 const struct pciserial_board *board,
02c9b5cf
KJ		 115 struct uart_port *port, int idx)
116{
117 unsigned int bar = 0, offset = board->first_offset;
118 bar = FL_GET_BASE(board->flags);
119
120 if (idx < 2) {
121 offset += idx * board->uart_offset;
122 } else if ((idx >= 2) && (idx < 4)) {
123 bar += 1;
124 offset += ((idx - 2) * board->uart_offset);
125 } else if ((idx >= 4) && (idx < 6)) {
126 bar += 2;
127 offset += ((idx - 4) * board->uart_offset);
128 } else if (idx >= 6) {
129 bar += 3;
130 offset += ((idx - 6) * board->uart_offset);
131 }
132
133 return setup_port(priv, port, bar, offset, board->reg_shift);
134}
135
1da177e4
LT		 136/*
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
139 */
140static int
975a1a7d 141afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 142 struct uart_port *port, int idx)
143{
144 unsigned int bar, offset = board->first_offset;
5756ee99 145
1da177e4
LT		 146 bar = FL_GET_BASE(board->flags);
147 if (idx < 4)
148 bar += idx;
149 else {
150 bar = 4;
151 offset += (idx - 4) * board->uart_offset;
152 }
153
70db3d91 154 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 155}
156
157/*
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
163 */
61a116ef 164static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 165{
166 int rc = 0;
167
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 rc = 3;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 rc = 2;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 rc = 4;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 182 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 183 rc = 1;
184 break;
185 }
186
187 return rc;
188}
189
190/*
191 * HP's Diva chip puts the 4th/5th serial port further out, and
192 * some serial ports are supposed to be hidden on certain models.
193 */
194static int
975a1a7d
RK		 195pci_hp_diva_setup(struct serial_private *priv,
196 const struct pciserial_board *board,
197 struct uart_port *port, int idx)
1da177e4
LT		 198{
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
70db3d91 202 switch (priv->dev->subsystem_device) {
1da177e4
LT		 203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
70db3d91 219 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 220}
221
222/*
223 * Added for EKF Intel i960 serial boards
224 */
61a116ef 225static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 226{
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
5756ee99
AC		 233 pci_read_config_dword(dev, 0x44, (void *)&oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 235 printk(KERN_DEBUG "Local i960 firmware missing");
236 return -ENODEV;
237 }
238 return 0;
239}
240
241/*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
61a116ef 247static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 248{
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
add7b58e 258 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 259 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 260 irq_config = 0x43;
5756ee99 261
1da177e4 262 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 263 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 264 /*
265 * As the megawolf cards have the int pins active
266 * high, and have 2 UART chips, both ints must be
267 * enabled on the 9050. Also, the UARTS are set in
268 * 16450 mode by default, so we have to enable the
269 * 16C950 'enhanced' mode so that we can use the
270 * deep FIFOs
271 */
272 irq_config = 0x5b;
1da177e4
LT		 273 /*
274 * enable/disable interrupts
275 */
6f441fe9 276 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288}
289
290static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291{
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
6f441fe9 300 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310}
311
04bf7e74
WP		 312#define NI8420_INT_ENABLE_REG 0x38
313#define NI8420_INT_ENABLE_BIT 0x2000
314
315static void __devexit pci_ni8420_exit(struct pci_dev *dev)
316{
317 void __iomem *p;
318 unsigned long base, len;
319 unsigned int bar = 0;
320
321 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322 moan_device("no memory in bar", dev);
323 return;
324 }
325
326 base = pci_resource_start(dev, bar);
327 len = pci_resource_len(dev, bar);
328 p = ioremap_nocache(base, len);
329 if (p == NULL)
330 return;
331
332 /* Disable the CPU Interrupt */
333 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334 p + NI8420_INT_ENABLE_REG);
335 iounmap(p);
336}
337
338
46a0fac9
SB		 339/* MITE registers */
340#define MITE_IOWBSR1 0xc4
341#define MITE_IOWCR1 0xf4
342#define MITE_LCIMR1 0x08
343#define MITE_LCIMR2 0x10
344
345#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346
347static void __devexit pci_ni8430_exit(struct pci_dev *dev)
348{
349 void __iomem *p;
350 unsigned long base, len;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 base = pci_resource_start(dev, bar);
359 len = pci_resource_len(dev, bar);
360 p = ioremap_nocache(base, len);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367}
368
1da177e4
LT		 369/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370static int
975a1a7d 371sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 372 struct uart_port *port, int idx)
373{
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
70db3d91 387 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 388}
389
390/*
391* This does initialization for PMC OCTALPRO cards:
392* maps the device memory, resets the UARTs (needed, bc
393* if the module is removed and inserted again, the card
394* is in the sleep mode) and enables global interrupt.
395*/
396
397/* global control register offset for SBS PMC-OctalPro */
398#define OCT_REG_CR_OFF 0x500
399
61a116ef 400static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 401{
402 u8 __iomem *p;
403
24ed3aba 404 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 409 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 410 udelay(50);
5756ee99 411 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418}
419
420/*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
424static void __devexit sbs_exit(struct pci_dev *dev)
425{
426 u8 __iomem *p;
427
24ed3aba 428 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
1da177e4 431 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 432 iounmap(p);
433}
434
435/*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
25985edc 438 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 447 *
1da177e4
LT		 448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
67d74b87
RK		 453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
fbc0dc0d
AP		 456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
1da177e4
LT		 459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465static int pci_siig10x_init(struct pci_dev *dev)
466{
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
6f441fe9 482 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490}
491
492#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495static int pci_siig20x_init(struct pci_dev *dev)
496{
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510}
511
67d74b87
RK		 512static int pci_siig_init(struct pci_dev *dev)
513{
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523}
524
3ec9c594 525static int pci_siig_setup(struct serial_private *priv,
975a1a7d 526 const struct pciserial_board *board,
3ec9c594
AP		 527 struct uart_port *port, int idx)
528{
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537}
538
1da177e4
LT		 539/*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
e9422e09 544static const unsigned short timedia_single_port[] = {
1da177e4
LT		 545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546};
547
e9422e09 548static const unsigned short timedia_dual_port[] = {
1da177e4 549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554};
555
e9422e09 556static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561};
562
e9422e09 563static const unsigned short timedia_eight_port[] = {
5756ee99 564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566};
567
cb3592be 568static const struct timedia_struct {
1da177e4 569 int num;
e9422e09 570 const unsigned short *ids;
1da177e4
LT		 571} timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
e9422e09 575 { 8, timedia_eight_port }
1da177e4
LT		 576};
577
b9b24558
FB		 578/*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584static int pci_timedia_probe(struct pci_dev *dev)
585{
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598}
599
61a116ef 600static int pci_timedia_init(struct pci_dev *dev)
1da177e4 601{
e9422e09 602 const unsigned short *ids;
1da177e4
LT		 603 int i, j;
604
e9422e09 605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612}
613
614/*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618static int
975a1a7d
RK		 619pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
1da177e4
LT		 621 struct uart_port *port, int idx)
622{
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
c2cd6d3c 638 /* FALLTHROUGH */
1da177e4
LT		 639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
70db3d91 646 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 647}
648
649/*
650 * Some Titan cards are also a little weird
651 */
652static int
70db3d91 653titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 654 const struct pciserial_board *board,
1da177e4
LT		 655 struct uart_port *port, int idx)
656{
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
70db3d91 671 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 672}
673
61a116ef 674static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 675{
676 msleep(100);
677 return 0;
678}
679
04bf7e74
WP		 680static int pci_ni8420_init(struct pci_dev *dev)
681{
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar = 0;
685
686 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687 moan_device("no memory in bar", dev);
688 return 0;
689 }
690
691 base = pci_resource_start(dev, bar);
692 len = pci_resource_len(dev, bar);
693 p = ioremap_nocache(base, len);
694 if (p == NULL)
695 return -ENOMEM;
696
697 /* Enable CPU Interrupt */
698 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699 p + NI8420_INT_ENABLE_REG);
700
701 iounmap(p);
702 return 0;
703}
704
46a0fac9
SB		 705#define MITE_IOWBSR1_WSIZE 0xa
706#define MITE_IOWBSR1_WIN_OFFSET 0x800
707#define MITE_IOWBSR1_WENAB (1 << 7)
708#define MITE_LCIMR1_IO_IE_0 (1 << 24)
709#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
710#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712static int pci_ni8430_init(struct pci_dev *dev)
713{
714 void __iomem *p;
715 unsigned long base, len;
716 u32 device_window;
717 unsigned int bar = 0;
718
719 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720 moan_device("no memory in bar", dev);
721 return 0;
722 }
723
724 base = pci_resource_start(dev, bar);
725 len = pci_resource_len(dev, bar);
726 p = ioremap_nocache(base, len);
727 if (p == NULL)
728 return -ENOMEM;
729
730 /* Set device window address and size in BAR0 */
731 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747}
748
749/* UART Port Control Register */
750#define NI8430_PORTCON 0x0f
751#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753static int
bf538fe4
AC		 754pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
46a0fac9
SB		 756 struct uart_port *port, int idx)
757{
758 void __iomem *p;
759 unsigned long base, len;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 base = pci_resource_start(priv->dev, bar);
769 len = pci_resource_len(priv->dev, bar);
770 p = ioremap_nocache(base, len);
771
7c9d440e 772 /* enable the transceiver */
46a0fac9
SB		 773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779}
780
7808edcd
NG		 781static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_port *port, int idx)
784{
785 unsigned int bar;
786
787 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797}
798
799/* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807static int pci_netmos_9900_numports(struct pci_dev *dev)
808{
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
829 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836}
46a0fac9 837
61a116ef 838static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 839{
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
ac6ec5b1
IS		 843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 845 return 0;
7808edcd 846
25cf9bc1
JS		 847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
7808edcd
NG		 851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
1da177e4
LT		 865 if (num_serial == 0)
866 return -ENODEV;
7808edcd 867
1da177e4
LT		 868 return num_serial;
869}
870
84f8c6fc 871/*
84f8c6fc
NV		 872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881/* registers */
882#define ITE_887x_MISCR 0x9c
883#define ITE_887x_INTCBAR 0x78
884#define ITE_887x_UARTBAR 0x7c
885#define ITE_887x_PS0BAR 0x10
886#define ITE_887x_POSIO0 0x60
887
888/* I/O space size */
889#define ITE_887x_IOSIZE 32
890/* I/O space size (bits 26-24; 8 bytes = 011b) */
891#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892/* I/O space size (bits 26-24; 32 bytes = 101b) */
893#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895#define ITE_887x_POSIO_SPEED (3 << 29)
896/* enable IO_Space bit */
897#define ITE_887x_POSIO_ENABLE (1 << 31)
898
f79abb82 899static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 900{
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
5756ee99
AC		 919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
84f8c6fc
NV		 921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
933 printk(KERN_ERR "ite887x: could not find iobase\n");
934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991}
992
993static void __devexit pci_ite887x_exit(struct pci_dev *dev)
994{
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000}
1001
9f2a036a
RK		 1002/*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008{
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1026 printk(KERN_DEBUG
1027 "%d ports detected on Oxford PCI Express device\n",
1028 number_uarts);
1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032}
1033
1da177e4 1034static int
975a1a7d
RK		 1035pci_default_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1da177e4
LT		 1037 struct uart_port *port, int idx)
1038{
1039 unsigned int bar, offset = board->first_offset, maxnr;
1040
1041 bar = FL_GET_BASE(board->flags);
1042 if (board->flags & FL_BASE_BARS)
1043 bar += idx;
1044 else
1045 offset += idx * board->uart_offset;
1046
2427ddd8
GKH		 1047 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048 (board->reg_shift + 3);
1da177e4
LT		 1049
1050 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051 return 1;
5756ee99 1052
70db3d91 1053 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1054}
1055
095e24b0
DB		 1056static int
1057ce4100_serial_setup(struct serial_private *priv,
1058 const struct pciserial_board *board,
1059 struct uart_port *port, int idx)
1060{
1061 int ret;
1062
1063 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064 port->iotype = UPIO_MEM32;
1065 port->type = PORT_XSCALE;
1066 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067 port->regshift = 2;
1068
1069 return ret;
1070}
1071
d9a0fbfd
AP		 1072static int
1073pci_omegapci_setup(struct serial_private *priv,
1798ca13 1074 const struct pciserial_board *board,
d9a0fbfd
AP		 1075 struct uart_port *port, int idx)
1076{
1077 return setup_port(priv, port, 2, idx * 8, 0);
1078}
1079
b6adea33
MCC		 1080static int skip_tx_en_setup(struct serial_private *priv,
1081 const struct pciserial_board *board,
1082 struct uart_port *port, int idx)
1083{
1084 port->flags |= UPF_NO_TXEN_TEST;
1085 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086 "[%04x:%04x] subsystem [%04x:%04x]\n",
1087 priv->dev->vendor,
1088 priv->dev->device,
1089 priv->dev->subsystem_vendor,
1090 priv->dev->subsystem_device);
1091
1092 return pci_default_setup(priv, board, port, idx);
1093}
1094
448ac154
DW		 1095static int kt_serial_setup(struct serial_private *priv,
1096 const struct pciserial_board *board,
1097 struct uart_port *port, int idx)
1098{
1099 port->flags |= UPF_IIR_ONCE;
1100 return skip_tx_en_setup(priv, board, port, idx);
1101}
1102
eb7073db
TM		 1103static int pci_eg20t_init(struct pci_dev *dev)
1104{
1105#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1106 return -ENODEV;
1107#else
1108 return 0;
1109#endif
1110}
1111
06315348
SH		 1112static int
1113pci_xr17c154_setup(struct serial_private *priv,
1114 const struct pciserial_board *board,
1115 struct uart_port *port, int idx)
1116{
1117 port->flags |= UPF_EXAR_EFR;
1118 return pci_default_setup(priv, board, port, idx);
1119}
1120
1da177e4
LT		 1121#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1122#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1123#define PCI_DEVICE_ID_OCTPRO 0x0001
1124#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1125#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1126#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1127#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48 1128#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1129#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1130#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1131#define PCI_DEVICE_ID_TITAN_200I 0x8028
1132#define PCI_DEVICE_ID_TITAN_400I 0x8048
1133#define PCI_DEVICE_ID_TITAN_800I 0x8088
1134#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1135#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1136#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1137#define PCI_DEVICE_ID_TITAN_100E 0xA010
1138#define PCI_DEVICE_ID_TITAN_200E 0xA012
1139#define PCI_DEVICE_ID_TITAN_400E 0xA013
1140#define PCI_DEVICE_ID_TITAN_800E 0xA014
1141#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1142#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
e847003f 1143#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1144#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1145#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
448ac154 1146#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1da177e4 1147
b76c5a07
CB		 1148/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1149#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1150
1da177e4
LT		 1151/*
1152 * Master list of serial port init/setup/exit quirks.
1153 * This does not describe the general nature of the port.
1154 * (ie, baud base, number and location of ports, etc)
1155 *
1156 * This list is ordered alphabetically by vendor then device.
1157 * Specific entries must come before more generic entries.
1158 */
7a63ce5a 1159static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1160 /*
1161 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1162 */
1163 {
1164 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1165 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1166 .subvendor = PCI_ANY_ID,
1167 .subdevice = PCI_ANY_ID,
1168 .setup = addidata_apci7800_setup,
1169 },
1da177e4 1170 /*
61a116ef 1171 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1172 * It is not clear whether this applies to all products.
1173 */
1174 {
1175 .vendor = PCI_VENDOR_ID_AFAVLAB,
1176 .device = PCI_ANY_ID,
1177 .subvendor = PCI_ANY_ID,
1178 .subdevice = PCI_ANY_ID,
1179 .setup = afavlab_setup,
1180 },
1181 /*
1182 * HP Diva
1183 */
1184 {
1185 .vendor = PCI_VENDOR_ID_HP,
1186 .device = PCI_DEVICE_ID_HP_DIVA,
1187 .subvendor = PCI_ANY_ID,
1188 .subdevice = PCI_ANY_ID,
1189 .init = pci_hp_diva_init,
1190 .setup = pci_hp_diva_setup,
1191 },
1192 /*
1193 * Intel
1194 */
1195 {
1196 .vendor = PCI_VENDOR_ID_INTEL,
1197 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1198 .subvendor = 0xe4bf,
1199 .subdevice = PCI_ANY_ID,
1200 .init = pci_inteli960ni_init,
1201 .setup = pci_default_setup,
1202 },
b6adea33
MCC		 1203 {
1204 .vendor = PCI_VENDOR_ID_INTEL,
1205 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1206 .subvendor = PCI_ANY_ID,
1207 .subdevice = PCI_ANY_ID,
1208 .setup = skip_tx_en_setup,
1209 },
1210 {
1211 .vendor = PCI_VENDOR_ID_INTEL,
1212 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1213 .subvendor = PCI_ANY_ID,
1214 .subdevice = PCI_ANY_ID,
1215 .setup = skip_tx_en_setup,
1216 },
1217 {
1218 .vendor = PCI_VENDOR_ID_INTEL,
1219 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1220 .subvendor = PCI_ANY_ID,
1221 .subdevice = PCI_ANY_ID,
1222 .setup = skip_tx_en_setup,
1223 },
095e24b0
DB		 1224 {
1225 .vendor = PCI_VENDOR_ID_INTEL,
1226 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1227 .subvendor = PCI_ANY_ID,
1228 .subdevice = PCI_ANY_ID,
1229 .setup = ce4100_serial_setup,
1230 },
448ac154
DW		 1231 {
1232 .vendor = PCI_VENDOR_ID_INTEL,
1233 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1234 .subvendor = PCI_ANY_ID,
1235 .subdevice = PCI_ANY_ID,
1236 .setup = kt_serial_setup,
1237 },
84f8c6fc
NV		 1238 /*
1239 * ITE
1240 */
1241 {
1242 .vendor = PCI_VENDOR_ID_ITE,
1243 .device = PCI_DEVICE_ID_ITE_8872,
1244 .subvendor = PCI_ANY_ID,
1245 .subdevice = PCI_ANY_ID,
1246 .init = pci_ite887x_init,
1247 .setup = pci_default_setup,
1248 .exit = __devexit_p(pci_ite887x_exit),
1249 },
46a0fac9
SB		 1250 /*
1251 * National Instruments
1252 */
04bf7e74
WP		 1253 {
1254 .vendor = PCI_VENDOR_ID_NI,
1255 .device = PCI_DEVICE_ID_NI_PCI23216,
1256 .subvendor = PCI_ANY_ID,
1257 .subdevice = PCI_ANY_ID,
1258 .init = pci_ni8420_init,
1259 .setup = pci_default_setup,
1260 .exit = __devexit_p(pci_ni8420_exit),
1261 },
1262 {
1263 .vendor = PCI_VENDOR_ID_NI,
1264 .device = PCI_DEVICE_ID_NI_PCI2328,
1265 .subvendor = PCI_ANY_ID,
1266 .subdevice = PCI_ANY_ID,
1267 .init = pci_ni8420_init,
1268 .setup = pci_default_setup,
1269 .exit = __devexit_p(pci_ni8420_exit),
1270 },
1271 {
1272 .vendor = PCI_VENDOR_ID_NI,
1273 .device = PCI_DEVICE_ID_NI_PCI2324,
1274 .subvendor = PCI_ANY_ID,
1275 .subdevice = PCI_ANY_ID,
1276 .init = pci_ni8420_init,
1277 .setup = pci_default_setup,
1278 .exit = __devexit_p(pci_ni8420_exit),
1279 },
1280 {
1281 .vendor = PCI_VENDOR_ID_NI,
1282 .device = PCI_DEVICE_ID_NI_PCI2322,
1283 .subvendor = PCI_ANY_ID,
1284 .subdevice = PCI_ANY_ID,
1285 .init = pci_ni8420_init,
1286 .setup = pci_default_setup,
1287 .exit = __devexit_p(pci_ni8420_exit),
1288 },
1289 {
1290 .vendor = PCI_VENDOR_ID_NI,
1291 .device = PCI_DEVICE_ID_NI_PCI2324I,
1292 .subvendor = PCI_ANY_ID,
1293 .subdevice = PCI_ANY_ID,
1294 .init = pci_ni8420_init,
1295 .setup = pci_default_setup,
1296 .exit = __devexit_p(pci_ni8420_exit),
1297 },
1298 {
1299 .vendor = PCI_VENDOR_ID_NI,
1300 .device = PCI_DEVICE_ID_NI_PCI2322I,
1301 .subvendor = PCI_ANY_ID,
1302 .subdevice = PCI_ANY_ID,
1303 .init = pci_ni8420_init,
1304 .setup = pci_default_setup,
1305 .exit = __devexit_p(pci_ni8420_exit),
1306 },
1307 {
1308 .vendor = PCI_VENDOR_ID_NI,
1309 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1310 .subvendor = PCI_ANY_ID,
1311 .subdevice = PCI_ANY_ID,
1312 .init = pci_ni8420_init,
1313 .setup = pci_default_setup,
1314 .exit = __devexit_p(pci_ni8420_exit),
1315 },
1316 {
1317 .vendor = PCI_VENDOR_ID_NI,
1318 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1319 .subvendor = PCI_ANY_ID,
1320 .subdevice = PCI_ANY_ID,
1321 .init = pci_ni8420_init,
1322 .setup = pci_default_setup,
1323 .exit = __devexit_p(pci_ni8420_exit),
1324 },
1325 {
1326 .vendor = PCI_VENDOR_ID_NI,
1327 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1328 .subvendor = PCI_ANY_ID,
1329 .subdevice = PCI_ANY_ID,
1330 .init = pci_ni8420_init,
1331 .setup = pci_default_setup,
1332 .exit = __devexit_p(pci_ni8420_exit),
1333 },
1334 {
1335 .vendor = PCI_VENDOR_ID_NI,
1336 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1337 .subvendor = PCI_ANY_ID,
1338 .subdevice = PCI_ANY_ID,
1339 .init = pci_ni8420_init,
1340 .setup = pci_default_setup,
1341 .exit = __devexit_p(pci_ni8420_exit),
1342 },
1343 {
1344 .vendor = PCI_VENDOR_ID_NI,
1345 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1346 .subvendor = PCI_ANY_ID,
1347 .subdevice = PCI_ANY_ID,
1348 .init = pci_ni8420_init,
1349 .setup = pci_default_setup,
1350 .exit = __devexit_p(pci_ni8420_exit),
1351 },
1352 {
1353 .vendor = PCI_VENDOR_ID_NI,
1354 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1355 .subvendor = PCI_ANY_ID,
1356 .subdevice = PCI_ANY_ID,
1357 .init = pci_ni8420_init,
1358 .setup = pci_default_setup,
1359 .exit = __devexit_p(pci_ni8420_exit),
1360 },
46a0fac9
SB		 1361 {
1362 .vendor = PCI_VENDOR_ID_NI,
1363 .device = PCI_ANY_ID,
1364 .subvendor = PCI_ANY_ID,
1365 .subdevice = PCI_ANY_ID,
1366 .init = pci_ni8430_init,
1367 .setup = pci_ni8430_setup,
1368 .exit = __devexit_p(pci_ni8430_exit),
1369 },
1da177e4
LT		 1370 /*
1371 * Panacom
1372 */
1373 {
1374 .vendor = PCI_VENDOR_ID_PANACOM,
1375 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1376 .subvendor = PCI_ANY_ID,
1377 .subdevice = PCI_ANY_ID,
1378 .init = pci_plx9050_init,
1379 .setup = pci_default_setup,
1380 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 1381 },
1da177e4
LT		 1382 {
1383 .vendor = PCI_VENDOR_ID_PANACOM,
1384 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1385 .subvendor = PCI_ANY_ID,
1386 .subdevice = PCI_ANY_ID,
1387 .init = pci_plx9050_init,
1388 .setup = pci_default_setup,
1389 .exit = __devexit_p(pci_plx9050_exit),
1390 },
1391 /*
1392 * PLX
1393 */
48212008
TH		 1394 {
1395 .vendor = PCI_VENDOR_ID_PLX,
1396 .device = PCI_DEVICE_ID_PLX_9030,
1397 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1398 .subdevice = PCI_ANY_ID,
1399 .setup = pci_default_setup,
1400 },
add7b58e
BH		 1401 {
1402 .vendor = PCI_VENDOR_ID_PLX,
1403 .device = PCI_DEVICE_ID_PLX_9050,
1404 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1405 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1406 .init = pci_plx9050_init,
1407 .setup = pci_default_setup,
1408 .exit = __devexit_p(pci_plx9050_exit),
1409 },
1da177e4
LT		 1410 {
1411 .vendor = PCI_VENDOR_ID_PLX,
1412 .device = PCI_DEVICE_ID_PLX_9050,
1413 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1414 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1415 .init = pci_plx9050_init,
1416 .setup = pci_default_setup,
1417 .exit = __devexit_p(pci_plx9050_exit),
1418 },
b76c5a07
CB		 1419 {
1420 .vendor = PCI_VENDOR_ID_PLX,
1421 .device = PCI_DEVICE_ID_PLX_9050,
1422 .subvendor = PCI_VENDOR_ID_PLX,
1423 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1424 .init = pci_plx9050_init,
1425 .setup = pci_default_setup,
1426 .exit = __devexit_p(pci_plx9050_exit),
1427 },
1da177e4
LT		 1428 {
1429 .vendor = PCI_VENDOR_ID_PLX,
1430 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1431 .subvendor = PCI_VENDOR_ID_PLX,
1432 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1433 .init = pci_plx9050_init,
1434 .setup = pci_default_setup,
1435 .exit = __devexit_p(pci_plx9050_exit),
1436 },
1437 /*
1438 * SBS Technologies, Inc., PMC-OCTALPRO 232
1439 */
1440 {
1441 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1442 .device = PCI_DEVICE_ID_OCTPRO,
1443 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1444 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1445 .init = sbs_init,
1446 .setup = sbs_setup,
1447 .exit = __devexit_p(sbs_exit),
1448 },
1449 /*
1450 * SBS Technologies, Inc., PMC-OCTALPRO 422
1451 */
1452 {
1453 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1454 .device = PCI_DEVICE_ID_OCTPRO,
1455 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1456 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1457 .init = sbs_init,
1458 .setup = sbs_setup,
1459 .exit = __devexit_p(sbs_exit),
1460 },
1461 /*
1462 * SBS Technologies, Inc., P-Octal 232
1463 */
1464 {
1465 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1466 .device = PCI_DEVICE_ID_OCTPRO,
1467 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1468 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1469 .init = sbs_init,
1470 .setup = sbs_setup,
1471 .exit = __devexit_p(sbs_exit),
1472 },
1473 /*
1474 * SBS Technologies, Inc., P-Octal 422
1475 */
1476 {
1477 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1478 .device = PCI_DEVICE_ID_OCTPRO,
1479 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1480 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1481 .init = sbs_init,
1482 .setup = sbs_setup,
1483 .exit = __devexit_p(sbs_exit),
1484 },
1da177e4 1485 /*
61a116ef 1486 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1487 */
1488 {
1489 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1490 .device = PCI_ANY_ID,
1da177e4
LT		 1491 .subvendor = PCI_ANY_ID,
1492 .subdevice = PCI_ANY_ID,
67d74b87 1493 .init = pci_siig_init,
3ec9c594 1494 .setup = pci_siig_setup,
1da177e4
LT		 1495 },
1496 /*
1497 * Titan cards
1498 */
1499 {
1500 .vendor = PCI_VENDOR_ID_TITAN,
1501 .device = PCI_DEVICE_ID_TITAN_400L,
1502 .subvendor = PCI_ANY_ID,
1503 .subdevice = PCI_ANY_ID,
1504 .setup = titan_400l_800l_setup,
1505 },
1506 {
1507 .vendor = PCI_VENDOR_ID_TITAN,
1508 .device = PCI_DEVICE_ID_TITAN_800L,
1509 .subvendor = PCI_ANY_ID,
1510 .subdevice = PCI_ANY_ID,
1511 .setup = titan_400l_800l_setup,
1512 },
1513 /*
1514 * Timedia cards
1515 */
1516 {
1517 .vendor = PCI_VENDOR_ID_TIMEDIA,
1518 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1519 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1520 .subdevice = PCI_ANY_ID,
b9b24558 1521 .probe = pci_timedia_probe,
1da177e4
LT		 1522 .init = pci_timedia_init,
1523 .setup = pci_timedia_setup,
1524 },
1525 {
1526 .vendor = PCI_VENDOR_ID_TIMEDIA,
1527 .device = PCI_ANY_ID,
1528 .subvendor = PCI_ANY_ID,
1529 .subdevice = PCI_ANY_ID,
1530 .setup = pci_timedia_setup,
1531 },
06315348
SH		 1532 /*
1533 * Exar cards
1534 */
1535 {
1536 .vendor = PCI_VENDOR_ID_EXAR,
1537 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1538 .subvendor = PCI_ANY_ID,
1539 .subdevice = PCI_ANY_ID,
1540 .setup = pci_xr17c154_setup,
1541 },
1542 {
1543 .vendor = PCI_VENDOR_ID_EXAR,
1544 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1545 .subvendor = PCI_ANY_ID,
1546 .subdevice = PCI_ANY_ID,
1547 .setup = pci_xr17c154_setup,
1548 },
1549 {
1550 .vendor = PCI_VENDOR_ID_EXAR,
1551 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1552 .subvendor = PCI_ANY_ID,
1553 .subdevice = PCI_ANY_ID,
1554 .setup = pci_xr17c154_setup,
1555 },
1da177e4
LT		 1556 /*
1557 * Xircom cards
1558 */
1559 {
1560 .vendor = PCI_VENDOR_ID_XIRCOM,
1561 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1562 .subvendor = PCI_ANY_ID,
1563 .subdevice = PCI_ANY_ID,
1564 .init = pci_xircom_init,
1565 .setup = pci_default_setup,
1566 },
1567 /*
61a116ef 1568 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1569 */
1570 {
1571 .vendor = PCI_VENDOR_ID_NETMOS,
1572 .device = PCI_ANY_ID,
1573 .subvendor = PCI_ANY_ID,
1574 .subdevice = PCI_ANY_ID,
1575 .init = pci_netmos_init,
7808edcd 1576 .setup = pci_netmos_9900_setup,
1da177e4 1577 },
9f2a036a 1578 /*
aa273ae5 1579 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 1580 */
1581 {
1582 .vendor = PCI_VENDOR_ID_OXSEMI,
1583 .device = PCI_ANY_ID,
1584 .subvendor = PCI_ANY_ID,
1585 .subdevice = PCI_ANY_ID,
1586 .init = pci_oxsemi_tornado_init,
1587 .setup = pci_default_setup,
1588 },
1589 {
1590 .vendor = PCI_VENDOR_ID_MAINPINE,
1591 .device = PCI_ANY_ID,
1592 .subvendor = PCI_ANY_ID,
1593 .subdevice = PCI_ANY_ID,
1594 .init = pci_oxsemi_tornado_init,
1595 .setup = pci_default_setup,
1596 },
aa273ae5
SK		 1597 {
1598 .vendor = PCI_VENDOR_ID_DIGI,
1599 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1600 .subvendor = PCI_SUBVENDOR_ID_IBM,
1601 .subdevice = PCI_ANY_ID,
1602 .init = pci_oxsemi_tornado_init,
1603 .setup = pci_default_setup,
1604 },
eb7073db
TM		 1605 {
1606 .vendor = PCI_VENDOR_ID_INTEL,
1607 .device = 0x8811,
1608 .init = pci_eg20t_init,
64d91cfa 1609 .setup = pci_default_setup,
eb7073db
TM		 1610 },
1611 {
1612 .vendor = PCI_VENDOR_ID_INTEL,
1613 .device = 0x8812,
1614 .init = pci_eg20t_init,
64d91cfa 1615 .setup = pci_default_setup,
eb7073db
TM		 1616 },
1617 {
1618 .vendor = PCI_VENDOR_ID_INTEL,
1619 .device = 0x8813,
1620 .init = pci_eg20t_init,
64d91cfa 1621 .setup = pci_default_setup,
eb7073db
TM		 1622 },
1623 {
1624 .vendor = PCI_VENDOR_ID_INTEL,
1625 .device = 0x8814,
1626 .init = pci_eg20t_init,
64d91cfa 1627 .setup = pci_default_setup,
eb7073db
TM		 1628 },
1629 {
1630 .vendor = 0x10DB,
1631 .device = 0x8027,
1632 .init = pci_eg20t_init,
64d91cfa 1633 .setup = pci_default_setup,
eb7073db
TM		 1634 },
1635 {
1636 .vendor = 0x10DB,
1637 .device = 0x8028,
1638 .init = pci_eg20t_init,
64d91cfa 1639 .setup = pci_default_setup,
eb7073db
TM		 1640 },
1641 {
1642 .vendor = 0x10DB,
1643 .device = 0x8029,
1644 .init = pci_eg20t_init,
64d91cfa 1645 .setup = pci_default_setup,
eb7073db
TM		 1646 },
1647 {
1648 .vendor = 0x10DB,
1649 .device = 0x800C,
1650 .init = pci_eg20t_init,
64d91cfa 1651 .setup = pci_default_setup,
eb7073db
TM		 1652 },
1653 {
1654 .vendor = 0x10DB,
1655 .device = 0x800D,
1656 .init = pci_eg20t_init,
64d91cfa 1657 .setup = pci_default_setup,
eb7073db 1658 },
d9a0fbfd
AP		 1659 /*
1660 * Cronyx Omega PCI (PLX-chip based)
1661 */
1662 {
1663 .vendor = PCI_VENDOR_ID_PLX,
1664 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1665 .subvendor = PCI_ANY_ID,
1666 .subdevice = PCI_ANY_ID,
1667 .setup = pci_omegapci_setup,
1668 },
1da177e4
LT		 1669 /*
1670 * Default "match everything" terminator entry
1671 */
1672 {
1673 .vendor = PCI_ANY_ID,
1674 .device = PCI_ANY_ID,
1675 .subvendor = PCI_ANY_ID,
1676 .subdevice = PCI_ANY_ID,
1677 .setup = pci_default_setup,
1678 }
1679};
1680
1681static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1682{
1683 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1684}
1685
1686static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1687{
1688 struct pci_serial_quirk *quirk;
1689
1690 for (quirk = pci_serial_quirks; ; quirk++)
1691 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1692 quirk_id_matches(quirk->device, dev->device) &&
1693 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1694 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1695 break;
1da177e4
LT		 1696 return quirk;
1697}
1698
dd68e88c 1699static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1700 const struct pciserial_board *board)
1da177e4
LT		 1701{
1702 if (board->flags & FL_NOIRQ)
1703 return 0;
1704 else
1705 return dev->irq;
1706}
1707
1708/*
1709 * This is the configuration table for all of the PCI serial boards
1710 * which we support. It is directly indexed by the pci_board_num_t enum
1711 * value, which is encoded in the pci_device_id PCI probe table's
1712 * driver_data member.
1713 *
1714 * The makeup of these names are:
26e92861 1715 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1716 *
26e92861
GH		 1717 * bn = PCI BAR number
1718 * bt = Index using PCI BARs
1719 * n = number of serial ports
1720 * baud = baud rate
1721 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1722 *
26e92861 1723 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1724 *
1da177e4
LT		 1725 * Please note: in theory if n = 1, _bt infix should make no difference.
1726 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1727 */
1728enum pci_board_num_t {
1729 pbn_default = 0,
1730
1731 pbn_b0_1_115200,
1732 pbn_b0_2_115200,
1733 pbn_b0_4_115200,
1734 pbn_b0_5_115200,
bf0df636 1735 pbn_b0_8_115200,
1da177e4
LT		 1736
1737 pbn_b0_1_921600,
1738 pbn_b0_2_921600,
1739 pbn_b0_4_921600,
1740
db1de159
DR		 1741 pbn_b0_2_1130000,
1742
fbc0dc0d
AP		 1743 pbn_b0_4_1152000,
1744
26e92861
GH		 1745 pbn_b0_2_1843200,
1746 pbn_b0_4_1843200,
1747
1748 pbn_b0_2_1843200_200,
1749 pbn_b0_4_1843200_200,
1750 pbn_b0_8_1843200_200,
1751
7106b4e3
LH		 1752 pbn_b0_1_4000000,
1753
1da177e4
LT		 1754 pbn_b0_bt_1_115200,
1755 pbn_b0_bt_2_115200,
ac6ec5b1 1756 pbn_b0_bt_4_115200,
1da177e4
LT		 1757 pbn_b0_bt_8_115200,
1758
1759 pbn_b0_bt_1_460800,
1760 pbn_b0_bt_2_460800,
1761 pbn_b0_bt_4_460800,
1762
1763 pbn_b0_bt_1_921600,
1764 pbn_b0_bt_2_921600,
1765 pbn_b0_bt_4_921600,
1766 pbn_b0_bt_8_921600,
1767
1768 pbn_b1_1_115200,
1769 pbn_b1_2_115200,
1770 pbn_b1_4_115200,
1771 pbn_b1_8_115200,
04bf7e74 1772 pbn_b1_16_115200,
1da177e4
LT		 1773
1774 pbn_b1_1_921600,
1775 pbn_b1_2_921600,
1776 pbn_b1_4_921600,
1777 pbn_b1_8_921600,
1778
26e92861
GH		 1779 pbn_b1_2_1250000,
1780
84f8c6fc 1781 pbn_b1_bt_1_115200,
04bf7e74
WP		 1782 pbn_b1_bt_2_115200,
1783 pbn_b1_bt_4_115200,
1784
1da177e4
LT		 1785 pbn_b1_bt_2_921600,
1786
1787 pbn_b1_1_1382400,
1788 pbn_b1_2_1382400,
1789 pbn_b1_4_1382400,
1790 pbn_b1_8_1382400,
1791
1792 pbn_b2_1_115200,
737c1756 1793 pbn_b2_2_115200,
a9cccd34 1794 pbn_b2_4_115200,
1da177e4
LT		 1795 pbn_b2_8_115200,
1796
1797 pbn_b2_1_460800,
1798 pbn_b2_4_460800,
1799 pbn_b2_8_460800,
1800 pbn_b2_16_460800,
1801
1802 pbn_b2_1_921600,
1803 pbn_b2_4_921600,
1804 pbn_b2_8_921600,
1805
e847003f
LB		 1806 pbn_b2_8_1152000,
1807
1da177e4
LT		 1808 pbn_b2_bt_1_115200,
1809 pbn_b2_bt_2_115200,
1810 pbn_b2_bt_4_115200,
1811
1812 pbn_b2_bt_2_921600,
1813 pbn_b2_bt_4_921600,
1814
d9004eb4 1815 pbn_b3_2_115200,
1da177e4
LT		 1816 pbn_b3_4_115200,
1817 pbn_b3_8_115200,
1818
66169ad1
YY		 1819 pbn_b4_bt_2_921600,
1820 pbn_b4_bt_4_921600,
1821 pbn_b4_bt_8_921600,
1822
1da177e4
LT		 1823 /*
1824 * Board-specific versions.
1825 */
1826 pbn_panacom,
1827 pbn_panacom2,
1828 pbn_panacom4,
add7b58e 1829 pbn_exsys_4055,
1da177e4
LT		 1830 pbn_plx_romulus,
1831 pbn_oxsemi,
7106b4e3
LH		 1832 pbn_oxsemi_1_4000000,
1833 pbn_oxsemi_2_4000000,
1834 pbn_oxsemi_4_4000000,
1835 pbn_oxsemi_8_4000000,
1da177e4
LT		 1836 pbn_intel_i960,
1837 pbn_sgi_ioc3,
1da177e4
LT		 1838 pbn_computone_4,
1839 pbn_computone_6,
1840 pbn_computone_8,
1841 pbn_sbsxrsio,
1842 pbn_exar_XR17C152,
1843 pbn_exar_XR17C154,
1844 pbn_exar_XR17C158,
c68d2b15 1845 pbn_exar_ibm_saturn,
aa798505 1846 pbn_pasemi_1682M,
46a0fac9
SB		 1847 pbn_ni8430_2,
1848 pbn_ni8430_4,
1849 pbn_ni8430_8,
1850 pbn_ni8430_16,
1b62cbf2
KJ		 1851 pbn_ADDIDATA_PCIe_1_3906250,
1852 pbn_ADDIDATA_PCIe_2_3906250,
1853 pbn_ADDIDATA_PCIe_4_3906250,
1854 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 1855 pbn_ce4100_1_115200,
d9a0fbfd 1856 pbn_omegapci,
7808edcd 1857 pbn_NETMOS9900_2s_115200,
1da177e4
LT		 1858};
1859
1860/*
1861 * uart_offset - the space between channels
1862 * reg_shift - describes how the UART registers are mapped
1863 * to PCI memory by the card.
1864 * For example IER register on SBS, Inc. PMC-OctPro is located at
1865 * offset 0x10 from the UART base, while UART_IER is defined as 1
1866 * in include/linux/serial_reg.h,
1867 * see first lines of serial_in() and serial_out() in 8250.c
1868*/
1869
1c7c1fe5 1870static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1871 [pbn_default] = {
1872 .flags = FL_BASE0,
1873 .num_ports = 1,
1874 .base_baud = 115200,
1875 .uart_offset = 8,
1876 },
1877 [pbn_b0_1_115200] = {
1878 .flags = FL_BASE0,
1879 .num_ports = 1,
1880 .base_baud = 115200,
1881 .uart_offset = 8,
1882 },
1883 [pbn_b0_2_115200] = {
1884 .flags = FL_BASE0,
1885 .num_ports = 2,
1886 .base_baud = 115200,
1887 .uart_offset = 8,
1888 },
1889 [pbn_b0_4_115200] = {
1890 .flags = FL_BASE0,
1891 .num_ports = 4,
1892 .base_baud = 115200,
1893 .uart_offset = 8,
1894 },
1895 [pbn_b0_5_115200] = {
1896 .flags = FL_BASE0,
1897 .num_ports = 5,
1898 .base_baud = 115200,
1899 .uart_offset = 8,
1900 },
bf0df636
AC		 1901 [pbn_b0_8_115200] = {
1902 .flags = FL_BASE0,
1903 .num_ports = 8,
1904 .base_baud = 115200,
1905 .uart_offset = 8,
1906 },
1da177e4
LT		 1907 [pbn_b0_1_921600] = {
1908 .flags = FL_BASE0,
1909 .num_ports = 1,
1910 .base_baud = 921600,
1911 .uart_offset = 8,
1912 },
1913 [pbn_b0_2_921600] = {
1914 .flags = FL_BASE0,
1915 .num_ports = 2,
1916 .base_baud = 921600,
1917 .uart_offset = 8,
1918 },
1919 [pbn_b0_4_921600] = {
1920 .flags = FL_BASE0,
1921 .num_ports = 4,
1922 .base_baud = 921600,
1923 .uart_offset = 8,
1924 },
db1de159
DR		 1925
1926 [pbn_b0_2_1130000] = {
1927 .flags = FL_BASE0,
1928 .num_ports = 2,
1929 .base_baud = 1130000,
1930 .uart_offset = 8,
1931 },
1932
fbc0dc0d
AP		 1933 [pbn_b0_4_1152000] = {
1934 .flags = FL_BASE0,
1935 .num_ports = 4,
1936 .base_baud = 1152000,
1937 .uart_offset = 8,
1938 },
1da177e4 1939
26e92861
GH		 1940 [pbn_b0_2_1843200] = {
1941 .flags = FL_BASE0,
1942 .num_ports = 2,
1943 .base_baud = 1843200,
1944 .uart_offset = 8,
1945 },
1946 [pbn_b0_4_1843200] = {
1947 .flags = FL_BASE0,
1948 .num_ports = 4,
1949 .base_baud = 1843200,
1950 .uart_offset = 8,
1951 },
1952
1953 [pbn_b0_2_1843200_200] = {
1954 .flags = FL_BASE0,
1955 .num_ports = 2,
1956 .base_baud = 1843200,
1957 .uart_offset = 0x200,
1958 },
1959 [pbn_b0_4_1843200_200] = {
1960 .flags = FL_BASE0,
1961 .num_ports = 4,
1962 .base_baud = 1843200,
1963 .uart_offset = 0x200,
1964 },
1965 [pbn_b0_8_1843200_200] = {
1966 .flags = FL_BASE0,
1967 .num_ports = 8,
1968 .base_baud = 1843200,
1969 .uart_offset = 0x200,
1970 },
7106b4e3
LH		 1971 [pbn_b0_1_4000000] = {
1972 .flags = FL_BASE0,
1973 .num_ports = 1,
1974 .base_baud = 4000000,
1975 .uart_offset = 8,
1976 },
26e92861 1977
1da177e4
LT		 1978 [pbn_b0_bt_1_115200] = {
1979 .flags = FL_BASE0|FL_BASE_BARS,
1980 .num_ports = 1,
1981 .base_baud = 115200,
1982 .uart_offset = 8,
1983 },
1984 [pbn_b0_bt_2_115200] = {
1985 .flags = FL_BASE0|FL_BASE_BARS,
1986 .num_ports = 2,
1987 .base_baud = 115200,
1988 .uart_offset = 8,
1989 },
ac6ec5b1
IS		 1990 [pbn_b0_bt_4_115200] = {
1991 .flags = FL_BASE0|FL_BASE_BARS,
1992 .num_ports = 4,
1993 .base_baud = 115200,
1994 .uart_offset = 8,
1995 },
1da177e4
LT		 1996 [pbn_b0_bt_8_115200] = {
1997 .flags = FL_BASE0|FL_BASE_BARS,
1998 .num_ports = 8,
1999 .base_baud = 115200,
2000 .uart_offset = 8,
2001 },
2002
2003 [pbn_b0_bt_1_460800] = {
2004 .flags = FL_BASE0|FL_BASE_BARS,
2005 .num_ports = 1,
2006 .base_baud = 460800,
2007 .uart_offset = 8,
2008 },
2009 [pbn_b0_bt_2_460800] = {
2010 .flags = FL_BASE0|FL_BASE_BARS,
2011 .num_ports = 2,
2012 .base_baud = 460800,
2013 .uart_offset = 8,
2014 },
2015 [pbn_b0_bt_4_460800] = {
2016 .flags = FL_BASE0|FL_BASE_BARS,
2017 .num_ports = 4,
2018 .base_baud = 460800,
2019 .uart_offset = 8,
2020 },
2021
2022 [pbn_b0_bt_1_921600] = {
2023 .flags = FL_BASE0|FL_BASE_BARS,
2024 .num_ports = 1,
2025 .base_baud = 921600,
2026 .uart_offset = 8,
2027 },
2028 [pbn_b0_bt_2_921600] = {
2029 .flags = FL_BASE0|FL_BASE_BARS,
2030 .num_ports = 2,
2031 .base_baud = 921600,
2032 .uart_offset = 8,
2033 },
2034 [pbn_b0_bt_4_921600] = {
2035 .flags = FL_BASE0|FL_BASE_BARS,
2036 .num_ports = 4,
2037 .base_baud = 921600,
2038 .uart_offset = 8,
2039 },
2040 [pbn_b0_bt_8_921600] = {
2041 .flags = FL_BASE0|FL_BASE_BARS,
2042 .num_ports = 8,
2043 .base_baud = 921600,
2044 .uart_offset = 8,
2045 },
2046
2047 [pbn_b1_1_115200] = {
2048 .flags = FL_BASE1,
2049 .num_ports = 1,
2050 .base_baud = 115200,
2051 .uart_offset = 8,
2052 },
2053 [pbn_b1_2_115200] = {
2054 .flags = FL_BASE1,
2055 .num_ports = 2,
2056 .base_baud = 115200,
2057 .uart_offset = 8,
2058 },
2059 [pbn_b1_4_115200] = {
2060 .flags = FL_BASE1,
2061 .num_ports = 4,
2062 .base_baud = 115200,
2063 .uart_offset = 8,
2064 },
2065 [pbn_b1_8_115200] = {
2066 .flags = FL_BASE1,
2067 .num_ports = 8,
2068 .base_baud = 115200,
2069 .uart_offset = 8,
2070 },
04bf7e74
WP		 2071 [pbn_b1_16_115200] = {
2072 .flags = FL_BASE1,
2073 .num_ports = 16,
2074 .base_baud = 115200,
2075 .uart_offset = 8,
2076 },
1da177e4
LT		 2077
2078 [pbn_b1_1_921600] = {
2079 .flags = FL_BASE1,
2080 .num_ports = 1,
2081 .base_baud = 921600,
2082 .uart_offset = 8,
2083 },
2084 [pbn_b1_2_921600] = {
2085 .flags = FL_BASE1,
2086 .num_ports = 2,
2087 .base_baud = 921600,
2088 .uart_offset = 8,
2089 },
2090 [pbn_b1_4_921600] = {
2091 .flags = FL_BASE1,
2092 .num_ports = 4,
2093 .base_baud = 921600,
2094 .uart_offset = 8,
2095 },
2096 [pbn_b1_8_921600] = {
2097 .flags = FL_BASE1,
2098 .num_ports = 8,
2099 .base_baud = 921600,
2100 .uart_offset = 8,
2101 },
26e92861
GH		 2102 [pbn_b1_2_1250000] = {
2103 .flags = FL_BASE1,
2104 .num_ports = 2,
2105 .base_baud = 1250000,
2106 .uart_offset = 8,
2107 },
1da177e4 2108
84f8c6fc
NV		 2109 [pbn_b1_bt_1_115200] = {
2110 .flags = FL_BASE1|FL_BASE_BARS,
2111 .num_ports = 1,
2112 .base_baud = 115200,
2113 .uart_offset = 8,
2114 },
04bf7e74
WP		 2115 [pbn_b1_bt_2_115200] = {
2116 .flags = FL_BASE1|FL_BASE_BARS,
2117 .num_ports = 2,
2118 .base_baud = 115200,
2119 .uart_offset = 8,
2120 },
2121 [pbn_b1_bt_4_115200] = {
2122 .flags = FL_BASE1|FL_BASE_BARS,
2123 .num_ports = 4,
2124 .base_baud = 115200,
2125 .uart_offset = 8,
2126 },
84f8c6fc 2127
1da177e4
LT		 2128 [pbn_b1_bt_2_921600] = {
2129 .flags = FL_BASE1|FL_BASE_BARS,
2130 .num_ports = 2,
2131 .base_baud = 921600,
2132 .uart_offset = 8,
2133 },
2134
2135 [pbn_b1_1_1382400] = {
2136 .flags = FL_BASE1,
2137 .num_ports = 1,
2138 .base_baud = 1382400,
2139 .uart_offset = 8,
2140 },
2141 [pbn_b1_2_1382400] = {
2142 .flags = FL_BASE1,
2143 .num_ports = 2,
2144 .base_baud = 1382400,
2145 .uart_offset = 8,
2146 },
2147 [pbn_b1_4_1382400] = {
2148 .flags = FL_BASE1,
2149 .num_ports = 4,
2150 .base_baud = 1382400,
2151 .uart_offset = 8,
2152 },
2153 [pbn_b1_8_1382400] = {
2154 .flags = FL_BASE1,
2155 .num_ports = 8,
2156 .base_baud = 1382400,
2157 .uart_offset = 8,
2158 },
2159
2160 [pbn_b2_1_115200] = {
2161 .flags = FL_BASE2,
2162 .num_ports = 1,
2163 .base_baud = 115200,
2164 .uart_offset = 8,
2165 },
737c1756
PH		 2166 [pbn_b2_2_115200] = {
2167 .flags = FL_BASE2,
2168 .num_ports = 2,
2169 .base_baud = 115200,
2170 .uart_offset = 8,
2171 },
a9cccd34
MF		 2172 [pbn_b2_4_115200] = {
2173 .flags = FL_BASE2,
2174 .num_ports = 4,
2175 .base_baud = 115200,
2176 .uart_offset = 8,
2177 },
1da177e4
LT		 2178 [pbn_b2_8_115200] = {
2179 .flags = FL_BASE2,
2180 .num_ports = 8,
2181 .base_baud = 115200,
2182 .uart_offset = 8,
2183 },
2184
2185 [pbn_b2_1_460800] = {
2186 .flags = FL_BASE2,
2187 .num_ports = 1,
2188 .base_baud = 460800,
2189 .uart_offset = 8,
2190 },
2191 [pbn_b2_4_460800] = {
2192 .flags = FL_BASE2,
2193 .num_ports = 4,
2194 .base_baud = 460800,
2195 .uart_offset = 8,
2196 },
2197 [pbn_b2_8_460800] = {
2198 .flags = FL_BASE2,
2199 .num_ports = 8,
2200 .base_baud = 460800,
2201 .uart_offset = 8,
2202 },
2203 [pbn_b2_16_460800] = {
2204 .flags = FL_BASE2,
2205 .num_ports = 16,
2206 .base_baud = 460800,
2207 .uart_offset = 8,
2208 },
2209
2210 [pbn_b2_1_921600] = {
2211 .flags = FL_BASE2,
2212 .num_ports = 1,
2213 .base_baud = 921600,
2214 .uart_offset = 8,
2215 },
2216 [pbn_b2_4_921600] = {
2217 .flags = FL_BASE2,
2218 .num_ports = 4,
2219 .base_baud = 921600,
2220 .uart_offset = 8,
2221 },
2222 [pbn_b2_8_921600] = {
2223 .flags = FL_BASE2,
2224 .num_ports = 8,
2225 .base_baud = 921600,
2226 .uart_offset = 8,
2227 },
2228
e847003f
LB		 2229 [pbn_b2_8_1152000] = {
2230 .flags = FL_BASE2,
2231 .num_ports = 8,
2232 .base_baud = 1152000,
2233 .uart_offset = 8,
2234 },
2235
1da177e4
LT		 2236 [pbn_b2_bt_1_115200] = {
2237 .flags = FL_BASE2|FL_BASE_BARS,
2238 .num_ports = 1,
2239 .base_baud = 115200,
2240 .uart_offset = 8,
2241 },
2242 [pbn_b2_bt_2_115200] = {
2243 .flags = FL_BASE2|FL_BASE_BARS,
2244 .num_ports = 2,
2245 .base_baud = 115200,
2246 .uart_offset = 8,
2247 },
2248 [pbn_b2_bt_4_115200] = {
2249 .flags = FL_BASE2|FL_BASE_BARS,
2250 .num_ports = 4,
2251 .base_baud = 115200,
2252 .uart_offset = 8,
2253 },
2254
2255 [pbn_b2_bt_2_921600] = {
2256 .flags = FL_BASE2|FL_BASE_BARS,
2257 .num_ports = 2,
2258 .base_baud = 921600,
2259 .uart_offset = 8,
2260 },
2261 [pbn_b2_bt_4_921600] = {
2262 .flags = FL_BASE2|FL_BASE_BARS,
2263 .num_ports = 4,
2264 .base_baud = 921600,
2265 .uart_offset = 8,
2266 },
2267
d9004eb4
ABL		 2268 [pbn_b3_2_115200] = {
2269 .flags = FL_BASE3,
2270 .num_ports = 2,
2271 .base_baud = 115200,
2272 .uart_offset = 8,
2273 },
1da177e4
LT		 2274 [pbn_b3_4_115200] = {
2275 .flags = FL_BASE3,
2276 .num_ports = 4,
2277 .base_baud = 115200,
2278 .uart_offset = 8,
2279 },
2280 [pbn_b3_8_115200] = {
2281 .flags = FL_BASE3,
2282 .num_ports = 8,
2283 .base_baud = 115200,
2284 .uart_offset = 8,
2285 },
2286
66169ad1
YY		 2287 [pbn_b4_bt_2_921600] = {
2288 .flags = FL_BASE4,
2289 .num_ports = 2,
2290 .base_baud = 921600,
2291 .uart_offset = 8,
2292 },
2293 [pbn_b4_bt_4_921600] = {
2294 .flags = FL_BASE4,
2295 .num_ports = 4,
2296 .base_baud = 921600,
2297 .uart_offset = 8,
2298 },
2299 [pbn_b4_bt_8_921600] = {
2300 .flags = FL_BASE4,
2301 .num_ports = 8,
2302 .base_baud = 921600,
2303 .uart_offset = 8,
2304 },
2305
1da177e4
LT		 2306 /*
2307 * Entries following this are board-specific.
2308 */
2309
2310 /*
2311 * Panacom - IOMEM
2312 */
2313 [pbn_panacom] = {
2314 .flags = FL_BASE2,
2315 .num_ports = 2,
2316 .base_baud = 921600,
2317 .uart_offset = 0x400,
2318 .reg_shift = 7,
2319 },
2320 [pbn_panacom2] = {
2321 .flags = FL_BASE2|FL_BASE_BARS,
2322 .num_ports = 2,
2323 .base_baud = 921600,
2324 .uart_offset = 0x400,
2325 .reg_shift = 7,
2326 },
2327 [pbn_panacom4] = {
2328 .flags = FL_BASE2|FL_BASE_BARS,
2329 .num_ports = 4,
2330 .base_baud = 921600,
2331 .uart_offset = 0x400,
2332 .reg_shift = 7,
2333 },
2334
add7b58e
BH		 2335 [pbn_exsys_4055] = {
2336 .flags = FL_BASE2,
2337 .num_ports = 4,
2338 .base_baud = 115200,
2339 .uart_offset = 8,
2340 },
2341
1da177e4
LT		 2342 /* I think this entry is broken - the first_offset looks wrong --rmk */
2343 [pbn_plx_romulus] = {
2344 .flags = FL_BASE2,
2345 .num_ports = 4,
2346 .base_baud = 921600,
2347 .uart_offset = 8 << 2,
2348 .reg_shift = 2,
2349 .first_offset = 0x03,
2350 },
2351
2352 /*
2353 * This board uses the size of PCI Base region 0 to
2354 * signal now many ports are available
2355 */
2356 [pbn_oxsemi] = {
2357 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2358 .num_ports = 32,
2359 .base_baud = 115200,
2360 .uart_offset = 8,
2361 },
7106b4e3
LH		 2362 [pbn_oxsemi_1_4000000] = {
2363 .flags = FL_BASE0,
2364 .num_ports = 1,
2365 .base_baud = 4000000,
2366 .uart_offset = 0x200,
2367 .first_offset = 0x1000,
2368 },
2369 [pbn_oxsemi_2_4000000] = {
2370 .flags = FL_BASE0,
2371 .num_ports = 2,
2372 .base_baud = 4000000,
2373 .uart_offset = 0x200,
2374 .first_offset = 0x1000,
2375 },
2376 [pbn_oxsemi_4_4000000] = {
2377 .flags = FL_BASE0,
2378 .num_ports = 4,
2379 .base_baud = 4000000,
2380 .uart_offset = 0x200,
2381 .first_offset = 0x1000,
2382 },
2383 [pbn_oxsemi_8_4000000] = {
2384 .flags = FL_BASE0,
2385 .num_ports = 8,
2386 .base_baud = 4000000,
2387 .uart_offset = 0x200,
2388 .first_offset = 0x1000,
2389 },
2390
1da177e4
LT		 2391
2392 /*
2393 * EKF addition for i960 Boards form EKF with serial port.
2394 * Max 256 ports.
2395 */
2396 [pbn_intel_i960] = {
2397 .flags = FL_BASE0,
2398 .num_ports = 32,
2399 .base_baud = 921600,
2400 .uart_offset = 8 << 2,
2401 .reg_shift = 2,
2402 .first_offset = 0x10000,
2403 },
2404 [pbn_sgi_ioc3] = {
2405 .flags = FL_BASE0|FL_NOIRQ,
2406 .num_ports = 1,
2407 .base_baud = 458333,
2408 .uart_offset = 8,
2409 .reg_shift = 0,
2410 .first_offset = 0x20178,
2411 },
2412
1da177e4
LT		 2413 /*
2414 * Computone - uses IOMEM.
2415 */
2416 [pbn_computone_4] = {
2417 .flags = FL_BASE0,
2418 .num_ports = 4,
2419 .base_baud = 921600,
2420 .uart_offset = 0x40,
2421 .reg_shift = 2,
2422 .first_offset = 0x200,
2423 },
2424 [pbn_computone_6] = {
2425 .flags = FL_BASE0,
2426 .num_ports = 6,
2427 .base_baud = 921600,
2428 .uart_offset = 0x40,
2429 .reg_shift = 2,
2430 .first_offset = 0x200,
2431 },
2432 [pbn_computone_8] = {
2433 .flags = FL_BASE0,
2434 .num_ports = 8,
2435 .base_baud = 921600,
2436 .uart_offset = 0x40,
2437 .reg_shift = 2,
2438 .first_offset = 0x200,
2439 },
2440 [pbn_sbsxrsio] = {
2441 .flags = FL_BASE0,
2442 .num_ports = 8,
2443 .base_baud = 460800,
2444 .uart_offset = 256,
2445 .reg_shift = 4,
2446 },
2447 /*
2448 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2449 * Only basic 16550A support.
2450 * XR17C15[24] are not tested, but they should work.
2451 */
2452 [pbn_exar_XR17C152] = {
2453 .flags = FL_BASE0,
2454 .num_ports = 2,
2455 .base_baud = 921600,
2456 .uart_offset = 0x200,
2457 },
2458 [pbn_exar_XR17C154] = {
2459 .flags = FL_BASE0,
2460 .num_ports = 4,
2461 .base_baud = 921600,
2462 .uart_offset = 0x200,
2463 },
2464 [pbn_exar_XR17C158] = {
2465 .flags = FL_BASE0,
2466 .num_ports = 8,
2467 .base_baud = 921600,
2468 .uart_offset = 0x200,
2469 },
c68d2b15
BH		 2470 [pbn_exar_ibm_saturn] = {
2471 .flags = FL_BASE0,
2472 .num_ports = 1,
2473 .base_baud = 921600,
2474 .uart_offset = 0x200,
2475 },
2476
aa798505
OJ		 2477 /*
2478 * PA Semi PWRficient PA6T-1682M on-chip UART
2479 */
2480 [pbn_pasemi_1682M] = {
2481 .flags = FL_BASE0,
2482 .num_ports = 1,
2483 .base_baud = 8333333,
2484 },
46a0fac9
SB		 2485 /*
2486 * National Instruments 843x
2487 */
2488 [pbn_ni8430_16] = {
2489 .flags = FL_BASE0,
2490 .num_ports = 16,
2491 .base_baud = 3686400,
2492 .uart_offset = 0x10,
2493 .first_offset = 0x800,
2494 },
2495 [pbn_ni8430_8] = {
2496 .flags = FL_BASE0,
2497 .num_ports = 8,
2498 .base_baud = 3686400,
2499 .uart_offset = 0x10,
2500 .first_offset = 0x800,
2501 },
2502 [pbn_ni8430_4] = {
2503 .flags = FL_BASE0,
2504 .num_ports = 4,
2505 .base_baud = 3686400,
2506 .uart_offset = 0x10,
2507 .first_offset = 0x800,
2508 },
2509 [pbn_ni8430_2] = {
2510 .flags = FL_BASE0,
2511 .num_ports = 2,
2512 .base_baud = 3686400,
2513 .uart_offset = 0x10,
2514 .first_offset = 0x800,
2515 },
1b62cbf2
KJ		 2516 /*
2517 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2518 */
2519 [pbn_ADDIDATA_PCIe_1_3906250] = {
2520 .flags = FL_BASE0,
2521 .num_ports = 1,
2522 .base_baud = 3906250,
2523 .uart_offset = 0x200,
2524 .first_offset = 0x1000,
2525 },
2526 [pbn_ADDIDATA_PCIe_2_3906250] = {
2527 .flags = FL_BASE0,
2528 .num_ports = 2,
2529 .base_baud = 3906250,
2530 .uart_offset = 0x200,
2531 .first_offset = 0x1000,
2532 },
2533 [pbn_ADDIDATA_PCIe_4_3906250] = {
2534 .flags = FL_BASE0,
2535 .num_ports = 4,
2536 .base_baud = 3906250,
2537 .uart_offset = 0x200,
2538 .first_offset = 0x1000,
2539 },
2540 [pbn_ADDIDATA_PCIe_8_3906250] = {
2541 .flags = FL_BASE0,
2542 .num_ports = 8,
2543 .base_baud = 3906250,
2544 .uart_offset = 0x200,
2545 .first_offset = 0x1000,
2546 },
095e24b0
DB		 2547 [pbn_ce4100_1_115200] = {
2548 .flags = FL_BASE0,
2549 .num_ports = 1,
2550 .base_baud = 921600,
2551 .reg_shift = 2,
2552 },
d9a0fbfd
AP		 2553 [pbn_omegapci] = {
2554 .flags = FL_BASE0,
2555 .num_ports = 8,
2556 .base_baud = 115200,
2557 .uart_offset = 0x200,
2558 },
7808edcd
NG		 2559 [pbn_NETMOS9900_2s_115200] = {
2560 .flags = FL_BASE0,
2561 .num_ports = 2,
2562 .base_baud = 115200,
2563 },
1da177e4
LT		 2564};
2565
436bbd43 2566static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 2567 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 2568 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2569 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
436bbd43
CS		 2570};
2571
1da177e4
LT		 2572/*
2573 * Given a complete unknown PCI device, try to use some heuristics to
2574 * guess what the configuration might be, based on the pitiful PCI
2575 * serial specs. Returns 0 on success, 1 on failure.
2576 */
2577static int __devinit
1c7c1fe5 2578serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2579{
436bbd43 2580 const struct pci_device_id *blacklist;
1da177e4 2581 int num_iomem, num_port, first_port = -1, i;
5756ee99 2582
1da177e4
LT		 2583 /*
2584 * If it is not a communications device or the programming
2585 * interface is greater than 6, give up.
2586 *
2587 * (Should we try to make guesses for multiport serial devices
5756ee99 2588 * later?)
1da177e4
LT		 2589 */
2590 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2591 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2592 (dev->class & 0xff) > 6)
2593 return -ENODEV;
2594
436bbd43
CS		 2595 /*
2596 * Do not access blacklisted devices that are known not to
2597 * feature serial ports.
2598 */
2599 for (blacklist = softmodem_blacklist;
2600 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2601 blacklist++) {
2602 if (dev->vendor == blacklist->vendor &&
2603 dev->device == blacklist->device)
2604 return -ENODEV;
2605 }
2606
1da177e4
LT		 2607 num_iomem = num_port = 0;
2608 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2609 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2610 num_port++;
2611 if (first_port == -1)
2612 first_port = i;
2613 }
2614 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2615 num_iomem++;
2616 }
2617
2618 /*
2619 * If there is 1 or 0 iomem regions, and exactly one port,
2620 * use it. We guess the number of ports based on the IO
2621 * region size.
2622 */
2623 if (num_iomem <= 1 && num_port == 1) {
2624 board->flags = first_port;
2625 board->num_ports = pci_resource_len(dev, first_port) / 8;
2626 return 0;
2627 }
2628
2629 /*
2630 * Now guess if we've got a board which indexes by BARs.
2631 * Each IO BAR should be 8 bytes, and they should follow
2632 * consecutively.
2633 */
2634 first_port = -1;
2635 num_port = 0;
2636 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2637 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2638 pci_resource_len(dev, i) == 8 &&
2639 (first_port == -1 || (first_port + num_port) == i)) {
2640 num_port++;
2641 if (first_port == -1)
2642 first_port = i;
2643 }
2644 }
2645
2646 if (num_port > 1) {
2647 board->flags = first_port | FL_BASE_BARS;
2648 board->num_ports = num_port;
2649 return 0;
2650 }
2651
2652 return -ENODEV;
2653}
2654
2655static inline int
975a1a7d
RK		 2656serial_pci_matches(const struct pciserial_board *board,
2657 const struct pciserial_board *guessed)
1da177e4
LT		 2658{
2659 return
2660 board->num_ports == guessed->num_ports &&
2661 board->base_baud == guessed->base_baud &&
2662 board->uart_offset == guessed->uart_offset &&
2663 board->reg_shift == guessed->reg_shift &&
2664 board->first_offset == guessed->first_offset;
2665}
2666
241fc436 2667struct serial_private *
975a1a7d 2668pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2669{
72ce9a83 2670 struct uart_port serial_port;
1da177e4 2671 struct serial_private *priv;
1da177e4
LT		 2672 struct pci_serial_quirk *quirk;
2673 int rc, nr_ports, i;
2674
1da177e4
LT		 2675 nr_ports = board->num_ports;
2676
2677 /*
2678 * Find an init and setup quirks.
2679 */
2680 quirk = find_quirk(dev);
2681
2682 /*
2683 * Run the new-style initialization function.
2684 * The initialization function returns:
2685 * <0 - error
2686 * 0 - use board->num_ports
2687 * >0 - number of ports
2688 */
2689 if (quirk->init) {
2690 rc = quirk->init(dev);
241fc436
RK		 2691 if (rc < 0) {
2692 priv = ERR_PTR(rc);
2693 goto err_out;
2694 }
1da177e4
LT		 2695 if (rc)
2696 nr_ports = rc;
2697 }
2698
8f31bb39 2699 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2700 sizeof(unsigned int) * nr_ports,
2701 GFP_KERNEL);
2702 if (!priv) {
241fc436
RK		 2703 priv = ERR_PTR(-ENOMEM);
2704 goto err_deinit;
1da177e4
LT		 2705 }
2706
70db3d91 2707 priv->dev = dev;
1da177e4 2708 priv->quirk = quirk;
1da177e4 2709
72ce9a83
RK		 2710 memset(&serial_port, 0, sizeof(struct uart_port));
2711 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2712 serial_port.uartclk = board->base_baud * 16;
2713 serial_port.irq = get_pci_irq(dev, board);
2714 serial_port.dev = &dev->dev;
2715
1da177e4 2716 for (i = 0; i < nr_ports; i++) {
70db3d91 2717 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 2718 break;
72ce9a83 2719
1da177e4 2720#ifdef SERIAL_DEBUG_PCI
80647b95 2721 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
1da177e4
LT		 2722 serial_port.iobase, serial_port.irq, serial_port.iotype);
2723#endif
5756ee99 2724
1da177e4
LT		 2725 priv->line[i] = serial8250_register_port(&serial_port);
2726 if (priv->line[i] < 0) {
2727 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2728 break;
2729 }
2730 }
1da177e4 2731 priv->nr = i;
241fc436 2732 return priv;
1da177e4 2733
5756ee99 2734err_deinit:
1da177e4
LT		 2735 if (quirk->exit)
2736 quirk->exit(dev);
5756ee99 2737err_out:
241fc436 2738 return priv;
1da177e4 2739}
241fc436 2740EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2741
241fc436 2742void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2743{
056a8763
RK		 2744 struct pci_serial_quirk *quirk;
2745 int i;
1da177e4 2746
056a8763
RK		 2747 for (i = 0; i < priv->nr; i++)
2748 serial8250_unregister_port(priv->line[i]);
1da177e4 2749
056a8763
RK		 2750 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2751 if (priv->remapped_bar[i])
2752 iounmap(priv->remapped_bar[i]);
2753 priv->remapped_bar[i] = NULL;
2754 }
1da177e4 2755
056a8763
RK		 2756 /*
2757 * Find the exit quirks.
2758 */
241fc436 2759 quirk = find_quirk(priv->dev);
056a8763 2760 if (quirk->exit)
241fc436
RK		 2761 quirk->exit(priv->dev);
2762
2763 kfree(priv);
2764}
2765EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2766
2767void pciserial_suspend_ports(struct serial_private *priv)
2768{
2769 int i;
2770
2771 for (i = 0; i < priv->nr; i++)
2772 if (priv->line[i] >= 0)
2773 serial8250_suspend_port(priv->line[i]);
2774}
2775EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2776
2777void pciserial_resume_ports(struct serial_private *priv)
2778{
2779 int i;
2780
2781 /*
2782 * Ensure that the board is correctly configured.
2783 */
2784 if (priv->quirk->init)
2785 priv->quirk->init(priv->dev);
2786
2787 for (i = 0; i < priv->nr; i++)
2788 if (priv->line[i] >= 0)
2789 serial8250_resume_port(priv->line[i]);
2790}
2791EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2792
2793/*
2794 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2795 * to the arrangement of serial ports on a PCI card.
2796 */
2797static int __devinit
2798pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2799{
5bf8f501 2800 struct pci_serial_quirk *quirk;
241fc436 2801 struct serial_private *priv;
975a1a7d
RK		 2802 const struct pciserial_board *board;
2803 struct pciserial_board tmp;
241fc436
RK		 2804 int rc;
2805
5bf8f501
FB		 2806 quirk = find_quirk(dev);
2807 if (quirk->probe) {
2808 rc = quirk->probe(dev);
2809 if (rc)
2810 return rc;
2811 }
2812
241fc436
RK		 2813 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2814 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2815 ent->driver_data);
2816 return -EINVAL;
2817 }
2818
2819 board = &pci_boards[ent->driver_data];
2820
2821 rc = pci_enable_device(dev);
2807190b 2822 pci_save_state(dev);
241fc436
RK		 2823 if (rc)
2824 return rc;
2825
2826 if (ent->driver_data == pbn_default) {
2827 /*
2828 * Use a copy of the pci_board entry for this;
2829 * avoid changing entries in the table.
2830 */
2831 memcpy(&tmp, board, sizeof(struct pciserial_board));
2832 board = &tmp;
2833
2834 /*
2835 * We matched one of our class entries. Try to
2836 * determine the parameters of this board.
2837 */
975a1a7d 2838 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2839 if (rc)
2840 goto disable;
2841 } else {
2842 /*
2843 * We matched an explicit entry. If we are able to
2844 * detect this boards settings with our heuristic,
2845 * then we no longer need this entry.
2846 */
2847 memcpy(&tmp, &pci_boards[pbn_default],
2848 sizeof(struct pciserial_board));
2849 rc = serial_pci_guess_board(dev, &tmp);
2850 if (rc == 0 && serial_pci_matches(board, &tmp))
2851 moan_device("Redundant entry in serial pci_table.",
2852 dev);
2853 }
2854
2855 priv = pciserial_init_ports(dev, board);
2856 if (!IS_ERR(priv)) {
2857 pci_set_drvdata(dev, priv);
2858 return 0;
2859 }
2860
2861 rc = PTR_ERR(priv);
1da177e4 2862
241fc436 2863 disable:
056a8763 2864 pci_disable_device(dev);
241fc436
RK		 2865 return rc;
2866}
1da177e4 2867
241fc436
RK		 2868static void __devexit pciserial_remove_one(struct pci_dev *dev)
2869{
2870 struct serial_private *priv = pci_get_drvdata(dev);
2871
2872 pci_set_drvdata(dev, NULL);
2873
2874 pciserial_remove_ports(priv);
2875
2876 pci_disable_device(dev);
1da177e4
LT		 2877}
2878
1d5e7996 2879#ifdef CONFIG_PM
1da177e4
LT		 2880static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2881{
2882 struct serial_private *priv = pci_get_drvdata(dev);
2883
241fc436
RK		 2884 if (priv)
2885 pciserial_suspend_ports(priv);
1da177e4 2886
1da177e4
LT		 2887 pci_save_state(dev);
2888 pci_set_power_state(dev, pci_choose_state(dev, state));
2889 return 0;
2890}
2891
2892static int pciserial_resume_one(struct pci_dev *dev)
2893{
ccb9d59e 2894 int err;
1da177e4
LT		 2895 struct serial_private *priv = pci_get_drvdata(dev);
2896
2897 pci_set_power_state(dev, PCI_D0);
2898 pci_restore_state(dev);
2899
2900 if (priv) {
1da177e4
LT		 2901 /*
2902 * The device may have been disabled. Re-enable it.
2903 */
ccb9d59e 2904 err = pci_enable_device(dev);
40836c48 2905 /* FIXME: We cannot simply error out here */
ccb9d59e 2906 if (err)
40836c48 2907 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2908 pciserial_resume_ports(priv);
1da177e4
LT		 2909 }
2910 return 0;
2911}
1d5e7996 2912#endif
1da177e4
LT		 2913
2914static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2915 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2916 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2917 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2918 pbn_b2_8_921600 },
1da177e4
LT		 2919 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2920 PCI_SUBVENDOR_ID_CONNECT_TECH,
2921 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2922 pbn_b1_8_1382400 },
2923 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2924 PCI_SUBVENDOR_ID_CONNECT_TECH,
2925 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2926 pbn_b1_4_1382400 },
2927 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2928 PCI_SUBVENDOR_ID_CONNECT_TECH,
2929 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2930 pbn_b1_2_1382400 },
2931 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2932 PCI_SUBVENDOR_ID_CONNECT_TECH,
2933 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2934 pbn_b1_8_1382400 },
2935 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2936 PCI_SUBVENDOR_ID_CONNECT_TECH,
2937 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2938 pbn_b1_4_1382400 },
2939 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2940 PCI_SUBVENDOR_ID_CONNECT_TECH,
2941 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2942 pbn_b1_2_1382400 },
2943 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2944 PCI_SUBVENDOR_ID_CONNECT_TECH,
2945 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2946 pbn_b1_8_921600 },
2947 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2948 PCI_SUBVENDOR_ID_CONNECT_TECH,
2949 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2950 pbn_b1_8_921600 },
2951 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2952 PCI_SUBVENDOR_ID_CONNECT_TECH,
2953 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2954 pbn_b1_4_921600 },
2955 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2956 PCI_SUBVENDOR_ID_CONNECT_TECH,
2957 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2958 pbn_b1_4_921600 },
2959 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2960 PCI_SUBVENDOR_ID_CONNECT_TECH,
2961 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2962 pbn_b1_2_921600 },
2963 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2964 PCI_SUBVENDOR_ID_CONNECT_TECH,
2965 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2966 pbn_b1_8_921600 },
2967 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2968 PCI_SUBVENDOR_ID_CONNECT_TECH,
2969 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2970 pbn_b1_8_921600 },
2971 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2972 PCI_SUBVENDOR_ID_CONNECT_TECH,
2973 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2974 pbn_b1_4_921600 },
26e92861
GH		 2975 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2976 PCI_SUBVENDOR_ID_CONNECT_TECH,
2977 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2978 pbn_b1_2_1250000 },
2979 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2980 PCI_SUBVENDOR_ID_CONNECT_TECH,
2981 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2982 pbn_b0_2_1843200 },
2983 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2984 PCI_SUBVENDOR_ID_CONNECT_TECH,
2985 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2986 pbn_b0_4_1843200 },
85d1494e
YY		 2987 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2988 PCI_VENDOR_ID_AFAVLAB,
2989 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2990 pbn_b0_4_1152000 },
26e92861
GH		 2991 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2992 PCI_SUBVENDOR_ID_CONNECT_TECH,
2993 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2994 pbn_b0_2_1843200_200 },
2995 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2996 PCI_SUBVENDOR_ID_CONNECT_TECH,
2997 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2998 pbn_b0_4_1843200_200 },
2999 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3000 PCI_SUBVENDOR_ID_CONNECT_TECH,
3001 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3002 pbn_b0_8_1843200_200 },
3003 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3004 PCI_SUBVENDOR_ID_CONNECT_TECH,
3005 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3006 pbn_b0_2_1843200_200 },
3007 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3008 PCI_SUBVENDOR_ID_CONNECT_TECH,
3009 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3010 pbn_b0_4_1843200_200 },
3011 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3012 PCI_SUBVENDOR_ID_CONNECT_TECH,
3013 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3014 pbn_b0_8_1843200_200 },
3015 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3016 PCI_SUBVENDOR_ID_CONNECT_TECH,
3017 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3018 pbn_b0_2_1843200_200 },
3019 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3020 PCI_SUBVENDOR_ID_CONNECT_TECH,
3021 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3022 pbn_b0_4_1843200_200 },
3023 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3024 PCI_SUBVENDOR_ID_CONNECT_TECH,
3025 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3026 pbn_b0_8_1843200_200 },
3027 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3028 PCI_SUBVENDOR_ID_CONNECT_TECH,
3029 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3030 pbn_b0_2_1843200_200 },
3031 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3032 PCI_SUBVENDOR_ID_CONNECT_TECH,
3033 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3034 pbn_b0_4_1843200_200 },
3035 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3036 PCI_SUBVENDOR_ID_CONNECT_TECH,
3037 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3038 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3039 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3040 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3041 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3042
3043 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3045 pbn_b2_bt_1_115200 },
3046 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3048 pbn_b2_bt_2_115200 },
3049 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3051 pbn_b2_bt_4_115200 },
3052 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3054 pbn_b2_bt_2_115200 },
3055 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3057 pbn_b2_bt_4_115200 },
3058 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3060 pbn_b2_8_115200 },
e65f0f82
FL		 3061 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3063 pbn_b2_8_460800 },
1da177e4
LT		 3064 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3066 pbn_b2_8_115200 },
3067
3068 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3070 pbn_b2_bt_2_115200 },
3071 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3073 pbn_b2_bt_2_921600 },
3074 /*
3075 * VScom SPCOM800, from sl@s.pl
3076 */
5756ee99
AC		 3077 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3079 pbn_b2_8_921600 },
3080 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 3081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3082 pbn_b2_4_921600 },
b76c5a07
CB		 3083 /* Unknown card - subdevice 0x1584 */
3084 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3085 PCI_VENDOR_ID_PLX,
3086 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3087 pbn_b0_4_115200 },
1da177e4
LT		 3088 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3089 PCI_SUBVENDOR_ID_KEYSPAN,
3090 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3091 pbn_panacom },
3092 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3094 pbn_panacom4 },
3095 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3097 pbn_panacom2 },
a9cccd34
MF		 3098 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3099 PCI_VENDOR_ID_ESDGMBH,
3100 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3101 pbn_b2_4_115200 },
1da177e4
LT		 3102 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3103 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3104 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 3105 pbn_b2_4_460800 },
3106 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3107 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3108 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 3109 pbn_b2_8_460800 },
3110 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3111 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3112 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 3113 pbn_b2_16_460800 },
3114 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3115 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3116 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 3117 pbn_b2_16_460800 },
3118 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3119 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3120 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 3121 pbn_b2_4_460800 },
3122 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3123 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3124 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 3125 pbn_b2_8_460800 },
add7b58e
BH		 3126 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3127 PCI_SUBVENDOR_ID_EXSYS,
3128 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3129 pbn_exsys_4055 },
1da177e4
LT		 3130 /*
3131 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3132 * (Exoray@isys.ca)
3133 */
3134 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3135 0x10b5, 0x106a, 0, 0,
3136 pbn_plx_romulus },
3137 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3139 pbn_b1_4_115200 },
3140 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3142 pbn_b1_2_115200 },
3143 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3145 pbn_b1_8_115200 },
3146 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3148 pbn_b1_8_115200 },
3149 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3150 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3151 0, 0,
1da177e4 3152 pbn_b0_4_921600 },
fbc0dc0d 3153 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3154 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3155 0, 0,
fbc0dc0d 3156 pbn_b0_4_1152000 },
c9bd9d01
MP		 3157 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3159 pbn_b0_bt_2_921600 },
db1de159
DR		 3160
3161 /*
3162 * The below card is a little controversial since it is the
3163 * subject of a PCI vendor/device ID clash. (See
3164 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3165 * For now just used the hex ID 0x950a.
3166 */
39aced68
NV		 3167 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3168 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3169 pbn_b0_2_115200 },
db1de159
DR		 3170 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3172 pbn_b0_2_1130000 },
70fd8fde
AP		 3173 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3174 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3175 pbn_b0_1_921600 },
1da177e4
LT		 3176 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178 pbn_b0_4_115200 },
3179 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181 pbn_b0_bt_2_921600 },
e847003f
LB		 3182 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3183 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3184 pbn_b2_8_1152000 },
1da177e4 3185
7106b4e3
LH		 3186 /*
3187 * Oxford Semiconductor Inc. Tornado PCI express device range.
3188 */
3189 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3191 pbn_b0_1_4000000 },
3192 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3194 pbn_b0_1_4000000 },
3195 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3197 pbn_oxsemi_1_4000000 },
3198 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3200 pbn_oxsemi_1_4000000 },
3201 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3203 pbn_b0_1_4000000 },
3204 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3206 pbn_b0_1_4000000 },
3207 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3209 pbn_oxsemi_1_4000000 },
3210 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212 pbn_oxsemi_1_4000000 },
3213 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215 pbn_b0_1_4000000 },
3216 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218 pbn_b0_1_4000000 },
3219 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3221 pbn_b0_1_4000000 },
3222 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3224 pbn_b0_1_4000000 },
3225 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227 pbn_oxsemi_2_4000000 },
3228 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230 pbn_oxsemi_2_4000000 },
3231 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233 pbn_oxsemi_4_4000000 },
3234 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236 pbn_oxsemi_4_4000000 },
3237 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239 pbn_oxsemi_8_4000000 },
3240 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242 pbn_oxsemi_8_4000000 },
3243 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245 pbn_oxsemi_1_4000000 },
3246 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248 pbn_oxsemi_1_4000000 },
3249 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251 pbn_oxsemi_1_4000000 },
3252 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254 pbn_oxsemi_1_4000000 },
3255 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257 pbn_oxsemi_1_4000000 },
3258 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260 pbn_oxsemi_1_4000000 },
3261 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263 pbn_oxsemi_1_4000000 },
3264 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266 pbn_oxsemi_1_4000000 },
3267 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269 pbn_oxsemi_1_4000000 },
3270 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272 pbn_oxsemi_1_4000000 },
3273 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275 pbn_oxsemi_1_4000000 },
3276 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278 pbn_oxsemi_1_4000000 },
3279 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281 pbn_oxsemi_1_4000000 },
3282 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284 pbn_oxsemi_1_4000000 },
3285 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287 pbn_oxsemi_1_4000000 },
3288 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290 pbn_oxsemi_1_4000000 },
3291 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293 pbn_oxsemi_1_4000000 },
3294 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296 pbn_oxsemi_1_4000000 },
3297 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299 pbn_oxsemi_1_4000000 },
3300 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302 pbn_oxsemi_1_4000000 },
3303 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305 pbn_oxsemi_1_4000000 },
3306 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3308 pbn_oxsemi_1_4000000 },
3309 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3311 pbn_oxsemi_1_4000000 },
3312 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314 pbn_oxsemi_1_4000000 },
3315 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3317 pbn_oxsemi_1_4000000 },
3318 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3320 pbn_oxsemi_1_4000000 },
b80de369
LH		 3321 /*
3322 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3323 */
3324 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3325 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3326 pbn_oxsemi_1_4000000 },
3327 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3328 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3329 pbn_oxsemi_2_4000000 },
3330 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3331 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3332 pbn_oxsemi_4_4000000 },
3333 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3334 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3335 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 3336
3337 /*
3338 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3339 */
3340 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3341 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3342 pbn_oxsemi_2_4000000 },
3343
1da177e4
LT		 3344 /*
3345 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3346 * from skokodyn@yahoo.com
3347 */
3348 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3349 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3350 pbn_sbsxrsio },
3351 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3352 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3353 pbn_sbsxrsio },
3354 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3355 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3356 pbn_sbsxrsio },
3357 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3358 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3359 pbn_sbsxrsio },
3360
3361 /*
3362 * Digitan DS560-558, from jimd@esoft.com
3363 */
3364 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 3365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3366 pbn_b1_1_115200 },
3367
3368 /*
3369 * Titan Electronic cards
3370 * The 400L and 800L have a custom setup quirk.
3371 */
3372 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 3373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3374 pbn_b0_1_921600 },
3375 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 3376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3377 pbn_b0_2_921600 },
3378 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 3379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3380 pbn_b0_4_921600 },
3381 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 3382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3383 pbn_b0_4_921600 },
3384 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3386 pbn_b1_1_921600 },
3387 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3389 pbn_b1_bt_2_921600 },
3390 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3392 pbn_b0_bt_4_921600 },
3393 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395 pbn_b0_bt_8_921600 },
66169ad1
YY		 3396 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398 pbn_b4_bt_2_921600 },
3399 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401 pbn_b4_bt_4_921600 },
3402 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404 pbn_b4_bt_8_921600 },
3405 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407 pbn_b0_4_921600 },
3408 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410 pbn_b0_4_921600 },
3411 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413 pbn_b0_4_921600 },
3414 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416 pbn_oxsemi_1_4000000 },
3417 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419 pbn_oxsemi_2_4000000 },
3420 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422 pbn_oxsemi_4_4000000 },
3423 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425 pbn_oxsemi_8_4000000 },
3426 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428 pbn_oxsemi_2_4000000 },
3429 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431 pbn_oxsemi_2_4000000 },
1da177e4
LT		 3432
3433 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3435 pbn_b2_1_460800 },
3436 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438 pbn_b2_1_460800 },
3439 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3441 pbn_b2_1_460800 },
3442 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3444 pbn_b2_bt_2_921600 },
3445 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3447 pbn_b2_bt_2_921600 },
3448 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3450 pbn_b2_bt_2_921600 },
3451 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3453 pbn_b2_bt_4_921600 },
3454 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3456 pbn_b2_bt_4_921600 },
3457 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3459 pbn_b2_bt_4_921600 },
3460 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3462 pbn_b0_1_921600 },
3463 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465 pbn_b0_1_921600 },
3466 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3468 pbn_b0_1_921600 },
3469 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3471 pbn_b0_bt_2_921600 },
3472 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474 pbn_b0_bt_2_921600 },
3475 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477 pbn_b0_bt_2_921600 },
3478 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480 pbn_b0_bt_4_921600 },
3481 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483 pbn_b0_bt_4_921600 },
3484 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486 pbn_b0_bt_4_921600 },
3ec9c594
AP		 3487 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489 pbn_b0_bt_8_921600 },
3490 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492 pbn_b0_bt_8_921600 },
3493 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495 pbn_b0_bt_8_921600 },
1da177e4
LT		 3496
3497 /*
3498 * Computone devices submitted by Doug McNash dmcnash@computone.com
3499 */
3500 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3501 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3502 0, 0, pbn_computone_4 },
3503 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3504 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3505 0, 0, pbn_computone_8 },
3506 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3507 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3508 0, 0, pbn_computone_6 },
3509
3510 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3512 pbn_oxsemi },
3513 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3514 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3515 pbn_b0_bt_1_921600 },
3516
3517 /*
3518 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3519 */
3520 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522 pbn_b0_bt_8_115200 },
3523 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525 pbn_b0_bt_8_115200 },
3526
3527 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3529 pbn_b0_bt_2_115200 },
3530 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3532 pbn_b0_bt_2_115200 },
3533 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3535 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 3536 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3538 pbn_b0_bt_2_115200 },
3539 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3541 pbn_b0_bt_2_115200 },
1da177e4
LT		 3542 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3544 pbn_b0_bt_4_460800 },
3545 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3547 pbn_b0_bt_4_460800 },
3548 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3550 pbn_b0_bt_2_460800 },
3551 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3553 pbn_b0_bt_2_460800 },
3554 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3556 pbn_b0_bt_2_460800 },
3557 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3559 pbn_b0_bt_1_115200 },
3560 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3562 pbn_b0_bt_1_460800 },
3563
1fb8cacc
RK		 3564 /*
3565 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3566 * Cards are identified by their subsystem vendor IDs, which
3567 * (in hex) match the model number.
3568 *
3569 * Note that JC140x are RS422/485 cards which require ox950
3570 * ACR = 0x10, and as such are not currently fully supported.
3571 */
3572 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3573 0x1204, 0x0004, 0, 0,
3574 pbn_b0_4_921600 },
3575 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3576 0x1208, 0x0004, 0, 0,
3577 pbn_b0_4_921600 },
3578/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3579 0x1402, 0x0002, 0, 0,
3580 pbn_b0_2_921600 }, */
3581/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3582 0x1404, 0x0004, 0, 0,
3583 pbn_b0_4_921600 }, */
3584 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3585 0x1208, 0x0004, 0, 0,
3586 pbn_b0_4_921600 },
3587
2a52fcb5
KY		 3588 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3589 0x1204, 0x0004, 0, 0,
3590 pbn_b0_4_921600 },
3591 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3592 0x1208, 0x0004, 0, 0,
3593 pbn_b0_4_921600 },
3594 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3595 0x1208, 0x0004, 0, 0,
3596 pbn_b0_4_921600 },
1da177e4
LT		 3597 /*
3598 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3599 */
3600 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3602 pbn_b1_1_1382400 },
3603
3604 /*
3605 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3606 */
3607 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3609 pbn_b1_1_1382400 },
3610
3611 /*
3612 * RAStel 2 port modem, gerg@moreton.com.au
3613 */
3614 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616 pbn_b2_bt_2_115200 },
3617
3618 /*
3619 * EKF addition for i960 Boards form EKF with serial port
3620 */
3621 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3622 0xE4BF, PCI_ANY_ID, 0, 0,
3623 pbn_intel_i960 },
3624
3625 /*
3626 * Xircom Cardbus/Ethernet combos
3627 */
3628 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3630 pbn_b0_1_115200 },
3631 /*
3632 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3633 */
3634 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3636 pbn_b0_1_115200 },
3637
3638 /*
3639 * Untested PCI modems, sent in from various folks...
3640 */
3641
3642 /*
3643 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3644 */
3645 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3646 0x1048, 0x1500, 0, 0,
3647 pbn_b1_1_115200 },
3648
3649 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3650 0xFF00, 0, 0, 0,
3651 pbn_sgi_ioc3 },
3652
3653 /*
3654 * HP Diva card
3655 */
3656 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3657 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3658 pbn_b1_1_115200 },
3659 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3661 pbn_b0_5_115200 },
3662 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3664 pbn_b2_1_115200 },
3665
d9004eb4
ABL		 3666 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3668 pbn_b3_2_115200 },
1da177e4
LT		 3669 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3671 pbn_b3_4_115200 },
3672 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3674 pbn_b3_8_115200 },
3675
3676 /*
3677 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3678 */
3679 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3680 PCI_ANY_ID, PCI_ANY_ID,
3681 0,
3682 0, pbn_exar_XR17C152 },
3683 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3684 PCI_ANY_ID, PCI_ANY_ID,
3685 0,
3686 0, pbn_exar_XR17C154 },
3687 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3688 PCI_ANY_ID, PCI_ANY_ID,
3689 0,
3690 0, pbn_exar_XR17C158 },
3691
3692 /*
3693 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3694 */
3695 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3697 pbn_b0_1_115200 },
84f8c6fc
NV		 3698 /*
3699 * ITE
3700 */
3701 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3702 PCI_ANY_ID, PCI_ANY_ID,
3703 0, 0,
3704 pbn_b1_bt_1_115200 },
1da177e4 3705
737c1756
PH		 3706 /*
3707 * IntaShield IS-200
3708 */
3709 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3710 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3711 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3712 /*
3713 * IntaShield IS-400
3714 */
3715 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3717 pbn_b2_4_115200 },
48212008
TH		 3718 /*
3719 * Perle PCI-RAS cards
3720 */
3721 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3722 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3723 0, 0, pbn_b2_4_921600 },
3724 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3725 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3726 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3727
3728 /*
3729 * Mainpine series cards: Fairly standard layout but fools
3730 * parts of the autodetect in some cases and uses otherwise
3731 * unmatched communications subclasses in the PCI Express case
3732 */
3733
3734 { /* RockForceDUO */
3735 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3736 PCI_VENDOR_ID_MAINPINE, 0x0200,
3737 0, 0, pbn_b0_2_115200 },
3738 { /* RockForceQUATRO */
3739 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3740 PCI_VENDOR_ID_MAINPINE, 0x0300,
3741 0, 0, pbn_b0_4_115200 },
3742 { /* RockForceDUO+ */
3743 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3744 PCI_VENDOR_ID_MAINPINE, 0x0400,
3745 0, 0, pbn_b0_2_115200 },
3746 { /* RockForceQUATRO+ */
3747 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3748 PCI_VENDOR_ID_MAINPINE, 0x0500,
3749 0, 0, pbn_b0_4_115200 },
3750 { /* RockForce+ */
3751 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3752 PCI_VENDOR_ID_MAINPINE, 0x0600,
3753 0, 0, pbn_b0_2_115200 },
3754 { /* RockForce+ */
3755 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3756 PCI_VENDOR_ID_MAINPINE, 0x0700,
3757 0, 0, pbn_b0_4_115200 },
3758 { /* RockForceOCTO+ */
3759 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3760 PCI_VENDOR_ID_MAINPINE, 0x0800,
3761 0, 0, pbn_b0_8_115200 },
3762 { /* RockForceDUO+ */
3763 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3764 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3765 0, 0, pbn_b0_2_115200 },
3766 { /* RockForceQUARTRO+ */
3767 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3768 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3769 0, 0, pbn_b0_4_115200 },
3770 { /* RockForceOCTO+ */
3771 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3772 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3773 0, 0, pbn_b0_8_115200 },
3774 { /* RockForceD1 */
3775 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3776 PCI_VENDOR_ID_MAINPINE, 0x2000,
3777 0, 0, pbn_b0_1_115200 },
3778 { /* RockForceF1 */
3779 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3780 PCI_VENDOR_ID_MAINPINE, 0x2100,
3781 0, 0, pbn_b0_1_115200 },
3782 { /* RockForceD2 */
3783 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3784 PCI_VENDOR_ID_MAINPINE, 0x2200,
3785 0, 0, pbn_b0_2_115200 },
3786 { /* RockForceF2 */
3787 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3788 PCI_VENDOR_ID_MAINPINE, 0x2300,
3789 0, 0, pbn_b0_2_115200 },
3790 { /* RockForceD4 */
3791 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3792 PCI_VENDOR_ID_MAINPINE, 0x2400,
3793 0, 0, pbn_b0_4_115200 },
3794 { /* RockForceF4 */
3795 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3796 PCI_VENDOR_ID_MAINPINE, 0x2500,
3797 0, 0, pbn_b0_4_115200 },
3798 { /* RockForceD8 */
3799 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3800 PCI_VENDOR_ID_MAINPINE, 0x2600,
3801 0, 0, pbn_b0_8_115200 },
3802 { /* RockForceF8 */
3803 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3804 PCI_VENDOR_ID_MAINPINE, 0x2700,
3805 0, 0, pbn_b0_8_115200 },
3806 { /* IQ Express D1 */
3807 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3808 PCI_VENDOR_ID_MAINPINE, 0x3000,
3809 0, 0, pbn_b0_1_115200 },
3810 { /* IQ Express F1 */
3811 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3812 PCI_VENDOR_ID_MAINPINE, 0x3100,
3813 0, 0, pbn_b0_1_115200 },
3814 { /* IQ Express D2 */
3815 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3816 PCI_VENDOR_ID_MAINPINE, 0x3200,
3817 0, 0, pbn_b0_2_115200 },
3818 { /* IQ Express F2 */
3819 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3820 PCI_VENDOR_ID_MAINPINE, 0x3300,
3821 0, 0, pbn_b0_2_115200 },
3822 { /* IQ Express D4 */
3823 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3824 PCI_VENDOR_ID_MAINPINE, 0x3400,
3825 0, 0, pbn_b0_4_115200 },
3826 { /* IQ Express F4 */
3827 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3828 PCI_VENDOR_ID_MAINPINE, 0x3500,
3829 0, 0, pbn_b0_4_115200 },
3830 { /* IQ Express D8 */
3831 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3832 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3833 0, 0, pbn_b0_8_115200 },
3834 { /* IQ Express F8 */
3835 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3836 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3837 0, 0, pbn_b0_8_115200 },
3838
3839
aa798505
OJ		 3840 /*
3841 * PA Semi PA6T-1682M on-chip UART
3842 */
3843 { PCI_VENDOR_ID_PASEMI, 0xa004,
3844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3845 pbn_pasemi_1682M },
3846
46a0fac9
SB		 3847 /*
3848 * National Instruments
3849 */
04bf7e74
WP		 3850 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3852 pbn_b1_16_115200 },
3853 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3855 pbn_b1_8_115200 },
3856 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3858 pbn_b1_bt_4_115200 },
3859 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3861 pbn_b1_bt_2_115200 },
3862 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3864 pbn_b1_bt_4_115200 },
3865 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3867 pbn_b1_bt_2_115200 },
3868 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3870 pbn_b1_16_115200 },
3871 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3873 pbn_b1_8_115200 },
3874 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3876 pbn_b1_bt_4_115200 },
3877 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3879 pbn_b1_bt_2_115200 },
3880 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3882 pbn_b1_bt_4_115200 },
3883 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3885 pbn_b1_bt_2_115200 },
46a0fac9
SB		 3886 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3888 pbn_ni8430_2 },
3889 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3891 pbn_ni8430_2 },
3892 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3894 pbn_ni8430_4 },
3895 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3897 pbn_ni8430_4 },
3898 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3900 pbn_ni8430_8 },
3901 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3903 pbn_ni8430_8 },
3904 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3906 pbn_ni8430_16 },
3907 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3909 pbn_ni8430_16 },
3910 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3912 pbn_ni8430_2 },
3913 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3915 pbn_ni8430_2 },
3916 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3918 pbn_ni8430_4 },
3919 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3921 pbn_ni8430_4 },
3922
02c9b5cf
KJ		 3923 /*
3924 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3925 */
3926 { PCI_VENDOR_ID_ADDIDATA,
3927 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3928 PCI_ANY_ID,
3929 PCI_ANY_ID,
3930 0,
3931 0,
3932 pbn_b0_4_115200 },
3933
3934 { PCI_VENDOR_ID_ADDIDATA,
3935 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3936 PCI_ANY_ID,
3937 PCI_ANY_ID,
3938 0,
3939 0,
3940 pbn_b0_2_115200 },
3941
3942 { PCI_VENDOR_ID_ADDIDATA,
3943 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3944 PCI_ANY_ID,
3945 PCI_ANY_ID,
3946 0,
3947 0,
3948 pbn_b0_1_115200 },
3949
3950 { PCI_VENDOR_ID_ADDIDATA_OLD,
3951 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3952 PCI_ANY_ID,
3953 PCI_ANY_ID,
3954 0,
3955 0,
3956 pbn_b1_8_115200 },
3957
3958 { PCI_VENDOR_ID_ADDIDATA,
3959 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3960 PCI_ANY_ID,
3961 PCI_ANY_ID,
3962 0,
3963 0,
3964 pbn_b0_4_115200 },
3965
3966 { PCI_VENDOR_ID_ADDIDATA,
3967 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3968 PCI_ANY_ID,
3969 PCI_ANY_ID,
3970 0,
3971 0,
3972 pbn_b0_2_115200 },
3973
3974 { PCI_VENDOR_ID_ADDIDATA,
3975 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3976 PCI_ANY_ID,
3977 PCI_ANY_ID,
3978 0,
3979 0,
3980 pbn_b0_1_115200 },
3981
3982 { PCI_VENDOR_ID_ADDIDATA,
3983 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3984 PCI_ANY_ID,
3985 PCI_ANY_ID,
3986 0,
3987 0,
3988 pbn_b0_4_115200 },
3989
3990 { PCI_VENDOR_ID_ADDIDATA,
3991 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3992 PCI_ANY_ID,
3993 PCI_ANY_ID,
3994 0,
3995 0,
3996 pbn_b0_2_115200 },
3997
3998 { PCI_VENDOR_ID_ADDIDATA,
3999 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4000 PCI_ANY_ID,
4001 PCI_ANY_ID,
4002 0,
4003 0,
4004 pbn_b0_1_115200 },
4005
4006 { PCI_VENDOR_ID_ADDIDATA,
4007 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4008 PCI_ANY_ID,
4009 PCI_ANY_ID,
4010 0,
4011 0,
4012 pbn_b0_8_115200 },
4013
1b62cbf2
KJ		 4014 { PCI_VENDOR_ID_ADDIDATA,
4015 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4016 PCI_ANY_ID,
4017 PCI_ANY_ID,
4018 0,
4019 0,
4020 pbn_ADDIDATA_PCIe_4_3906250 },
4021
4022 { PCI_VENDOR_ID_ADDIDATA,
4023 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4024 PCI_ANY_ID,
4025 PCI_ANY_ID,
4026 0,
4027 0,
4028 pbn_ADDIDATA_PCIe_2_3906250 },
4029
4030 { PCI_VENDOR_ID_ADDIDATA,
4031 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4032 PCI_ANY_ID,
4033 PCI_ANY_ID,
4034 0,
4035 0,
4036 pbn_ADDIDATA_PCIe_1_3906250 },
4037
4038 { PCI_VENDOR_ID_ADDIDATA,
4039 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4040 PCI_ANY_ID,
4041 PCI_ANY_ID,
4042 0,
4043 0,
4044 pbn_ADDIDATA_PCIe_8_3906250 },
4045
25cf9bc1
JS		 4046 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4047 PCI_VENDOR_ID_IBM, 0x0299,
4048 0, 0, pbn_b0_bt_2_115200 },
4049
c4285b47
MB		 4050 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4051 0xA000, 0x1000,
4052 0, 0, pbn_b0_1_115200 },
4053
7808edcd
NG		 4054 /* the 9901 is a rebranded 9912 */
4055 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4056 0xA000, 0x1000,
4057 0, 0, pbn_b0_1_115200 },
4058
4059 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4060 0xA000, 0x1000,
4061 0, 0, pbn_b0_1_115200 },
4062
4063 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4064 0xA000, 0x1000,
4065 0, 0, pbn_b0_1_115200 },
4066
4067 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4068 0xA000, 0x1000,
4069 0, 0, pbn_b0_1_115200 },
4070
4071 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4072 0xA000, 0x3002,
4073 0, 0, pbn_NETMOS9900_2s_115200 },
4074
ac6ec5b1 4075 /*
44178176 4076 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 4077 */
4078
4079 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4080 0xA000, 0x1000,
4081 0, 0, pbn_b0_1_115200 },
4082
44178176
ES		 4083 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4084 0xA000, 0x3002,
4085 0, 0, pbn_b0_bt_2_115200 },
4086
ac6ec5b1
IS		 4087 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4088 0xA000, 0x3004,
4089 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 4090 /* Intel CE4100 */
4091 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4093 pbn_ce4100_1_115200 },
4094
d9a0fbfd
AP		 4095 /*
4096 * Cronyx Omega PCI
4097 */
4098 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4100 pbn_omegapci },
ac6ec5b1 4101
1da177e4
LT		 4102 /*
4103 * These entries match devices with class COMMUNICATION_SERIAL,
4104 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4105 */
4106 { PCI_ANY_ID, PCI_ANY_ID,
4107 PCI_ANY_ID, PCI_ANY_ID,
4108 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4109 0xffff00, pbn_default },
4110 { PCI_ANY_ID, PCI_ANY_ID,
4111 PCI_ANY_ID, PCI_ANY_ID,
4112 PCI_CLASS_COMMUNICATION_MODEM << 8,
4113 0xffff00, pbn_default },
4114 { PCI_ANY_ID, PCI_ANY_ID,
4115 PCI_ANY_ID, PCI_ANY_ID,
4116 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4117 0xffff00, pbn_default },
4118 { 0, }
4119};
4120
2807190b
MR		 4121static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4122 pci_channel_state_t state)
4123{
4124 struct serial_private *priv = pci_get_drvdata(dev);
4125
4126 if (state == pci_channel_io_perm_failure)
4127 return PCI_ERS_RESULT_DISCONNECT;
4128
4129 if (priv)
4130 pciserial_suspend_ports(priv);
4131
4132 pci_disable_device(dev);
4133
4134 return PCI_ERS_RESULT_NEED_RESET;
4135}
4136
4137static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4138{
4139 int rc;
4140
4141 rc = pci_enable_device(dev);
4142
4143 if (rc)
4144 return PCI_ERS_RESULT_DISCONNECT;
4145
4146 pci_restore_state(dev);
4147 pci_save_state(dev);
4148
4149 return PCI_ERS_RESULT_RECOVERED;
4150}
4151
4152static void serial8250_io_resume(struct pci_dev *dev)
4153{
4154 struct serial_private *priv = pci_get_drvdata(dev);
4155
4156 if (priv)
4157 pciserial_resume_ports(priv);
4158}
4159
4160static struct pci_error_handlers serial8250_err_handler = {
4161 .error_detected = serial8250_io_error_detected,
4162 .slot_reset = serial8250_io_slot_reset,
4163 .resume = serial8250_io_resume,
4164};
4165
1da177e4
LT		 4166static struct pci_driver serial_pci_driver = {
4167 .name = "serial",
4168 .probe = pciserial_init_one,
4169 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 4170#ifdef CONFIG_PM
1da177e4
LT		 4171 .suspend = pciserial_suspend_one,
4172 .resume = pciserial_resume_one,
1d5e7996 4173#endif
1da177e4 4174 .id_table = serial_pci_tbl,
2807190b 4175 .err_handler = &serial8250_err_handler,
1da177e4
LT		 4176};
4177
4178static int __init serial8250_pci_init(void)
4179{
4180 return pci_register_driver(&serial_pci_driver);
4181}
4182
4183static void __exit serial8250_pci_exit(void)
4184{
4185 pci_unregister_driver(&serial_pci_driver);
4186}
4187
4188module_init(serial8250_pci_init);
4189module_exit(serial8250_pci_exit);
4190
4191MODULE_LICENSE("GPL");
4192MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4193MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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