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serial/8250_pci: init-quirk msi support for kt serial controller
[deliverable/linux.git] / drivers / tty / serial / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <linux/8250_pci.h>
22#include <linux/bitops.h>
23
24#include <asm/byteorder.h>
25#include <asm/io.h>
26
27#include "8250.h"
28
29#undef SERIAL_DEBUG_PCI
30
1da177e4
LT		 31/*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
5bf8f501 42 int (*probe)(struct pci_dev *dev);
1da177e4 43 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 44 int (*setup)(struct serial_private *,
45 const struct pciserial_board *,
05caac58 46 struct uart_port *, int);
1da177e4
LT		 47 void (*exit)(struct pci_dev *dev);
48};
49
50#define PCI_NUM_BAR_RESOURCES 6
51
52struct serial_private {
70db3d91 53 struct pci_dev *dev;
1da177e4
LT		 54 unsigned int nr;
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
57 int line[0];
58};
59
7808edcd
NG		 60static int pci_default_setup(struct serial_private*,
61 const struct pciserial_board*, struct uart_port*, int);
62
1da177e4
LT		 63static void moan_device(const char *str, struct pci_dev *dev)
64{
ad361c98
JP		 65 printk(KERN_WARNING
66 "%s: %s\n"
67 "Please send the output of lspci -vv, this\n"
68 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69 "manufacturer and name of serial board or\n"
70 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 71 pci_name(dev), str, dev->vendor, dev->device,
72 dev->subsystem_vendor, dev->subsystem_device);
73}
74
75static int
70db3d91 76setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 77 int bar, int offset, int regshift)
78{
70db3d91 79 struct pci_dev *dev = priv->dev;
1da177e4
LT		 80 unsigned long base, len;
81
82 if (bar >= PCI_NUM_BAR_RESOURCES)
83 return -EINVAL;
84
72ce9a83
RK		 85 base = pci_resource_start(dev, bar);
86
1da177e4 87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 88 len = pci_resource_len(dev, bar);
89
90 if (!priv->remapped_bar[bar])
6f441fe9 91 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 92 if (!priv->remapped_bar[bar])
93 return -ENOMEM;
94
95 port->iotype = UPIO_MEM;
72ce9a83 96 port->iobase = 0;
1da177e4
LT		 97 port->mapbase = base + offset;
98 port->membase = priv->remapped_bar[bar] + offset;
99 port->regshift = regshift;
100 } else {
1da177e4 101 port->iotype = UPIO_PORT;
72ce9a83
RK		 102 port->iobase = base + offset;
103 port->mapbase = 0;
104 port->membase = NULL;
105 port->regshift = 0;
1da177e4
LT		 106 }
107 return 0;
108}
109
02c9b5cf
KJ		 110/*
111 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 */
113static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 114 const struct pciserial_board *board,
02c9b5cf
KJ		 115 struct uart_port *port, int idx)
116{
117 unsigned int bar = 0, offset = board->first_offset;
118 bar = FL_GET_BASE(board->flags);
119
120 if (idx < 2) {
121 offset += idx * board->uart_offset;
122 } else if ((idx >= 2) && (idx < 4)) {
123 bar += 1;
124 offset += ((idx - 2) * board->uart_offset);
125 } else if ((idx >= 4) && (idx < 6)) {
126 bar += 2;
127 offset += ((idx - 4) * board->uart_offset);
128 } else if (idx >= 6) {
129 bar += 3;
130 offset += ((idx - 6) * board->uart_offset);
131 }
132
133 return setup_port(priv, port, bar, offset, board->reg_shift);
134}
135
1da177e4
LT		 136/*
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
139 */
140static int
975a1a7d 141afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 142 struct uart_port *port, int idx)
143{
144 unsigned int bar, offset = board->first_offset;
5756ee99 145
1da177e4
LT		 146 bar = FL_GET_BASE(board->flags);
147 if (idx < 4)
148 bar += idx;
149 else {
150 bar = 4;
151 offset += (idx - 4) * board->uart_offset;
152 }
153
70db3d91 154 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 155}
156
157/*
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
163 */
61a116ef 164static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 165{
166 int rc = 0;
167
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 rc = 3;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 rc = 2;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 rc = 4;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 182 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 183 rc = 1;
184 break;
185 }
186
187 return rc;
188}
189
190/*
191 * HP's Diva chip puts the 4th/5th serial port further out, and
192 * some serial ports are supposed to be hidden on certain models.
193 */
194static int
975a1a7d
RK		 195pci_hp_diva_setup(struct serial_private *priv,
196 const struct pciserial_board *board,
197 struct uart_port *port, int idx)
1da177e4
LT		 198{
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
70db3d91 202 switch (priv->dev->subsystem_device) {
1da177e4
LT		 203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
70db3d91 219 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 220}
221
222/*
223 * Added for EKF Intel i960 serial boards
224 */
61a116ef 225static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 226{
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
5756ee99
AC		 233 pci_read_config_dword(dev, 0x44, (void *)&oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 235 printk(KERN_DEBUG "Local i960 firmware missing");
236 return -ENODEV;
237 }
238 return 0;
239}
240
241/*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
61a116ef 247static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 248{
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
add7b58e 258 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 259 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 260 irq_config = 0x43;
5756ee99 261
1da177e4 262 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 263 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 264 /*
265 * As the megawolf cards have the int pins active
266 * high, and have 2 UART chips, both ints must be
267 * enabled on the 9050. Also, the UARTS are set in
268 * 16450 mode by default, so we have to enable the
269 * 16C950 'enhanced' mode so that we can use the
270 * deep FIFOs
271 */
272 irq_config = 0x5b;
1da177e4
LT		 273 /*
274 * enable/disable interrupts
275 */
6f441fe9 276 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288}
289
290static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291{
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
6f441fe9 300 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310}
311
04bf7e74
WP		 312#define NI8420_INT_ENABLE_REG 0x38
313#define NI8420_INT_ENABLE_BIT 0x2000
314
315static void __devexit pci_ni8420_exit(struct pci_dev *dev)
316{
317 void __iomem *p;
318 unsigned long base, len;
319 unsigned int bar = 0;
320
321 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322 moan_device("no memory in bar", dev);
323 return;
324 }
325
326 base = pci_resource_start(dev, bar);
327 len = pci_resource_len(dev, bar);
328 p = ioremap_nocache(base, len);
329 if (p == NULL)
330 return;
331
332 /* Disable the CPU Interrupt */
333 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334 p + NI8420_INT_ENABLE_REG);
335 iounmap(p);
336}
337
338
46a0fac9
SB		 339/* MITE registers */
340#define MITE_IOWBSR1 0xc4
341#define MITE_IOWCR1 0xf4
342#define MITE_LCIMR1 0x08
343#define MITE_LCIMR2 0x10
344
345#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346
347static void __devexit pci_ni8430_exit(struct pci_dev *dev)
348{
349 void __iomem *p;
350 unsigned long base, len;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 base = pci_resource_start(dev, bar);
359 len = pci_resource_len(dev, bar);
360 p = ioremap_nocache(base, len);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367}
368
1da177e4
LT		 369/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370static int
975a1a7d 371sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 372 struct uart_port *port, int idx)
373{
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
70db3d91 387 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 388}
389
390/*
391* This does initialization for PMC OCTALPRO cards:
392* maps the device memory, resets the UARTs (needed, bc
393* if the module is removed and inserted again, the card
394* is in the sleep mode) and enables global interrupt.
395*/
396
397/* global control register offset for SBS PMC-OctalPro */
398#define OCT_REG_CR_OFF 0x500
399
61a116ef 400static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 401{
402 u8 __iomem *p;
403
24ed3aba 404 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 409 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 410 udelay(50);
5756ee99 411 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418}
419
420/*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
424static void __devexit sbs_exit(struct pci_dev *dev)
425{
426 u8 __iomem *p;
427
24ed3aba 428 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
1da177e4 431 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 432 iounmap(p);
433}
434
435/*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
25985edc 438 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 447 *
1da177e4
LT		 448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
67d74b87
RK		 453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
fbc0dc0d
AP		 456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
1da177e4
LT		 459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465static int pci_siig10x_init(struct pci_dev *dev)
466{
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
6f441fe9 482 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490}
491
492#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495static int pci_siig20x_init(struct pci_dev *dev)
496{
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510}
511
67d74b87
RK		 512static int pci_siig_init(struct pci_dev *dev)
513{
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523}
524
3ec9c594 525static int pci_siig_setup(struct serial_private *priv,
975a1a7d 526 const struct pciserial_board *board,
3ec9c594
AP		 527 struct uart_port *port, int idx)
528{
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537}
538
1da177e4
LT		 539/*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
e9422e09 544static const unsigned short timedia_single_port[] = {
1da177e4
LT		 545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546};
547
e9422e09 548static const unsigned short timedia_dual_port[] = {
1da177e4 549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554};
555
e9422e09 556static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561};
562
e9422e09 563static const unsigned short timedia_eight_port[] = {
5756ee99 564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566};
567
cb3592be 568static const struct timedia_struct {
1da177e4 569 int num;
e9422e09 570 const unsigned short *ids;
1da177e4
LT		 571} timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
e9422e09 575 { 8, timedia_eight_port }
1da177e4
LT		 576};
577
b9b24558
FB		 578/*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584static int pci_timedia_probe(struct pci_dev *dev)
585{
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598}
599
61a116ef 600static int pci_timedia_init(struct pci_dev *dev)
1da177e4 601{
e9422e09 602 const unsigned short *ids;
1da177e4
LT		 603 int i, j;
604
e9422e09 605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612}
613
614/*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618static int
975a1a7d
RK		 619pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
1da177e4
LT		 621 struct uart_port *port, int idx)
622{
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
c2cd6d3c 638 /* FALLTHROUGH */
1da177e4
LT		 639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
70db3d91 646 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 647}
648
649/*
650 * Some Titan cards are also a little weird
651 */
652static int
70db3d91 653titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 654 const struct pciserial_board *board,
1da177e4
LT		 655 struct uart_port *port, int idx)
656{
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
70db3d91 671 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 672}
673
61a116ef 674static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 675{
676 msleep(100);
677 return 0;
678}
679
04bf7e74
WP		 680static int pci_ni8420_init(struct pci_dev *dev)
681{
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar = 0;
685
686 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687 moan_device("no memory in bar", dev);
688 return 0;
689 }
690
691 base = pci_resource_start(dev, bar);
692 len = pci_resource_len(dev, bar);
693 p = ioremap_nocache(base, len);
694 if (p == NULL)
695 return -ENOMEM;
696
697 /* Enable CPU Interrupt */
698 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699 p + NI8420_INT_ENABLE_REG);
700
701 iounmap(p);
702 return 0;
703}
704
46a0fac9
SB		 705#define MITE_IOWBSR1_WSIZE 0xa
706#define MITE_IOWBSR1_WIN_OFFSET 0x800
707#define MITE_IOWBSR1_WENAB (1 << 7)
708#define MITE_LCIMR1_IO_IE_0 (1 << 24)
709#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
710#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712static int pci_ni8430_init(struct pci_dev *dev)
713{
714 void __iomem *p;
715 unsigned long base, len;
716 u32 device_window;
717 unsigned int bar = 0;
718
719 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720 moan_device("no memory in bar", dev);
721 return 0;
722 }
723
724 base = pci_resource_start(dev, bar);
725 len = pci_resource_len(dev, bar);
726 p = ioremap_nocache(base, len);
727 if (p == NULL)
728 return -ENOMEM;
729
730 /* Set device window address and size in BAR0 */
731 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747}
748
749/* UART Port Control Register */
750#define NI8430_PORTCON 0x0f
751#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753static int
bf538fe4
AC		 754pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
46a0fac9
SB		 756 struct uart_port *port, int idx)
757{
758 void __iomem *p;
759 unsigned long base, len;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 base = pci_resource_start(priv->dev, bar);
769 len = pci_resource_len(priv->dev, bar);
770 p = ioremap_nocache(base, len);
771
7c9d440e 772 /* enable the transceiver */
46a0fac9
SB		 773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779}
780
7808edcd
NG		 781static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_port *port, int idx)
784{
785 unsigned int bar;
786
787 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797}
798
799/* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807static int pci_netmos_9900_numports(struct pci_dev *dev)
808{
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
829 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836}
46a0fac9 837
61a116ef 838static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 839{
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
ac6ec5b1
IS		 843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 845 return 0;
7808edcd 846
25cf9bc1
JS		 847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
7808edcd
NG		 851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
1da177e4
LT		 865 if (num_serial == 0)
866 return -ENODEV;
7808edcd 867
1da177e4
LT		 868 return num_serial;
869}
870
84f8c6fc 871/*
84f8c6fc
NV		 872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881/* registers */
882#define ITE_887x_MISCR 0x9c
883#define ITE_887x_INTCBAR 0x78
884#define ITE_887x_UARTBAR 0x7c
885#define ITE_887x_PS0BAR 0x10
886#define ITE_887x_POSIO0 0x60
887
888/* I/O space size */
889#define ITE_887x_IOSIZE 32
890/* I/O space size (bits 26-24; 8 bytes = 011b) */
891#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892/* I/O space size (bits 26-24; 32 bytes = 101b) */
893#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895#define ITE_887x_POSIO_SPEED (3 << 29)
896/* enable IO_Space bit */
897#define ITE_887x_POSIO_ENABLE (1 << 31)
898
f79abb82 899static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 900{
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
5756ee99
AC		 919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
84f8c6fc
NV		 921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
933 printk(KERN_ERR "ite887x: could not find iobase\n");
934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991}
992
993static void __devexit pci_ite887x_exit(struct pci_dev *dev)
994{
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000}
1001
9f2a036a
RK		 1002/*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008{
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1026 printk(KERN_DEBUG
1027 "%d ports detected on Oxford PCI Express device\n",
1028 number_uarts);
1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032}
1033
1da177e4 1034static int
975a1a7d
RK		 1035pci_default_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1da177e4
LT		 1037 struct uart_port *port, int idx)
1038{
1039 unsigned int bar, offset = board->first_offset, maxnr;
1040
1041 bar = FL_GET_BASE(board->flags);
1042 if (board->flags & FL_BASE_BARS)
1043 bar += idx;
1044 else
1045 offset += idx * board->uart_offset;
1046
2427ddd8
GKH		 1047 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048 (board->reg_shift + 3);
1da177e4
LT		 1049
1050 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051 return 1;
5756ee99 1052
70db3d91 1053 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1054}
1055
095e24b0
DB		 1056static int
1057ce4100_serial_setup(struct serial_private *priv,
1058 const struct pciserial_board *board,
1059 struct uart_port *port, int idx)
1060{
1061 int ret;
1062
1063 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064 port->iotype = UPIO_MEM32;
1065 port->type = PORT_XSCALE;
1066 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067 port->regshift = 2;
1068
1069 return ret;
1070}
1071
d9a0fbfd
AP		 1072static int
1073pci_omegapci_setup(struct serial_private *priv,
1798ca13 1074 const struct pciserial_board *board,
d9a0fbfd
AP		 1075 struct uart_port *port, int idx)
1076{
1077 return setup_port(priv, port, 2, idx * 8, 0);
1078}
1079
b6adea33
MCC		 1080static int skip_tx_en_setup(struct serial_private *priv,
1081 const struct pciserial_board *board,
1082 struct uart_port *port, int idx)
1083{
1084 port->flags |= UPF_NO_TXEN_TEST;
1085 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086 "[%04x:%04x] subsystem [%04x:%04x]\n",
1087 priv->dev->vendor,
1088 priv->dev->device,
1089 priv->dev->subsystem_vendor,
1090 priv->dev->subsystem_device);
1091
1092 return pci_default_setup(priv, board, port, idx);
1093}
1094
448ac154
DW		 1095static int kt_serial_setup(struct serial_private *priv,
1096 const struct pciserial_board *board,
1097 struct uart_port *port, int idx)
1098{
1099 port->flags |= UPF_IIR_ONCE;
1100 return skip_tx_en_setup(priv, board, port, idx);
1101}
1102
eb7073db
TM		 1103static int pci_eg20t_init(struct pci_dev *dev)
1104{
1105#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1106 return -ENODEV;
1107#else
1108 return 0;
1109#endif
1110}
1111
06315348
SH		 1112static int
1113pci_xr17c154_setup(struct serial_private *priv,
1114 const struct pciserial_board *board,
1115 struct uart_port *port, int idx)
1116{
1117 port->flags |= UPF_EXAR_EFR;
1118 return pci_default_setup(priv, board, port, idx);
1119}
1120
e86ff4a6
DW		 1121static int try_enable_msi(struct pci_dev *dev)
1122{
1123 /* use msi if available, but fallback to legacy otherwise */
1124 pci_enable_msi(dev);
1125 return 0;
1126}
1127
1128static void disable_msi(struct pci_dev *dev)
1129{
1130 pci_disable_msi(dev);
1131}
1132
1da177e4
LT		 1133#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1134#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1135#define PCI_DEVICE_ID_OCTPRO 0x0001
1136#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1137#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1138#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1139#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48 1140#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1141#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1142#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1143#define PCI_DEVICE_ID_TITAN_200I 0x8028
1144#define PCI_DEVICE_ID_TITAN_400I 0x8048
1145#define PCI_DEVICE_ID_TITAN_800I 0x8088
1146#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1147#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1148#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1149#define PCI_DEVICE_ID_TITAN_100E 0xA010
1150#define PCI_DEVICE_ID_TITAN_200E 0xA012
1151#define PCI_DEVICE_ID_TITAN_400E 0xA013
1152#define PCI_DEVICE_ID_TITAN_800E 0xA014
1153#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1154#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
e847003f 1155#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1156#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1157#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
448ac154 1158#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1da177e4 1159
b76c5a07
CB		 1160/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1161#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1162
1da177e4
LT		 1163/*
1164 * Master list of serial port init/setup/exit quirks.
1165 * This does not describe the general nature of the port.
1166 * (ie, baud base, number and location of ports, etc)
1167 *
1168 * This list is ordered alphabetically by vendor then device.
1169 * Specific entries must come before more generic entries.
1170 */
7a63ce5a 1171static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1172 /*
1173 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1174 */
1175 {
1176 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1177 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1178 .subvendor = PCI_ANY_ID,
1179 .subdevice = PCI_ANY_ID,
1180 .setup = addidata_apci7800_setup,
1181 },
1da177e4 1182 /*
61a116ef 1183 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1184 * It is not clear whether this applies to all products.
1185 */
1186 {
1187 .vendor = PCI_VENDOR_ID_AFAVLAB,
1188 .device = PCI_ANY_ID,
1189 .subvendor = PCI_ANY_ID,
1190 .subdevice = PCI_ANY_ID,
1191 .setup = afavlab_setup,
1192 },
1193 /*
1194 * HP Diva
1195 */
1196 {
1197 .vendor = PCI_VENDOR_ID_HP,
1198 .device = PCI_DEVICE_ID_HP_DIVA,
1199 .subvendor = PCI_ANY_ID,
1200 .subdevice = PCI_ANY_ID,
1201 .init = pci_hp_diva_init,
1202 .setup = pci_hp_diva_setup,
1203 },
1204 /*
1205 * Intel
1206 */
1207 {
1208 .vendor = PCI_VENDOR_ID_INTEL,
1209 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1210 .subvendor = 0xe4bf,
1211 .subdevice = PCI_ANY_ID,
1212 .init = pci_inteli960ni_init,
1213 .setup = pci_default_setup,
1214 },
b6adea33
MCC		 1215 {
1216 .vendor = PCI_VENDOR_ID_INTEL,
1217 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1218 .subvendor = PCI_ANY_ID,
1219 .subdevice = PCI_ANY_ID,
1220 .setup = skip_tx_en_setup,
1221 },
1222 {
1223 .vendor = PCI_VENDOR_ID_INTEL,
1224 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1225 .subvendor = PCI_ANY_ID,
1226 .subdevice = PCI_ANY_ID,
1227 .setup = skip_tx_en_setup,
1228 },
1229 {
1230 .vendor = PCI_VENDOR_ID_INTEL,
1231 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1232 .subvendor = PCI_ANY_ID,
1233 .subdevice = PCI_ANY_ID,
1234 .setup = skip_tx_en_setup,
1235 },
095e24b0
DB		 1236 {
1237 .vendor = PCI_VENDOR_ID_INTEL,
1238 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1239 .subvendor = PCI_ANY_ID,
1240 .subdevice = PCI_ANY_ID,
1241 .setup = ce4100_serial_setup,
1242 },
448ac154
DW		 1243 {
1244 .vendor = PCI_VENDOR_ID_INTEL,
1245 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1246 .subvendor = PCI_ANY_ID,
1247 .subdevice = PCI_ANY_ID,
e86ff4a6 1248 .init = try_enable_msi,
448ac154 1249 .setup = kt_serial_setup,
e86ff4a6 1250 .exit = disable_msi,
448ac154 1251 },
84f8c6fc
NV		 1252 /*
1253 * ITE
1254 */
1255 {
1256 .vendor = PCI_VENDOR_ID_ITE,
1257 .device = PCI_DEVICE_ID_ITE_8872,
1258 .subvendor = PCI_ANY_ID,
1259 .subdevice = PCI_ANY_ID,
1260 .init = pci_ite887x_init,
1261 .setup = pci_default_setup,
1262 .exit = __devexit_p(pci_ite887x_exit),
1263 },
46a0fac9
SB		 1264 /*
1265 * National Instruments
1266 */
04bf7e74
WP		 1267 {
1268 .vendor = PCI_VENDOR_ID_NI,
1269 .device = PCI_DEVICE_ID_NI_PCI23216,
1270 .subvendor = PCI_ANY_ID,
1271 .subdevice = PCI_ANY_ID,
1272 .init = pci_ni8420_init,
1273 .setup = pci_default_setup,
1274 .exit = __devexit_p(pci_ni8420_exit),
1275 },
1276 {
1277 .vendor = PCI_VENDOR_ID_NI,
1278 .device = PCI_DEVICE_ID_NI_PCI2328,
1279 .subvendor = PCI_ANY_ID,
1280 .subdevice = PCI_ANY_ID,
1281 .init = pci_ni8420_init,
1282 .setup = pci_default_setup,
1283 .exit = __devexit_p(pci_ni8420_exit),
1284 },
1285 {
1286 .vendor = PCI_VENDOR_ID_NI,
1287 .device = PCI_DEVICE_ID_NI_PCI2324,
1288 .subvendor = PCI_ANY_ID,
1289 .subdevice = PCI_ANY_ID,
1290 .init = pci_ni8420_init,
1291 .setup = pci_default_setup,
1292 .exit = __devexit_p(pci_ni8420_exit),
1293 },
1294 {
1295 .vendor = PCI_VENDOR_ID_NI,
1296 .device = PCI_DEVICE_ID_NI_PCI2322,
1297 .subvendor = PCI_ANY_ID,
1298 .subdevice = PCI_ANY_ID,
1299 .init = pci_ni8420_init,
1300 .setup = pci_default_setup,
1301 .exit = __devexit_p(pci_ni8420_exit),
1302 },
1303 {
1304 .vendor = PCI_VENDOR_ID_NI,
1305 .device = PCI_DEVICE_ID_NI_PCI2324I,
1306 .subvendor = PCI_ANY_ID,
1307 .subdevice = PCI_ANY_ID,
1308 .init = pci_ni8420_init,
1309 .setup = pci_default_setup,
1310 .exit = __devexit_p(pci_ni8420_exit),
1311 },
1312 {
1313 .vendor = PCI_VENDOR_ID_NI,
1314 .device = PCI_DEVICE_ID_NI_PCI2322I,
1315 .subvendor = PCI_ANY_ID,
1316 .subdevice = PCI_ANY_ID,
1317 .init = pci_ni8420_init,
1318 .setup = pci_default_setup,
1319 .exit = __devexit_p(pci_ni8420_exit),
1320 },
1321 {
1322 .vendor = PCI_VENDOR_ID_NI,
1323 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1324 .subvendor = PCI_ANY_ID,
1325 .subdevice = PCI_ANY_ID,
1326 .init = pci_ni8420_init,
1327 .setup = pci_default_setup,
1328 .exit = __devexit_p(pci_ni8420_exit),
1329 },
1330 {
1331 .vendor = PCI_VENDOR_ID_NI,
1332 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1333 .subvendor = PCI_ANY_ID,
1334 .subdevice = PCI_ANY_ID,
1335 .init = pci_ni8420_init,
1336 .setup = pci_default_setup,
1337 .exit = __devexit_p(pci_ni8420_exit),
1338 },
1339 {
1340 .vendor = PCI_VENDOR_ID_NI,
1341 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1342 .subvendor = PCI_ANY_ID,
1343 .subdevice = PCI_ANY_ID,
1344 .init = pci_ni8420_init,
1345 .setup = pci_default_setup,
1346 .exit = __devexit_p(pci_ni8420_exit),
1347 },
1348 {
1349 .vendor = PCI_VENDOR_ID_NI,
1350 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1351 .subvendor = PCI_ANY_ID,
1352 .subdevice = PCI_ANY_ID,
1353 .init = pci_ni8420_init,
1354 .setup = pci_default_setup,
1355 .exit = __devexit_p(pci_ni8420_exit),
1356 },
1357 {
1358 .vendor = PCI_VENDOR_ID_NI,
1359 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1360 .subvendor = PCI_ANY_ID,
1361 .subdevice = PCI_ANY_ID,
1362 .init = pci_ni8420_init,
1363 .setup = pci_default_setup,
1364 .exit = __devexit_p(pci_ni8420_exit),
1365 },
1366 {
1367 .vendor = PCI_VENDOR_ID_NI,
1368 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1369 .subvendor = PCI_ANY_ID,
1370 .subdevice = PCI_ANY_ID,
1371 .init = pci_ni8420_init,
1372 .setup = pci_default_setup,
1373 .exit = __devexit_p(pci_ni8420_exit),
1374 },
46a0fac9
SB		 1375 {
1376 .vendor = PCI_VENDOR_ID_NI,
1377 .device = PCI_ANY_ID,
1378 .subvendor = PCI_ANY_ID,
1379 .subdevice = PCI_ANY_ID,
1380 .init = pci_ni8430_init,
1381 .setup = pci_ni8430_setup,
1382 .exit = __devexit_p(pci_ni8430_exit),
1383 },
1da177e4
LT		 1384 /*
1385 * Panacom
1386 */
1387 {
1388 .vendor = PCI_VENDOR_ID_PANACOM,
1389 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1390 .subvendor = PCI_ANY_ID,
1391 .subdevice = PCI_ANY_ID,
1392 .init = pci_plx9050_init,
1393 .setup = pci_default_setup,
1394 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 1395 },
1da177e4
LT		 1396 {
1397 .vendor = PCI_VENDOR_ID_PANACOM,
1398 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1399 .subvendor = PCI_ANY_ID,
1400 .subdevice = PCI_ANY_ID,
1401 .init = pci_plx9050_init,
1402 .setup = pci_default_setup,
1403 .exit = __devexit_p(pci_plx9050_exit),
1404 },
1405 /*
1406 * PLX
1407 */
48212008
TH		 1408 {
1409 .vendor = PCI_VENDOR_ID_PLX,
1410 .device = PCI_DEVICE_ID_PLX_9030,
1411 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1412 .subdevice = PCI_ANY_ID,
1413 .setup = pci_default_setup,
1414 },
add7b58e
BH		 1415 {
1416 .vendor = PCI_VENDOR_ID_PLX,
1417 .device = PCI_DEVICE_ID_PLX_9050,
1418 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1419 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1420 .init = pci_plx9050_init,
1421 .setup = pci_default_setup,
1422 .exit = __devexit_p(pci_plx9050_exit),
1423 },
1da177e4
LT		 1424 {
1425 .vendor = PCI_VENDOR_ID_PLX,
1426 .device = PCI_DEVICE_ID_PLX_9050,
1427 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1428 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1429 .init = pci_plx9050_init,
1430 .setup = pci_default_setup,
1431 .exit = __devexit_p(pci_plx9050_exit),
1432 },
b76c5a07
CB		 1433 {
1434 .vendor = PCI_VENDOR_ID_PLX,
1435 .device = PCI_DEVICE_ID_PLX_9050,
1436 .subvendor = PCI_VENDOR_ID_PLX,
1437 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1438 .init = pci_plx9050_init,
1439 .setup = pci_default_setup,
1440 .exit = __devexit_p(pci_plx9050_exit),
1441 },
1da177e4
LT		 1442 {
1443 .vendor = PCI_VENDOR_ID_PLX,
1444 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1445 .subvendor = PCI_VENDOR_ID_PLX,
1446 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1447 .init = pci_plx9050_init,
1448 .setup = pci_default_setup,
1449 .exit = __devexit_p(pci_plx9050_exit),
1450 },
1451 /*
1452 * SBS Technologies, Inc., PMC-OCTALPRO 232
1453 */
1454 {
1455 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1456 .device = PCI_DEVICE_ID_OCTPRO,
1457 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1458 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1459 .init = sbs_init,
1460 .setup = sbs_setup,
1461 .exit = __devexit_p(sbs_exit),
1462 },
1463 /*
1464 * SBS Technologies, Inc., PMC-OCTALPRO 422
1465 */
1466 {
1467 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1468 .device = PCI_DEVICE_ID_OCTPRO,
1469 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1470 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1471 .init = sbs_init,
1472 .setup = sbs_setup,
1473 .exit = __devexit_p(sbs_exit),
1474 },
1475 /*
1476 * SBS Technologies, Inc., P-Octal 232
1477 */
1478 {
1479 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1480 .device = PCI_DEVICE_ID_OCTPRO,
1481 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1482 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1483 .init = sbs_init,
1484 .setup = sbs_setup,
1485 .exit = __devexit_p(sbs_exit),
1486 },
1487 /*
1488 * SBS Technologies, Inc., P-Octal 422
1489 */
1490 {
1491 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1492 .device = PCI_DEVICE_ID_OCTPRO,
1493 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1494 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1495 .init = sbs_init,
1496 .setup = sbs_setup,
1497 .exit = __devexit_p(sbs_exit),
1498 },
1da177e4 1499 /*
61a116ef 1500 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1501 */
1502 {
1503 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1504 .device = PCI_ANY_ID,
1da177e4
LT		 1505 .subvendor = PCI_ANY_ID,
1506 .subdevice = PCI_ANY_ID,
67d74b87 1507 .init = pci_siig_init,
3ec9c594 1508 .setup = pci_siig_setup,
1da177e4
LT		 1509 },
1510 /*
1511 * Titan cards
1512 */
1513 {
1514 .vendor = PCI_VENDOR_ID_TITAN,
1515 .device = PCI_DEVICE_ID_TITAN_400L,
1516 .subvendor = PCI_ANY_ID,
1517 .subdevice = PCI_ANY_ID,
1518 .setup = titan_400l_800l_setup,
1519 },
1520 {
1521 .vendor = PCI_VENDOR_ID_TITAN,
1522 .device = PCI_DEVICE_ID_TITAN_800L,
1523 .subvendor = PCI_ANY_ID,
1524 .subdevice = PCI_ANY_ID,
1525 .setup = titan_400l_800l_setup,
1526 },
1527 /*
1528 * Timedia cards
1529 */
1530 {
1531 .vendor = PCI_VENDOR_ID_TIMEDIA,
1532 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1533 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1534 .subdevice = PCI_ANY_ID,
b9b24558 1535 .probe = pci_timedia_probe,
1da177e4
LT		 1536 .init = pci_timedia_init,
1537 .setup = pci_timedia_setup,
1538 },
1539 {
1540 .vendor = PCI_VENDOR_ID_TIMEDIA,
1541 .device = PCI_ANY_ID,
1542 .subvendor = PCI_ANY_ID,
1543 .subdevice = PCI_ANY_ID,
1544 .setup = pci_timedia_setup,
1545 },
06315348
SH		 1546 /*
1547 * Exar cards
1548 */
1549 {
1550 .vendor = PCI_VENDOR_ID_EXAR,
1551 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1552 .subvendor = PCI_ANY_ID,
1553 .subdevice = PCI_ANY_ID,
1554 .setup = pci_xr17c154_setup,
1555 },
1556 {
1557 .vendor = PCI_VENDOR_ID_EXAR,
1558 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1559 .subvendor = PCI_ANY_ID,
1560 .subdevice = PCI_ANY_ID,
1561 .setup = pci_xr17c154_setup,
1562 },
1563 {
1564 .vendor = PCI_VENDOR_ID_EXAR,
1565 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1566 .subvendor = PCI_ANY_ID,
1567 .subdevice = PCI_ANY_ID,
1568 .setup = pci_xr17c154_setup,
1569 },
1da177e4
LT		 1570 /*
1571 * Xircom cards
1572 */
1573 {
1574 .vendor = PCI_VENDOR_ID_XIRCOM,
1575 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1576 .subvendor = PCI_ANY_ID,
1577 .subdevice = PCI_ANY_ID,
1578 .init = pci_xircom_init,
1579 .setup = pci_default_setup,
1580 },
1581 /*
61a116ef 1582 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1583 */
1584 {
1585 .vendor = PCI_VENDOR_ID_NETMOS,
1586 .device = PCI_ANY_ID,
1587 .subvendor = PCI_ANY_ID,
1588 .subdevice = PCI_ANY_ID,
1589 .init = pci_netmos_init,
7808edcd 1590 .setup = pci_netmos_9900_setup,
1da177e4 1591 },
9f2a036a 1592 /*
aa273ae5 1593 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 1594 */
1595 {
1596 .vendor = PCI_VENDOR_ID_OXSEMI,
1597 .device = PCI_ANY_ID,
1598 .subvendor = PCI_ANY_ID,
1599 .subdevice = PCI_ANY_ID,
1600 .init = pci_oxsemi_tornado_init,
1601 .setup = pci_default_setup,
1602 },
1603 {
1604 .vendor = PCI_VENDOR_ID_MAINPINE,
1605 .device = PCI_ANY_ID,
1606 .subvendor = PCI_ANY_ID,
1607 .subdevice = PCI_ANY_ID,
1608 .init = pci_oxsemi_tornado_init,
1609 .setup = pci_default_setup,
1610 },
aa273ae5
SK		 1611 {
1612 .vendor = PCI_VENDOR_ID_DIGI,
1613 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1614 .subvendor = PCI_SUBVENDOR_ID_IBM,
1615 .subdevice = PCI_ANY_ID,
1616 .init = pci_oxsemi_tornado_init,
1617 .setup = pci_default_setup,
1618 },
eb7073db
TM		 1619 {
1620 .vendor = PCI_VENDOR_ID_INTEL,
1621 .device = 0x8811,
1622 .init = pci_eg20t_init,
64d91cfa 1623 .setup = pci_default_setup,
eb7073db
TM		 1624 },
1625 {
1626 .vendor = PCI_VENDOR_ID_INTEL,
1627 .device = 0x8812,
1628 .init = pci_eg20t_init,
64d91cfa 1629 .setup = pci_default_setup,
eb7073db
TM		 1630 },
1631 {
1632 .vendor = PCI_VENDOR_ID_INTEL,
1633 .device = 0x8813,
1634 .init = pci_eg20t_init,
64d91cfa 1635 .setup = pci_default_setup,
eb7073db
TM		 1636 },
1637 {
1638 .vendor = PCI_VENDOR_ID_INTEL,
1639 .device = 0x8814,
1640 .init = pci_eg20t_init,
64d91cfa 1641 .setup = pci_default_setup,
eb7073db
TM		 1642 },
1643 {
1644 .vendor = 0x10DB,
1645 .device = 0x8027,
1646 .init = pci_eg20t_init,
64d91cfa 1647 .setup = pci_default_setup,
eb7073db
TM		 1648 },
1649 {
1650 .vendor = 0x10DB,
1651 .device = 0x8028,
1652 .init = pci_eg20t_init,
64d91cfa 1653 .setup = pci_default_setup,
eb7073db
TM		 1654 },
1655 {
1656 .vendor = 0x10DB,
1657 .device = 0x8029,
1658 .init = pci_eg20t_init,
64d91cfa 1659 .setup = pci_default_setup,
eb7073db
TM		 1660 },
1661 {
1662 .vendor = 0x10DB,
1663 .device = 0x800C,
1664 .init = pci_eg20t_init,
64d91cfa 1665 .setup = pci_default_setup,
eb7073db
TM		 1666 },
1667 {
1668 .vendor = 0x10DB,
1669 .device = 0x800D,
1670 .init = pci_eg20t_init,
64d91cfa 1671 .setup = pci_default_setup,
eb7073db 1672 },
d9a0fbfd
AP		 1673 /*
1674 * Cronyx Omega PCI (PLX-chip based)
1675 */
1676 {
1677 .vendor = PCI_VENDOR_ID_PLX,
1678 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1679 .subvendor = PCI_ANY_ID,
1680 .subdevice = PCI_ANY_ID,
1681 .setup = pci_omegapci_setup,
1682 },
1da177e4
LT		 1683 /*
1684 * Default "match everything" terminator entry
1685 */
1686 {
1687 .vendor = PCI_ANY_ID,
1688 .device = PCI_ANY_ID,
1689 .subvendor = PCI_ANY_ID,
1690 .subdevice = PCI_ANY_ID,
1691 .setup = pci_default_setup,
1692 }
1693};
1694
1695static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1696{
1697 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1698}
1699
1700static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1701{
1702 struct pci_serial_quirk *quirk;
1703
1704 for (quirk = pci_serial_quirks; ; quirk++)
1705 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1706 quirk_id_matches(quirk->device, dev->device) &&
1707 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1708 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1709 break;
1da177e4
LT		 1710 return quirk;
1711}
1712
dd68e88c 1713static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1714 const struct pciserial_board *board)
1da177e4
LT		 1715{
1716 if (board->flags & FL_NOIRQ)
1717 return 0;
1718 else
1719 return dev->irq;
1720}
1721
1722/*
1723 * This is the configuration table for all of the PCI serial boards
1724 * which we support. It is directly indexed by the pci_board_num_t enum
1725 * value, which is encoded in the pci_device_id PCI probe table's
1726 * driver_data member.
1727 *
1728 * The makeup of these names are:
26e92861 1729 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1730 *
26e92861
GH		 1731 * bn = PCI BAR number
1732 * bt = Index using PCI BARs
1733 * n = number of serial ports
1734 * baud = baud rate
1735 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1736 *
26e92861 1737 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1738 *
1da177e4
LT		 1739 * Please note: in theory if n = 1, _bt infix should make no difference.
1740 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1741 */
1742enum pci_board_num_t {
1743 pbn_default = 0,
1744
1745 pbn_b0_1_115200,
1746 pbn_b0_2_115200,
1747 pbn_b0_4_115200,
1748 pbn_b0_5_115200,
bf0df636 1749 pbn_b0_8_115200,
1da177e4
LT		 1750
1751 pbn_b0_1_921600,
1752 pbn_b0_2_921600,
1753 pbn_b0_4_921600,
1754
db1de159
DR		 1755 pbn_b0_2_1130000,
1756
fbc0dc0d
AP		 1757 pbn_b0_4_1152000,
1758
26e92861
GH		 1759 pbn_b0_2_1843200,
1760 pbn_b0_4_1843200,
1761
1762 pbn_b0_2_1843200_200,
1763 pbn_b0_4_1843200_200,
1764 pbn_b0_8_1843200_200,
1765
7106b4e3
LH		 1766 pbn_b0_1_4000000,
1767
1da177e4
LT		 1768 pbn_b0_bt_1_115200,
1769 pbn_b0_bt_2_115200,
ac6ec5b1 1770 pbn_b0_bt_4_115200,
1da177e4
LT		 1771 pbn_b0_bt_8_115200,
1772
1773 pbn_b0_bt_1_460800,
1774 pbn_b0_bt_2_460800,
1775 pbn_b0_bt_4_460800,
1776
1777 pbn_b0_bt_1_921600,
1778 pbn_b0_bt_2_921600,
1779 pbn_b0_bt_4_921600,
1780 pbn_b0_bt_8_921600,
1781
1782 pbn_b1_1_115200,
1783 pbn_b1_2_115200,
1784 pbn_b1_4_115200,
1785 pbn_b1_8_115200,
04bf7e74 1786 pbn_b1_16_115200,
1da177e4
LT		 1787
1788 pbn_b1_1_921600,
1789 pbn_b1_2_921600,
1790 pbn_b1_4_921600,
1791 pbn_b1_8_921600,
1792
26e92861
GH		 1793 pbn_b1_2_1250000,
1794
84f8c6fc 1795 pbn_b1_bt_1_115200,
04bf7e74
WP		 1796 pbn_b1_bt_2_115200,
1797 pbn_b1_bt_4_115200,
1798
1da177e4
LT		 1799 pbn_b1_bt_2_921600,
1800
1801 pbn_b1_1_1382400,
1802 pbn_b1_2_1382400,
1803 pbn_b1_4_1382400,
1804 pbn_b1_8_1382400,
1805
1806 pbn_b2_1_115200,
737c1756 1807 pbn_b2_2_115200,
a9cccd34 1808 pbn_b2_4_115200,
1da177e4
LT		 1809 pbn_b2_8_115200,
1810
1811 pbn_b2_1_460800,
1812 pbn_b2_4_460800,
1813 pbn_b2_8_460800,
1814 pbn_b2_16_460800,
1815
1816 pbn_b2_1_921600,
1817 pbn_b2_4_921600,
1818 pbn_b2_8_921600,
1819
e847003f
LB		 1820 pbn_b2_8_1152000,
1821
1da177e4
LT		 1822 pbn_b2_bt_1_115200,
1823 pbn_b2_bt_2_115200,
1824 pbn_b2_bt_4_115200,
1825
1826 pbn_b2_bt_2_921600,
1827 pbn_b2_bt_4_921600,
1828
d9004eb4 1829 pbn_b3_2_115200,
1da177e4
LT		 1830 pbn_b3_4_115200,
1831 pbn_b3_8_115200,
1832
66169ad1
YY		 1833 pbn_b4_bt_2_921600,
1834 pbn_b4_bt_4_921600,
1835 pbn_b4_bt_8_921600,
1836
1da177e4
LT		 1837 /*
1838 * Board-specific versions.
1839 */
1840 pbn_panacom,
1841 pbn_panacom2,
1842 pbn_panacom4,
add7b58e 1843 pbn_exsys_4055,
1da177e4
LT		 1844 pbn_plx_romulus,
1845 pbn_oxsemi,
7106b4e3
LH		 1846 pbn_oxsemi_1_4000000,
1847 pbn_oxsemi_2_4000000,
1848 pbn_oxsemi_4_4000000,
1849 pbn_oxsemi_8_4000000,
1da177e4
LT		 1850 pbn_intel_i960,
1851 pbn_sgi_ioc3,
1da177e4
LT		 1852 pbn_computone_4,
1853 pbn_computone_6,
1854 pbn_computone_8,
1855 pbn_sbsxrsio,
1856 pbn_exar_XR17C152,
1857 pbn_exar_XR17C154,
1858 pbn_exar_XR17C158,
c68d2b15 1859 pbn_exar_ibm_saturn,
aa798505 1860 pbn_pasemi_1682M,
46a0fac9
SB		 1861 pbn_ni8430_2,
1862 pbn_ni8430_4,
1863 pbn_ni8430_8,
1864 pbn_ni8430_16,
1b62cbf2
KJ		 1865 pbn_ADDIDATA_PCIe_1_3906250,
1866 pbn_ADDIDATA_PCIe_2_3906250,
1867 pbn_ADDIDATA_PCIe_4_3906250,
1868 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 1869 pbn_ce4100_1_115200,
d9a0fbfd 1870 pbn_omegapci,
7808edcd 1871 pbn_NETMOS9900_2s_115200,
1da177e4
LT		 1872};
1873
1874/*
1875 * uart_offset - the space between channels
1876 * reg_shift - describes how the UART registers are mapped
1877 * to PCI memory by the card.
1878 * For example IER register on SBS, Inc. PMC-OctPro is located at
1879 * offset 0x10 from the UART base, while UART_IER is defined as 1
1880 * in include/linux/serial_reg.h,
1881 * see first lines of serial_in() and serial_out() in 8250.c
1882*/
1883
1c7c1fe5 1884static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1885 [pbn_default] = {
1886 .flags = FL_BASE0,
1887 .num_ports = 1,
1888 .base_baud = 115200,
1889 .uart_offset = 8,
1890 },
1891 [pbn_b0_1_115200] = {
1892 .flags = FL_BASE0,
1893 .num_ports = 1,
1894 .base_baud = 115200,
1895 .uart_offset = 8,
1896 },
1897 [pbn_b0_2_115200] = {
1898 .flags = FL_BASE0,
1899 .num_ports = 2,
1900 .base_baud = 115200,
1901 .uart_offset = 8,
1902 },
1903 [pbn_b0_4_115200] = {
1904 .flags = FL_BASE0,
1905 .num_ports = 4,
1906 .base_baud = 115200,
1907 .uart_offset = 8,
1908 },
1909 [pbn_b0_5_115200] = {
1910 .flags = FL_BASE0,
1911 .num_ports = 5,
1912 .base_baud = 115200,
1913 .uart_offset = 8,
1914 },
bf0df636
AC		 1915 [pbn_b0_8_115200] = {
1916 .flags = FL_BASE0,
1917 .num_ports = 8,
1918 .base_baud = 115200,
1919 .uart_offset = 8,
1920 },
1da177e4
LT		 1921 [pbn_b0_1_921600] = {
1922 .flags = FL_BASE0,
1923 .num_ports = 1,
1924 .base_baud = 921600,
1925 .uart_offset = 8,
1926 },
1927 [pbn_b0_2_921600] = {
1928 .flags = FL_BASE0,
1929 .num_ports = 2,
1930 .base_baud = 921600,
1931 .uart_offset = 8,
1932 },
1933 [pbn_b0_4_921600] = {
1934 .flags = FL_BASE0,
1935 .num_ports = 4,
1936 .base_baud = 921600,
1937 .uart_offset = 8,
1938 },
db1de159
DR		 1939
1940 [pbn_b0_2_1130000] = {
1941 .flags = FL_BASE0,
1942 .num_ports = 2,
1943 .base_baud = 1130000,
1944 .uart_offset = 8,
1945 },
1946
fbc0dc0d
AP		 1947 [pbn_b0_4_1152000] = {
1948 .flags = FL_BASE0,
1949 .num_ports = 4,
1950 .base_baud = 1152000,
1951 .uart_offset = 8,
1952 },
1da177e4 1953
26e92861
GH		 1954 [pbn_b0_2_1843200] = {
1955 .flags = FL_BASE0,
1956 .num_ports = 2,
1957 .base_baud = 1843200,
1958 .uart_offset = 8,
1959 },
1960 [pbn_b0_4_1843200] = {
1961 .flags = FL_BASE0,
1962 .num_ports = 4,
1963 .base_baud = 1843200,
1964 .uart_offset = 8,
1965 },
1966
1967 [pbn_b0_2_1843200_200] = {
1968 .flags = FL_BASE0,
1969 .num_ports = 2,
1970 .base_baud = 1843200,
1971 .uart_offset = 0x200,
1972 },
1973 [pbn_b0_4_1843200_200] = {
1974 .flags = FL_BASE0,
1975 .num_ports = 4,
1976 .base_baud = 1843200,
1977 .uart_offset = 0x200,
1978 },
1979 [pbn_b0_8_1843200_200] = {
1980 .flags = FL_BASE0,
1981 .num_ports = 8,
1982 .base_baud = 1843200,
1983 .uart_offset = 0x200,
1984 },
7106b4e3
LH		 1985 [pbn_b0_1_4000000] = {
1986 .flags = FL_BASE0,
1987 .num_ports = 1,
1988 .base_baud = 4000000,
1989 .uart_offset = 8,
1990 },
26e92861 1991
1da177e4
LT		 1992 [pbn_b0_bt_1_115200] = {
1993 .flags = FL_BASE0|FL_BASE_BARS,
1994 .num_ports = 1,
1995 .base_baud = 115200,
1996 .uart_offset = 8,
1997 },
1998 [pbn_b0_bt_2_115200] = {
1999 .flags = FL_BASE0|FL_BASE_BARS,
2000 .num_ports = 2,
2001 .base_baud = 115200,
2002 .uart_offset = 8,
2003 },
ac6ec5b1
IS		 2004 [pbn_b0_bt_4_115200] = {
2005 .flags = FL_BASE0|FL_BASE_BARS,
2006 .num_ports = 4,
2007 .base_baud = 115200,
2008 .uart_offset = 8,
2009 },
1da177e4
LT		 2010 [pbn_b0_bt_8_115200] = {
2011 .flags = FL_BASE0|FL_BASE_BARS,
2012 .num_ports = 8,
2013 .base_baud = 115200,
2014 .uart_offset = 8,
2015 },
2016
2017 [pbn_b0_bt_1_460800] = {
2018 .flags = FL_BASE0|FL_BASE_BARS,
2019 .num_ports = 1,
2020 .base_baud = 460800,
2021 .uart_offset = 8,
2022 },
2023 [pbn_b0_bt_2_460800] = {
2024 .flags = FL_BASE0|FL_BASE_BARS,
2025 .num_ports = 2,
2026 .base_baud = 460800,
2027 .uart_offset = 8,
2028 },
2029 [pbn_b0_bt_4_460800] = {
2030 .flags = FL_BASE0|FL_BASE_BARS,
2031 .num_ports = 4,
2032 .base_baud = 460800,
2033 .uart_offset = 8,
2034 },
2035
2036 [pbn_b0_bt_1_921600] = {
2037 .flags = FL_BASE0|FL_BASE_BARS,
2038 .num_ports = 1,
2039 .base_baud = 921600,
2040 .uart_offset = 8,
2041 },
2042 [pbn_b0_bt_2_921600] = {
2043 .flags = FL_BASE0|FL_BASE_BARS,
2044 .num_ports = 2,
2045 .base_baud = 921600,
2046 .uart_offset = 8,
2047 },
2048 [pbn_b0_bt_4_921600] = {
2049 .flags = FL_BASE0|FL_BASE_BARS,
2050 .num_ports = 4,
2051 .base_baud = 921600,
2052 .uart_offset = 8,
2053 },
2054 [pbn_b0_bt_8_921600] = {
2055 .flags = FL_BASE0|FL_BASE_BARS,
2056 .num_ports = 8,
2057 .base_baud = 921600,
2058 .uart_offset = 8,
2059 },
2060
2061 [pbn_b1_1_115200] = {
2062 .flags = FL_BASE1,
2063 .num_ports = 1,
2064 .base_baud = 115200,
2065 .uart_offset = 8,
2066 },
2067 [pbn_b1_2_115200] = {
2068 .flags = FL_BASE1,
2069 .num_ports = 2,
2070 .base_baud = 115200,
2071 .uart_offset = 8,
2072 },
2073 [pbn_b1_4_115200] = {
2074 .flags = FL_BASE1,
2075 .num_ports = 4,
2076 .base_baud = 115200,
2077 .uart_offset = 8,
2078 },
2079 [pbn_b1_8_115200] = {
2080 .flags = FL_BASE1,
2081 .num_ports = 8,
2082 .base_baud = 115200,
2083 .uart_offset = 8,
2084 },
04bf7e74
WP		 2085 [pbn_b1_16_115200] = {
2086 .flags = FL_BASE1,
2087 .num_ports = 16,
2088 .base_baud = 115200,
2089 .uart_offset = 8,
2090 },
1da177e4
LT		 2091
2092 [pbn_b1_1_921600] = {
2093 .flags = FL_BASE1,
2094 .num_ports = 1,
2095 .base_baud = 921600,
2096 .uart_offset = 8,
2097 },
2098 [pbn_b1_2_921600] = {
2099 .flags = FL_BASE1,
2100 .num_ports = 2,
2101 .base_baud = 921600,
2102 .uart_offset = 8,
2103 },
2104 [pbn_b1_4_921600] = {
2105 .flags = FL_BASE1,
2106 .num_ports = 4,
2107 .base_baud = 921600,
2108 .uart_offset = 8,
2109 },
2110 [pbn_b1_8_921600] = {
2111 .flags = FL_BASE1,
2112 .num_ports = 8,
2113 .base_baud = 921600,
2114 .uart_offset = 8,
2115 },
26e92861
GH		 2116 [pbn_b1_2_1250000] = {
2117 .flags = FL_BASE1,
2118 .num_ports = 2,
2119 .base_baud = 1250000,
2120 .uart_offset = 8,
2121 },
1da177e4 2122
84f8c6fc
NV		 2123 [pbn_b1_bt_1_115200] = {
2124 .flags = FL_BASE1|FL_BASE_BARS,
2125 .num_ports = 1,
2126 .base_baud = 115200,
2127 .uart_offset = 8,
2128 },
04bf7e74
WP		 2129 [pbn_b1_bt_2_115200] = {
2130 .flags = FL_BASE1|FL_BASE_BARS,
2131 .num_ports = 2,
2132 .base_baud = 115200,
2133 .uart_offset = 8,
2134 },
2135 [pbn_b1_bt_4_115200] = {
2136 .flags = FL_BASE1|FL_BASE_BARS,
2137 .num_ports = 4,
2138 .base_baud = 115200,
2139 .uart_offset = 8,
2140 },
84f8c6fc 2141
1da177e4
LT		 2142 [pbn_b1_bt_2_921600] = {
2143 .flags = FL_BASE1|FL_BASE_BARS,
2144 .num_ports = 2,
2145 .base_baud = 921600,
2146 .uart_offset = 8,
2147 },
2148
2149 [pbn_b1_1_1382400] = {
2150 .flags = FL_BASE1,
2151 .num_ports = 1,
2152 .base_baud = 1382400,
2153 .uart_offset = 8,
2154 },
2155 [pbn_b1_2_1382400] = {
2156 .flags = FL_BASE1,
2157 .num_ports = 2,
2158 .base_baud = 1382400,
2159 .uart_offset = 8,
2160 },
2161 [pbn_b1_4_1382400] = {
2162 .flags = FL_BASE1,
2163 .num_ports = 4,
2164 .base_baud = 1382400,
2165 .uart_offset = 8,
2166 },
2167 [pbn_b1_8_1382400] = {
2168 .flags = FL_BASE1,
2169 .num_ports = 8,
2170 .base_baud = 1382400,
2171 .uart_offset = 8,
2172 },
2173
2174 [pbn_b2_1_115200] = {
2175 .flags = FL_BASE2,
2176 .num_ports = 1,
2177 .base_baud = 115200,
2178 .uart_offset = 8,
2179 },
737c1756
PH		 2180 [pbn_b2_2_115200] = {
2181 .flags = FL_BASE2,
2182 .num_ports = 2,
2183 .base_baud = 115200,
2184 .uart_offset = 8,
2185 },
a9cccd34
MF		 2186 [pbn_b2_4_115200] = {
2187 .flags = FL_BASE2,
2188 .num_ports = 4,
2189 .base_baud = 115200,
2190 .uart_offset = 8,
2191 },
1da177e4
LT		 2192 [pbn_b2_8_115200] = {
2193 .flags = FL_BASE2,
2194 .num_ports = 8,
2195 .base_baud = 115200,
2196 .uart_offset = 8,
2197 },
2198
2199 [pbn_b2_1_460800] = {
2200 .flags = FL_BASE2,
2201 .num_ports = 1,
2202 .base_baud = 460800,
2203 .uart_offset = 8,
2204 },
2205 [pbn_b2_4_460800] = {
2206 .flags = FL_BASE2,
2207 .num_ports = 4,
2208 .base_baud = 460800,
2209 .uart_offset = 8,
2210 },
2211 [pbn_b2_8_460800] = {
2212 .flags = FL_BASE2,
2213 .num_ports = 8,
2214 .base_baud = 460800,
2215 .uart_offset = 8,
2216 },
2217 [pbn_b2_16_460800] = {
2218 .flags = FL_BASE2,
2219 .num_ports = 16,
2220 .base_baud = 460800,
2221 .uart_offset = 8,
2222 },
2223
2224 [pbn_b2_1_921600] = {
2225 .flags = FL_BASE2,
2226 .num_ports = 1,
2227 .base_baud = 921600,
2228 .uart_offset = 8,
2229 },
2230 [pbn_b2_4_921600] = {
2231 .flags = FL_BASE2,
2232 .num_ports = 4,
2233 .base_baud = 921600,
2234 .uart_offset = 8,
2235 },
2236 [pbn_b2_8_921600] = {
2237 .flags = FL_BASE2,
2238 .num_ports = 8,
2239 .base_baud = 921600,
2240 .uart_offset = 8,
2241 },
2242
e847003f
LB		 2243 [pbn_b2_8_1152000] = {
2244 .flags = FL_BASE2,
2245 .num_ports = 8,
2246 .base_baud = 1152000,
2247 .uart_offset = 8,
2248 },
2249
1da177e4
LT		 2250 [pbn_b2_bt_1_115200] = {
2251 .flags = FL_BASE2|FL_BASE_BARS,
2252 .num_ports = 1,
2253 .base_baud = 115200,
2254 .uart_offset = 8,
2255 },
2256 [pbn_b2_bt_2_115200] = {
2257 .flags = FL_BASE2|FL_BASE_BARS,
2258 .num_ports = 2,
2259 .base_baud = 115200,
2260 .uart_offset = 8,
2261 },
2262 [pbn_b2_bt_4_115200] = {
2263 .flags = FL_BASE2|FL_BASE_BARS,
2264 .num_ports = 4,
2265 .base_baud = 115200,
2266 .uart_offset = 8,
2267 },
2268
2269 [pbn_b2_bt_2_921600] = {
2270 .flags = FL_BASE2|FL_BASE_BARS,
2271 .num_ports = 2,
2272 .base_baud = 921600,
2273 .uart_offset = 8,
2274 },
2275 [pbn_b2_bt_4_921600] = {
2276 .flags = FL_BASE2|FL_BASE_BARS,
2277 .num_ports = 4,
2278 .base_baud = 921600,
2279 .uart_offset = 8,
2280 },
2281
d9004eb4
ABL		 2282 [pbn_b3_2_115200] = {
2283 .flags = FL_BASE3,
2284 .num_ports = 2,
2285 .base_baud = 115200,
2286 .uart_offset = 8,
2287 },
1da177e4
LT		 2288 [pbn_b3_4_115200] = {
2289 .flags = FL_BASE3,
2290 .num_ports = 4,
2291 .base_baud = 115200,
2292 .uart_offset = 8,
2293 },
2294 [pbn_b3_8_115200] = {
2295 .flags = FL_BASE3,
2296 .num_ports = 8,
2297 .base_baud = 115200,
2298 .uart_offset = 8,
2299 },
2300
66169ad1
YY		 2301 [pbn_b4_bt_2_921600] = {
2302 .flags = FL_BASE4,
2303 .num_ports = 2,
2304 .base_baud = 921600,
2305 .uart_offset = 8,
2306 },
2307 [pbn_b4_bt_4_921600] = {
2308 .flags = FL_BASE4,
2309 .num_ports = 4,
2310 .base_baud = 921600,
2311 .uart_offset = 8,
2312 },
2313 [pbn_b4_bt_8_921600] = {
2314 .flags = FL_BASE4,
2315 .num_ports = 8,
2316 .base_baud = 921600,
2317 .uart_offset = 8,
2318 },
2319
1da177e4
LT		 2320 /*
2321 * Entries following this are board-specific.
2322 */
2323
2324 /*
2325 * Panacom - IOMEM
2326 */
2327 [pbn_panacom] = {
2328 .flags = FL_BASE2,
2329 .num_ports = 2,
2330 .base_baud = 921600,
2331 .uart_offset = 0x400,
2332 .reg_shift = 7,
2333 },
2334 [pbn_panacom2] = {
2335 .flags = FL_BASE2|FL_BASE_BARS,
2336 .num_ports = 2,
2337 .base_baud = 921600,
2338 .uart_offset = 0x400,
2339 .reg_shift = 7,
2340 },
2341 [pbn_panacom4] = {
2342 .flags = FL_BASE2|FL_BASE_BARS,
2343 .num_ports = 4,
2344 .base_baud = 921600,
2345 .uart_offset = 0x400,
2346 .reg_shift = 7,
2347 },
2348
add7b58e
BH		 2349 [pbn_exsys_4055] = {
2350 .flags = FL_BASE2,
2351 .num_ports = 4,
2352 .base_baud = 115200,
2353 .uart_offset = 8,
2354 },
2355
1da177e4
LT		 2356 /* I think this entry is broken - the first_offset looks wrong --rmk */
2357 [pbn_plx_romulus] = {
2358 .flags = FL_BASE2,
2359 .num_ports = 4,
2360 .base_baud = 921600,
2361 .uart_offset = 8 << 2,
2362 .reg_shift = 2,
2363 .first_offset = 0x03,
2364 },
2365
2366 /*
2367 * This board uses the size of PCI Base region 0 to
2368 * signal now many ports are available
2369 */
2370 [pbn_oxsemi] = {
2371 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2372 .num_ports = 32,
2373 .base_baud = 115200,
2374 .uart_offset = 8,
2375 },
7106b4e3
LH		 2376 [pbn_oxsemi_1_4000000] = {
2377 .flags = FL_BASE0,
2378 .num_ports = 1,
2379 .base_baud = 4000000,
2380 .uart_offset = 0x200,
2381 .first_offset = 0x1000,
2382 },
2383 [pbn_oxsemi_2_4000000] = {
2384 .flags = FL_BASE0,
2385 .num_ports = 2,
2386 .base_baud = 4000000,
2387 .uart_offset = 0x200,
2388 .first_offset = 0x1000,
2389 },
2390 [pbn_oxsemi_4_4000000] = {
2391 .flags = FL_BASE0,
2392 .num_ports = 4,
2393 .base_baud = 4000000,
2394 .uart_offset = 0x200,
2395 .first_offset = 0x1000,
2396 },
2397 [pbn_oxsemi_8_4000000] = {
2398 .flags = FL_BASE0,
2399 .num_ports = 8,
2400 .base_baud = 4000000,
2401 .uart_offset = 0x200,
2402 .first_offset = 0x1000,
2403 },
2404
1da177e4
LT		 2405
2406 /*
2407 * EKF addition for i960 Boards form EKF with serial port.
2408 * Max 256 ports.
2409 */
2410 [pbn_intel_i960] = {
2411 .flags = FL_BASE0,
2412 .num_ports = 32,
2413 .base_baud = 921600,
2414 .uart_offset = 8 << 2,
2415 .reg_shift = 2,
2416 .first_offset = 0x10000,
2417 },
2418 [pbn_sgi_ioc3] = {
2419 .flags = FL_BASE0|FL_NOIRQ,
2420 .num_ports = 1,
2421 .base_baud = 458333,
2422 .uart_offset = 8,
2423 .reg_shift = 0,
2424 .first_offset = 0x20178,
2425 },
2426
1da177e4
LT		 2427 /*
2428 * Computone - uses IOMEM.
2429 */
2430 [pbn_computone_4] = {
2431 .flags = FL_BASE0,
2432 .num_ports = 4,
2433 .base_baud = 921600,
2434 .uart_offset = 0x40,
2435 .reg_shift = 2,
2436 .first_offset = 0x200,
2437 },
2438 [pbn_computone_6] = {
2439 .flags = FL_BASE0,
2440 .num_ports = 6,
2441 .base_baud = 921600,
2442 .uart_offset = 0x40,
2443 .reg_shift = 2,
2444 .first_offset = 0x200,
2445 },
2446 [pbn_computone_8] = {
2447 .flags = FL_BASE0,
2448 .num_ports = 8,
2449 .base_baud = 921600,
2450 .uart_offset = 0x40,
2451 .reg_shift = 2,
2452 .first_offset = 0x200,
2453 },
2454 [pbn_sbsxrsio] = {
2455 .flags = FL_BASE0,
2456 .num_ports = 8,
2457 .base_baud = 460800,
2458 .uart_offset = 256,
2459 .reg_shift = 4,
2460 },
2461 /*
2462 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2463 * Only basic 16550A support.
2464 * XR17C15[24] are not tested, but they should work.
2465 */
2466 [pbn_exar_XR17C152] = {
2467 .flags = FL_BASE0,
2468 .num_ports = 2,
2469 .base_baud = 921600,
2470 .uart_offset = 0x200,
2471 },
2472 [pbn_exar_XR17C154] = {
2473 .flags = FL_BASE0,
2474 .num_ports = 4,
2475 .base_baud = 921600,
2476 .uart_offset = 0x200,
2477 },
2478 [pbn_exar_XR17C158] = {
2479 .flags = FL_BASE0,
2480 .num_ports = 8,
2481 .base_baud = 921600,
2482 .uart_offset = 0x200,
2483 },
c68d2b15
BH		 2484 [pbn_exar_ibm_saturn] = {
2485 .flags = FL_BASE0,
2486 .num_ports = 1,
2487 .base_baud = 921600,
2488 .uart_offset = 0x200,
2489 },
2490
aa798505
OJ		 2491 /*
2492 * PA Semi PWRficient PA6T-1682M on-chip UART
2493 */
2494 [pbn_pasemi_1682M] = {
2495 .flags = FL_BASE0,
2496 .num_ports = 1,
2497 .base_baud = 8333333,
2498 },
46a0fac9
SB		 2499 /*
2500 * National Instruments 843x
2501 */
2502 [pbn_ni8430_16] = {
2503 .flags = FL_BASE0,
2504 .num_ports = 16,
2505 .base_baud = 3686400,
2506 .uart_offset = 0x10,
2507 .first_offset = 0x800,
2508 },
2509 [pbn_ni8430_8] = {
2510 .flags = FL_BASE0,
2511 .num_ports = 8,
2512 .base_baud = 3686400,
2513 .uart_offset = 0x10,
2514 .first_offset = 0x800,
2515 },
2516 [pbn_ni8430_4] = {
2517 .flags = FL_BASE0,
2518 .num_ports = 4,
2519 .base_baud = 3686400,
2520 .uart_offset = 0x10,
2521 .first_offset = 0x800,
2522 },
2523 [pbn_ni8430_2] = {
2524 .flags = FL_BASE0,
2525 .num_ports = 2,
2526 .base_baud = 3686400,
2527 .uart_offset = 0x10,
2528 .first_offset = 0x800,
2529 },
1b62cbf2
KJ		 2530 /*
2531 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2532 */
2533 [pbn_ADDIDATA_PCIe_1_3906250] = {
2534 .flags = FL_BASE0,
2535 .num_ports = 1,
2536 .base_baud = 3906250,
2537 .uart_offset = 0x200,
2538 .first_offset = 0x1000,
2539 },
2540 [pbn_ADDIDATA_PCIe_2_3906250] = {
2541 .flags = FL_BASE0,
2542 .num_ports = 2,
2543 .base_baud = 3906250,
2544 .uart_offset = 0x200,
2545 .first_offset = 0x1000,
2546 },
2547 [pbn_ADDIDATA_PCIe_4_3906250] = {
2548 .flags = FL_BASE0,
2549 .num_ports = 4,
2550 .base_baud = 3906250,
2551 .uart_offset = 0x200,
2552 .first_offset = 0x1000,
2553 },
2554 [pbn_ADDIDATA_PCIe_8_3906250] = {
2555 .flags = FL_BASE0,
2556 .num_ports = 8,
2557 .base_baud = 3906250,
2558 .uart_offset = 0x200,
2559 .first_offset = 0x1000,
2560 },
095e24b0
DB		 2561 [pbn_ce4100_1_115200] = {
2562 .flags = FL_BASE0,
2563 .num_ports = 1,
2564 .base_baud = 921600,
2565 .reg_shift = 2,
2566 },
d9a0fbfd
AP		 2567 [pbn_omegapci] = {
2568 .flags = FL_BASE0,
2569 .num_ports = 8,
2570 .base_baud = 115200,
2571 .uart_offset = 0x200,
2572 },
7808edcd
NG		 2573 [pbn_NETMOS9900_2s_115200] = {
2574 .flags = FL_BASE0,
2575 .num_ports = 2,
2576 .base_baud = 115200,
2577 },
1da177e4
LT		 2578};
2579
436bbd43 2580static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 2581 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 2582 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2583 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
436bbd43
CS		 2584};
2585
1da177e4
LT		 2586/*
2587 * Given a complete unknown PCI device, try to use some heuristics to
2588 * guess what the configuration might be, based on the pitiful PCI
2589 * serial specs. Returns 0 on success, 1 on failure.
2590 */
2591static int __devinit
1c7c1fe5 2592serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2593{
436bbd43 2594 const struct pci_device_id *blacklist;
1da177e4 2595 int num_iomem, num_port, first_port = -1, i;
5756ee99 2596
1da177e4
LT		 2597 /*
2598 * If it is not a communications device or the programming
2599 * interface is greater than 6, give up.
2600 *
2601 * (Should we try to make guesses for multiport serial devices
5756ee99 2602 * later?)
1da177e4
LT		 2603 */
2604 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2605 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2606 (dev->class & 0xff) > 6)
2607 return -ENODEV;
2608
436bbd43
CS		 2609 /*
2610 * Do not access blacklisted devices that are known not to
2611 * feature serial ports.
2612 */
2613 for (blacklist = softmodem_blacklist;
2614 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2615 blacklist++) {
2616 if (dev->vendor == blacklist->vendor &&
2617 dev->device == blacklist->device)
2618 return -ENODEV;
2619 }
2620
1da177e4
LT		 2621 num_iomem = num_port = 0;
2622 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2623 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2624 num_port++;
2625 if (first_port == -1)
2626 first_port = i;
2627 }
2628 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2629 num_iomem++;
2630 }
2631
2632 /*
2633 * If there is 1 or 0 iomem regions, and exactly one port,
2634 * use it. We guess the number of ports based on the IO
2635 * region size.
2636 */
2637 if (num_iomem <= 1 && num_port == 1) {
2638 board->flags = first_port;
2639 board->num_ports = pci_resource_len(dev, first_port) / 8;
2640 return 0;
2641 }
2642
2643 /*
2644 * Now guess if we've got a board which indexes by BARs.
2645 * Each IO BAR should be 8 bytes, and they should follow
2646 * consecutively.
2647 */
2648 first_port = -1;
2649 num_port = 0;
2650 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2651 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2652 pci_resource_len(dev, i) == 8 &&
2653 (first_port == -1 || (first_port + num_port) == i)) {
2654 num_port++;
2655 if (first_port == -1)
2656 first_port = i;
2657 }
2658 }
2659
2660 if (num_port > 1) {
2661 board->flags = first_port | FL_BASE_BARS;
2662 board->num_ports = num_port;
2663 return 0;
2664 }
2665
2666 return -ENODEV;
2667}
2668
2669static inline int
975a1a7d
RK		 2670serial_pci_matches(const struct pciserial_board *board,
2671 const struct pciserial_board *guessed)
1da177e4
LT		 2672{
2673 return
2674 board->num_ports == guessed->num_ports &&
2675 board->base_baud == guessed->base_baud &&
2676 board->uart_offset == guessed->uart_offset &&
2677 board->reg_shift == guessed->reg_shift &&
2678 board->first_offset == guessed->first_offset;
2679}
2680
241fc436 2681struct serial_private *
975a1a7d 2682pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2683{
72ce9a83 2684 struct uart_port serial_port;
1da177e4 2685 struct serial_private *priv;
1da177e4
LT		 2686 struct pci_serial_quirk *quirk;
2687 int rc, nr_ports, i;
2688
1da177e4
LT		 2689 nr_ports = board->num_ports;
2690
2691 /*
2692 * Find an init and setup quirks.
2693 */
2694 quirk = find_quirk(dev);
2695
2696 /*
2697 * Run the new-style initialization function.
2698 * The initialization function returns:
2699 * <0 - error
2700 * 0 - use board->num_ports
2701 * >0 - number of ports
2702 */
2703 if (quirk->init) {
2704 rc = quirk->init(dev);
241fc436
RK		 2705 if (rc < 0) {
2706 priv = ERR_PTR(rc);
2707 goto err_out;
2708 }
1da177e4
LT		 2709 if (rc)
2710 nr_ports = rc;
2711 }
2712
8f31bb39 2713 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2714 sizeof(unsigned int) * nr_ports,
2715 GFP_KERNEL);
2716 if (!priv) {
241fc436
RK		 2717 priv = ERR_PTR(-ENOMEM);
2718 goto err_deinit;
1da177e4
LT		 2719 }
2720
70db3d91 2721 priv->dev = dev;
1da177e4 2722 priv->quirk = quirk;
1da177e4 2723
72ce9a83
RK		 2724 memset(&serial_port, 0, sizeof(struct uart_port));
2725 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2726 serial_port.uartclk = board->base_baud * 16;
2727 serial_port.irq = get_pci_irq(dev, board);
2728 serial_port.dev = &dev->dev;
2729
1da177e4 2730 for (i = 0; i < nr_ports; i++) {
70db3d91 2731 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 2732 break;
72ce9a83 2733
1da177e4 2734#ifdef SERIAL_DEBUG_PCI
80647b95 2735 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
1da177e4
LT		 2736 serial_port.iobase, serial_port.irq, serial_port.iotype);
2737#endif
5756ee99 2738
1da177e4
LT		 2739 priv->line[i] = serial8250_register_port(&serial_port);
2740 if (priv->line[i] < 0) {
2741 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2742 break;
2743 }
2744 }
1da177e4 2745 priv->nr = i;
241fc436 2746 return priv;
1da177e4 2747
5756ee99 2748err_deinit:
1da177e4
LT		 2749 if (quirk->exit)
2750 quirk->exit(dev);
5756ee99 2751err_out:
241fc436 2752 return priv;
1da177e4 2753}
241fc436 2754EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2755
241fc436 2756void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2757{
056a8763
RK		 2758 struct pci_serial_quirk *quirk;
2759 int i;
1da177e4 2760
056a8763
RK		 2761 for (i = 0; i < priv->nr; i++)
2762 serial8250_unregister_port(priv->line[i]);
1da177e4 2763
056a8763
RK		 2764 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2765 if (priv->remapped_bar[i])
2766 iounmap(priv->remapped_bar[i]);
2767 priv->remapped_bar[i] = NULL;
2768 }
1da177e4 2769
056a8763
RK		 2770 /*
2771 * Find the exit quirks.
2772 */
241fc436 2773 quirk = find_quirk(priv->dev);
056a8763 2774 if (quirk->exit)
241fc436
RK		 2775 quirk->exit(priv->dev);
2776
2777 kfree(priv);
2778}
2779EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2780
2781void pciserial_suspend_ports(struct serial_private *priv)
2782{
2783 int i;
2784
2785 for (i = 0; i < priv->nr; i++)
2786 if (priv->line[i] >= 0)
2787 serial8250_suspend_port(priv->line[i]);
2788}
2789EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2790
2791void pciserial_resume_ports(struct serial_private *priv)
2792{
2793 int i;
2794
2795 /*
2796 * Ensure that the board is correctly configured.
2797 */
2798 if (priv->quirk->init)
2799 priv->quirk->init(priv->dev);
2800
2801 for (i = 0; i < priv->nr; i++)
2802 if (priv->line[i] >= 0)
2803 serial8250_resume_port(priv->line[i]);
2804}
2805EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2806
2807/*
2808 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2809 * to the arrangement of serial ports on a PCI card.
2810 */
2811static int __devinit
2812pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2813{
5bf8f501 2814 struct pci_serial_quirk *quirk;
241fc436 2815 struct serial_private *priv;
975a1a7d
RK		 2816 const struct pciserial_board *board;
2817 struct pciserial_board tmp;
241fc436
RK		 2818 int rc;
2819
5bf8f501
FB		 2820 quirk = find_quirk(dev);
2821 if (quirk->probe) {
2822 rc = quirk->probe(dev);
2823 if (rc)
2824 return rc;
2825 }
2826
241fc436
RK		 2827 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2828 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2829 ent->driver_data);
2830 return -EINVAL;
2831 }
2832
2833 board = &pci_boards[ent->driver_data];
2834
2835 rc = pci_enable_device(dev);
2807190b 2836 pci_save_state(dev);
241fc436
RK		 2837 if (rc)
2838 return rc;
2839
2840 if (ent->driver_data == pbn_default) {
2841 /*
2842 * Use a copy of the pci_board entry for this;
2843 * avoid changing entries in the table.
2844 */
2845 memcpy(&tmp, board, sizeof(struct pciserial_board));
2846 board = &tmp;
2847
2848 /*
2849 * We matched one of our class entries. Try to
2850 * determine the parameters of this board.
2851 */
975a1a7d 2852 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2853 if (rc)
2854 goto disable;
2855 } else {
2856 /*
2857 * We matched an explicit entry. If we are able to
2858 * detect this boards settings with our heuristic,
2859 * then we no longer need this entry.
2860 */
2861 memcpy(&tmp, &pci_boards[pbn_default],
2862 sizeof(struct pciserial_board));
2863 rc = serial_pci_guess_board(dev, &tmp);
2864 if (rc == 0 && serial_pci_matches(board, &tmp))
2865 moan_device("Redundant entry in serial pci_table.",
2866 dev);
2867 }
2868
2869 priv = pciserial_init_ports(dev, board);
2870 if (!IS_ERR(priv)) {
2871 pci_set_drvdata(dev, priv);
2872 return 0;
2873 }
2874
2875 rc = PTR_ERR(priv);
1da177e4 2876
241fc436 2877 disable:
056a8763 2878 pci_disable_device(dev);
241fc436
RK		 2879 return rc;
2880}
1da177e4 2881
241fc436
RK		 2882static void __devexit pciserial_remove_one(struct pci_dev *dev)
2883{
2884 struct serial_private *priv = pci_get_drvdata(dev);
2885
2886 pci_set_drvdata(dev, NULL);
2887
2888 pciserial_remove_ports(priv);
2889
2890 pci_disable_device(dev);
1da177e4
LT		 2891}
2892
1d5e7996 2893#ifdef CONFIG_PM
1da177e4
LT		 2894static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2895{
2896 struct serial_private *priv = pci_get_drvdata(dev);
2897
241fc436
RK		 2898 if (priv)
2899 pciserial_suspend_ports(priv);
1da177e4 2900
1da177e4
LT		 2901 pci_save_state(dev);
2902 pci_set_power_state(dev, pci_choose_state(dev, state));
2903 return 0;
2904}
2905
2906static int pciserial_resume_one(struct pci_dev *dev)
2907{
ccb9d59e 2908 int err;
1da177e4
LT		 2909 struct serial_private *priv = pci_get_drvdata(dev);
2910
2911 pci_set_power_state(dev, PCI_D0);
2912 pci_restore_state(dev);
2913
2914 if (priv) {
1da177e4
LT		 2915 /*
2916 * The device may have been disabled. Re-enable it.
2917 */
ccb9d59e 2918 err = pci_enable_device(dev);
40836c48 2919 /* FIXME: We cannot simply error out here */
ccb9d59e 2920 if (err)
40836c48 2921 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2922 pciserial_resume_ports(priv);
1da177e4
LT		 2923 }
2924 return 0;
2925}
1d5e7996 2926#endif
1da177e4
LT		 2927
2928static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2929 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2930 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2931 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2932 pbn_b2_8_921600 },
1da177e4
LT		 2933 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2934 PCI_SUBVENDOR_ID_CONNECT_TECH,
2935 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2936 pbn_b1_8_1382400 },
2937 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2938 PCI_SUBVENDOR_ID_CONNECT_TECH,
2939 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2940 pbn_b1_4_1382400 },
2941 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2942 PCI_SUBVENDOR_ID_CONNECT_TECH,
2943 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2944 pbn_b1_2_1382400 },
2945 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2946 PCI_SUBVENDOR_ID_CONNECT_TECH,
2947 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2948 pbn_b1_8_1382400 },
2949 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2950 PCI_SUBVENDOR_ID_CONNECT_TECH,
2951 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2952 pbn_b1_4_1382400 },
2953 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2954 PCI_SUBVENDOR_ID_CONNECT_TECH,
2955 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2956 pbn_b1_2_1382400 },
2957 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2958 PCI_SUBVENDOR_ID_CONNECT_TECH,
2959 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2960 pbn_b1_8_921600 },
2961 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2962 PCI_SUBVENDOR_ID_CONNECT_TECH,
2963 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2964 pbn_b1_8_921600 },
2965 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2966 PCI_SUBVENDOR_ID_CONNECT_TECH,
2967 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2968 pbn_b1_4_921600 },
2969 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2970 PCI_SUBVENDOR_ID_CONNECT_TECH,
2971 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2972 pbn_b1_4_921600 },
2973 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2974 PCI_SUBVENDOR_ID_CONNECT_TECH,
2975 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2976 pbn_b1_2_921600 },
2977 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2978 PCI_SUBVENDOR_ID_CONNECT_TECH,
2979 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2980 pbn_b1_8_921600 },
2981 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2982 PCI_SUBVENDOR_ID_CONNECT_TECH,
2983 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2984 pbn_b1_8_921600 },
2985 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2986 PCI_SUBVENDOR_ID_CONNECT_TECH,
2987 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2988 pbn_b1_4_921600 },
26e92861
GH		 2989 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2990 PCI_SUBVENDOR_ID_CONNECT_TECH,
2991 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2992 pbn_b1_2_1250000 },
2993 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2994 PCI_SUBVENDOR_ID_CONNECT_TECH,
2995 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2996 pbn_b0_2_1843200 },
2997 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2998 PCI_SUBVENDOR_ID_CONNECT_TECH,
2999 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3000 pbn_b0_4_1843200 },
85d1494e
YY		 3001 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3002 PCI_VENDOR_ID_AFAVLAB,
3003 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3004 pbn_b0_4_1152000 },
26e92861
GH		 3005 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3006 PCI_SUBVENDOR_ID_CONNECT_TECH,
3007 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3008 pbn_b0_2_1843200_200 },
3009 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3010 PCI_SUBVENDOR_ID_CONNECT_TECH,
3011 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3012 pbn_b0_4_1843200_200 },
3013 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3014 PCI_SUBVENDOR_ID_CONNECT_TECH,
3015 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3016 pbn_b0_8_1843200_200 },
3017 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3018 PCI_SUBVENDOR_ID_CONNECT_TECH,
3019 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3020 pbn_b0_2_1843200_200 },
3021 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3022 PCI_SUBVENDOR_ID_CONNECT_TECH,
3023 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3024 pbn_b0_4_1843200_200 },
3025 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3026 PCI_SUBVENDOR_ID_CONNECT_TECH,
3027 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3028 pbn_b0_8_1843200_200 },
3029 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3030 PCI_SUBVENDOR_ID_CONNECT_TECH,
3031 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3032 pbn_b0_2_1843200_200 },
3033 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3034 PCI_SUBVENDOR_ID_CONNECT_TECH,
3035 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3036 pbn_b0_4_1843200_200 },
3037 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3038 PCI_SUBVENDOR_ID_CONNECT_TECH,
3039 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3040 pbn_b0_8_1843200_200 },
3041 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3042 PCI_SUBVENDOR_ID_CONNECT_TECH,
3043 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3044 pbn_b0_2_1843200_200 },
3045 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3046 PCI_SUBVENDOR_ID_CONNECT_TECH,
3047 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3048 pbn_b0_4_1843200_200 },
3049 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3050 PCI_SUBVENDOR_ID_CONNECT_TECH,
3051 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3052 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3053 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3054 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3055 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3056
3057 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3059 pbn_b2_bt_1_115200 },
3060 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3062 pbn_b2_bt_2_115200 },
3063 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3065 pbn_b2_bt_4_115200 },
3066 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3068 pbn_b2_bt_2_115200 },
3069 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3071 pbn_b2_bt_4_115200 },
3072 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3074 pbn_b2_8_115200 },
e65f0f82
FL		 3075 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3077 pbn_b2_8_460800 },
1da177e4
LT		 3078 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3080 pbn_b2_8_115200 },
3081
3082 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3084 pbn_b2_bt_2_115200 },
3085 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3087 pbn_b2_bt_2_921600 },
3088 /*
3089 * VScom SPCOM800, from sl@s.pl
3090 */
5756ee99
AC		 3091 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3093 pbn_b2_8_921600 },
3094 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 3095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3096 pbn_b2_4_921600 },
b76c5a07
CB		 3097 /* Unknown card - subdevice 0x1584 */
3098 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3099 PCI_VENDOR_ID_PLX,
3100 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3101 pbn_b0_4_115200 },
1da177e4
LT		 3102 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3103 PCI_SUBVENDOR_ID_KEYSPAN,
3104 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3105 pbn_panacom },
3106 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3108 pbn_panacom4 },
3109 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3111 pbn_panacom2 },
a9cccd34
MF		 3112 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3113 PCI_VENDOR_ID_ESDGMBH,
3114 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3115 pbn_b2_4_115200 },
1da177e4
LT		 3116 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3117 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3118 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 3119 pbn_b2_4_460800 },
3120 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3121 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3122 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 3123 pbn_b2_8_460800 },
3124 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3125 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3126 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 3127 pbn_b2_16_460800 },
3128 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3129 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3130 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 3131 pbn_b2_16_460800 },
3132 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3133 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3134 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 3135 pbn_b2_4_460800 },
3136 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3137 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3138 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 3139 pbn_b2_8_460800 },
add7b58e
BH		 3140 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3141 PCI_SUBVENDOR_ID_EXSYS,
3142 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3143 pbn_exsys_4055 },
1da177e4
LT		 3144 /*
3145 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3146 * (Exoray@isys.ca)
3147 */
3148 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3149 0x10b5, 0x106a, 0, 0,
3150 pbn_plx_romulus },
3151 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3153 pbn_b1_4_115200 },
3154 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3156 pbn_b1_2_115200 },
3157 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3159 pbn_b1_8_115200 },
3160 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3162 pbn_b1_8_115200 },
3163 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3164 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3165 0, 0,
1da177e4 3166 pbn_b0_4_921600 },
fbc0dc0d 3167 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3168 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3169 0, 0,
fbc0dc0d 3170 pbn_b0_4_1152000 },
c9bd9d01
MP		 3171 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3173 pbn_b0_bt_2_921600 },
db1de159
DR		 3174
3175 /*
3176 * The below card is a little controversial since it is the
3177 * subject of a PCI vendor/device ID clash. (See
3178 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3179 * For now just used the hex ID 0x950a.
3180 */
39aced68
NV		 3181 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3182 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3183 pbn_b0_2_115200 },
db1de159
DR		 3184 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3186 pbn_b0_2_1130000 },
70fd8fde
AP		 3187 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3188 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3189 pbn_b0_1_921600 },
1da177e4
LT		 3190 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3192 pbn_b0_4_115200 },
3193 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3195 pbn_b0_bt_2_921600 },
e847003f
LB		 3196 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3197 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3198 pbn_b2_8_1152000 },
1da177e4 3199
7106b4e3
LH		 3200 /*
3201 * Oxford Semiconductor Inc. Tornado PCI express device range.
3202 */
3203 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3205 pbn_b0_1_4000000 },
3206 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208 pbn_b0_1_4000000 },
3209 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3211 pbn_oxsemi_1_4000000 },
3212 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214 pbn_oxsemi_1_4000000 },
3215 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217 pbn_b0_1_4000000 },
3218 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220 pbn_b0_1_4000000 },
3221 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223 pbn_oxsemi_1_4000000 },
3224 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3226 pbn_oxsemi_1_4000000 },
3227 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3229 pbn_b0_1_4000000 },
3230 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3232 pbn_b0_1_4000000 },
3233 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3235 pbn_b0_1_4000000 },
3236 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3238 pbn_b0_1_4000000 },
3239 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241 pbn_oxsemi_2_4000000 },
3242 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244 pbn_oxsemi_2_4000000 },
3245 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3247 pbn_oxsemi_4_4000000 },
3248 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250 pbn_oxsemi_4_4000000 },
3251 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3253 pbn_oxsemi_8_4000000 },
3254 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3256 pbn_oxsemi_8_4000000 },
3257 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259 pbn_oxsemi_1_4000000 },
3260 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262 pbn_oxsemi_1_4000000 },
3263 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265 pbn_oxsemi_1_4000000 },
3266 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3268 pbn_oxsemi_1_4000000 },
3269 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271 pbn_oxsemi_1_4000000 },
3272 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274 pbn_oxsemi_1_4000000 },
3275 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3277 pbn_oxsemi_1_4000000 },
3278 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3280 pbn_oxsemi_1_4000000 },
3281 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3283 pbn_oxsemi_1_4000000 },
3284 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3286 pbn_oxsemi_1_4000000 },
3287 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3289 pbn_oxsemi_1_4000000 },
3290 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3292 pbn_oxsemi_1_4000000 },
3293 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3295 pbn_oxsemi_1_4000000 },
3296 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298 pbn_oxsemi_1_4000000 },
3299 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3301 pbn_oxsemi_1_4000000 },
3302 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3304 pbn_oxsemi_1_4000000 },
3305 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307 pbn_oxsemi_1_4000000 },
3308 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3310 pbn_oxsemi_1_4000000 },
3311 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3313 pbn_oxsemi_1_4000000 },
3314 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3316 pbn_oxsemi_1_4000000 },
3317 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3319 pbn_oxsemi_1_4000000 },
3320 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3322 pbn_oxsemi_1_4000000 },
3323 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3325 pbn_oxsemi_1_4000000 },
3326 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328 pbn_oxsemi_1_4000000 },
3329 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3331 pbn_oxsemi_1_4000000 },
3332 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334 pbn_oxsemi_1_4000000 },
b80de369
LH		 3335 /*
3336 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3337 */
3338 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3339 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3340 pbn_oxsemi_1_4000000 },
3341 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3342 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3343 pbn_oxsemi_2_4000000 },
3344 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3345 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3346 pbn_oxsemi_4_4000000 },
3347 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3348 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3349 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 3350
3351 /*
3352 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3353 */
3354 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3355 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3356 pbn_oxsemi_2_4000000 },
3357
1da177e4
LT		 3358 /*
3359 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3360 * from skokodyn@yahoo.com
3361 */
3362 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3363 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3364 pbn_sbsxrsio },
3365 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3366 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3367 pbn_sbsxrsio },
3368 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3369 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3370 pbn_sbsxrsio },
3371 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3372 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3373 pbn_sbsxrsio },
3374
3375 /*
3376 * Digitan DS560-558, from jimd@esoft.com
3377 */
3378 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 3379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3380 pbn_b1_1_115200 },
3381
3382 /*
3383 * Titan Electronic cards
3384 * The 400L and 800L have a custom setup quirk.
3385 */
3386 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 3387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3388 pbn_b0_1_921600 },
3389 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 3390 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3391 pbn_b0_2_921600 },
3392 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 3393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3394 pbn_b0_4_921600 },
3395 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 3396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3397 pbn_b0_4_921600 },
3398 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3400 pbn_b1_1_921600 },
3401 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3403 pbn_b1_bt_2_921600 },
3404 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3406 pbn_b0_bt_4_921600 },
3407 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3409 pbn_b0_bt_8_921600 },
66169ad1
YY		 3410 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3412 pbn_b4_bt_2_921600 },
3413 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3415 pbn_b4_bt_4_921600 },
3416 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3418 pbn_b4_bt_8_921600 },
3419 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3421 pbn_b0_4_921600 },
3422 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3424 pbn_b0_4_921600 },
3425 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3427 pbn_b0_4_921600 },
3428 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3430 pbn_oxsemi_1_4000000 },
3431 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3433 pbn_oxsemi_2_4000000 },
3434 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436 pbn_oxsemi_4_4000000 },
3437 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3439 pbn_oxsemi_8_4000000 },
3440 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3442 pbn_oxsemi_2_4000000 },
3443 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3445 pbn_oxsemi_2_4000000 },
1da177e4
LT		 3446
3447 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449 pbn_b2_1_460800 },
3450 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452 pbn_b2_1_460800 },
3453 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455 pbn_b2_1_460800 },
3456 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458 pbn_b2_bt_2_921600 },
3459 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461 pbn_b2_bt_2_921600 },
3462 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464 pbn_b2_bt_2_921600 },
3465 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3467 pbn_b2_bt_4_921600 },
3468 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3470 pbn_b2_bt_4_921600 },
3471 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3473 pbn_b2_bt_4_921600 },
3474 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3476 pbn_b0_1_921600 },
3477 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3479 pbn_b0_1_921600 },
3480 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3482 pbn_b0_1_921600 },
3483 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3485 pbn_b0_bt_2_921600 },
3486 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3488 pbn_b0_bt_2_921600 },
3489 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3491 pbn_b0_bt_2_921600 },
3492 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3494 pbn_b0_bt_4_921600 },
3495 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3497 pbn_b0_bt_4_921600 },
3498 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3500 pbn_b0_bt_4_921600 },
3ec9c594
AP		 3501 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3503 pbn_b0_bt_8_921600 },
3504 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3506 pbn_b0_bt_8_921600 },
3507 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3509 pbn_b0_bt_8_921600 },
1da177e4
LT		 3510
3511 /*
3512 * Computone devices submitted by Doug McNash dmcnash@computone.com
3513 */
3514 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3515 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3516 0, 0, pbn_computone_4 },
3517 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3518 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3519 0, 0, pbn_computone_8 },
3520 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3521 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3522 0, 0, pbn_computone_6 },
3523
3524 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3526 pbn_oxsemi },
3527 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3528 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3529 pbn_b0_bt_1_921600 },
3530
3531 /*
3532 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3533 */
3534 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3536 pbn_b0_bt_8_115200 },
3537 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3539 pbn_b0_bt_8_115200 },
3540
3541 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3543 pbn_b0_bt_2_115200 },
3544 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3546 pbn_b0_bt_2_115200 },
3547 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3549 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 3550 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3552 pbn_b0_bt_2_115200 },
3553 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3555 pbn_b0_bt_2_115200 },
1da177e4
LT		 3556 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3557 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3558 pbn_b0_bt_4_460800 },
3559 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3560 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3561 pbn_b0_bt_4_460800 },
3562 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3563 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3564 pbn_b0_bt_2_460800 },
3565 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3567 pbn_b0_bt_2_460800 },
3568 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3570 pbn_b0_bt_2_460800 },
3571 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3573 pbn_b0_bt_1_115200 },
3574 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3576 pbn_b0_bt_1_460800 },
3577
1fb8cacc
RK		 3578 /*
3579 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3580 * Cards are identified by their subsystem vendor IDs, which
3581 * (in hex) match the model number.
3582 *
3583 * Note that JC140x are RS422/485 cards which require ox950
3584 * ACR = 0x10, and as such are not currently fully supported.
3585 */
3586 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3587 0x1204, 0x0004, 0, 0,
3588 pbn_b0_4_921600 },
3589 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3590 0x1208, 0x0004, 0, 0,
3591 pbn_b0_4_921600 },
3592/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3593 0x1402, 0x0002, 0, 0,
3594 pbn_b0_2_921600 }, */
3595/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3596 0x1404, 0x0004, 0, 0,
3597 pbn_b0_4_921600 }, */
3598 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3599 0x1208, 0x0004, 0, 0,
3600 pbn_b0_4_921600 },
3601
2a52fcb5
KY		 3602 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3603 0x1204, 0x0004, 0, 0,
3604 pbn_b0_4_921600 },
3605 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3606 0x1208, 0x0004, 0, 0,
3607 pbn_b0_4_921600 },
3608 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3609 0x1208, 0x0004, 0, 0,
3610 pbn_b0_4_921600 },
1da177e4
LT		 3611 /*
3612 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3613 */
3614 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616 pbn_b1_1_1382400 },
3617
3618 /*
3619 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3620 */
3621 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3623 pbn_b1_1_1382400 },
3624
3625 /*
3626 * RAStel 2 port modem, gerg@moreton.com.au
3627 */
3628 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3630 pbn_b2_bt_2_115200 },
3631
3632 /*
3633 * EKF addition for i960 Boards form EKF with serial port
3634 */
3635 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3636 0xE4BF, PCI_ANY_ID, 0, 0,
3637 pbn_intel_i960 },
3638
3639 /*
3640 * Xircom Cardbus/Ethernet combos
3641 */
3642 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3644 pbn_b0_1_115200 },
3645 /*
3646 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3647 */
3648 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3650 pbn_b0_1_115200 },
3651
3652 /*
3653 * Untested PCI modems, sent in from various folks...
3654 */
3655
3656 /*
3657 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3658 */
3659 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3660 0x1048, 0x1500, 0, 0,
3661 pbn_b1_1_115200 },
3662
3663 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3664 0xFF00, 0, 0, 0,
3665 pbn_sgi_ioc3 },
3666
3667 /*
3668 * HP Diva card
3669 */
3670 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3671 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3672 pbn_b1_1_115200 },
3673 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3675 pbn_b0_5_115200 },
3676 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3678 pbn_b2_1_115200 },
3679
d9004eb4
ABL		 3680 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3682 pbn_b3_2_115200 },
1da177e4
LT		 3683 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3685 pbn_b3_4_115200 },
3686 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3688 pbn_b3_8_115200 },
3689
3690 /*
3691 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3692 */
3693 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3694 PCI_ANY_ID, PCI_ANY_ID,
3695 0,
3696 0, pbn_exar_XR17C152 },
3697 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3698 PCI_ANY_ID, PCI_ANY_ID,
3699 0,
3700 0, pbn_exar_XR17C154 },
3701 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3702 PCI_ANY_ID, PCI_ANY_ID,
3703 0,
3704 0, pbn_exar_XR17C158 },
3705
3706 /*
3707 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3708 */
3709 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3711 pbn_b0_1_115200 },
84f8c6fc
NV		 3712 /*
3713 * ITE
3714 */
3715 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3716 PCI_ANY_ID, PCI_ANY_ID,
3717 0, 0,
3718 pbn_b1_bt_1_115200 },
1da177e4 3719
737c1756
PH		 3720 /*
3721 * IntaShield IS-200
3722 */
3723 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3725 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3726 /*
3727 * IntaShield IS-400
3728 */
3729 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3731 pbn_b2_4_115200 },
48212008
TH		 3732 /*
3733 * Perle PCI-RAS cards
3734 */
3735 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3736 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3737 0, 0, pbn_b2_4_921600 },
3738 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3739 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3740 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3741
3742 /*
3743 * Mainpine series cards: Fairly standard layout but fools
3744 * parts of the autodetect in some cases and uses otherwise
3745 * unmatched communications subclasses in the PCI Express case
3746 */
3747
3748 { /* RockForceDUO */
3749 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3750 PCI_VENDOR_ID_MAINPINE, 0x0200,
3751 0, 0, pbn_b0_2_115200 },
3752 { /* RockForceQUATRO */
3753 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3754 PCI_VENDOR_ID_MAINPINE, 0x0300,
3755 0, 0, pbn_b0_4_115200 },
3756 { /* RockForceDUO+ */
3757 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3758 PCI_VENDOR_ID_MAINPINE, 0x0400,
3759 0, 0, pbn_b0_2_115200 },
3760 { /* RockForceQUATRO+ */
3761 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3762 PCI_VENDOR_ID_MAINPINE, 0x0500,
3763 0, 0, pbn_b0_4_115200 },
3764 { /* RockForce+ */
3765 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3766 PCI_VENDOR_ID_MAINPINE, 0x0600,
3767 0, 0, pbn_b0_2_115200 },
3768 { /* RockForce+ */
3769 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3770 PCI_VENDOR_ID_MAINPINE, 0x0700,
3771 0, 0, pbn_b0_4_115200 },
3772 { /* RockForceOCTO+ */
3773 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3774 PCI_VENDOR_ID_MAINPINE, 0x0800,
3775 0, 0, pbn_b0_8_115200 },
3776 { /* RockForceDUO+ */
3777 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3778 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3779 0, 0, pbn_b0_2_115200 },
3780 { /* RockForceQUARTRO+ */
3781 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3782 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3783 0, 0, pbn_b0_4_115200 },
3784 { /* RockForceOCTO+ */
3785 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3786 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3787 0, 0, pbn_b0_8_115200 },
3788 { /* RockForceD1 */
3789 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3790 PCI_VENDOR_ID_MAINPINE, 0x2000,
3791 0, 0, pbn_b0_1_115200 },
3792 { /* RockForceF1 */
3793 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3794 PCI_VENDOR_ID_MAINPINE, 0x2100,
3795 0, 0, pbn_b0_1_115200 },
3796 { /* RockForceD2 */
3797 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3798 PCI_VENDOR_ID_MAINPINE, 0x2200,
3799 0, 0, pbn_b0_2_115200 },
3800 { /* RockForceF2 */
3801 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3802 PCI_VENDOR_ID_MAINPINE, 0x2300,
3803 0, 0, pbn_b0_2_115200 },
3804 { /* RockForceD4 */
3805 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3806 PCI_VENDOR_ID_MAINPINE, 0x2400,
3807 0, 0, pbn_b0_4_115200 },
3808 { /* RockForceF4 */
3809 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3810 PCI_VENDOR_ID_MAINPINE, 0x2500,
3811 0, 0, pbn_b0_4_115200 },
3812 { /* RockForceD8 */
3813 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3814 PCI_VENDOR_ID_MAINPINE, 0x2600,
3815 0, 0, pbn_b0_8_115200 },
3816 { /* RockForceF8 */
3817 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3818 PCI_VENDOR_ID_MAINPINE, 0x2700,
3819 0, 0, pbn_b0_8_115200 },
3820 { /* IQ Express D1 */
3821 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3822 PCI_VENDOR_ID_MAINPINE, 0x3000,
3823 0, 0, pbn_b0_1_115200 },
3824 { /* IQ Express F1 */
3825 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3826 PCI_VENDOR_ID_MAINPINE, 0x3100,
3827 0, 0, pbn_b0_1_115200 },
3828 { /* IQ Express D2 */
3829 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3830 PCI_VENDOR_ID_MAINPINE, 0x3200,
3831 0, 0, pbn_b0_2_115200 },
3832 { /* IQ Express F2 */
3833 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3834 PCI_VENDOR_ID_MAINPINE, 0x3300,
3835 0, 0, pbn_b0_2_115200 },
3836 { /* IQ Express D4 */
3837 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3838 PCI_VENDOR_ID_MAINPINE, 0x3400,
3839 0, 0, pbn_b0_4_115200 },
3840 { /* IQ Express F4 */
3841 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3842 PCI_VENDOR_ID_MAINPINE, 0x3500,
3843 0, 0, pbn_b0_4_115200 },
3844 { /* IQ Express D8 */
3845 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3846 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3847 0, 0, pbn_b0_8_115200 },
3848 { /* IQ Express F8 */
3849 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3850 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3851 0, 0, pbn_b0_8_115200 },
3852
3853
aa798505
OJ		 3854 /*
3855 * PA Semi PA6T-1682M on-chip UART
3856 */
3857 { PCI_VENDOR_ID_PASEMI, 0xa004,
3858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3859 pbn_pasemi_1682M },
3860
46a0fac9
SB		 3861 /*
3862 * National Instruments
3863 */
04bf7e74
WP		 3864 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3866 pbn_b1_16_115200 },
3867 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3868 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3869 pbn_b1_8_115200 },
3870 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3872 pbn_b1_bt_4_115200 },
3873 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3875 pbn_b1_bt_2_115200 },
3876 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3878 pbn_b1_bt_4_115200 },
3879 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3881 pbn_b1_bt_2_115200 },
3882 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3884 pbn_b1_16_115200 },
3885 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3887 pbn_b1_8_115200 },
3888 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3890 pbn_b1_bt_4_115200 },
3891 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3893 pbn_b1_bt_2_115200 },
3894 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3896 pbn_b1_bt_4_115200 },
3897 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3899 pbn_b1_bt_2_115200 },
46a0fac9
SB		 3900 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3902 pbn_ni8430_2 },
3903 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3905 pbn_ni8430_2 },
3906 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3908 pbn_ni8430_4 },
3909 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3911 pbn_ni8430_4 },
3912 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3914 pbn_ni8430_8 },
3915 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3917 pbn_ni8430_8 },
3918 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3920 pbn_ni8430_16 },
3921 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3923 pbn_ni8430_16 },
3924 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3926 pbn_ni8430_2 },
3927 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3929 pbn_ni8430_2 },
3930 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3932 pbn_ni8430_4 },
3933 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3935 pbn_ni8430_4 },
3936
02c9b5cf
KJ		 3937 /*
3938 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3939 */
3940 { PCI_VENDOR_ID_ADDIDATA,
3941 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3942 PCI_ANY_ID,
3943 PCI_ANY_ID,
3944 0,
3945 0,
3946 pbn_b0_4_115200 },
3947
3948 { PCI_VENDOR_ID_ADDIDATA,
3949 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3950 PCI_ANY_ID,
3951 PCI_ANY_ID,
3952 0,
3953 0,
3954 pbn_b0_2_115200 },
3955
3956 { PCI_VENDOR_ID_ADDIDATA,
3957 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3958 PCI_ANY_ID,
3959 PCI_ANY_ID,
3960 0,
3961 0,
3962 pbn_b0_1_115200 },
3963
3964 { PCI_VENDOR_ID_ADDIDATA_OLD,
3965 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3966 PCI_ANY_ID,
3967 PCI_ANY_ID,
3968 0,
3969 0,
3970 pbn_b1_8_115200 },
3971
3972 { PCI_VENDOR_ID_ADDIDATA,
3973 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3974 PCI_ANY_ID,
3975 PCI_ANY_ID,
3976 0,
3977 0,
3978 pbn_b0_4_115200 },
3979
3980 { PCI_VENDOR_ID_ADDIDATA,
3981 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3982 PCI_ANY_ID,
3983 PCI_ANY_ID,
3984 0,
3985 0,
3986 pbn_b0_2_115200 },
3987
3988 { PCI_VENDOR_ID_ADDIDATA,
3989 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3990 PCI_ANY_ID,
3991 PCI_ANY_ID,
3992 0,
3993 0,
3994 pbn_b0_1_115200 },
3995
3996 { PCI_VENDOR_ID_ADDIDATA,
3997 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3998 PCI_ANY_ID,
3999 PCI_ANY_ID,
4000 0,
4001 0,
4002 pbn_b0_4_115200 },
4003
4004 { PCI_VENDOR_ID_ADDIDATA,
4005 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4006 PCI_ANY_ID,
4007 PCI_ANY_ID,
4008 0,
4009 0,
4010 pbn_b0_2_115200 },
4011
4012 { PCI_VENDOR_ID_ADDIDATA,
4013 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4014 PCI_ANY_ID,
4015 PCI_ANY_ID,
4016 0,
4017 0,
4018 pbn_b0_1_115200 },
4019
4020 { PCI_VENDOR_ID_ADDIDATA,
4021 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4022 PCI_ANY_ID,
4023 PCI_ANY_ID,
4024 0,
4025 0,
4026 pbn_b0_8_115200 },
4027
1b62cbf2
KJ		 4028 { PCI_VENDOR_ID_ADDIDATA,
4029 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4030 PCI_ANY_ID,
4031 PCI_ANY_ID,
4032 0,
4033 0,
4034 pbn_ADDIDATA_PCIe_4_3906250 },
4035
4036 { PCI_VENDOR_ID_ADDIDATA,
4037 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4038 PCI_ANY_ID,
4039 PCI_ANY_ID,
4040 0,
4041 0,
4042 pbn_ADDIDATA_PCIe_2_3906250 },
4043
4044 { PCI_VENDOR_ID_ADDIDATA,
4045 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4046 PCI_ANY_ID,
4047 PCI_ANY_ID,
4048 0,
4049 0,
4050 pbn_ADDIDATA_PCIe_1_3906250 },
4051
4052 { PCI_VENDOR_ID_ADDIDATA,
4053 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4054 PCI_ANY_ID,
4055 PCI_ANY_ID,
4056 0,
4057 0,
4058 pbn_ADDIDATA_PCIe_8_3906250 },
4059
25cf9bc1
JS		 4060 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4061 PCI_VENDOR_ID_IBM, 0x0299,
4062 0, 0, pbn_b0_bt_2_115200 },
4063
c4285b47
MB		 4064 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4065 0xA000, 0x1000,
4066 0, 0, pbn_b0_1_115200 },
4067
7808edcd
NG		 4068 /* the 9901 is a rebranded 9912 */
4069 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4070 0xA000, 0x1000,
4071 0, 0, pbn_b0_1_115200 },
4072
4073 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4074 0xA000, 0x1000,
4075 0, 0, pbn_b0_1_115200 },
4076
4077 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4078 0xA000, 0x1000,
4079 0, 0, pbn_b0_1_115200 },
4080
4081 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4082 0xA000, 0x1000,
4083 0, 0, pbn_b0_1_115200 },
4084
4085 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4086 0xA000, 0x3002,
4087 0, 0, pbn_NETMOS9900_2s_115200 },
4088
ac6ec5b1 4089 /*
44178176 4090 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 4091 */
4092
4093 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4094 0xA000, 0x1000,
4095 0, 0, pbn_b0_1_115200 },
4096
44178176
ES		 4097 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4098 0xA000, 0x3002,
4099 0, 0, pbn_b0_bt_2_115200 },
4100
ac6ec5b1
IS		 4101 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4102 0xA000, 0x3004,
4103 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 4104 /* Intel CE4100 */
4105 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4107 pbn_ce4100_1_115200 },
4108
d9a0fbfd
AP		 4109 /*
4110 * Cronyx Omega PCI
4111 */
4112 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4114 pbn_omegapci },
ac6ec5b1 4115
1da177e4
LT		 4116 /*
4117 * These entries match devices with class COMMUNICATION_SERIAL,
4118 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4119 */
4120 { PCI_ANY_ID, PCI_ANY_ID,
4121 PCI_ANY_ID, PCI_ANY_ID,
4122 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4123 0xffff00, pbn_default },
4124 { PCI_ANY_ID, PCI_ANY_ID,
4125 PCI_ANY_ID, PCI_ANY_ID,
4126 PCI_CLASS_COMMUNICATION_MODEM << 8,
4127 0xffff00, pbn_default },
4128 { PCI_ANY_ID, PCI_ANY_ID,
4129 PCI_ANY_ID, PCI_ANY_ID,
4130 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4131 0xffff00, pbn_default },
4132 { 0, }
4133};
4134
2807190b
MR		 4135static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4136 pci_channel_state_t state)
4137{
4138 struct serial_private *priv = pci_get_drvdata(dev);
4139
4140 if (state == pci_channel_io_perm_failure)
4141 return PCI_ERS_RESULT_DISCONNECT;
4142
4143 if (priv)
4144 pciserial_suspend_ports(priv);
4145
4146 pci_disable_device(dev);
4147
4148 return PCI_ERS_RESULT_NEED_RESET;
4149}
4150
4151static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4152{
4153 int rc;
4154
4155 rc = pci_enable_device(dev);
4156
4157 if (rc)
4158 return PCI_ERS_RESULT_DISCONNECT;
4159
4160 pci_restore_state(dev);
4161 pci_save_state(dev);
4162
4163 return PCI_ERS_RESULT_RECOVERED;
4164}
4165
4166static void serial8250_io_resume(struct pci_dev *dev)
4167{
4168 struct serial_private *priv = pci_get_drvdata(dev);
4169
4170 if (priv)
4171 pciserial_resume_ports(priv);
4172}
4173
4174static struct pci_error_handlers serial8250_err_handler = {
4175 .error_detected = serial8250_io_error_detected,
4176 .slot_reset = serial8250_io_slot_reset,
4177 .resume = serial8250_io_resume,
4178};
4179
1da177e4
LT		 4180static struct pci_driver serial_pci_driver = {
4181 .name = "serial",
4182 .probe = pciserial_init_one,
4183 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 4184#ifdef CONFIG_PM
1da177e4
LT		 4185 .suspend = pciserial_suspend_one,
4186 .resume = pciserial_resume_one,
1d5e7996 4187#endif
1da177e4 4188 .id_table = serial_pci_tbl,
2807190b 4189 .err_handler = &serial8250_err_handler,
1da177e4
LT		 4190};
4191
4192static int __init serial8250_pci_init(void)
4193{
4194 return pci_register_driver(&serial_pci_driver);
4195}
4196
4197static void __exit serial8250_pci_exit(void)
4198{
4199 pci_unregister_driver(&serial_pci_driver);
4200}
4201
4202module_init(serial8250_pci_init);
4203module_exit(serial8250_pci_exit);
4204
4205MODULE_LICENSE("GPL");
4206MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4207MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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