Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 LT |
31 | |
32 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
33 | #define SUPPORT_SYSRQ | |
34 | #endif | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/ioport.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/console.h> | |
40 | #include <linux/sysrq.h> | |
41 | #include <linux/device.h> | |
42 | #include <linux/tty.h> | |
43 | #include <linux/tty_flip.h> | |
44 | #include <linux/serial_core.h> | |
45 | #include <linux/serial.h> | |
a62c80e5 RK |
46 | #include <linux/amba/bus.h> |
47 | #include <linux/amba/serial.h> | |
f8ce2547 | 48 | #include <linux/clk.h> |
5a0e3ad6 | 49 | #include <linux/slab.h> |
68b65f73 RK |
50 | #include <linux/dmaengine.h> |
51 | #include <linux/dma-mapping.h> | |
52 | #include <linux/scatterlist.h> | |
c16d51a3 | 53 | #include <linux/delay.h> |
1da177e4 LT |
54 | |
55 | #include <asm/io.h> | |
c6b8fdad | 56 | #include <asm/sizes.h> |
1da177e4 LT |
57 | |
58 | #define UART_NR 14 | |
59 | ||
60 | #define SERIAL_AMBA_MAJOR 204 | |
61 | #define SERIAL_AMBA_MINOR 64 | |
62 | #define SERIAL_AMBA_NR UART_NR | |
63 | ||
64 | #define AMBA_ISR_PASS_LIMIT 256 | |
65 | ||
b63d4f0f RK |
66 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
67 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 68 | |
c16d51a3 SKS |
69 | |
70 | #define UART_WA_SAVE_NR 14 | |
71 | ||
72 | static void pl011_lockup_wa(unsigned long data); | |
73 | static const u32 uart_wa_reg[UART_WA_SAVE_NR] = { | |
74 | ST_UART011_DMAWM, | |
75 | ST_UART011_TIMEOUT, | |
76 | ST_UART011_LCRH_RX, | |
77 | UART011_IBRD, | |
78 | UART011_FBRD, | |
79 | ST_UART011_LCRH_TX, | |
80 | UART011_IFLS, | |
81 | ST_UART011_XFCR, | |
82 | ST_UART011_XON1, | |
83 | ST_UART011_XON2, | |
84 | ST_UART011_XOFF1, | |
85 | ST_UART011_XOFF2, | |
86 | UART011_CR, | |
87 | UART011_IMSC | |
88 | }; | |
89 | ||
90 | static u32 uart_wa_regdata[UART_WA_SAVE_NR]; | |
91 | static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0); | |
92 | ||
5926a295 AR |
93 | /* There is by now at least one vendor with differing details, so handle it */ |
94 | struct vendor_data { | |
95 | unsigned int ifls; | |
96 | unsigned int fifosize; | |
ec489aa8 LW |
97 | unsigned int lcrh_tx; |
98 | unsigned int lcrh_rx; | |
ac3e3fb4 | 99 | bool oversampling; |
c16d51a3 | 100 | bool interrupt_may_hang; /* vendor-specific */ |
38d62436 | 101 | bool dma_threshold; |
5926a295 AR |
102 | }; |
103 | ||
104 | static struct vendor_data vendor_arm = { | |
105 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
106 | .fifosize = 16, | |
ec489aa8 LW |
107 | .lcrh_tx = UART011_LCRH, |
108 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 109 | .oversampling = false, |
38d62436 | 110 | .dma_threshold = false, |
5926a295 AR |
111 | }; |
112 | ||
113 | static struct vendor_data vendor_st = { | |
114 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
115 | .fifosize = 64, | |
ec489aa8 LW |
116 | .lcrh_tx = ST_UART011_LCRH_TX, |
117 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 118 | .oversampling = true, |
c16d51a3 | 119 | .interrupt_may_hang = true, |
38d62436 | 120 | .dma_threshold = true, |
1da177e4 LT |
121 | }; |
122 | ||
c16d51a3 SKS |
123 | static struct uart_amba_port *amba_ports[UART_NR]; |
124 | ||
68b65f73 | 125 | /* Deals with DMA transactions */ |
ead76f32 LW |
126 | |
127 | struct pl011_sgbuf { | |
128 | struct scatterlist sg; | |
129 | char *buf; | |
130 | }; | |
131 | ||
132 | struct pl011_dmarx_data { | |
133 | struct dma_chan *chan; | |
134 | struct completion complete; | |
135 | bool use_buf_b; | |
136 | struct pl011_sgbuf sgbuf_a; | |
137 | struct pl011_sgbuf sgbuf_b; | |
138 | dma_cookie_t cookie; | |
139 | bool running; | |
140 | }; | |
141 | ||
68b65f73 RK |
142 | struct pl011_dmatx_data { |
143 | struct dma_chan *chan; | |
144 | struct scatterlist sg; | |
145 | char *buf; | |
146 | bool queued; | |
147 | }; | |
148 | ||
c19f12b5 RK |
149 | /* |
150 | * We wrap our port structure around the generic uart_port. | |
151 | */ | |
152 | struct uart_amba_port { | |
153 | struct uart_port port; | |
154 | struct clk *clk; | |
155 | const struct vendor_data *vendor; | |
68b65f73 | 156 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
157 | unsigned int im; /* interrupt mask */ |
158 | unsigned int old_status; | |
ffca2b11 | 159 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
160 | unsigned int lcrh_tx; /* vendor-specific */ |
161 | unsigned int lcrh_rx; /* vendor-specific */ | |
162 | bool autorts; | |
163 | char type[12]; | |
c16d51a3 | 164 | bool interrupt_may_hang; /* vendor-specific */ |
68b65f73 RK |
165 | #ifdef CONFIG_DMA_ENGINE |
166 | /* DMA stuff */ | |
ead76f32 LW |
167 | bool using_tx_dma; |
168 | bool using_rx_dma; | |
169 | struct pl011_dmarx_data dmarx; | |
68b65f73 RK |
170 | struct pl011_dmatx_data dmatx; |
171 | #endif | |
172 | }; | |
173 | ||
29772c4e LW |
174 | /* |
175 | * Reads up to 256 characters from the FIFO or until it's empty and | |
176 | * inserts them into the TTY layer. Returns the number of characters | |
177 | * read from the FIFO. | |
178 | */ | |
179 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
180 | { | |
181 | u16 status, ch; | |
182 | unsigned int flag, max_count = 256; | |
183 | int fifotaken = 0; | |
184 | ||
185 | while (max_count--) { | |
186 | status = readw(uap->port.membase + UART01x_FR); | |
187 | if (status & UART01x_FR_RXFE) | |
188 | break; | |
189 | ||
190 | /* Take chars from the FIFO and update status */ | |
191 | ch = readw(uap->port.membase + UART01x_DR) | | |
192 | UART_DUMMY_DR_RX; | |
193 | flag = TTY_NORMAL; | |
194 | uap->port.icount.rx++; | |
195 | fifotaken++; | |
196 | ||
197 | if (unlikely(ch & UART_DR_ERROR)) { | |
198 | if (ch & UART011_DR_BE) { | |
199 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
200 | uap->port.icount.brk++; | |
201 | if (uart_handle_break(&uap->port)) | |
202 | continue; | |
203 | } else if (ch & UART011_DR_PE) | |
204 | uap->port.icount.parity++; | |
205 | else if (ch & UART011_DR_FE) | |
206 | uap->port.icount.frame++; | |
207 | if (ch & UART011_DR_OE) | |
208 | uap->port.icount.overrun++; | |
209 | ||
210 | ch &= uap->port.read_status_mask; | |
211 | ||
212 | if (ch & UART011_DR_BE) | |
213 | flag = TTY_BREAK; | |
214 | else if (ch & UART011_DR_PE) | |
215 | flag = TTY_PARITY; | |
216 | else if (ch & UART011_DR_FE) | |
217 | flag = TTY_FRAME; | |
218 | } | |
219 | ||
220 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
221 | continue; | |
222 | ||
223 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
224 | } | |
225 | ||
226 | return fifotaken; | |
227 | } | |
228 | ||
229 | ||
68b65f73 RK |
230 | /* |
231 | * All the DMA operation mode stuff goes inside this ifdef. | |
232 | * This assumes that you have a generic DMA device interface, | |
233 | * no custom DMA interfaces are supported. | |
234 | */ | |
235 | #ifdef CONFIG_DMA_ENGINE | |
236 | ||
237 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
238 | ||
ead76f32 LW |
239 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
240 | enum dma_data_direction dir) | |
241 | { | |
242 | sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
243 | if (!sg->buf) | |
244 | return -ENOMEM; | |
245 | ||
246 | sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE); | |
247 | ||
248 | if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) { | |
249 | kfree(sg->buf); | |
250 | return -EINVAL; | |
251 | } | |
252 | return 0; | |
253 | } | |
254 | ||
255 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
256 | enum dma_data_direction dir) | |
257 | { | |
258 | if (sg->buf) { | |
259 | dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir); | |
260 | kfree(sg->buf); | |
261 | } | |
262 | } | |
263 | ||
68b65f73 RK |
264 | static void pl011_dma_probe_initcall(struct uart_amba_port *uap) |
265 | { | |
266 | /* DMA is the sole user of the platform data right now */ | |
267 | struct amba_pl011_data *plat = uap->port.dev->platform_data; | |
268 | struct dma_slave_config tx_conf = { | |
269 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
270 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 271 | .direction = DMA_MEM_TO_DEV, |
68b65f73 RK |
272 | .dst_maxburst = uap->fifosize >> 1, |
273 | }; | |
274 | struct dma_chan *chan; | |
275 | dma_cap_mask_t mask; | |
276 | ||
277 | /* We need platform data */ | |
278 | if (!plat || !plat->dma_filter) { | |
279 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
280 | return; | |
281 | } | |
282 | ||
ead76f32 | 283 | /* Try to acquire a generic DMA engine slave TX channel */ |
68b65f73 RK |
284 | dma_cap_zero(mask); |
285 | dma_cap_set(DMA_SLAVE, mask); | |
286 | ||
287 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param); | |
288 | if (!chan) { | |
289 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
290 | return; | |
291 | } | |
292 | ||
293 | dmaengine_slave_config(chan, &tx_conf); | |
294 | uap->dmatx.chan = chan; | |
295 | ||
296 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
297 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
298 | |
299 | /* Optionally make use of an RX channel as well */ | |
300 | if (plat->dma_rx_param) { | |
301 | struct dma_slave_config rx_conf = { | |
302 | .src_addr = uap->port.mapbase + UART01x_DR, | |
303 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 304 | .direction = DMA_DEV_TO_MEM, |
ead76f32 LW |
305 | .src_maxburst = uap->fifosize >> 1, |
306 | }; | |
307 | ||
308 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
309 | if (!chan) { | |
310 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
311 | return; | |
312 | } | |
313 | ||
314 | dmaengine_slave_config(chan, &rx_conf); | |
315 | uap->dmarx.chan = chan; | |
316 | ||
317 | dev_info(uap->port.dev, "DMA channel RX %s\n", | |
318 | dma_chan_name(uap->dmarx.chan)); | |
319 | } | |
68b65f73 RK |
320 | } |
321 | ||
322 | #ifndef MODULE | |
323 | /* | |
324 | * Stack up the UARTs and let the above initcall be done at device | |
325 | * initcall time, because the serial driver is called as an arch | |
326 | * initcall, and at this time the DMA subsystem is not yet registered. | |
327 | * At this point the driver will switch over to using DMA where desired. | |
328 | */ | |
329 | struct dma_uap { | |
330 | struct list_head node; | |
331 | struct uart_amba_port *uap; | |
c19f12b5 RK |
332 | }; |
333 | ||
68b65f73 RK |
334 | static LIST_HEAD(pl011_dma_uarts); |
335 | ||
336 | static int __init pl011_dma_initcall(void) | |
337 | { | |
338 | struct list_head *node, *tmp; | |
339 | ||
340 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | |
341 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | |
342 | pl011_dma_probe_initcall(dmau->uap); | |
343 | list_del(node); | |
344 | kfree(dmau); | |
345 | } | |
346 | return 0; | |
347 | } | |
348 | ||
349 | device_initcall(pl011_dma_initcall); | |
350 | ||
351 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
352 | { | |
353 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | |
354 | if (dmau) { | |
355 | dmau->uap = uap; | |
356 | list_add_tail(&dmau->node, &pl011_dma_uarts); | |
357 | } | |
358 | } | |
359 | #else | |
360 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
361 | { | |
362 | pl011_dma_probe_initcall(uap); | |
363 | } | |
364 | #endif | |
365 | ||
366 | static void pl011_dma_remove(struct uart_amba_port *uap) | |
367 | { | |
368 | /* TODO: remove the initcall if it has not yet executed */ | |
369 | if (uap->dmatx.chan) | |
370 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
371 | if (uap->dmarx.chan) |
372 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
373 | } |
374 | ||
68b65f73 RK |
375 | /* Forward declare this for the refill routine */ |
376 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); | |
377 | ||
378 | /* | |
379 | * The current DMA TX buffer has been sent. | |
380 | * Try to queue up another DMA buffer. | |
381 | */ | |
382 | static void pl011_dma_tx_callback(void *data) | |
383 | { | |
384 | struct uart_amba_port *uap = data; | |
385 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
386 | unsigned long flags; | |
387 | u16 dmacr; | |
388 | ||
389 | spin_lock_irqsave(&uap->port.lock, flags); | |
390 | if (uap->dmatx.queued) | |
391 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
392 | DMA_TO_DEVICE); | |
393 | ||
394 | dmacr = uap->dmacr; | |
395 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
396 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
397 | ||
398 | /* | |
399 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
400 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
401 | * | |
402 | * Note: we need to be careful here of a potential race between DMA | |
403 | * and the rest of the driver - if the driver disables TX DMA while | |
404 | * a TX buffer completing, we must update the tx queued status to | |
405 | * get further refills (hence we check dmacr). | |
406 | */ | |
407 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
408 | uart_circ_empty(&uap->port.state->xmit)) { | |
409 | uap->dmatx.queued = false; | |
410 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
411 | return; | |
412 | } | |
413 | ||
414 | if (pl011_dma_tx_refill(uap) <= 0) { | |
415 | /* | |
416 | * We didn't queue a DMA buffer for some reason, but we | |
417 | * have data pending to be sent. Re-enable the TX IRQ. | |
418 | */ | |
419 | uap->im |= UART011_TXIM; | |
420 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
421 | } | |
422 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
423 | } | |
424 | ||
425 | /* | |
426 | * Try to refill the TX DMA buffer. | |
427 | * Locking: called with port lock held and IRQs disabled. | |
428 | * Returns: | |
429 | * 1 if we queued up a TX DMA buffer. | |
430 | * 0 if we didn't want to handle this by DMA | |
431 | * <0 on error | |
432 | */ | |
433 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
434 | { | |
435 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
436 | struct dma_chan *chan = dmatx->chan; | |
437 | struct dma_device *dma_dev = chan->device; | |
438 | struct dma_async_tx_descriptor *desc; | |
439 | struct circ_buf *xmit = &uap->port.state->xmit; | |
440 | unsigned int count; | |
441 | ||
442 | /* | |
443 | * Try to avoid the overhead involved in using DMA if the | |
444 | * transaction fits in the first half of the FIFO, by using | |
445 | * the standard interrupt handling. This ensures that we | |
446 | * issue a uart_write_wakeup() at the appropriate time. | |
447 | */ | |
448 | count = uart_circ_chars_pending(xmit); | |
449 | if (count < (uap->fifosize >> 1)) { | |
450 | uap->dmatx.queued = false; | |
451 | return 0; | |
452 | } | |
453 | ||
454 | /* | |
455 | * Bodge: don't send the last character by DMA, as this | |
456 | * will prevent XON from notifying us to restart DMA. | |
457 | */ | |
458 | count -= 1; | |
459 | ||
460 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
461 | if (count > PL011_DMA_BUFFER_SIZE) | |
462 | count = PL011_DMA_BUFFER_SIZE; | |
463 | ||
464 | if (xmit->tail < xmit->head) | |
465 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
466 | else { | |
467 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
468 | size_t second = xmit->head; | |
469 | ||
470 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
471 | if (second) | |
472 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
473 | } | |
474 | ||
475 | dmatx->sg.length = count; | |
476 | ||
477 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
478 | uap->dmatx.queued = false; | |
479 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
480 | return -EBUSY; | |
481 | } | |
482 | ||
a485df4b | 483 | desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
484 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
485 | if (!desc) { | |
486 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
487 | uap->dmatx.queued = false; | |
488 | /* | |
489 | * If DMA cannot be used right now, we complete this | |
490 | * transaction via IRQ and let the TTY layer retry. | |
491 | */ | |
492 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
493 | return -EBUSY; | |
494 | } | |
495 | ||
496 | /* Some data to go along to the callback */ | |
497 | desc->callback = pl011_dma_tx_callback; | |
498 | desc->callback_param = uap; | |
499 | ||
500 | /* All errors should happen at prepare time */ | |
501 | dmaengine_submit(desc); | |
502 | ||
503 | /* Fire the DMA transaction */ | |
504 | dma_dev->device_issue_pending(chan); | |
505 | ||
506 | uap->dmacr |= UART011_TXDMAE; | |
507 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
508 | uap->dmatx.queued = true; | |
509 | ||
510 | /* | |
511 | * Now we know that DMA will fire, so advance the ring buffer | |
512 | * with the stuff we just dispatched. | |
513 | */ | |
514 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
515 | uap->port.icount.tx += count; | |
516 | ||
517 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
518 | uart_write_wakeup(&uap->port); | |
519 | ||
520 | return 1; | |
521 | } | |
522 | ||
523 | /* | |
524 | * We received a transmit interrupt without a pending X-char but with | |
525 | * pending characters. | |
526 | * Locking: called with port lock held and IRQs disabled. | |
527 | * Returns: | |
528 | * false if we want to use PIO to transmit | |
529 | * true if we queued a DMA buffer | |
530 | */ | |
531 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
532 | { | |
ead76f32 | 533 | if (!uap->using_tx_dma) |
68b65f73 RK |
534 | return false; |
535 | ||
536 | /* | |
537 | * If we already have a TX buffer queued, but received a | |
538 | * TX interrupt, it will be because we've just sent an X-char. | |
539 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
540 | */ | |
541 | if (uap->dmatx.queued) { | |
542 | uap->dmacr |= UART011_TXDMAE; | |
543 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
544 | uap->im &= ~UART011_TXIM; | |
545 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
546 | return true; | |
547 | } | |
548 | ||
549 | /* | |
550 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 551 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
552 | */ |
553 | if (pl011_dma_tx_refill(uap) > 0) { | |
554 | uap->im &= ~UART011_TXIM; | |
555 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
556 | return true; | |
557 | } | |
558 | return false; | |
559 | } | |
560 | ||
561 | /* | |
562 | * Stop the DMA transmit (eg, due to received XOFF). | |
563 | * Locking: called with port lock held and IRQs disabled. | |
564 | */ | |
565 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
566 | { | |
567 | if (uap->dmatx.queued) { | |
568 | uap->dmacr &= ~UART011_TXDMAE; | |
569 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
570 | } | |
571 | } | |
572 | ||
573 | /* | |
574 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
575 | * character queued for send, try to get that character out ASAP. | |
576 | * Locking: called with port lock held and IRQs disabled. | |
577 | * Returns: | |
578 | * false if we want the TX IRQ to be enabled | |
579 | * true if we have a buffer queued | |
580 | */ | |
581 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
582 | { | |
583 | u16 dmacr; | |
584 | ||
ead76f32 | 585 | if (!uap->using_tx_dma) |
68b65f73 RK |
586 | return false; |
587 | ||
588 | if (!uap->port.x_char) { | |
589 | /* no X-char, try to push chars out in DMA mode */ | |
590 | bool ret = true; | |
591 | ||
592 | if (!uap->dmatx.queued) { | |
593 | if (pl011_dma_tx_refill(uap) > 0) { | |
594 | uap->im &= ~UART011_TXIM; | |
595 | ret = true; | |
596 | } else { | |
597 | uap->im |= UART011_TXIM; | |
598 | ret = false; | |
599 | } | |
600 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
601 | } else if (!(uap->dmacr & UART011_TXDMAE)) { | |
602 | uap->dmacr |= UART011_TXDMAE; | |
603 | writew(uap->dmacr, | |
604 | uap->port.membase + UART011_DMACR); | |
605 | } | |
606 | return ret; | |
607 | } | |
608 | ||
609 | /* | |
610 | * We have an X-char to send. Disable DMA to prevent it loading | |
611 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
612 | */ | |
613 | dmacr = uap->dmacr; | |
614 | uap->dmacr &= ~UART011_TXDMAE; | |
615 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
616 | ||
617 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
618 | /* | |
619 | * No space in the FIFO, so enable the transmit interrupt | |
620 | * so we know when there is space. Note that once we've | |
621 | * loaded the character, we should just re-enable DMA. | |
622 | */ | |
623 | return false; | |
624 | } | |
625 | ||
626 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
627 | uap->port.icount.tx++; | |
628 | uap->port.x_char = 0; | |
629 | ||
630 | /* Success - restore the DMA state */ | |
631 | uap->dmacr = dmacr; | |
632 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
633 | ||
634 | return true; | |
635 | } | |
636 | ||
637 | /* | |
638 | * Flush the transmit buffer. | |
639 | * Locking: called with port lock held and IRQs disabled. | |
640 | */ | |
641 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
642 | { | |
643 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
644 | ||
ead76f32 | 645 | if (!uap->using_tx_dma) |
68b65f73 RK |
646 | return; |
647 | ||
648 | /* Avoid deadlock with the DMA engine callback */ | |
649 | spin_unlock(&uap->port.lock); | |
650 | dmaengine_terminate_all(uap->dmatx.chan); | |
651 | spin_lock(&uap->port.lock); | |
652 | if (uap->dmatx.queued) { | |
653 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
654 | DMA_TO_DEVICE); | |
655 | uap->dmatx.queued = false; | |
656 | uap->dmacr &= ~UART011_TXDMAE; | |
657 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
658 | } | |
659 | } | |
660 | ||
ead76f32 LW |
661 | static void pl011_dma_rx_callback(void *data); |
662 | ||
663 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
664 | { | |
665 | struct dma_chan *rxchan = uap->dmarx.chan; | |
666 | struct dma_device *dma_dev; | |
667 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
668 | struct dma_async_tx_descriptor *desc; | |
669 | struct pl011_sgbuf *sgbuf; | |
670 | ||
671 | if (!rxchan) | |
672 | return -EIO; | |
673 | ||
674 | /* Start the RX DMA job */ | |
675 | sgbuf = uap->dmarx.use_buf_b ? | |
676 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
677 | dma_dev = rxchan->device; | |
678 | desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1, | |
a485df4b | 679 | DMA_DEV_TO_MEM, |
ead76f32 LW |
680 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
681 | /* | |
682 | * If the DMA engine is busy and cannot prepare a | |
683 | * channel, no big deal, the driver will fall back | |
684 | * to interrupt mode as a result of this error code. | |
685 | */ | |
686 | if (!desc) { | |
687 | uap->dmarx.running = false; | |
688 | dmaengine_terminate_all(rxchan); | |
689 | return -EBUSY; | |
690 | } | |
691 | ||
692 | /* Some data to go along to the callback */ | |
693 | desc->callback = pl011_dma_rx_callback; | |
694 | desc->callback_param = uap; | |
695 | dmarx->cookie = dmaengine_submit(desc); | |
696 | dma_async_issue_pending(rxchan); | |
697 | ||
698 | uap->dmacr |= UART011_RXDMAE; | |
699 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
700 | uap->dmarx.running = true; | |
701 | ||
702 | uap->im &= ~UART011_RXIM; | |
703 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
708 | /* | |
709 | * This is called when either the DMA job is complete, or | |
710 | * the FIFO timeout interrupt occurred. This must be called | |
711 | * with the port spinlock uap->port.lock held. | |
712 | */ | |
713 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
714 | u32 pending, bool use_buf_b, | |
715 | bool readfifo) | |
716 | { | |
717 | struct tty_struct *tty = uap->port.state->port.tty; | |
718 | struct pl011_sgbuf *sgbuf = use_buf_b ? | |
719 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
720 | struct device *dev = uap->dmarx.chan->device->dev; | |
ead76f32 LW |
721 | int dma_count = 0; |
722 | u32 fifotaken = 0; /* only used for vdbg() */ | |
723 | ||
724 | /* Pick everything from the DMA first */ | |
725 | if (pending) { | |
726 | /* Sync in buffer */ | |
727 | dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE); | |
728 | ||
729 | /* | |
730 | * First take all chars in the DMA pipe, then look in the FIFO. | |
731 | * Note that tty_insert_flip_buf() tries to take as many chars | |
732 | * as it can. | |
733 | */ | |
734 | dma_count = tty_insert_flip_string(uap->port.state->port.tty, | |
735 | sgbuf->buf, pending); | |
736 | ||
737 | /* Return buffer to device */ | |
738 | dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE); | |
739 | ||
740 | uap->port.icount.rx += dma_count; | |
741 | if (dma_count < pending) | |
742 | dev_warn(uap->port.dev, | |
743 | "couldn't insert all characters (TTY is full?)\n"); | |
744 | } | |
745 | ||
746 | /* | |
747 | * Only continue with trying to read the FIFO if all DMA chars have | |
748 | * been taken first. | |
749 | */ | |
750 | if (dma_count == pending && readfifo) { | |
751 | /* Clear any error flags */ | |
752 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
753 | uap->port.membase + UART011_ICR); | |
754 | ||
755 | /* | |
756 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
757 | * incomplete buffer, that could be due to an rx error, or |
758 | * maybe we just timed out. Read any pending chars and check | |
759 | * the error status. | |
760 | * | |
761 | * Error conditions will only occur in the FIFO, these will | |
762 | * trigger an immediate interrupt and stop the DMA job, so we | |
763 | * will always find the error in the FIFO, never in the DMA | |
764 | * buffer. | |
ead76f32 | 765 | */ |
29772c4e | 766 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
767 | } |
768 | ||
769 | spin_unlock(&uap->port.lock); | |
770 | dev_vdbg(uap->port.dev, | |
771 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
772 | dma_count, fifotaken); | |
773 | tty_flip_buffer_push(tty); | |
774 | spin_lock(&uap->port.lock); | |
775 | } | |
776 | ||
777 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
778 | { | |
779 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
780 | struct dma_chan *rxchan = dmarx->chan; | |
781 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
782 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
783 | size_t pending; | |
784 | struct dma_tx_state state; | |
785 | enum dma_status dmastat; | |
786 | ||
787 | /* | |
788 | * Pause the transfer so we can trust the current counter, | |
789 | * do this before we pause the PL011 block, else we may | |
790 | * overflow the FIFO. | |
791 | */ | |
792 | if (dmaengine_pause(rxchan)) | |
793 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
794 | dmastat = rxchan->device->device_tx_status(rxchan, | |
795 | dmarx->cookie, &state); | |
796 | if (dmastat != DMA_PAUSED) | |
797 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
798 | ||
799 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
800 | uap->dmacr &= ~UART011_RXDMAE; | |
801 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
802 | uap->dmarx.running = false; | |
803 | ||
804 | pending = sgbuf->sg.length - state.residue; | |
805 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
806 | /* Then we terminate the transfer - we now know our residue */ | |
807 | dmaengine_terminate_all(rxchan); | |
808 | ||
809 | /* | |
810 | * This will take the chars we have so far and insert | |
811 | * into the framework. | |
812 | */ | |
813 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
814 | ||
815 | /* Switch buffer & re-trigger DMA job */ | |
816 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
817 | if (pl011_dma_rx_trigger_dma(uap)) { | |
818 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
819 | "fall back to interrupt mode\n"); | |
820 | uap->im |= UART011_RXIM; | |
821 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
822 | } | |
823 | } | |
824 | ||
825 | static void pl011_dma_rx_callback(void *data) | |
826 | { | |
827 | struct uart_amba_port *uap = data; | |
828 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
829 | bool lastbuf = dmarx->use_buf_b; | |
830 | int ret; | |
831 | ||
832 | /* | |
833 | * This completion interrupt occurs typically when the | |
834 | * RX buffer is totally stuffed but no timeout has yet | |
835 | * occurred. When that happens, we just want the RX | |
836 | * routine to flush out the secondary DMA buffer while | |
837 | * we immediately trigger the next DMA job. | |
838 | */ | |
839 | spin_lock_irq(&uap->port.lock); | |
840 | uap->dmarx.running = false; | |
841 | dmarx->use_buf_b = !lastbuf; | |
842 | ret = pl011_dma_rx_trigger_dma(uap); | |
843 | ||
844 | pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false); | |
845 | spin_unlock_irq(&uap->port.lock); | |
846 | /* | |
847 | * Do this check after we picked the DMA chars so we don't | |
848 | * get some IRQ immediately from RX. | |
849 | */ | |
850 | if (ret) { | |
851 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
852 | "fall back to interrupt mode\n"); | |
853 | uap->im |= UART011_RXIM; | |
854 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
855 | } | |
856 | } | |
857 | ||
858 | /* | |
859 | * Stop accepting received characters, when we're shutting down or | |
860 | * suspending this port. | |
861 | * Locking: called with port lock held and IRQs disabled. | |
862 | */ | |
863 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
864 | { | |
865 | /* FIXME. Just disable the DMA enable */ | |
866 | uap->dmacr &= ~UART011_RXDMAE; | |
867 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
868 | } | |
68b65f73 RK |
869 | |
870 | static void pl011_dma_startup(struct uart_amba_port *uap) | |
871 | { | |
ead76f32 LW |
872 | int ret; |
873 | ||
68b65f73 RK |
874 | if (!uap->dmatx.chan) |
875 | return; | |
876 | ||
877 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
878 | if (!uap->dmatx.buf) { | |
879 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
880 | uap->port.fifosize = uap->fifosize; | |
881 | return; | |
882 | } | |
883 | ||
884 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
885 | ||
886 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
887 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
888 | uap->using_tx_dma = true; |
889 | ||
890 | if (!uap->dmarx.chan) | |
891 | goto skip_rx; | |
892 | ||
893 | /* Allocate and map DMA RX buffers */ | |
894 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
895 | DMA_FROM_DEVICE); | |
896 | if (ret) { | |
897 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
898 | "RX buffer A", ret); | |
899 | goto skip_rx; | |
900 | } | |
68b65f73 | 901 | |
ead76f32 LW |
902 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
903 | DMA_FROM_DEVICE); | |
904 | if (ret) { | |
905 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
906 | "RX buffer B", ret); | |
907 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
908 | DMA_FROM_DEVICE); | |
909 | goto skip_rx; | |
910 | } | |
911 | ||
912 | uap->using_rx_dma = true; | |
68b65f73 | 913 | |
ead76f32 | 914 | skip_rx: |
68b65f73 RK |
915 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
916 | uap->dmacr |= UART011_DMAONERR; | |
917 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
38d62436 RK |
918 | |
919 | /* | |
920 | * ST Micro variants has some specific dma burst threshold | |
921 | * compensation. Set this to 16 bytes, so burst will only | |
922 | * be issued above/below 16 bytes. | |
923 | */ | |
924 | if (uap->vendor->dma_threshold) | |
925 | writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, | |
926 | uap->port.membase + ST_UART011_DMAWM); | |
ead76f32 LW |
927 | |
928 | if (uap->using_rx_dma) { | |
929 | if (pl011_dma_rx_trigger_dma(uap)) | |
930 | dev_dbg(uap->port.dev, "could not trigger initial " | |
931 | "RX DMA job, fall back to interrupt mode\n"); | |
932 | } | |
68b65f73 RK |
933 | } |
934 | ||
935 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
936 | { | |
ead76f32 | 937 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
938 | return; |
939 | ||
940 | /* Disable RX and TX DMA */ | |
941 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
942 | barrier(); | |
943 | ||
944 | spin_lock_irq(&uap->port.lock); | |
945 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
946 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
947 | spin_unlock_irq(&uap->port.lock); | |
948 | ||
ead76f32 LW |
949 | if (uap->using_tx_dma) { |
950 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
951 | dmaengine_terminate_all(uap->dmatx.chan); | |
952 | if (uap->dmatx.queued) { | |
953 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
954 | DMA_TO_DEVICE); | |
955 | uap->dmatx.queued = false; | |
956 | } | |
957 | ||
958 | kfree(uap->dmatx.buf); | |
959 | uap->using_tx_dma = false; | |
68b65f73 RK |
960 | } |
961 | ||
ead76f32 LW |
962 | if (uap->using_rx_dma) { |
963 | dmaengine_terminate_all(uap->dmarx.chan); | |
964 | /* Clean up the RX DMA */ | |
965 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
966 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
967 | uap->using_rx_dma = false; | |
968 | } | |
969 | } | |
68b65f73 | 970 | |
ead76f32 LW |
971 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
972 | { | |
973 | return uap->using_rx_dma; | |
68b65f73 RK |
974 | } |
975 | ||
ead76f32 LW |
976 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
977 | { | |
978 | return uap->using_rx_dma && uap->dmarx.running; | |
979 | } | |
980 | ||
981 | ||
68b65f73 RK |
982 | #else |
983 | /* Blank functions if the DMA engine is not available */ | |
984 | static inline void pl011_dma_probe(struct uart_amba_port *uap) | |
985 | { | |
986 | } | |
987 | ||
988 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
989 | { | |
990 | } | |
991 | ||
992 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
993 | { | |
994 | } | |
995 | ||
996 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
997 | { | |
998 | } | |
999 | ||
1000 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1001 | { | |
1002 | return false; | |
1003 | } | |
1004 | ||
1005 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1006 | { | |
1007 | } | |
1008 | ||
1009 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1010 | { | |
1011 | return false; | |
1012 | } | |
1013 | ||
ead76f32 LW |
1014 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1015 | { | |
1016 | } | |
1017 | ||
1018 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1019 | { | |
1020 | } | |
1021 | ||
1022 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1023 | { | |
1024 | return -EIO; | |
1025 | } | |
1026 | ||
1027 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1028 | { | |
1029 | return false; | |
1030 | } | |
1031 | ||
1032 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1033 | { | |
1034 | return false; | |
1035 | } | |
1036 | ||
68b65f73 RK |
1037 | #define pl011_dma_flush_buffer NULL |
1038 | #endif | |
1039 | ||
1040 | ||
c16d51a3 SKS |
1041 | /* |
1042 | * pl011_lockup_wa | |
1043 | * This workaround aims to break the deadlock situation | |
1044 | * when after long transfer over uart in hardware flow | |
1045 | * control, uart interrupt registers cannot be cleared. | |
1046 | * Hence uart transfer gets blocked. | |
1047 | * | |
1048 | * It is seen that during such deadlock condition ICR | |
1049 | * don't get cleared even on multiple write. This leads | |
1050 | * pass_counter to decrease and finally reach zero. This | |
1051 | * can be taken as trigger point to run this UART_BT_WA. | |
1052 | * | |
1053 | */ | |
1054 | static void pl011_lockup_wa(unsigned long data) | |
1055 | { | |
1056 | struct uart_amba_port *uap = amba_ports[0]; | |
1057 | void __iomem *base = uap->port.membase; | |
1058 | struct circ_buf *xmit = &uap->port.state->xmit; | |
1059 | struct tty_struct *tty = uap->port.state->port.tty; | |
1060 | int buf_empty_retries = 200; | |
1061 | int loop; | |
1062 | ||
1063 | /* Stop HCI layer from submitting data for tx */ | |
1064 | tty->hw_stopped = 1; | |
1065 | while (!uart_circ_empty(xmit)) { | |
1066 | if (buf_empty_retries-- == 0) | |
1067 | break; | |
1068 | udelay(100); | |
1069 | } | |
1070 | ||
1071 | /* Backup registers */ | |
1072 | for (loop = 0; loop < UART_WA_SAVE_NR; loop++) | |
1073 | uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]); | |
1074 | ||
1075 | /* Disable UART so that FIFO data is flushed out */ | |
1076 | writew(0x00, uap->port.membase + UART011_CR); | |
1077 | ||
1078 | /* Soft reset UART module */ | |
1079 | if (uap->port.dev->platform_data) { | |
1080 | struct amba_pl011_data *plat; | |
1081 | ||
1082 | plat = uap->port.dev->platform_data; | |
1083 | if (plat->reset) | |
1084 | plat->reset(); | |
1085 | } | |
1086 | ||
1087 | /* Restore registers */ | |
1088 | for (loop = 0; loop < UART_WA_SAVE_NR; loop++) | |
1089 | writew(uart_wa_regdata[loop] , | |
1090 | uap->port.membase + uart_wa_reg[loop]); | |
1091 | ||
1092 | /* Initialise the old status of the modem signals */ | |
1093 | uap->old_status = readw(uap->port.membase + UART01x_FR) & | |
1094 | UART01x_FR_MODEM_ANY; | |
1095 | ||
1096 | if (readl(base + UART011_MIS) & 0x2) | |
1097 | printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n"); | |
1098 | ||
1099 | /* Start Tx/Rx */ | |
1100 | tty->hw_stopped = 0; | |
1101 | } | |
1102 | ||
b129a8cc | 1103 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 LT |
1104 | { |
1105 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1106 | ||
1107 | uap->im &= ~UART011_TXIM; | |
1108 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 1109 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1110 | } |
1111 | ||
b129a8cc | 1112 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 LT |
1113 | { |
1114 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1115 | ||
68b65f73 RK |
1116 | if (!pl011_dma_tx_start(uap)) { |
1117 | uap->im |= UART011_TXIM; | |
1118 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1119 | } | |
1da177e4 LT |
1120 | } |
1121 | ||
1122 | static void pl011_stop_rx(struct uart_port *port) | |
1123 | { | |
1124 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1125 | ||
1126 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1127 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
1128 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
ead76f32 LW |
1129 | |
1130 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1131 | } |
1132 | ||
1133 | static void pl011_enable_ms(struct uart_port *port) | |
1134 | { | |
1135 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1136 | ||
1137 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
1138 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1139 | } | |
1140 | ||
7d12e780 | 1141 | static void pl011_rx_chars(struct uart_amba_port *uap) |
1da177e4 | 1142 | { |
ebd2c8f6 | 1143 | struct tty_struct *tty = uap->port.state->port.tty; |
1da177e4 | 1144 | |
29772c4e | 1145 | pl011_fifo_to_tty(uap); |
1da177e4 | 1146 | |
2389b272 | 1147 | spin_unlock(&uap->port.lock); |
1da177e4 | 1148 | tty_flip_buffer_push(tty); |
ead76f32 LW |
1149 | /* |
1150 | * If we were temporarily out of DMA mode for a while, | |
1151 | * attempt to switch back to DMA mode again. | |
1152 | */ | |
1153 | if (pl011_dma_rx_available(uap)) { | |
1154 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1155 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1156 | "fall back to interrupt mode again\n"); | |
1157 | uap->im |= UART011_RXIM; | |
1158 | } else | |
1159 | uap->im &= ~UART011_RXIM; | |
1160 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1161 | } | |
2389b272 | 1162 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1163 | } |
1164 | ||
1165 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
1166 | { | |
ebd2c8f6 | 1167 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
1168 | int count; |
1169 | ||
1170 | if (uap->port.x_char) { | |
1171 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
1172 | uap->port.icount.tx++; | |
1173 | uap->port.x_char = 0; | |
1174 | return; | |
1175 | } | |
1176 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1177 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1178 | return; |
1179 | } | |
1180 | ||
68b65f73 RK |
1181 | /* If we are using DMA mode, try to send some characters. */ |
1182 | if (pl011_dma_tx_irq(uap)) | |
1183 | return; | |
1184 | ||
ffca2b11 | 1185 | count = uap->fifosize >> 1; |
1da177e4 LT |
1186 | do { |
1187 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
1188 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1189 | uap->port.icount.tx++; | |
1190 | if (uart_circ_empty(xmit)) | |
1191 | break; | |
1192 | } while (--count > 0); | |
1193 | ||
1194 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1195 | uart_write_wakeup(&uap->port); | |
1196 | ||
1197 | if (uart_circ_empty(xmit)) | |
b129a8cc | 1198 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1199 | } |
1200 | ||
1201 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1202 | { | |
1203 | unsigned int status, delta; | |
1204 | ||
1205 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1206 | ||
1207 | delta = status ^ uap->old_status; | |
1208 | uap->old_status = status; | |
1209 | ||
1210 | if (!delta) | |
1211 | return; | |
1212 | ||
1213 | if (delta & UART01x_FR_DCD) | |
1214 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1215 | ||
1216 | if (delta & UART01x_FR_DSR) | |
1217 | uap->port.icount.dsr++; | |
1218 | ||
1219 | if (delta & UART01x_FR_CTS) | |
1220 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1221 | ||
bdc04e31 | 1222 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1223 | } |
1224 | ||
7d12e780 | 1225 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1226 | { |
1227 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1228 | unsigned long flags; |
1da177e4 LT |
1229 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
1230 | int handled = 0; | |
1231 | ||
963cc981 | 1232 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
1233 | |
1234 | status = readw(uap->port.membase + UART011_MIS); | |
1235 | if (status) { | |
1236 | do { | |
1237 | writew(status & ~(UART011_TXIS|UART011_RTIS| | |
1238 | UART011_RXIS), | |
1239 | uap->port.membase + UART011_ICR); | |
1240 | ||
ead76f32 LW |
1241 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1242 | if (pl011_dma_rx_running(uap)) | |
1243 | pl011_dma_rx_irq(uap); | |
1244 | else | |
1245 | pl011_rx_chars(uap); | |
1246 | } | |
1da177e4 LT |
1247 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1248 | UART011_CTSMIS|UART011_RIMIS)) | |
1249 | pl011_modem_status(uap); | |
1250 | if (status & UART011_TXIS) | |
1251 | pl011_tx_chars(uap); | |
1252 | ||
c16d51a3 SKS |
1253 | if (pass_counter-- == 0) { |
1254 | if (uap->interrupt_may_hang) | |
1255 | tasklet_schedule(&pl011_lockup_tlet); | |
1da177e4 | 1256 | break; |
c16d51a3 | 1257 | } |
1da177e4 LT |
1258 | |
1259 | status = readw(uap->port.membase + UART011_MIS); | |
1260 | } while (status != 0); | |
1261 | handled = 1; | |
1262 | } | |
1263 | ||
963cc981 | 1264 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1265 | |
1266 | return IRQ_RETVAL(handled); | |
1267 | } | |
1268 | ||
1269 | static unsigned int pl01x_tx_empty(struct uart_port *port) | |
1270 | { | |
1271 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1272 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1273 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
1274 | } | |
1275 | ||
1276 | static unsigned int pl01x_get_mctrl(struct uart_port *port) | |
1277 | { | |
1278 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1279 | unsigned int result = 0; | |
1280 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1281 | ||
5159f407 | 1282 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1283 | if (status & uartbit) \ |
1284 | result |= tiocmbit | |
1285 | ||
5159f407 JS |
1286 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
1287 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
1288 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1289 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
1290 | #undef TIOCMBIT | |
1da177e4 LT |
1291 | return result; |
1292 | } | |
1293 | ||
1294 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1295 | { | |
1296 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1297 | unsigned int cr; | |
1298 | ||
1299 | cr = readw(uap->port.membase + UART011_CR); | |
1300 | ||
5159f407 | 1301 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1302 | if (mctrl & tiocmbit) \ |
1303 | cr |= uartbit; \ | |
1304 | else \ | |
1305 | cr &= ~uartbit | |
1306 | ||
5159f407 JS |
1307 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1308 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1309 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1310 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1311 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1312 | |
1313 | if (uap->autorts) { | |
1314 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1315 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1316 | } | |
5159f407 | 1317 | #undef TIOCMBIT |
1da177e4 LT |
1318 | |
1319 | writew(cr, uap->port.membase + UART011_CR); | |
1320 | } | |
1321 | ||
1322 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1323 | { | |
1324 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1325 | unsigned long flags; | |
1326 | unsigned int lcr_h; | |
1327 | ||
1328 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 1329 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1330 | if (break_state == -1) |
1331 | lcr_h |= UART01x_LCRH_BRK; | |
1332 | else | |
1333 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 1334 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1335 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1336 | } | |
1337 | ||
84b5ae15 JW |
1338 | #ifdef CONFIG_CONSOLE_POLL |
1339 | static int pl010_get_poll_char(struct uart_port *port) | |
1340 | { | |
1341 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1342 | unsigned int status; | |
1343 | ||
f5316b4a JW |
1344 | status = readw(uap->port.membase + UART01x_FR); |
1345 | if (status & UART01x_FR_RXFE) | |
1346 | return NO_POLL_CHAR; | |
84b5ae15 JW |
1347 | |
1348 | return readw(uap->port.membase + UART01x_DR); | |
1349 | } | |
1350 | ||
1351 | static void pl010_put_poll_char(struct uart_port *port, | |
1352 | unsigned char ch) | |
1353 | { | |
1354 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1355 | ||
1356 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1357 | barrier(); | |
1358 | ||
1359 | writew(ch, uap->port.membase + UART01x_DR); | |
1360 | } | |
1361 | ||
1362 | #endif /* CONFIG_CONSOLE_POLL */ | |
1363 | ||
1da177e4 LT |
1364 | static int pl011_startup(struct uart_port *port) |
1365 | { | |
1366 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1367 | unsigned int cr; | |
1368 | int retval; | |
1369 | ||
1370 | /* | |
1371 | * Try to enable the clock producer. | |
1372 | */ | |
1373 | retval = clk_enable(uap->clk); | |
1374 | if (retval) | |
1375 | goto out; | |
1376 | ||
1377 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1378 | ||
1379 | /* | |
1380 | * Allocate the IRQ | |
1381 | */ | |
1382 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1383 | if (retval) | |
1384 | goto clk_dis; | |
1385 | ||
c19f12b5 | 1386 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 LT |
1387 | |
1388 | /* | |
1389 | * Provoke TX FIFO interrupt into asserting. | |
1390 | */ | |
1391 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; | |
1392 | writew(cr, uap->port.membase + UART011_CR); | |
1393 | writew(0, uap->port.membase + UART011_FBRD); | |
1394 | writew(1, uap->port.membase + UART011_IBRD); | |
ec489aa8 LW |
1395 | writew(0, uap->port.membase + uap->lcrh_rx); |
1396 | if (uap->lcrh_tx != uap->lcrh_rx) { | |
1397 | int i; | |
1398 | /* | |
1399 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1400 | * to get this delay write read only register 10 times | |
1401 | */ | |
1402 | for (i = 0; i < 10; ++i) | |
1403 | writew(0xff, uap->port.membase + UART011_MIS); | |
1404 | writew(0, uap->port.membase + uap->lcrh_tx); | |
1405 | } | |
1da177e4 LT |
1406 | writew(0, uap->port.membase + UART01x_DR); |
1407 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1408 | barrier(); | |
1409 | ||
1410 | cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
1411 | writew(cr, uap->port.membase + UART011_CR); | |
1412 | ||
5063e2c5 RK |
1413 | /* Clear pending error interrupts */ |
1414 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
1415 | uap->port.membase + UART011_ICR); | |
1416 | ||
1da177e4 LT |
1417 | /* |
1418 | * initialise the old status of the modem signals | |
1419 | */ | |
1420 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1421 | ||
68b65f73 RK |
1422 | /* Startup DMA */ |
1423 | pl011_dma_startup(uap); | |
1424 | ||
1da177e4 | 1425 | /* |
ead76f32 LW |
1426 | * Finally, enable interrupts, only timeouts when using DMA |
1427 | * if initial RX DMA job failed, start in interrupt mode | |
1428 | * as well. | |
1da177e4 LT |
1429 | */ |
1430 | spin_lock_irq(&uap->port.lock); | |
ead76f32 LW |
1431 | uap->im = UART011_RTIM; |
1432 | if (!pl011_dma_rx_running(uap)) | |
1433 | uap->im |= UART011_RXIM; | |
1da177e4 LT |
1434 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1435 | spin_unlock_irq(&uap->port.lock); | |
1436 | ||
c16d51a3 SKS |
1437 | if (uap->port.dev->platform_data) { |
1438 | struct amba_pl011_data *plat; | |
1439 | ||
1440 | plat = uap->port.dev->platform_data; | |
1441 | if (plat->init) | |
1442 | plat->init(); | |
1443 | } | |
1444 | ||
1da177e4 LT |
1445 | return 0; |
1446 | ||
1447 | clk_dis: | |
1448 | clk_disable(uap->clk); | |
1449 | out: | |
1450 | return retval; | |
1451 | } | |
1452 | ||
ec489aa8 LW |
1453 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1454 | unsigned int lcrh) | |
1455 | { | |
1456 | unsigned long val; | |
1457 | ||
1458 | val = readw(uap->port.membase + lcrh); | |
1459 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1460 | writew(val, uap->port.membase + lcrh); | |
1461 | } | |
1462 | ||
1da177e4 LT |
1463 | static void pl011_shutdown(struct uart_port *port) |
1464 | { | |
1465 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1da177e4 LT |
1466 | |
1467 | /* | |
1468 | * disable all interrupts | |
1469 | */ | |
1470 | spin_lock_irq(&uap->port.lock); | |
1471 | uap->im = 0; | |
1472 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1473 | writew(0xffff, uap->port.membase + UART011_ICR); | |
1474 | spin_unlock_irq(&uap->port.lock); | |
1475 | ||
68b65f73 RK |
1476 | pl011_dma_shutdown(uap); |
1477 | ||
1da177e4 LT |
1478 | /* |
1479 | * Free the interrupt | |
1480 | */ | |
1481 | free_irq(uap->port.irq, uap); | |
1482 | ||
1483 | /* | |
1484 | * disable the port | |
1485 | */ | |
3b43816f | 1486 | uap->autorts = false; |
1da177e4 LT |
1487 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); |
1488 | ||
1489 | /* | |
1490 | * disable break condition and fifos | |
1491 | */ | |
ec489aa8 LW |
1492 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
1493 | if (uap->lcrh_rx != uap->lcrh_tx) | |
1494 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
1da177e4 LT |
1495 | |
1496 | /* | |
1497 | * Shut down the clock producer | |
1498 | */ | |
1499 | clk_disable(uap->clk); | |
c16d51a3 SKS |
1500 | |
1501 | if (uap->port.dev->platform_data) { | |
1502 | struct amba_pl011_data *plat; | |
1503 | ||
1504 | plat = uap->port.dev->platform_data; | |
1505 | if (plat->exit) | |
1506 | plat->exit(); | |
1507 | } | |
1508 | ||
1da177e4 LT |
1509 | } |
1510 | ||
1511 | static void | |
606d099c AC |
1512 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1513 | struct ktermios *old) | |
1da177e4 | 1514 | { |
3b43816f | 1515 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 LT |
1516 | unsigned int lcr_h, old_cr; |
1517 | unsigned long flags; | |
c19f12b5 RK |
1518 | unsigned int baud, quot, clkdiv; |
1519 | ||
1520 | if (uap->vendor->oversampling) | |
1521 | clkdiv = 8; | |
1522 | else | |
1523 | clkdiv = 16; | |
1da177e4 LT |
1524 | |
1525 | /* | |
1526 | * Ask the core to calculate the divisor for us. | |
1527 | */ | |
ac3e3fb4 | 1528 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1529 | port->uartclk / clkdiv); |
ac3e3fb4 LW |
1530 | |
1531 | if (baud > port->uartclk/16) | |
1532 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1533 | else | |
1534 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1535 | |
1536 | switch (termios->c_cflag & CSIZE) { | |
1537 | case CS5: | |
1538 | lcr_h = UART01x_LCRH_WLEN_5; | |
1539 | break; | |
1540 | case CS6: | |
1541 | lcr_h = UART01x_LCRH_WLEN_6; | |
1542 | break; | |
1543 | case CS7: | |
1544 | lcr_h = UART01x_LCRH_WLEN_7; | |
1545 | break; | |
1546 | default: // CS8 | |
1547 | lcr_h = UART01x_LCRH_WLEN_8; | |
1548 | break; | |
1549 | } | |
1550 | if (termios->c_cflag & CSTOPB) | |
1551 | lcr_h |= UART01x_LCRH_STP2; | |
1552 | if (termios->c_cflag & PARENB) { | |
1553 | lcr_h |= UART01x_LCRH_PEN; | |
1554 | if (!(termios->c_cflag & PARODD)) | |
1555 | lcr_h |= UART01x_LCRH_EPS; | |
1556 | } | |
ffca2b11 | 1557 | if (uap->fifosize > 1) |
1da177e4 LT |
1558 | lcr_h |= UART01x_LCRH_FEN; |
1559 | ||
1560 | spin_lock_irqsave(&port->lock, flags); | |
1561 | ||
1562 | /* | |
1563 | * Update the per-port timeout. | |
1564 | */ | |
1565 | uart_update_timeout(port, termios->c_cflag, baud); | |
1566 | ||
b63d4f0f | 1567 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 1568 | if (termios->c_iflag & INPCK) |
b63d4f0f | 1569 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1570 | if (termios->c_iflag & (BRKINT | PARMRK)) |
b63d4f0f | 1571 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1572 | |
1573 | /* | |
1574 | * Characters to ignore | |
1575 | */ | |
1576 | port->ignore_status_mask = 0; | |
1577 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1578 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1579 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 1580 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1581 | /* |
1582 | * If we're ignoring parity and break indicators, | |
1583 | * ignore overruns too (for real raw support). | |
1584 | */ | |
1585 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1586 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
1587 | } |
1588 | ||
1589 | /* | |
1590 | * Ignore all characters if CREAD is not set. | |
1591 | */ | |
1592 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 1593 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
1594 | |
1595 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1596 | pl011_enable_ms(port); | |
1597 | ||
1598 | /* first, disable everything */ | |
1599 | old_cr = readw(port->membase + UART011_CR); | |
1600 | writew(0, port->membase + UART011_CR); | |
1601 | ||
3b43816f RV |
1602 | if (termios->c_cflag & CRTSCTS) { |
1603 | if (old_cr & UART011_CR_RTS) | |
1604 | old_cr |= UART011_CR_RTSEN; | |
1605 | ||
1606 | old_cr |= UART011_CR_CTSEN; | |
1607 | uap->autorts = true; | |
1608 | } else { | |
1609 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1610 | uap->autorts = false; | |
1611 | } | |
1612 | ||
c19f12b5 RK |
1613 | if (uap->vendor->oversampling) { |
1614 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1615 | old_cr |= ST_UART011_CR_OVSFACT; |
1616 | else | |
1617 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1618 | } | |
1619 | ||
1da177e4 LT |
1620 | /* Set baud rate */ |
1621 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1622 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1623 | ||
1624 | /* | |
1625 | * ----------v----------v----------v----------v----- | |
1626 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
1627 | * ----------^----------^----------^----------^----- | |
1628 | */ | |
ec489aa8 LW |
1629 | writew(lcr_h, port->membase + uap->lcrh_rx); |
1630 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1631 | int i; | |
1632 | /* | |
1633 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1634 | * to get this delay write read only register 10 times | |
1635 | */ | |
1636 | for (i = 0; i < 10; ++i) | |
1637 | writew(0xff, uap->port.membase + UART011_MIS); | |
1638 | writew(lcr_h, port->membase + uap->lcrh_tx); | |
1639 | } | |
1da177e4 LT |
1640 | writew(old_cr, port->membase + UART011_CR); |
1641 | ||
1642 | spin_unlock_irqrestore(&port->lock, flags); | |
1643 | } | |
1644 | ||
1645 | static const char *pl011_type(struct uart_port *port) | |
1646 | { | |
e8a7ba86 RK |
1647 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1648 | return uap->port.type == PORT_AMBA ? uap->type : NULL; | |
1da177e4 LT |
1649 | } |
1650 | ||
1651 | /* | |
1652 | * Release the memory region(s) being used by 'port' | |
1653 | */ | |
1654 | static void pl010_release_port(struct uart_port *port) | |
1655 | { | |
1656 | release_mem_region(port->mapbase, SZ_4K); | |
1657 | } | |
1658 | ||
1659 | /* | |
1660 | * Request the memory region(s) being used by 'port' | |
1661 | */ | |
1662 | static int pl010_request_port(struct uart_port *port) | |
1663 | { | |
1664 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1665 | != NULL ? 0 : -EBUSY; | |
1666 | } | |
1667 | ||
1668 | /* | |
1669 | * Configure/autoconfigure the port. | |
1670 | */ | |
1671 | static void pl010_config_port(struct uart_port *port, int flags) | |
1672 | { | |
1673 | if (flags & UART_CONFIG_TYPE) { | |
1674 | port->type = PORT_AMBA; | |
1675 | pl010_request_port(port); | |
1676 | } | |
1677 | } | |
1678 | ||
1679 | /* | |
1680 | * verify the new serial_struct (for TIOCSSERIAL). | |
1681 | */ | |
1682 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1683 | { | |
1684 | int ret = 0; | |
1685 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1686 | ret = -EINVAL; | |
a62c4133 | 1687 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1688 | ret = -EINVAL; |
1689 | if (ser->baud_base < 9600) | |
1690 | ret = -EINVAL; | |
1691 | return ret; | |
1692 | } | |
1693 | ||
1694 | static struct uart_ops amba_pl011_pops = { | |
1695 | .tx_empty = pl01x_tx_empty, | |
1696 | .set_mctrl = pl011_set_mctrl, | |
1697 | .get_mctrl = pl01x_get_mctrl, | |
1698 | .stop_tx = pl011_stop_tx, | |
1699 | .start_tx = pl011_start_tx, | |
1700 | .stop_rx = pl011_stop_rx, | |
1701 | .enable_ms = pl011_enable_ms, | |
1702 | .break_ctl = pl011_break_ctl, | |
1703 | .startup = pl011_startup, | |
1704 | .shutdown = pl011_shutdown, | |
68b65f73 | 1705 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
1706 | .set_termios = pl011_set_termios, |
1707 | .type = pl011_type, | |
1708 | .release_port = pl010_release_port, | |
1709 | .request_port = pl010_request_port, | |
1710 | .config_port = pl010_config_port, | |
1711 | .verify_port = pl010_verify_port, | |
84b5ae15 JW |
1712 | #ifdef CONFIG_CONSOLE_POLL |
1713 | .poll_get_char = pl010_get_poll_char, | |
1714 | .poll_put_char = pl010_put_poll_char, | |
1715 | #endif | |
1da177e4 LT |
1716 | }; |
1717 | ||
1718 | static struct uart_amba_port *amba_ports[UART_NR]; | |
1719 | ||
1720 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
1721 | ||
d358788f | 1722 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 1723 | { |
d358788f | 1724 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 | 1725 | |
d358788f RK |
1726 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
1727 | barrier(); | |
1da177e4 LT |
1728 | writew(ch, uap->port.membase + UART01x_DR); |
1729 | } | |
1730 | ||
1731 | static void | |
1732 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
1733 | { | |
1734 | struct uart_amba_port *uap = amba_ports[co->index]; | |
1735 | unsigned int status, old_cr, new_cr; | |
1da177e4 LT |
1736 | |
1737 | clk_enable(uap->clk); | |
1738 | ||
1739 | /* | |
1740 | * First save the CR then disable the interrupts | |
1741 | */ | |
1742 | old_cr = readw(uap->port.membase + UART011_CR); | |
1743 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
1744 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1745 | writew(new_cr, uap->port.membase + UART011_CR); | |
1746 | ||
d358788f | 1747 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
1748 | |
1749 | /* | |
1750 | * Finally, wait for transmitter to become empty | |
1751 | * and restore the TCR | |
1752 | */ | |
1753 | do { | |
1754 | status = readw(uap->port.membase + UART01x_FR); | |
1755 | } while (status & UART01x_FR_BUSY); | |
1756 | writew(old_cr, uap->port.membase + UART011_CR); | |
1757 | ||
1758 | clk_disable(uap->clk); | |
1759 | } | |
1760 | ||
1761 | static void __init | |
1762 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
1763 | int *parity, int *bits) | |
1764 | { | |
1765 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
1766 | unsigned int lcr_h, ibrd, fbrd; | |
1767 | ||
ec489aa8 | 1768 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1769 | |
1770 | *parity = 'n'; | |
1771 | if (lcr_h & UART01x_LCRH_PEN) { | |
1772 | if (lcr_h & UART01x_LCRH_EPS) | |
1773 | *parity = 'e'; | |
1774 | else | |
1775 | *parity = 'o'; | |
1776 | } | |
1777 | ||
1778 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
1779 | *bits = 7; | |
1780 | else | |
1781 | *bits = 8; | |
1782 | ||
1783 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
1784 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
1785 | ||
1786 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 1787 | |
c19f12b5 | 1788 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
1789 | if (readw(uap->port.membase + UART011_CR) |
1790 | & ST_UART011_CR_OVSFACT) | |
1791 | *baud *= 2; | |
1792 | } | |
1da177e4 LT |
1793 | } |
1794 | } | |
1795 | ||
1796 | static int __init pl011_console_setup(struct console *co, char *options) | |
1797 | { | |
1798 | struct uart_amba_port *uap; | |
1799 | int baud = 38400; | |
1800 | int bits = 8; | |
1801 | int parity = 'n'; | |
1802 | int flow = 'n'; | |
1803 | ||
1804 | /* | |
1805 | * Check whether an invalid uart number has been specified, and | |
1806 | * if so, search for the first available port that does have | |
1807 | * console support. | |
1808 | */ | |
1809 | if (co->index >= UART_NR) | |
1810 | co->index = 0; | |
1811 | uap = amba_ports[co->index]; | |
d28122a5 RK |
1812 | if (!uap) |
1813 | return -ENODEV; | |
1da177e4 | 1814 | |
c16d51a3 SKS |
1815 | if (uap->port.dev->platform_data) { |
1816 | struct amba_pl011_data *plat; | |
1817 | ||
1818 | plat = uap->port.dev->platform_data; | |
1819 | if (plat->init) | |
1820 | plat->init(); | |
1821 | } | |
1822 | ||
1da177e4 LT |
1823 | uap->port.uartclk = clk_get_rate(uap->clk); |
1824 | ||
1825 | if (options) | |
1826 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1827 | else | |
1828 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
1829 | ||
1830 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
1831 | } | |
1832 | ||
2d93486c | 1833 | static struct uart_driver amba_reg; |
1da177e4 LT |
1834 | static struct console amba_console = { |
1835 | .name = "ttyAMA", | |
1836 | .write = pl011_console_write, | |
1837 | .device = uart_console_device, | |
1838 | .setup = pl011_console_setup, | |
1839 | .flags = CON_PRINTBUFFER, | |
1840 | .index = -1, | |
1841 | .data = &amba_reg, | |
1842 | }; | |
1843 | ||
1844 | #define AMBA_CONSOLE (&amba_console) | |
1845 | #else | |
1846 | #define AMBA_CONSOLE NULL | |
1847 | #endif | |
1848 | ||
1849 | static struct uart_driver amba_reg = { | |
1850 | .owner = THIS_MODULE, | |
1851 | .driver_name = "ttyAMA", | |
1852 | .dev_name = "ttyAMA", | |
1853 | .major = SERIAL_AMBA_MAJOR, | |
1854 | .minor = SERIAL_AMBA_MINOR, | |
1855 | .nr = UART_NR, | |
1856 | .cons = AMBA_CONSOLE, | |
1857 | }; | |
1858 | ||
aa25afad | 1859 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 LT |
1860 | { |
1861 | struct uart_amba_port *uap; | |
5926a295 | 1862 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
1863 | void __iomem *base; |
1864 | int i, ret; | |
1865 | ||
1866 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1867 | if (amba_ports[i] == NULL) | |
1868 | break; | |
1869 | ||
1870 | if (i == ARRAY_SIZE(amba_ports)) { | |
1871 | ret = -EBUSY; | |
1872 | goto out; | |
1873 | } | |
1874 | ||
dd00cc48 | 1875 | uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); |
1da177e4 LT |
1876 | if (uap == NULL) { |
1877 | ret = -ENOMEM; | |
1878 | goto out; | |
1879 | } | |
1880 | ||
dc890c2d | 1881 | base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1882 | if (!base) { |
1883 | ret = -ENOMEM; | |
1884 | goto free; | |
1885 | } | |
1886 | ||
ee569c43 | 1887 | uap->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1888 | if (IS_ERR(uap->clk)) { |
1889 | ret = PTR_ERR(uap->clk); | |
1890 | goto unmap; | |
1891 | } | |
1892 | ||
c19f12b5 | 1893 | uap->vendor = vendor; |
ec489aa8 LW |
1894 | uap->lcrh_rx = vendor->lcrh_rx; |
1895 | uap->lcrh_tx = vendor->lcrh_tx; | |
ffca2b11 | 1896 | uap->fifosize = vendor->fifosize; |
c16d51a3 | 1897 | uap->interrupt_may_hang = vendor->interrupt_may_hang; |
1da177e4 LT |
1898 | uap->port.dev = &dev->dev; |
1899 | uap->port.mapbase = dev->res.start; | |
1900 | uap->port.membase = base; | |
1901 | uap->port.iotype = UPIO_MEM; | |
1902 | uap->port.irq = dev->irq[0]; | |
ffca2b11 | 1903 | uap->port.fifosize = uap->fifosize; |
1da177e4 LT |
1904 | uap->port.ops = &amba_pl011_pops; |
1905 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
1906 | uap->port.line = i; | |
68b65f73 | 1907 | pl011_dma_probe(uap); |
1da177e4 | 1908 | |
e8a7ba86 RK |
1909 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
1910 | ||
1da177e4 LT |
1911 | amba_ports[i] = uap; |
1912 | ||
1913 | amba_set_drvdata(dev, uap); | |
1914 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
1915 | if (ret) { | |
1916 | amba_set_drvdata(dev, NULL); | |
1917 | amba_ports[i] = NULL; | |
68b65f73 | 1918 | pl011_dma_remove(uap); |
1da177e4 LT |
1919 | clk_put(uap->clk); |
1920 | unmap: | |
1921 | iounmap(base); | |
1922 | free: | |
1923 | kfree(uap); | |
1924 | } | |
1925 | out: | |
1926 | return ret; | |
1927 | } | |
1928 | ||
1929 | static int pl011_remove(struct amba_device *dev) | |
1930 | { | |
1931 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1932 | int i; | |
1933 | ||
1934 | amba_set_drvdata(dev, NULL); | |
1935 | ||
1936 | uart_remove_one_port(&amba_reg, &uap->port); | |
1937 | ||
1938 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1939 | if (amba_ports[i] == uap) | |
1940 | amba_ports[i] = NULL; | |
1941 | ||
68b65f73 | 1942 | pl011_dma_remove(uap); |
1da177e4 | 1943 | iounmap(uap->port.membase); |
1da177e4 LT |
1944 | clk_put(uap->clk); |
1945 | kfree(uap); | |
1946 | return 0; | |
1947 | } | |
1948 | ||
b736b89f LC |
1949 | #ifdef CONFIG_PM |
1950 | static int pl011_suspend(struct amba_device *dev, pm_message_t state) | |
1951 | { | |
1952 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1953 | ||
1954 | if (!uap) | |
1955 | return -EINVAL; | |
1956 | ||
1957 | return uart_suspend_port(&amba_reg, &uap->port); | |
1958 | } | |
1959 | ||
1960 | static int pl011_resume(struct amba_device *dev) | |
1961 | { | |
1962 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1963 | ||
1964 | if (!uap) | |
1965 | return -EINVAL; | |
1966 | ||
1967 | return uart_resume_port(&amba_reg, &uap->port); | |
1968 | } | |
1969 | #endif | |
1970 | ||
2c39c9e1 | 1971 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
1972 | { |
1973 | .id = 0x00041011, | |
1974 | .mask = 0x000fffff, | |
5926a295 AR |
1975 | .data = &vendor_arm, |
1976 | }, | |
1977 | { | |
1978 | .id = 0x00380802, | |
1979 | .mask = 0x00ffffff, | |
1980 | .data = &vendor_st, | |
1da177e4 LT |
1981 | }, |
1982 | { 0, 0 }, | |
1983 | }; | |
1984 | ||
1985 | static struct amba_driver pl011_driver = { | |
1986 | .drv = { | |
1987 | .name = "uart-pl011", | |
1988 | }, | |
1989 | .id_table = pl011_ids, | |
1990 | .probe = pl011_probe, | |
1991 | .remove = pl011_remove, | |
b736b89f LC |
1992 | #ifdef CONFIG_PM |
1993 | .suspend = pl011_suspend, | |
1994 | .resume = pl011_resume, | |
1995 | #endif | |
1da177e4 LT |
1996 | }; |
1997 | ||
1998 | static int __init pl011_init(void) | |
1999 | { | |
2000 | int ret; | |
2001 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); | |
2002 | ||
2003 | ret = uart_register_driver(&amba_reg); | |
2004 | if (ret == 0) { | |
2005 | ret = amba_driver_register(&pl011_driver); | |
2006 | if (ret) | |
2007 | uart_unregister_driver(&amba_reg); | |
2008 | } | |
2009 | return ret; | |
2010 | } | |
2011 | ||
2012 | static void __exit pl011_exit(void) | |
2013 | { | |
2014 | amba_driver_unregister(&pl011_driver); | |
2015 | uart_unregister_driver(&amba_reg); | |
2016 | } | |
2017 | ||
4dd9e742 AR |
2018 | /* |
2019 | * While this can be a module, if builtin it's most likely the console | |
2020 | * So let's leave module_exit but move module_init to an earlier place | |
2021 | */ | |
2022 | arch_initcall(pl011_init); | |
1da177e4 LT |
2023 | module_exit(pl011_exit); |
2024 | ||
2025 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2026 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2027 | MODULE_LICENSE("GPL"); |