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KVM: x86 emulator: Rename emulate_xxx() to em_xxx()
[deliverable/linux.git] / drivers / tty / serial / bfin_sport_uart.c
CommitLineData
2f351741 1/*
ccf68e59 2 * Blackfin On-Chip Sport Emulated UART Driver
2f351741 3 *
ccf68e59 4 * Copyright 2006-2009 Analog Devices Inc.
2f351741 5 *
ccf68e59 6 * Enter bugs at http://blackfin.uclinux.org/
2f351741 7 *
ccf68e59 8 * Licensed under the GPL-2 or later.
2f351741
BW		 9 */
10
11/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
631dd1a8 13 * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
2f351741
BW		 14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
ccf68e59 16 * Transmit Frame Sync is not used by this driver to transfer data out.
2f351741
BW		 17 */
18
ccf68e59 19/* #define DEBUG */
2f351741 20
ccf68e59 21#define DRV_NAME "bfin-sport-uart"
22#define DEVICE_NAME "ttySS"
23#define pr_fmt(fmt) DRV_NAME ": " fmt
2f351741
BW		 24
25#include <linux/module.h>
26#include <linux/ioport.h>
ccf68e59 27#include <linux/io.h>
2f351741
BW		 28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
5a0e3ad6 31#include <linux/slab.h>
2f351741
BW		 32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36
2ce1efc9 37#include <asm/bfin_sport.h>
2f351741
BW		 38#include <asm/delay.h>
39#include <asm/portmux.h>
40
41#include "bfin_sport_uart.h"
42
2f351741
BW		 43struct sport_uart_port {
44 struct uart_port port;
2f351741 45 int err_irq;
ccf68e59 46 unsigned short csize;
47 unsigned short rxmask;
48 unsigned short txmask1;
49 unsigned short txmask2;
50 unsigned char stopb;
51/* unsigned char parib; */
1f7d1c85
SZ		 52#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
53 int cts_pin;
54 int rts_pin;
55#endif
2f351741
BW		 56};
57
9356c461 58static int sport_uart_tx_chars(struct sport_uart_port *up);
2f351741
BW		 59static void sport_stop_tx(struct uart_port *port);
60
61static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
62{
ccf68e59 63 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
64 up->txmask1, up->txmask2);
65
66 /* Place Start and Stop bits */
4328e3e5 67 __asm__ __volatile__ (
ccf68e59 68 "%[val] <<= 1;"
69 "%[val] = %[val] & %[mask1];"
70 "%[val] = %[val] | %[mask2];"
71 : [val]"+d"(value)
72 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
73 : "ASTAT"
4328e3e5 74 );
6ef53066 75 pr_debug("%s value:%x\n", __func__, value);
2f351741
BW		 76
77 SPORT_PUT_TX(up, value);
78}
79
ccf68e59 80static inline unsigned char rx_one_byte(struct sport_uart_port *up)
2f351741 81{
ccf68e59 82 unsigned int value;
83 unsigned char extract;
4328e3e5 84 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
2f351741 85
ccf68e59 86 if ((up->csize + up->stopb) > 7)
87 value = SPORT_GET_RX32(up);
88 else
89 value = SPORT_GET_RX(up);
90
91 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
92 up->csize, up->rxmask);
2f351741 93
ccf68e59 94 /* Extract data */
4328e3e5
MF		 95 __asm__ __volatile__ (
96 "%[extr] = 0;"
ccf68e59 97 "%[mask1] = %[rxmask];"
98 "%[mask2] = 0x0200(Z);"
4328e3e5
MF		 99 "%[shift] = 0;"
100 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
101 ".Lloop_s:"
102 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
103 "%[tmp] <<= %[shift];"
104 "%[extr] = %[extr] | %[tmp];"
105 "%[mask1] = %[mask1] - %[mask2];"
106 ".Lloop_e:"
107 "%[shift] += 1;"
ccf68e59 108 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
109 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
110 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
4328e3e5
MF		 111 : "ASTAT", "LB0", "LC0", "LT0"
112 );
2f351741
BW		 113
114 pr_debug(" extract:%x\n", extract);
115 return extract;
116}
117
ccf68e59 118static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
2f351741 119{
ccf68e59 120 int tclkdiv, rclkdiv;
121 unsigned int sclk = get_sclk();
2f351741 122
ccf68e59 123 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
33674691 124 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
ccf68e59 125 SPORT_PUT_TCR2(up, size + 1);
6ef53066 126 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
2f351741
BW		 127
128 /* Set RCR1 and RCR2 */
129 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
ccf68e59 130 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
6ef53066 131 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
2f351741 132
ccf68e59 133 tclkdiv = sclk / (2 * baud_rate) - 1;
0dd25df1
SZ		 134 /* The actual uart baud rate of devices vary between +/-2%. The sport
135 * RX sample rate should be faster than the double of the worst case,
136 * otherwise, wrong data are received. So, set sport RX clock to be
137 * 3% faster.
138 */
139 rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
2f351741 140 SPORT_PUT_TCLKDIV(up, tclkdiv);
2f351741
BW		 141 SPORT_PUT_RCLKDIV(up, rclkdiv);
142 SSYNC();
ccf68e59 143 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
144 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
2f351741
BW		 145
146 return 0;
147}
148
149static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
150{
151 struct sport_uart_port *up = dev_id;
ebd2c8f6 152 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW		 153 unsigned int ch;
154
ccf68e59 155 spin_lock(&up->port.lock);
156
157 while (SPORT_GET_STAT(up) & RXNE) {
2f351741
BW		 158 ch = rx_one_byte(up);
159 up->port.icount.rx++;
160
ccf68e59 161 if (!uart_handle_sysrq_char(&up->port, ch))
2f351741 162 tty_insert_flip_char(tty, ch, TTY_NORMAL);
ccf68e59 163 }
2f351741
BW		 164 tty_flip_buffer_push(tty);
165
ccf68e59 166 spin_unlock(&up->port.lock);
167
2f351741
BW		 168 return IRQ_HANDLED;
169}
170
171static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
172{
ccf68e59 173 struct sport_uart_port *up = dev_id;
174
175 spin_lock(&up->port.lock);
176 sport_uart_tx_chars(up);
177 spin_unlock(&up->port.lock);
2f351741
BW		 178
179 return IRQ_HANDLED;
180}
181
182static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
183{
184 struct sport_uart_port *up = dev_id;
ebd2c8f6 185 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW		 186 unsigned int stat = SPORT_GET_STAT(up);
187
ccf68e59 188 spin_lock(&up->port.lock);
189
2f351741
BW		 190 /* Overflow in RX FIFO */
191 if (stat & ROVF) {
192 up->port.icount.overrun++;
193 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
194 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
195 }
196 /* These should not happen */
197 if (stat & (TOVF | TUVF | RUVF)) {
ccf68e59 198 pr_err("SPORT Error:%s %s %s\n",
199 (stat & TOVF) ? "TX overflow" : "",
200 (stat & TUVF) ? "TX underflow" : "",
201 (stat & RUVF) ? "RX underflow" : "");
2f351741
BW		 202 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
203 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
204 }
205 SSYNC();
206
ccf68e59 207 spin_unlock(&up->port.lock);
2f351741
BW		 208 return IRQ_HANDLED;
209}
210
1f7d1c85
SZ		 211#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
212static unsigned int sport_get_mctrl(struct uart_port *port)
213{
214 struct sport_uart_port *up = (struct sport_uart_port *)port;
215 if (up->cts_pin < 0)
216 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
217
218 /* CTS PIN is negative assertive. */
219 if (SPORT_UART_GET_CTS(up))
220 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
221 else
222 return TIOCM_DSR | TIOCM_CAR;
223}
224
225static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
226{
227 struct sport_uart_port *up = (struct sport_uart_port *)port;
228 if (up->rts_pin < 0)
229 return;
230
231 /* RTS PIN is negative assertive. */
232 if (mctrl & TIOCM_RTS)
233 SPORT_UART_ENABLE_RTS(up);
234 else
235 SPORT_UART_DISABLE_RTS(up);
236}
237
238/*
239 * Handle any change of modem status signal.
240 */
241static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
242{
243 struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
244 unsigned int status;
245
246 status = sport_get_mctrl(&up->port);
247 uart_handle_cts_change(&up->port, status & TIOCM_CTS);
248
249 return IRQ_HANDLED;
250}
251#else
252static unsigned int sport_get_mctrl(struct uart_port *port)
253{
254 pr_debug("%s enter\n", __func__);
255 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
256}
257
258static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
259{
260 pr_debug("%s enter\n", __func__);
261}
262#endif
263
2f351741
BW		 264/* Reqeust IRQ, Setup clock */
265static int sport_startup(struct uart_port *port)
266{
267 struct sport_uart_port *up = (struct sport_uart_port *)port;
ccf68e59 268 int ret;
2f351741 269
6ef53066 270 pr_debug("%s enter\n", __func__);
ccf68e59 271 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
272 "SPORT_UART_RX", up);
273 if (ret) {
274 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
275 return ret;
2f351741
BW		 276 }
277
ccf68e59 278 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
279 "SPORT_UART_TX", up);
280 if (ret) {
281 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
2f351741
BW		 282 goto fail1;
283 }
284
ccf68e59 285 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
286 "SPORT_UART_STATUS", up);
287 if (ret) {
288 dev_err(port->dev, "unable to request SPORT status interrupt\n");
2f351741
BW		 289 goto fail2;
290 }
291
1f7d1c85
SZ		 292#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
293 if (up->cts_pin >= 0) {
294 if (request_irq(gpio_to_irq(up->cts_pin),
295 sport_mctrl_cts_int,
296 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
297 IRQF_DISABLED, "BFIN_SPORT_UART_CTS", up)) {
298 up->cts_pin = -1;
85ee7a1d 299 dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n");
1f7d1c85
SZ		 300 }
301 }
302 if (up->rts_pin >= 0)
303 gpio_direction_output(up->rts_pin, 0);
304#endif
305
2f351741 306 return 0;
ccf68e59 307 fail2:
308 free_irq(up->port.irq+1, up);
309 fail1:
310 free_irq(up->port.irq, up);
2f351741 311
ccf68e59 312 return ret;
2f351741
BW		 313}
314
9356c461
SZ		 315/*
316 * sport_uart_tx_chars
317 *
318 * ret 1 means need to enable sport.
319 * ret 0 means do nothing.
320 */
321static int sport_uart_tx_chars(struct sport_uart_port *up)
2f351741 322{
ebd2c8f6 323 struct circ_buf *xmit = &up->port.state->xmit;
2f351741
BW		 324
325 if (SPORT_GET_STAT(up) & TXF)
9356c461 326 return 0;
2f351741
BW		 327
328 if (up->port.x_char) {
329 tx_one_byte(up, up->port.x_char);
330 up->port.icount.tx++;
331 up->port.x_char = 0;
9356c461 332 return 1;
2f351741
BW		 333 }
334
335 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
3f3a978b
SZ		 336 /* The waiting loop to stop SPORT TX from TX interrupt is
337 * too long. This may block SPORT RX interrupts and cause
338 * RX FIFO overflow. So, do stop sport TX only after the last
339 * char in TX FIFO is moved into the shift register.
340 */
341 if (SPORT_GET_STAT(up) & TXHRE)
342 sport_stop_tx(&up->port);
9356c461 343 return 0;
2f351741
BW		 344 }
345
346 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
347 tx_one_byte(up, xmit->buf[xmit->tail]);
348 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
349 up->port.icount.tx++;
350 }
351
352 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
353 uart_write_wakeup(&up->port);
9356c461
SZ		 354
355 return 1;
2f351741
BW		 356}
357
358static unsigned int sport_tx_empty(struct uart_port *port)
359{
360 struct sport_uart_port *up = (struct sport_uart_port *)port;
361 unsigned int stat;
362
363 stat = SPORT_GET_STAT(up);
6ef53066 364 pr_debug("%s stat:%04x\n", __func__, stat);
2f351741
BW		 365 if (stat & TXHRE) {
366 return TIOCSER_TEMT;
367 } else
368 return 0;
369}
370
2f351741
BW		 371static void sport_stop_tx(struct uart_port *port)
372{
373 struct sport_uart_port *up = (struct sport_uart_port *)port;
2f351741 374
6ef53066 375 pr_debug("%s enter\n", __func__);
2f351741 376
9356c461
SZ		 377 if (!(SPORT_GET_TCR1(up) & TSPEN))
378 return;
379
2f351741 380 /* Although the hold register is empty, last byte is still in shift
ccf68e59 381 * register and not sent out yet. So, put a dummy data into TX FIFO.
382 * Then, sport tx stops when last byte is shift out and the dummy
383 * data is moved into the shift register.
384 */
385 SPORT_PUT_TX(up, 0xffff);
386 while (!(SPORT_GET_STAT(up) & TXHRE))
387 cpu_relax();
2f351741
BW		 388
389 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
390 SSYNC();
391
392 return;
393}
394
395static void sport_start_tx(struct uart_port *port)
396{
397 struct sport_uart_port *up = (struct sport_uart_port *)port;
398
6ef53066 399 pr_debug("%s enter\n", __func__);
ccf68e59 400
2f351741 401 /* Write data into SPORT FIFO before enable SPROT to transmit */
9356c461
SZ		 402 if (sport_uart_tx_chars(up)) {
403 /* Enable transmit, then an interrupt will generated */
404 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
405 SSYNC();
406 }
2f351741 407
6ef53066 408 pr_debug("%s exit\n", __func__);
2f351741
BW		 409}
410
411static void sport_stop_rx(struct uart_port *port)
412{
413 struct sport_uart_port *up = (struct sport_uart_port *)port;
414
6ef53066 415 pr_debug("%s enter\n", __func__);
2f351741
BW		 416 /* Disable sport to stop rx */
417 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
418 SSYNC();
419}
420
421static void sport_enable_ms(struct uart_port *port)
422{
6ef53066 423 pr_debug("%s enter\n", __func__);
2f351741
BW		 424}
425
426static void sport_break_ctl(struct uart_port *port, int break_state)
427{
6ef53066 428 pr_debug("%s enter\n", __func__);
2f351741
BW		 429}
430
431static void sport_shutdown(struct uart_port *port)
432{
433 struct sport_uart_port *up = (struct sport_uart_port *)port;
434
ccf68e59 435 dev_dbg(port->dev, "%s enter\n", __func__);
2f351741
BW		 436
437 /* Disable sport */
438 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
439 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
440 SSYNC();
441
ccf68e59 442 free_irq(up->port.irq, up);
443 free_irq(up->port.irq+1, up);
2f351741 444 free_irq(up->err_irq, up);
1f7d1c85
SZ		 445#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
446 if (up->cts_pin >= 0)
447 free_irq(gpio_to_irq(up->cts_pin), up);
448#endif
2f351741
BW		 449}
450
2f351741
BW		 451static const char *sport_type(struct uart_port *port)
452{
453 struct sport_uart_port *up = (struct sport_uart_port *)port;
454
6ef53066 455 pr_debug("%s enter\n", __func__);
ccf68e59 456 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
2f351741
BW		 457}
458
459static void sport_release_port(struct uart_port *port)
460{
6ef53066 461 pr_debug("%s enter\n", __func__);
2f351741
BW		 462}
463
464static int sport_request_port(struct uart_port *port)
465{
6ef53066 466 pr_debug("%s enter\n", __func__);
2f351741
BW		 467 return 0;
468}
469
470static void sport_config_port(struct uart_port *port, int flags)
471{
472 struct sport_uart_port *up = (struct sport_uart_port *)port;
473
6ef53066 474 pr_debug("%s enter\n", __func__);
2f351741
BW		 475 up->port.type = PORT_BFIN_SPORT;
476}
477
478static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
479{
6ef53066 480 pr_debug("%s enter\n", __func__);
2f351741
BW		 481 return 0;
482}
483
ccf68e59 484static void sport_set_termios(struct uart_port *port,
485 struct ktermios *termios, struct ktermios *old)
486{
487 struct sport_uart_port *up = (struct sport_uart_port *)port;
488 unsigned long flags;
489 int i;
490
491 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
492
493 switch (termios->c_cflag & CSIZE) {
494 case CS8:
495 up->csize = 8;
496 break;
497 case CS7:
498 up->csize = 7;
499 break;
500 case CS6:
501 up->csize = 6;
502 break;
503 case CS5:
504 up->csize = 5;
505 break;
506 default:
507 pr_warning("requested word length not supported\n");
508 }
509
510 if (termios->c_cflag & CSTOPB) {
511 up->stopb = 1;
512 }
513 if (termios->c_cflag & PARENB) {
514 pr_warning("PAREN bits is not supported yet\n");
515 /* up->parib = 1; */
516 }
517
9498dc95
SZ		 518 spin_lock_irqsave(&up->port.lock, flags);
519
60bd940f 520 port->read_status_mask = 0;
ccf68e59 521
522 /*
523 * Characters to ignore
524 */
525 port->ignore_status_mask = 0;
ccf68e59 526
527 /* RX extract mask */
528 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
529 /* TX masks, 8 bit data and 1 bit stop for example:
530 * mask1 = b#0111111110
531 * mask2 = b#1000000000
532 */
533 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
534 up->txmask1 |= (1<<i);
535 up->txmask2 = (1<<i);
536 if (up->stopb) {
537 ++i;
538 up->txmask2 |= (1<<i);
539 }
540 up->txmask1 <<= 1;
541 up->txmask2 <<= 1;
542 /* uart baud rate */
543 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
544
ccf68e59 545 /* Disable UART */
546 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
547 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
548
549 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
550
551 /* driver TX line high after config, one dummy data is
552 * necessary to stop sport after shift one byte
553 */
554 SPORT_PUT_TX(up, 0xffff);
555 SPORT_PUT_TX(up, 0xffff);
556 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
557 SSYNC();
558 while (!(SPORT_GET_STAT(up) & TXHRE))
559 cpu_relax();
560 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
561 SSYNC();
562
563 /* Port speed changed, update the per-port timeout. */
564 uart_update_timeout(port, termios->c_cflag, port->uartclk);
565
566 /* Enable sport rx */
567 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
568 SSYNC();
569
570 spin_unlock_irqrestore(&up->port.lock, flags);
571}
572
2f351741
BW		 573struct uart_ops sport_uart_ops = {
574 .tx_empty = sport_tx_empty,
575 .set_mctrl = sport_set_mctrl,
576 .get_mctrl = sport_get_mctrl,
577 .stop_tx = sport_stop_tx,
578 .start_tx = sport_start_tx,
579 .stop_rx = sport_stop_rx,
580 .enable_ms = sport_enable_ms,
581 .break_ctl = sport_break_ctl,
582 .startup = sport_startup,
583 .shutdown = sport_shutdown,
584 .set_termios = sport_set_termios,
585 .type = sport_type,
586 .release_port = sport_release_port,
587 .request_port = sport_request_port,
588 .config_port = sport_config_port,
589 .verify_port = sport_verify_port,
590};
591
ccf68e59 592#define BFIN_SPORT_UART_MAX_PORTS 4
593
594static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
595
596#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
b59588aa
SZ		 597#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
598
ccf68e59 599static int __init
600sport_uart_console_setup(struct console *co, char *options)
601{
602 struct sport_uart_port *up;
603 int baud = 57600;
604 int bits = 8;
605 int parity = 'n';
1f7d1c85
SZ		 606# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
607 int flow = 'r';
608# else
ccf68e59 609 int flow = 'n';
1f7d1c85 610# endif
ccf68e59 611
612 /* Check whether an invalid uart number has been specified */
613 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
614 return -ENODEV;
615
616 up = bfin_sport_uart_ports[co->index];
617 if (!up)
618 return -ENODEV;
619
620 if (options)
621 uart_parse_options(options, &baud, &parity, &bits, &flow);
622
623 return uart_set_options(&up->port, co, baud, parity, bits, flow);
624}
625
626static void sport_uart_console_putchar(struct uart_port *port, int ch)
627{
628 struct sport_uart_port *up = (struct sport_uart_port *)port;
629
630 while (SPORT_GET_STAT(up) & TXF)
631 barrier();
632
633 tx_one_byte(up, ch);
634}
635
636/*
637 * Interrupts are disabled on entering
638 */
639static void
640sport_uart_console_write(struct console *co, const char *s, unsigned int count)
641{
642 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
643 unsigned long flags;
644
645 spin_lock_irqsave(&up->port.lock, flags);
646
647 if (SPORT_GET_TCR1(up) & TSPEN)
648 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
649 else {
650 /* dummy data to start sport */
651 while (SPORT_GET_STAT(up) & TXF)
652 barrier();
653 SPORT_PUT_TX(up, 0xffff);
654 /* Enable transmit, then an interrupt will generated */
655 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
656 SSYNC();
657
658 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
659
660 /* Although the hold register is empty, last byte is still in shift
661 * register and not sent out yet. So, put a dummy data into TX FIFO.
662 * Then, sport tx stops when last byte is shift out and the dummy
663 * data is moved into the shift register.
664 */
665 while (SPORT_GET_STAT(up) & TXF)
666 barrier();
667 SPORT_PUT_TX(up, 0xffff);
668 while (!(SPORT_GET_STAT(up) & TXHRE))
669 barrier();
670
671 /* Stop sport tx transfer */
672 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
673 SSYNC();
2f351741 674 }
ccf68e59 675
676 spin_unlock_irqrestore(&up->port.lock, flags);
677}
678
679static struct uart_driver sport_uart_reg;
680
681static struct console sport_uart_console = {
682 .name = DEVICE_NAME,
683 .write = sport_uart_console_write,
684 .device = uart_console_device,
685 .setup = sport_uart_console_setup,
686 .flags = CON_PRINTBUFFER,
687 .index = -1,
688 .data = &sport_uart_reg,
2f351741
BW		 689};
690
ccf68e59 691#define SPORT_UART_CONSOLE (&sport_uart_console)
692#else
693#define SPORT_UART_CONSOLE NULL
694#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
695
696
2f351741
BW		 697static struct uart_driver sport_uart_reg = {
698 .owner = THIS_MODULE,
ccf68e59 699 .driver_name = DRV_NAME,
700 .dev_name = DEVICE_NAME,
2f351741
BW		 701 .major = 204,
702 .minor = 84,
ccf68e59 703 .nr = BFIN_SPORT_UART_MAX_PORTS,
704 .cons = SPORT_UART_CONSOLE,
2f351741
BW		 705};
706
ccf68e59 707#ifdef CONFIG_PM
708static int sport_uart_suspend(struct device *dev)
2f351741 709{
ccf68e59 710 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 711
ccf68e59 712 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 713 if (sport)
714 uart_suspend_port(&sport_uart_reg, &sport->port);
715
716 return 0;
717}
718
ccf68e59 719static int sport_uart_resume(struct device *dev)
2f351741 720{
ccf68e59 721 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 722
ccf68e59 723 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 724 if (sport)
725 uart_resume_port(&sport_uart_reg, &sport->port);
726
727 return 0;
728}
729
ccf68e59 730static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
731 .suspend = sport_uart_suspend,
732 .resume = sport_uart_resume,
733};
734#endif
735
736static int __devinit sport_uart_probe(struct platform_device *pdev)
2f351741 737{
ccf68e59 738 struct resource *res;
739 struct sport_uart_port *sport;
740 int ret = 0;
2f351741 741
ccf68e59 742 dev_dbg(&pdev->dev, "%s enter\n", __func__);
743
744 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
745 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
746 return -ENOENT;
747 }
748
749 if (bfin_sport_uart_ports[pdev->id] == NULL) {
750 bfin_sport_uart_ports[pdev->id] =
f4d10ca8 751 kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
ccf68e59 752 sport = bfin_sport_uart_ports[pdev->id];
753 if (!sport) {
754 dev_err(&pdev->dev,
f4d10ca8 755 "Fail to malloc sport_uart_port\n");
ccf68e59 756 return -ENOMEM;
757 }
758
759 ret = peripheral_request_list(
760 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
761 if (ret) {
762 dev_err(&pdev->dev,
763 "Fail to request SPORT peripherals\n");
764 goto out_error_free_mem;
765 }
766
767 spin_lock_init(&sport->port.lock);
768 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
769 sport->port.ops = &sport_uart_ops;
770 sport->port.line = pdev->id;
771 sport->port.iotype = UPIO_MEM;
772 sport->port.flags = UPF_BOOT_AUTOCONF;
773
774 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
775 if (res == NULL) {
776 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
777 ret = -ENOENT;
778 goto out_error_free_peripherals;
779 }
780
e114474c 781 sport->port.membase = ioremap(res->start, resource_size(res));
ccf68e59 782 if (!sport->port.membase) {
783 dev_err(&pdev->dev, "Cannot map sport IO\n");
784 ret = -ENXIO;
785 goto out_error_free_peripherals;
786 }
e8126b32 787 sport->port.mapbase = res->start;
ccf68e59 788
789 sport->port.irq = platform_get_irq(pdev, 0);
940f3be4 790 if ((int)sport->port.irq < 0) {
ccf68e59 791 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
792 ret = -ENOENT;
793 goto out_error_unmap;
794 }
795
796 sport->err_irq = platform_get_irq(pdev, 1);
797 if (sport->err_irq < 0) {
798 dev_err(&pdev->dev, "No sport status IRQ specified\n");
799 ret = -ENOENT;
800 goto out_error_unmap;
801 }
1f7d1c85
SZ		 802#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
803 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
804 if (res == NULL)
805 sport->cts_pin = -1;
806 else
807 sport->cts_pin = res->start;
808
809 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
810 if (res == NULL)
811 sport->rts_pin = -1;
812 else
813 sport->rts_pin = res->start;
814
815 if (sport->rts_pin >= 0)
816 gpio_request(sport->rts_pin, DRV_NAME);
817#endif
ccf68e59 818 }
819
820#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
821 if (!is_early_platform_device(pdev)) {
822#endif
823 sport = bfin_sport_uart_ports[pdev->id];
824 sport->port.dev = &pdev->dev;
825 dev_set_drvdata(&pdev->dev, sport);
826 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
827#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
828 }
829#endif
830 if (!ret)
831 return 0;
832
833 if (sport) {
834out_error_unmap:
835 iounmap(sport->port.membase);
836out_error_free_peripherals:
837 peripheral_free_list(
838 (unsigned short *)pdev->dev.platform_data);
839out_error_free_mem:
840 kfree(sport);
841 bfin_sport_uart_ports[pdev->id] = NULL;
842 }
843
844 return ret;
2f351741
BW		 845}
846
ccf68e59 847static int __devexit sport_uart_remove(struct platform_device *pdev)
2f351741 848{
ccf68e59 849 struct sport_uart_port *sport = platform_get_drvdata(pdev);
2f351741 850
ccf68e59 851 dev_dbg(&pdev->dev, "%s enter\n", __func__);
852 dev_set_drvdata(&pdev->dev, NULL);
2f351741 853
ccf68e59 854 if (sport) {
2f351741 855 uart_remove_one_port(&sport_uart_reg, &sport->port);
1f7d1c85
SZ		 856#ifdef CONFIG_SERIAL_BFIN_CTSRTS
857 if (sport->rts_pin >= 0)
858 gpio_free(sport->rts_pin);
859#endif
ccf68e59 860 iounmap(sport->port.membase);
861 peripheral_free_list(
862 (unsigned short *)pdev->dev.platform_data);
863 kfree(sport);
864 bfin_sport_uart_ports[pdev->id] = NULL;
865 }
2f351741
BW		 866
867 return 0;
868}
869
870static struct platform_driver sport_uart_driver = {
871 .probe = sport_uart_probe,
ccf68e59 872 .remove = __devexit_p(sport_uart_remove),
2f351741
BW		 873 .driver = {
874 .name = DRV_NAME,
ccf68e59 875#ifdef CONFIG_PM
876 .pm = &bfin_sport_uart_dev_pm_ops,
877#endif
2f351741
BW		 878 },
879};
880
ccf68e59 881#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
882static __initdata struct early_platform_driver early_sport_uart_driver = {
b59588aa 883 .class_str = CLASS_BFIN_SPORT_CONSOLE,
ccf68e59 884 .pdrv = &sport_uart_driver,
885 .requested_id = EARLY_PLATFORM_ID_UNSET,
886};
887
888static int __init sport_uart_rs_console_init(void)
889{
890 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
891
b59588aa
SZ		 892 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
893 BFIN_SPORT_UART_MAX_PORTS, 0);
ccf68e59 894
895 register_console(&sport_uart_console);
896
897 return 0;
898}
899console_initcall(sport_uart_rs_console_init);
900#endif
901
2f351741
BW		 902static int __init sport_uart_init(void)
903{
904 int ret;
905
e8126b32 906 pr_info("Blackfin uart over sport driver\n");
ccf68e59 907
2f351741 908 ret = uart_register_driver(&sport_uart_reg);
ccf68e59 909 if (ret) {
910 pr_err("failed to register %s:%d\n",
2f351741
BW		 911 sport_uart_reg.driver_name, ret);
912 return ret;
913 }
914
915 ret = platform_driver_register(&sport_uart_driver);
ccf68e59 916 if (ret) {
917 pr_err("failed to register sport uart driver:%d\n", ret);
2f351741
BW		 918 uart_unregister_driver(&sport_uart_reg);
919 }
920
2f351741
BW		 921 return ret;
922}
ccf68e59 923module_init(sport_uart_init);
2f351741
BW		 924
925static void __exit sport_uart_exit(void)
926{
2f351741
BW		 927 platform_driver_unregister(&sport_uart_driver);
928 uart_unregister_driver(&sport_uart_reg);
929}
2f351741
BW		 930module_exit(sport_uart_exit);
931
ccf68e59 932MODULE_AUTHOR("Sonic Zhang, Roy Huang");
933MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
2f351741 934MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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