[deliverable/linux.git] / drivers / tty / serial / clps711x.c

/*
 *  Driver for CLPS711x serial ports
 *
 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
 *
 *  Copyright 1999 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif

#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <linux/platform_device.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#define UART_CLPS711X_NAME	"uart-clps711x"
#define UART_CLPS711X_NR	2
#define UART_CLPS711X_MAJOR	204
#define UART_CLPS711X_MINOR	40

#define UBRLCR(port)		((port)->line ? UBRLCR2 : UBRLCR1)
#define UARTDR(port)		((port)->line ? UARTDR2 : UARTDR1)
#define SYSFLG(port)		((port)->line ? SYSFLG2 : SYSFLG1)
#define SYSCON(port)		((port)->line ? SYSCON2 : SYSCON1)
#define TX_IRQ(port)		((port)->line ? IRQ_UTXINT2 : IRQ_UTXINT1)
#define RX_IRQ(port)		((port)->line ? IRQ_URXINT2 : IRQ_URXINT1)

#define UART_ANY_ERR		(UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR)

struct clps711x_port {
	struct uart_driver	uart;
	struct uart_port	port[UART_CLPS711X_NR];
	int			tx_enabled[UART_CLPS711X_NR];
#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
	struct console		console;
#endif
};

static void clps711xuart_stop_tx(struct uart_port *port)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);

	if (s->tx_enabled[port->line]) {
		disable_irq(TX_IRQ(port));
		s->tx_enabled[port->line] = 0;
	}
}

static void clps711xuart_start_tx(struct uart_port *port)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);

	if (!s->tx_enabled[port->line]) {
		enable_irq(TX_IRQ(port));
		s->tx_enabled[port->line] = 1;
	}
}

static void clps711xuart_stop_rx(struct uart_port *port)
{
	disable_irq(RX_IRQ(port));
}

static void clps711xuart_enable_ms(struct uart_port *port)
{
}

static irqreturn_t clps711xuart_int_rx(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	struct tty_struct *tty = port->state->port.tty;
	unsigned int status, ch, flg;

	status = clps_readl(SYSFLG(port));
	while (!(status & SYSFLG_URXFE)) {
		ch = clps_readl(UARTDR(port));

		port->icount.rx++;

		flg = TTY_NORMAL;

		/*
		 * Note that the error handling code is
		 * out of the main execution path
		 */
		if (unlikely(ch & UART_ANY_ERR)) {
			if (ch & UARTDR_PARERR)
				port->icount.parity++;
			else if (ch & UARTDR_FRMERR)
				port->icount.frame++;
			if (ch & UARTDR_OVERR)
				port->icount.overrun++;

			ch &= port->read_status_mask;

			if (ch & UARTDR_PARERR)
				flg = TTY_PARITY;
			else if (ch & UARTDR_FRMERR)
				flg = TTY_FRAME;

#ifdef SUPPORT_SYSRQ
			port->sysrq = 0;
#endif
		}

		if (uart_handle_sysrq_char(port, ch))
			goto ignore_char;

		/*
		 * CHECK: does overrun affect the current character?
		 * ASSUMPTION: it does not.
		 */
		uart_insert_char(port, ch, UARTDR_OVERR, ch, flg);

	ignore_char:
		status = clps_readl(SYSFLG(port));
	}
	tty_flip_buffer_push(tty);
	return IRQ_HANDLED;
}

static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	struct clps711x_port *s = dev_get_drvdata(port->dev);
	struct circ_buf *xmit = &port->state->xmit;
	int count;

	if (port->x_char) {
		clps_writel(port->x_char, UARTDR(port));
		port->icount.tx++;
		port->x_char = 0;
		return IRQ_HANDLED;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		disable_irq_nosync(TX_IRQ(port));
		s->tx_enabled[port->line] = 0;
		return IRQ_HANDLED;
	}

	count = port->fifosize >> 1;
	do {
		clps_writel(xmit->buf[xmit->tail], UARTDR(port));
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		port->icount.tx++;
		if (uart_circ_empty(xmit))
			break;
	} while (--count > 0);

	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	return IRQ_HANDLED;
}

static unsigned int clps711xuart_tx_empty(struct uart_port *port)
{
	unsigned int status = clps_readl(SYSFLG(port));
	return status & SYSFLG_UBUSY ? 0 : TIOCSER_TEMT;
}

static unsigned int clps711xuart_get_mctrl(struct uart_port *port)
{
	unsigned int port_addr;
	unsigned int result = 0;
	unsigned int status;

	port_addr = SYSFLG(port);
	if (port_addr == SYSFLG1) {
		status = clps_readl(SYSFLG1);
		if (status & SYSFLG1_DCD)
			result |= TIOCM_CAR;
		if (status & SYSFLG1_DSR)
			result |= TIOCM_DSR;
		if (status & SYSFLG1_CTS)
			result |= TIOCM_CTS;
	}

	return result;
}

static void
clps711xuart_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
{
}

static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
{
	unsigned long flags;
	unsigned int ubrlcr;

	spin_lock_irqsave(&port->lock, flags);
	ubrlcr = clps_readl(UBRLCR(port));
	if (break_state == -1)
		ubrlcr |= UBRLCR_BREAK;
	else
		ubrlcr &= ~UBRLCR_BREAK;
	clps_writel(ubrlcr, UBRLCR(port));
	spin_unlock_irqrestore(&port->lock, flags);
}

static int clps711xuart_startup(struct uart_port *port)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);
	unsigned int syscon;
	int retval;

	s->tx_enabled[port->line] = 1;

	/*
	 * Allocate the IRQs
	 */
	retval = request_irq(TX_IRQ(port), clps711xuart_int_tx, 0,
			     "clps711xuart_tx", port);
	if (retval)
		return retval;

	retval = request_irq(RX_IRQ(port), clps711xuart_int_rx, 0,
			     "clps711xuart_rx", port);
	if (retval) {
		free_irq(TX_IRQ(port), port);
		return retval;
	}

	/*
	 * enable the port
	 */
	syscon = clps_readl(SYSCON(port));
	syscon |= SYSCON_UARTEN;
	clps_writel(syscon, SYSCON(port));

	return 0;
}

static void clps711xuart_shutdown(struct uart_port *port)
{
	unsigned int ubrlcr, syscon;

	/*
	 * Free the interrupt
	 */
	free_irq(TX_IRQ(port), port);	/* TX interrupt */
	free_irq(RX_IRQ(port), port);	/* RX interrupt */

	/*
	 * disable the port
	 */
	syscon = clps_readl(SYSCON(port));
	syscon &= ~SYSCON_UARTEN;
	clps_writel(syscon, SYSCON(port));

	/*
	 * disable break condition and fifos
	 */
	ubrlcr = clps_readl(UBRLCR(port));
	ubrlcr &= ~(UBRLCR_FIFOEN | UBRLCR_BREAK);
	clps_writel(ubrlcr, UBRLCR(port));
}

static void
clps711xuart_set_termios(struct uart_port *port, struct ktermios *termios,
			 struct ktermios *old)
{
	unsigned int ubrlcr, baud, quot;
	unsigned long flags;

	/*
	 * We don't implement CREAD.
	 */
	termios->c_cflag |= CREAD;

	/*
	 * Ask the core to calculate the divisor for us.
	 */
	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 
	quot = uart_get_divisor(port, baud);

	switch (termios->c_cflag & CSIZE) {
	case CS5:
		ubrlcr = UBRLCR_WRDLEN5;
		break;
	case CS6:
		ubrlcr = UBRLCR_WRDLEN6;
		break;
	case CS7:
		ubrlcr = UBRLCR_WRDLEN7;
		break;
	default: // CS8
		ubrlcr = UBRLCR_WRDLEN8;
		break;
	}
	if (termios->c_cflag & CSTOPB)
		ubrlcr |= UBRLCR_XSTOP;
	if (termios->c_cflag & PARENB) {
		ubrlcr |= UBRLCR_PRTEN;
		if (!(termios->c_cflag & PARODD))
			ubrlcr |= UBRLCR_EVENPRT;
	}
	if (port->fifosize > 1)
		ubrlcr |= UBRLCR_FIFOEN;

	spin_lock_irqsave(&port->lock, flags);

	/*
	 * Update the per-port timeout.
	 */
	uart_update_timeout(port, termios->c_cflag, baud);

	port->read_status_mask = UARTDR_OVERR;
	if (termios->c_iflag & INPCK)
		port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;

	/*
	 * Characters to ignore
	 */
	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= UARTDR_FRMERR | UARTDR_PARERR;
	if (termios->c_iflag & IGNBRK) {
		/*
		 * If we're ignoring parity and break indicators,
		 * ignore overruns to (for real raw support).
		 */
		if (termios->c_iflag & IGNPAR)
			port->ignore_status_mask |= UARTDR_OVERR;
	}

	quot -= 1;

	clps_writel(ubrlcr | quot, UBRLCR(port));

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *clps711xuart_type(struct uart_port *port)
{
	return port->type == PORT_CLPS711X ? "CLPS711x" : NULL;
}

/*
 * Configure/autoconfigure the port.
 */
static void clps711xuart_config_port(struct uart_port *port, int flags)
{
	if (flags & UART_CONFIG_TYPE)
		port->type = PORT_CLPS711X;
}

static void clps711xuart_release_port(struct uart_port *port)
{
}

static int clps711xuart_request_port(struct uart_port *port)
{
	return 0;
}

static struct uart_ops uart_clps711x_ops = {
	.tx_empty	= clps711xuart_tx_empty,
	.set_mctrl	= clps711xuart_set_mctrl_null,
	.get_mctrl	= clps711xuart_get_mctrl,
	.stop_tx	= clps711xuart_stop_tx,
	.start_tx	= clps711xuart_start_tx,
	.stop_rx	= clps711xuart_stop_rx,
	.enable_ms	= clps711xuart_enable_ms,
	.break_ctl	= clps711xuart_break_ctl,
	.startup	= clps711xuart_startup,
	.shutdown	= clps711xuart_shutdown,
	.set_termios	= clps711xuart_set_termios,
	.type		= clps711xuart_type,
	.config_port	= clps711xuart_config_port,
	.release_port	= clps711xuart_release_port,
	.request_port	= clps711xuart_request_port,
};

#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
static void uart_clps711x_console_putchar(struct uart_port *port, int ch)
{
	while (clps_readl(SYSFLG(port)) & SYSFLG_UTXFF)
		barrier();

	clps_writew(ch, UARTDR(port));
}

static void uart_clps711x_console_write(struct console *co, const char *c,
					unsigned n)
{
	struct clps711x_port *s = (struct clps711x_port *)co->data;
	struct uart_port *port = &s->port[co->index];
	u32 syscon;

	/* Ensure that the port is enabled */
	syscon = clps_readl(SYSCON(port));
	clps_writel(syscon | SYSCON_UARTEN, SYSCON(port));

	uart_console_write(port, c, n, uart_clps711x_console_putchar);

	/* Wait for transmitter to become empty */
	while (clps_readl(SYSFLG(port)) & SYSFLG_UBUSY)
		barrier();

	/* Restore the uart state */
	clps_writel(syscon, SYSCON(port));
}

static void uart_clps711x_console_get_options(struct uart_port *port,
					      int *baud, int *parity,
					      int *bits)
{
	if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) {
		unsigned int ubrlcr, quot;

		ubrlcr = clps_readl(UBRLCR(port));

		*parity = 'n';
		if (ubrlcr & UBRLCR_PRTEN) {
			if (ubrlcr & UBRLCR_EVENPRT)
				*parity = 'e';
			else
				*parity = 'o';
		}

		if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
			*bits = 7;
		else
			*bits = 8;

		quot = ubrlcr & UBRLCR_BAUD_MASK;
		*baud = port->uartclk / (16 * (quot + 1));
	}
}

static int uart_clps711x_console_setup(struct console *co, char *options)
{
	int baud = 38400, bits = 8, parity = 'n', flow = 'n';
	struct clps711x_port *s = (struct clps711x_port *)co->data;
	struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);
	else
		uart_clps711x_console_get_options(port, &baud, &parity, &bits);

	return uart_set_options(port, co, baud, parity, bits, flow);
}
#endif

static int __devinit uart_clps711x_probe(struct platform_device *pdev)
{
	struct clps711x_port *s;
	int ret, i;

	s = devm_kzalloc(&pdev->dev, sizeof(struct clps711x_port), GFP_KERNEL);
	if (!s) {
		dev_err(&pdev->dev, "Error allocating port structure\n");
		return -ENOMEM;
	}
	platform_set_drvdata(pdev, s);

	s->uart.owner		= THIS_MODULE;
	s->uart.dev_name	= "ttyCL";
	s->uart.major		= UART_CLPS711X_MAJOR;
	s->uart.minor		= UART_CLPS711X_MINOR;
	s->uart.nr		= UART_CLPS711X_NR;
#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
	s->uart.cons		= &s->console;
	s->uart.cons->device	= uart_console_device;
	s->uart.cons->write	= uart_clps711x_console_write;
	s->uart.cons->setup	= uart_clps711x_console_setup;
	s->uart.cons->flags	= CON_PRINTBUFFER;
	s->uart.cons->index	= -1;
	s->uart.cons->data	= s;
	strcpy(s->uart.cons->name, "ttyCL");
#endif
	ret = uart_register_driver(&s->uart);
	if (ret) {
		dev_err(&pdev->dev, "Registering UART driver failed\n");
		goto err_out;
	}

	for (i = 0; i < UART_CLPS711X_NR; i++) {
		s->port[i].line		= i;
		s->port[i].dev		= &pdev->dev;
		s->port[i].irq		= TX_IRQ(&s->port[i]);
		s->port[i].iobase	= SYSCON(&s->port[i]);
		s->port[i].type		= PORT_CLPS711X;
		s->port[i].fifosize	= 16;
		s->port[i].flags	= UPF_SKIP_TEST | UPF_FIXED_TYPE;
		s->port[i].uartclk	= 3686400;
		s->port[i].ops		= &uart_clps711x_ops;
		WARN_ON(uart_add_one_port(&s->uart, &s->port[i]));
	}

	return 0;

err_out:
	platform_set_drvdata(pdev, NULL);

	return ret;
}

static int __devexit uart_clps711x_remove(struct platform_device *pdev)
{
	struct clps711x_port *s = platform_get_drvdata(pdev);
	int i;

	for (i = 0; i < UART_CLPS711X_NR; i++)
		uart_remove_one_port(&s->uart, &s->port[i]);

	uart_unregister_driver(&s->uart);
	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver clps711x_uart_driver = {
	.driver = {
		.name	= UART_CLPS711X_NAME,
		.owner	= THIS_MODULE,
	},
	.probe	= uart_clps711x_probe,
	.remove	= __devexit_p(uart_clps711x_remove),
};
module_platform_driver(clps711x_uart_driver);

static struct platform_device clps711x_uart_device = {
	.name	= UART_CLPS711X_NAME,
};

static int __init uart_clps711x_init(void)
{
	return platform_device_register(&clps711x_uart_device);
}
module_init(uart_clps711x_init);

static void __exit uart_clps711x_exit(void)
{
	platform_device_unregister(&clps711x_uart_device);
}
module_exit(uart_clps711x_exit);

MODULE_AUTHOR("Deep Blue Solutions Ltd");
MODULE_DESCRIPTION("CLPS711X serial driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Driver for CLPS711x serial ports
	3	*
	4	* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
	5	*
	6	* Copyright 1999 ARM Limited
	7	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1da177e4	22	*/
1da177e4 LT	23
	24	#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
	25	#define SUPPORT_SYSRQ
	26	#endif
	27
	28	#include <linux/module.h>
	29	#include <linux/ioport.h>
	30	#include <linux/init.h>
	31	#include <linux/console.h>
	32	#include <linux/sysrq.h>
	33	#include <linux/spinlock.h>
	34	#include <linux/device.h>
	35	#include <linux/tty.h>
	36	#include <linux/tty_flip.h>
	37	#include <linux/serial_core.h>
	38	#include <linux/serial.h>
99730225	39	#include <linux/io.h>
95113728	40	#include <linux/platform_device.h>
1da177e4	41
a09e64fb	42	#include <mach/hardware.h>
1da177e4	43	#include <asm/irq.h>
1da177e4	44
95113728	45	#define UART_CLPS711X_NAME "uart-clps711x"
117d5d42 AS	46	#define UART_CLPS711X_NR 2
	47	#define UART_CLPS711X_MAJOR 204
	48	#define UART_CLPS711X_MINOR 40
95113728	49
117d5d42 AS	50	#define UBRLCR(port) ((port)->line ? UBRLCR2 : UBRLCR1)
	51	#define UARTDR(port) ((port)->line ? UARTDR2 : UARTDR1)
	52	#define SYSFLG(port) ((port)->line ? SYSFLG2 : SYSFLG1)
	53	#define SYSCON(port) ((port)->line ? SYSCON2 : SYSCON1)
	54	#define TX_IRQ(port) ((port)->line ? IRQ_UTXINT2 : IRQ_UTXINT1)
	55	#define RX_IRQ(port) ((port)->line ? IRQ_URXINT2 : IRQ_URXINT1)
1da177e4 LT	56
	57	#define UART_ANY_ERR (UARTDR_FRMERR \| UARTDR_PARERR \| UARTDR_OVERR)
	58
117d5d42 AS	59	struct clps711x_port {
	60	struct uart_driver uart;
	61	struct uart_port port[UART_CLPS711X_NR];
3c7e9eb1	62	int tx_enabled[UART_CLPS711X_NR];
117d5d42 AS	63	#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
	64	struct console console;
	65	#endif
	66	};
	67
b129a8cc	68	static void clps711xuart_stop_tx(struct uart_port *port)
1da177e4	69	{
3c7e9eb1 AS	70	struct clps711x_port *s = dev_get_drvdata(port->dev);
	71
	72	if (s->tx_enabled[port->line]) {
1da177e4	73	disable_irq(TX_IRQ(port));
3c7e9eb1	74	s->tx_enabled[port->line] = 0;
1da177e4 LT	75	}
	76	}
	77
b129a8cc	78	static void clps711xuart_start_tx(struct uart_port *port)
1da177e4	79	{
3c7e9eb1 AS	80	struct clps711x_port *s = dev_get_drvdata(port->dev);
	81
	82	if (!s->tx_enabled[port->line]) {
1da177e4	83	enable_irq(TX_IRQ(port));
3c7e9eb1	84	s->tx_enabled[port->line] = 1;
1da177e4 LT	85	}
	86	}
	87
	88	static void clps711xuart_stop_rx(struct uart_port *port)
	89	{
	90	disable_irq(RX_IRQ(port));
	91	}
	92
	93	static void clps711xuart_enable_ms(struct uart_port *port)
	94	{
	95	}
	96
7d12e780	97	static irqreturn_t clps711xuart_int_rx(int irq, void *dev_id)
1da177e4 LT	98	{
1da177e4 LT	99	struct uart_port *port = dev_id;
ebd2c8f6	100	struct tty_struct *tty = port->state->port.tty;
f9937242	101	unsigned int status, ch, flg;
1da177e4 LT	102
	103	status = clps_readl(SYSFLG(port));
	104	while (!(status & SYSFLG_URXFE)) {
	105	ch = clps_readl(UARTDR(port));
	106
1da177e4 LT	107	port->icount.rx++;
	108
	109	flg = TTY_NORMAL;
	110
	111	/*
	112	* Note that the error handling code is
	113	* out of the main execution path
	114	*/
2a9604b8 RK	115	if (unlikely(ch & UART_ANY_ERR)) {
	116	if (ch & UARTDR_PARERR)
	117	port->icount.parity++;
	118	else if (ch & UARTDR_FRMERR)
	119	port->icount.frame++;
	120	if (ch & UARTDR_OVERR)
	121	port->icount.overrun++;
1da177e4	122
2a9604b8	123	ch &= port->read_status_mask;
1da177e4	124
2a9604b8 RK	125	if (ch & UARTDR_PARERR)
	126	flg = TTY_PARITY;
	127	else if (ch & UARTDR_FRMERR)
	128	flg = TTY_FRAME;
1da177e4	129
2a9604b8 RK	130	#ifdef SUPPORT_SYSRQ
	131	port->sysrq = 0;
	132	#endif
	133	}
1da177e4	134
7d12e780	135	if (uart_handle_sysrq_char(port, ch))
2a9604b8	136	goto ignore_char;
1da177e4	137
1da177e4 LT	138	/*
	139	* CHECK: does overrun affect the current character?
	140	* ASSUMPTION: it does not.
	141	*/
05ab3014	142	uart_insert_char(port, ch, UARTDR_OVERR, ch, flg);
2a9604b8 RK	143
	144	ignore_char:
	145	status = clps_readl(SYSFLG(port));
1da177e4	146	}
2a9604b8 RK	147	tty_flip_buffer_push(tty);
2a9604b8 RK	148	return IRQ_HANDLED;
1da177e4 LT	149	}
1da177e4 LT	150
7d12e780	151	static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
1da177e4 LT	152	{
1da177e4 LT	153	struct uart_port *port = dev_id;
3c7e9eb1	154	struct clps711x_port *s = dev_get_drvdata(port->dev);
ebd2c8f6	155	struct circ_buf *xmit = &port->state->xmit;
1da177e4 LT	156	int count;
	157
	158	if (port->x_char) {
	159	clps_writel(port->x_char, UARTDR(port));
	160	port->icount.tx++;
	161	port->x_char = 0;
	162	return IRQ_HANDLED;
	163	}
7a6fbc9a	164
3c7e9eb1 AS	165	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
	166	disable_irq_nosync(TX_IRQ(port));
	167	s->tx_enabled[port->line] = 0;
	168	return IRQ_HANDLED;
	169	}
1da177e4 LT	170
	171	count = port->fifosize >> 1;
	172	do {
	173	clps_writel(xmit->buf[xmit->tail], UARTDR(port));
	174	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
	175	port->icount.tx++;
	176	if (uart_circ_empty(xmit))
	177	break;
	178	} while (--count > 0);
	179
	180	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	181	uart_write_wakeup(port);
	182
1da177e4 LT	183	return IRQ_HANDLED;
	184	}
	185
	186	static unsigned int clps711xuart_tx_empty(struct uart_port *port)
	187	{
	188	unsigned int status = clps_readl(SYSFLG(port));
	189	return status & SYSFLG_UBUSY ? 0 : TIOCSER_TEMT;
	190	}
	191
	192	static unsigned int clps711xuart_get_mctrl(struct uart_port *port)
	193	{
	194	unsigned int port_addr;
	195	unsigned int result = 0;
	196	unsigned int status;
	197
	198	port_addr = SYSFLG(port);
	199	if (port_addr == SYSFLG1) {
	200	status = clps_readl(SYSFLG1);
	201	if (status & SYSFLG1_DCD)
	202	result \|= TIOCM_CAR;
	203	if (status & SYSFLG1_DSR)
	204	result \|= TIOCM_DSR;
	205	if (status & SYSFLG1_CTS)
	206	result \|= TIOCM_CTS;
	207	}
	208
	209	return result;
	210	}
	211
	212	static void
	213	clps711xuart_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
	214	{
	215	}
	216
	217	static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
	218	{
	219	unsigned long flags;
	220	unsigned int ubrlcr;
	221
	222	spin_lock_irqsave(&port->lock, flags);
	223	ubrlcr = clps_readl(UBRLCR(port));
	224	if (break_state == -1)
	225	ubrlcr \|= UBRLCR_BREAK;
	226	else
	227	ubrlcr &= ~UBRLCR_BREAK;
	228	clps_writel(ubrlcr, UBRLCR(port));
	229	spin_unlock_irqrestore(&port->lock, flags);
	230	}
	231
	232	static int clps711xuart_startup(struct uart_port *port)
	233	{
3c7e9eb1	234	struct clps711x_port *s = dev_get_drvdata(port->dev);
1da177e4 LT	235	unsigned int syscon;
	236	int retval;
	237
3c7e9eb1	238	s->tx_enabled[port->line] = 1;
1da177e4 LT	239
	240	/*
	241	* Allocate the IRQs
	242	*/
	243	retval = request_irq(TX_IRQ(port), clps711xuart_int_tx, 0,
	244	"clps711xuart_tx", port);
	245	if (retval)
	246	return retval;
	247
	248	retval = request_irq(RX_IRQ(port), clps711xuart_int_rx, 0,
	249	"clps711xuart_rx", port);
	250	if (retval) {
	251	free_irq(TX_IRQ(port), port);
	252	return retval;
	253	}
	254
	255	/*
	256	* enable the port
	257	*/
	258	syscon = clps_readl(SYSCON(port));
	259	syscon \|= SYSCON_UARTEN;
	260	clps_writel(syscon, SYSCON(port));
	261
	262	return 0;
	263	}
	264
	265	static void clps711xuart_shutdown(struct uart_port *port)
	266	{
	267	unsigned int ubrlcr, syscon;
	268
	269	/*
	270	* Free the interrupt
	271	*/
	272	free_irq(TX_IRQ(port), port); /* TX interrupt */
	273	free_irq(RX_IRQ(port), port); /* RX interrupt */
	274
	275	/*
	276	* disable the port
	277	*/
	278	syscon = clps_readl(SYSCON(port));
	279	syscon &= ~SYSCON_UARTEN;
	280	clps_writel(syscon, SYSCON(port));
	281
	282	/*
	283	* disable break condition and fifos
	284	*/
	285	ubrlcr = clps_readl(UBRLCR(port));
	286	ubrlcr &= ~(UBRLCR_FIFOEN \| UBRLCR_BREAK);
	287	clps_writel(ubrlcr, UBRLCR(port));
	288	}
	289
	290	static void
606d099c AC	291	clps711xuart_set_termios(struct uart_port port, struct ktermios termios,
606d099c AC	292	struct ktermios *old)
1da177e4 LT	293	{
	294	unsigned int ubrlcr, baud, quot;
	295	unsigned long flags;
	296
	297	/*
	298	* We don't implement CREAD.
	299	*/
	300	termios->c_cflag \|= CREAD;
	301
	302	/*
	303	* Ask the core to calculate the divisor for us.
	304	*/
	305	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
	306	quot = uart_get_divisor(port, baud);
	307
	308	switch (termios->c_cflag & CSIZE) {
	309	case CS5:
	310	ubrlcr = UBRLCR_WRDLEN5;
	311	break;
	312	case CS6:
	313	ubrlcr = UBRLCR_WRDLEN6;
	314	break;
	315	case CS7:
	316	ubrlcr = UBRLCR_WRDLEN7;
	317	break;
	318	default: // CS8
	319	ubrlcr = UBRLCR_WRDLEN8;
	320	break;
	321	}
	322	if (termios->c_cflag & CSTOPB)
	323	ubrlcr \|= UBRLCR_XSTOP;
	324	if (termios->c_cflag & PARENB) {
	325	ubrlcr \|= UBRLCR_PRTEN;
	326	if (!(termios->c_cflag & PARODD))
	327	ubrlcr \|= UBRLCR_EVENPRT;
	328	}
	329	if (port->fifosize > 1)
	330	ubrlcr \|= UBRLCR_FIFOEN;
	331
	332	spin_lock_irqsave(&port->lock, flags);
	333
	334	/*
	335	* Update the per-port timeout.
	336	*/
	337	uart_update_timeout(port, termios->c_cflag, baud);
	338
	339	port->read_status_mask = UARTDR_OVERR;
	340	if (termios->c_iflag & INPCK)
	341	port->read_status_mask \|= UARTDR_PARERR \| UARTDR_FRMERR;
	342
	343	/*
	344	* Characters to ignore
	345	*/
	346	port->ignore_status_mask = 0;
	347	if (termios->c_iflag & IGNPAR)
	348	port->ignore_status_mask \|= UARTDR_FRMERR \| UARTDR_PARERR;
	349	if (termios->c_iflag & IGNBRK) {
	350	/*
	351	* If we're ignoring parity and break indicators,
	352	* ignore overruns to (for real raw support).
	353	*/
	354	if (termios->c_iflag & IGNPAR)
	355	port->ignore_status_mask \|= UARTDR_OVERR;
	356	}
357
358	quot -= 1;
359
360	clps_writel(ubrlcr \| quot, UBRLCR(port));
361
362	spin_unlock_irqrestore(&port->lock, flags);
363	}
364
365	static const char clps711xuart_type(struct uart_port port)
366	{
367	return port->type == PORT_CLPS711X ? "CLPS711x" : NULL;
368	}
369
370	/*
371	* Configure/autoconfigure the port.
372	*/
373	static void clps711xuart_config_port(struct uart_port *port, int flags)
374	{
375	if (flags & UART_CONFIG_TYPE)
376	port->type = PORT_CLPS711X;
377	}
378
379	static void clps711xuart_release_port(struct uart_port *port)
380	{
381	}
382
383	static int clps711xuart_request_port(struct uart_port *port)
384	{
385	return 0;
386	}
387
117d5d42	388	static struct uart_ops uart_clps711x_ops = {
1da177e4 LT	389	.tx_empty = clps711xuart_tx_empty,
	390	.set_mctrl = clps711xuart_set_mctrl_null,
	391	.get_mctrl = clps711xuart_get_mctrl,
	392	.stop_tx = clps711xuart_stop_tx,
	393	.start_tx = clps711xuart_start_tx,
	394	.stop_rx = clps711xuart_stop_rx,
	395	.enable_ms = clps711xuart_enable_ms,
	396	.break_ctl = clps711xuart_break_ctl,
	397	.startup = clps711xuart_startup,
	398	.shutdown = clps711xuart_shutdown,
	399	.set_termios = clps711xuart_set_termios,
	400	.type = clps711xuart_type,
	401	.config_port = clps711xuart_config_port,
	402	.release_port = clps711xuart_release_port,
	403	.request_port = clps711xuart_request_port,
	404	};
	405
1da177e4	406	#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
117d5d42	407	static void uart_clps711x_console_putchar(struct uart_port *port, int ch)
d358788f RK	408	{
	409	while (clps_readl(SYSFLG(port)) & SYSFLG_UTXFF)
	410	barrier();
117d5d42 AS	411
117d5d42 AS	412	clps_writew(ch, UARTDR(port));
d358788f RK	413	}
d358788f RK	414
117d5d42 AS	415	static void uart_clps711x_console_write(struct console co, const char c,
117d5d42 AS	416	unsigned n)
1da177e4	417	{
117d5d42 AS	418	struct clps711x_port s = (struct clps711x_port )co->data;
	419	struct uart_port *port = &s->port[co->index];
	420	u32 syscon;
1da177e4	421
117d5d42	422	/* Ensure that the port is enabled */
1da177e4 LT	423	syscon = clps_readl(SYSCON(port));
	424	clps_writel(syscon \| SYSCON_UARTEN, SYSCON(port));
	425
117d5d42	426	uart_console_write(port, c, n, uart_clps711x_console_putchar);
1da177e4	427
117d5d42 AS	428	/* Wait for transmitter to become empty */
	429	while (clps_readl(SYSFLG(port)) & SYSFLG_UBUSY)
	430	barrier();
1da177e4	431
117d5d42	432	/* Restore the uart state */
1da177e4 LT	433	clps_writel(syscon, SYSCON(port));
	434	}
	435
117d5d42 AS	436	static void uart_clps711x_console_get_options(struct uart_port *port,
	437	int baud, int parity,
	438	int *bits)
1da177e4 LT	439	{
	440	if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) {
	441	unsigned int ubrlcr, quot;
	442
	443	ubrlcr = clps_readl(UBRLCR(port));
	444
	445	*parity = 'n';
	446	if (ubrlcr & UBRLCR_PRTEN) {
	447	if (ubrlcr & UBRLCR_EVENPRT)
	448	*parity = 'e';
	449	else
	450	*parity = 'o';
	451	}
	452
	453	if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
	454	*bits = 7;
	455	else
	456	*bits = 8;
	457
	458	quot = ubrlcr & UBRLCR_BAUD_MASK;
	459	baud = port->uartclk / (16 (quot + 1));
	460	}
	461	}
	462
117d5d42	463	static int uart_clps711x_console_setup(struct console co, char options)
1da177e4	464	{
117d5d42 AS	465	int baud = 38400, bits = 8, parity = 'n', flow = 'n';
	466	struct clps711x_port s = (struct clps711x_port )co->data;
	467	struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
1da177e4 LT	468
	469	if (options)
	470	uart_parse_options(options, &baud, &parity, &bits, &flow);
	471	else
117d5d42	472	uart_clps711x_console_get_options(port, &baud, &parity, &bits);
1da177e4 LT	473
	474	return uart_set_options(port, co, baud, parity, bits, flow);
	475	}
1da177e4 LT	476	#endif
1da177e4 LT	477
95113728	478	static int __devinit uart_clps711x_probe(struct platform_device *pdev)
1da177e4	479	{
117d5d42	480	struct clps711x_port *s;
1da177e4 LT	481	int ret, i;
1da177e4 LT	482
117d5d42 AS	483	s = devm_kzalloc(&pdev->dev, sizeof(struct clps711x_port), GFP_KERNEL);
	484	if (!s) {
	485	dev_err(&pdev->dev, "Error allocating port structure\n");
	486	return -ENOMEM;
	487	}
	488	platform_set_drvdata(pdev, s);
1da177e4	489
117d5d42 AS	490	s->uart.owner = THIS_MODULE;
	491	s->uart.dev_name = "ttyCL";
	492	s->uart.major = UART_CLPS711X_MAJOR;
	493	s->uart.minor = UART_CLPS711X_MINOR;
	494	s->uart.nr = UART_CLPS711X_NR;
	495	#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
	496	s->uart.cons = &s->console;
	497	s->uart.cons->device = uart_console_device;
	498	s->uart.cons->write = uart_clps711x_console_write;
	499	s->uart.cons->setup = uart_clps711x_console_setup;
	500	s->uart.cons->flags = CON_PRINTBUFFER;
	501	s->uart.cons->index = -1;
	502	s->uart.cons->data = s;
	503	strcpy(s->uart.cons->name, "ttyCL");
	504	#endif
	505	ret = uart_register_driver(&s->uart);
	506	if (ret) {
	507	dev_err(&pdev->dev, "Registering UART driver failed\n");
	508	goto err_out;
	509	}
1da177e4	510
117d5d42 AS	511	for (i = 0; i < UART_CLPS711X_NR; i++) {
	512	s->port[i].line = i;
	513	s->port[i].dev = &pdev->dev;
	514	s->port[i].irq = TX_IRQ(&s->port[i]);
	515	s->port[i].iobase = SYSCON(&s->port[i]);
	516	s->port[i].type = PORT_CLPS711X;
	517	s->port[i].fifosize = 16;
	518	s->port[i].flags = UPF_SKIP_TEST \| UPF_FIXED_TYPE;
	519	s->port[i].uartclk = 3686400;
	520	s->port[i].ops = &uart_clps711x_ops;
	521	WARN_ON(uart_add_one_port(&s->uart, &s->port[i]));
	522	}
1da177e4 LT	523
1da177e4 LT	524	return 0;
117d5d42 AS	525
	526	err_out:
	527	platform_set_drvdata(pdev, NULL);
	528
	529	return ret;
1da177e4 LT	530	}
1da177e4 LT	531
95113728	532	static int __devexit uart_clps711x_remove(struct platform_device *pdev)
1da177e4	533	{
117d5d42	534	struct clps711x_port *s = platform_get_drvdata(pdev);
1da177e4 LT	535	int i;
1da177e4 LT	536
117d5d42 AS	537	for (i = 0; i < UART_CLPS711X_NR; i++)
117d5d42 AS	538	uart_remove_one_port(&s->uart, &s->port[i]);
1da177e4	539
117d5d42 AS	540	uart_unregister_driver(&s->uart);
117d5d42 AS	541	platform_set_drvdata(pdev, NULL);
95113728 AS	542
95113728 AS	543	return 0;
1da177e4 LT	544	}
1da177e4 LT	545
95113728 AS	546	static struct platform_driver clps711x_uart_driver = {
	547	.driver = {
	548	.name = UART_CLPS711X_NAME,
	549	.owner = THIS_MODULE,
	550	},
	551	.probe = uart_clps711x_probe,
	552	.remove = __devexit_p(uart_clps711x_remove),
	553	};
	554	module_platform_driver(clps711x_uart_driver);
	555
	556	static struct platform_device clps711x_uart_device = {
	557	.name = UART_CLPS711X_NAME,
	558	};
	559
	560	static int __init uart_clps711x_init(void)
	561	{
	562	return platform_device_register(&clps711x_uart_device);
	563	}
	564	module_init(uart_clps711x_init);
	565
	566	static void __exit uart_clps711x_exit(void)
	567	{
	568	platform_device_unregister(&clps711x_uart_device);
	569	}
	570	module_exit(uart_clps711x_exit);
1da177e4 LT	571
1da177e4 LT	572	MODULE_AUTHOR("Deep Blue Solutions Ltd");
95113728	573	MODULE_DESCRIPTION("CLPS711X serial driver");
1da177e4	574	MODULE_LICENSE("GPL");