[deliverable/linux.git] / drivers / tty / serial / clps711x.c

/*
 *  Driver for CLPS711x serial ports
 *
 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
 *
 *  Copyright 1999 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif

#include <linux/module.h>
#include <linux/device.h>
#include <linux/console.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/clps711x.h>

#define UART_CLPS711X_DEVNAME	"ttyCL"
#define UART_CLPS711X_NR	2
#define UART_CLPS711X_MAJOR	204
#define UART_CLPS711X_MINOR	40

#define UARTDR_OFFSET		(0x00)
#define UBRLCR_OFFSET		(0x40)

#define UARTDR_FRMERR		(1 << 8)
#define UARTDR_PARERR		(1 << 9)
#define UARTDR_OVERR		(1 << 10)

#define UBRLCR_BAUD_MASK	((1 << 12) - 1)
#define UBRLCR_BREAK		(1 << 12)
#define UBRLCR_PRTEN		(1 << 13)
#define UBRLCR_EVENPRT		(1 << 14)
#define UBRLCR_XSTOP		(1 << 15)
#define UBRLCR_FIFOEN		(1 << 16)
#define UBRLCR_WRDLEN5		(0 << 17)
#define UBRLCR_WRDLEN6		(1 << 17)
#define UBRLCR_WRDLEN7		(2 << 17)
#define UBRLCR_WRDLEN8		(3 << 17)
#define UBRLCR_WRDLEN_MASK	(3 << 17)

struct clps711x_port {
	struct uart_port	port;
	unsigned int		tx_enabled;
	int			rx_irq;
	struct regmap		*syscon;
	bool			use_ms;
};

static struct uart_driver clps711x_uart = {
	.owner		= THIS_MODULE,
	.driver_name	= UART_CLPS711X_DEVNAME,
	.dev_name	= UART_CLPS711X_DEVNAME,
	.major		= UART_CLPS711X_MAJOR,
	.minor		= UART_CLPS711X_MINOR,
	.nr		= UART_CLPS711X_NR,
};

static void uart_clps711x_stop_tx(struct uart_port *port)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);

	if (s->tx_enabled) {
		disable_irq(port->irq);
		s->tx_enabled = 0;
	}
}

static void uart_clps711x_start_tx(struct uart_port *port)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);

	if (!s->tx_enabled) {
		s->tx_enabled = 1;
		enable_irq(port->irq);
	}
}

static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	struct clps711x_port *s = dev_get_drvdata(port->dev);
	unsigned int status, flg;
	u32 sysflg;
	u16 ch;

	for (;;) {
		regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
		if (sysflg & SYSFLG_URXFE)
			break;

		ch = readw_relaxed(port->membase + UARTDR_OFFSET);
		status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR);
		ch &= 0xff;

		port->icount.rx++;
		flg = TTY_NORMAL;

		if (unlikely(status)) {
			if (status & UARTDR_PARERR)
				port->icount.parity++;
			else if (status & UARTDR_FRMERR)
				port->icount.frame++;
			else if (status & UARTDR_OVERR)
				port->icount.overrun++;

			status &= port->read_status_mask;

			if (status & UARTDR_PARERR)
				flg = TTY_PARITY;
			else if (status & UARTDR_FRMERR)
				flg = TTY_FRAME;
			else if (status & UARTDR_OVERR)
				flg = TTY_OVERRUN;
		}

		if (uart_handle_sysrq_char(port, ch))
			continue;

		if (status & port->ignore_status_mask)
			continue;

		uart_insert_char(port, status, UARTDR_OVERR, ch, flg);
	}

	tty_flip_buffer_push(&port->state->port);

	return IRQ_HANDLED;
}

static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	struct clps711x_port *s = dev_get_drvdata(port->dev);
	struct circ_buf *xmit = &port->state->xmit;
	u32 sysflg;

	if (port->x_char) {
		writew_relaxed(port->x_char, port->membase + UARTDR_OFFSET);
		port->icount.tx++;
		port->x_char = 0;
		return IRQ_HANDLED;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		if (s->tx_enabled) {
			disable_irq_nosync(port->irq);
			s->tx_enabled = 0;
		}
		return IRQ_HANDLED;
	}

	while (!uart_circ_empty(xmit)) {
		writew_relaxed(xmit->buf[xmit->tail],
			       port->membase + UARTDR_OFFSET);
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		port->icount.tx++;

		regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
		if (sysflg & SYSFLG_UTXFF)
			break;
	}

	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	return IRQ_HANDLED;
}

static unsigned int uart_clps711x_tx_empty(struct uart_port *port)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);
	u32 sysflg;

	regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);

	return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT;
}

static unsigned int uart_clps711x_get_mctrl(struct uart_port *port)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);
	unsigned int result = 0;
	u32 sysflg;

	if (s->use_ms) {
		regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
		if (sysflg & SYSFLG1_DCD)
			result |= TIOCM_CAR;
		if (sysflg & SYSFLG1_DSR)
			result |= TIOCM_DSR;
		if (sysflg & SYSFLG1_CTS)
			result |= TIOCM_CTS;
	} else
		result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;

	return result;
}

static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	/* Do nothing */
}

static void uart_clps711x_break_ctl(struct uart_port *port, int break_state)
{
	unsigned int ubrlcr;

	ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET);
	if (break_state)
		ubrlcr |= UBRLCR_BREAK;
	else
		ubrlcr &= ~UBRLCR_BREAK;
	writel_relaxed(ubrlcr, port->membase + UBRLCR_OFFSET);
}

static int uart_clps711x_startup(struct uart_port *port)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);

	/* Disable break */
	writel_relaxed(readl_relaxed(port->membase + UBRLCR_OFFSET) &
		       ~UBRLCR_BREAK, port->membase + UBRLCR_OFFSET);

	/* Enable the port */
	return regmap_update_bits(s->syscon, SYSCON_OFFSET,
				  SYSCON_UARTEN, SYSCON_UARTEN);
}

static void uart_clps711x_shutdown(struct uart_port *port)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);

	/* Disable the port */
	regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
}

static void uart_clps711x_set_termios(struct uart_port *port,
				      struct ktermios *termios,
				      struct ktermios *old)
{
	u32 ubrlcr;
	unsigned int baud, quot;

	/* Mask termios capabilities we don't support */
	termios->c_cflag &= ~CMSPAR;
	termios->c_iflag &= ~(BRKINT | IGNBRK);

	/* Ask the core to calculate the divisor for us */
	baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096,
						      port->uartclk / 16);
	quot = uart_get_divisor(port, baud);

	switch (termios->c_cflag & CSIZE) {
	case CS5:
		ubrlcr = UBRLCR_WRDLEN5;
		break;
	case CS6:
		ubrlcr = UBRLCR_WRDLEN6;
		break;
	case CS7:
		ubrlcr = UBRLCR_WRDLEN7;
		break;
	case CS8:
	default:
		ubrlcr = UBRLCR_WRDLEN8;
		break;
	}

	if (termios->c_cflag & CSTOPB)
		ubrlcr |= UBRLCR_XSTOP;

	if (termios->c_cflag & PARENB) {
		ubrlcr |= UBRLCR_PRTEN;
		if (!(termios->c_cflag & PARODD))
			ubrlcr |= UBRLCR_EVENPRT;
	}

	/* Enable FIFO */
	ubrlcr |= UBRLCR_FIFOEN;

	/* Set read status mask */
	port->read_status_mask = UARTDR_OVERR;
	if (termios->c_iflag & INPCK)
		port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;

	/* Set status ignore mask */
	port->ignore_status_mask = 0;
	if (!(termios->c_cflag & CREAD))
		port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR |
					    UARTDR_FRMERR;

	uart_update_timeout(port, termios->c_cflag, baud);

	writel_relaxed(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
}

static const char *uart_clps711x_type(struct uart_port *port)
{
	return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL;
}

static void uart_clps711x_config_port(struct uart_port *port, int flags)
{
	if (flags & UART_CONFIG_TYPE)
		port->type = PORT_CLPS711X;
}

static void uart_clps711x_nop_void(struct uart_port *port)
{
}

static int uart_clps711x_nop_int(struct uart_port *port)
{
	return 0;
}

static const struct uart_ops uart_clps711x_ops = {
	.tx_empty	= uart_clps711x_tx_empty,
	.set_mctrl	= uart_clps711x_set_mctrl,
	.get_mctrl	= uart_clps711x_get_mctrl,
	.stop_tx	= uart_clps711x_stop_tx,
	.start_tx	= uart_clps711x_start_tx,
	.stop_rx	= uart_clps711x_nop_void,
	.enable_ms	= uart_clps711x_nop_void,
	.break_ctl	= uart_clps711x_break_ctl,
	.startup	= uart_clps711x_startup,
	.shutdown	= uart_clps711x_shutdown,
	.set_termios	= uart_clps711x_set_termios,
	.type		= uart_clps711x_type,
	.config_port	= uart_clps711x_config_port,
	.release_port	= uart_clps711x_nop_void,
	.request_port	= uart_clps711x_nop_int,
};

#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
static void uart_clps711x_console_putchar(struct uart_port *port, int ch)
{
	struct clps711x_port *s = dev_get_drvdata(port->dev);
	u32 sysflg;

	do {
		regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
	} while (sysflg & SYSFLG_UTXFF);

	writew_relaxed(ch, port->membase + UARTDR_OFFSET);
}

static void uart_clps711x_console_write(struct console *co, const char *c,
					unsigned n)
{
	struct uart_port *port = clps711x_uart.state[co->index].uart_port;
	struct clps711x_port *s = dev_get_drvdata(port->dev);
	u32 sysflg;

	uart_console_write(port, c, n, uart_clps711x_console_putchar);

	/* Wait for transmitter to become empty */
	do {
		regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
	} while (sysflg & SYSFLG_UBUSY);
}

static int uart_clps711x_console_setup(struct console *co, char *options)
{
	int baud = 38400, bits = 8, parity = 'n', flow = 'n';
	int ret, index = co->index;
	struct clps711x_port *s;
	struct uart_port *port;
	u32 ubrlcr, syscon;
	unsigned int quot;

	if (index < 0 || index >= UART_CLPS711X_NR)
		return -EINVAL;

	port = clps711x_uart.state[index].uart_port;
	if (!port)
		return -ENODEV;

	s = dev_get_drvdata(port->dev);

	if (!options) {
		regmap_read(s->syscon, SYSCON_OFFSET, &syscon);
		if (syscon & SYSCON_UARTEN) {
			ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET);

			if (ubrlcr & UBRLCR_PRTEN) {
				if (ubrlcr & UBRLCR_EVENPRT)
					parity = 'e';
				else
					parity = 'o';
			}

			if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
				bits = 7;

			quot = ubrlcr & UBRLCR_BAUD_MASK;
			baud = port->uartclk / (16 * (quot + 1));
		}
	} else
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	ret = uart_set_options(port, co, baud, parity, bits, flow);
	if (ret)
		return ret;

	return regmap_update_bits(s->syscon, SYSCON_OFFSET,
				  SYSCON_UARTEN, SYSCON_UARTEN);
}

static struct console clps711x_console = {
	.name	= UART_CLPS711X_DEVNAME,
	.device	= uart_console_device,
	.write	= uart_clps711x_console_write,
	.setup	= uart_clps711x_console_setup,
	.flags	= CON_PRINTBUFFER,
	.index	= -1,
};
#endif

static int uart_clps711x_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	int ret, index = np ? of_alias_get_id(np, "serial") : pdev->id;
	struct clps711x_port *s;
	struct resource *res;
	struct clk *uart_clk;

	if (index < 0 || index >= UART_CLPS711X_NR)
		return -EINVAL;

	s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
	if (!s)
		return -ENOMEM;

	uart_clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(uart_clk))
		return PTR_ERR(uart_clk);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	s->port.membase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(s->port.membase))
		return PTR_ERR(s->port.membase);

	s->port.irq = platform_get_irq(pdev, 0);
	if (IS_ERR_VALUE(s->port.irq))
		return s->port.irq;

	s->rx_irq = platform_get_irq(pdev, 1);
	if (IS_ERR_VALUE(s->rx_irq))
		return s->rx_irq;

	if (!np) {
		char syscon_name[9];

		sprintf(syscon_name, "syscon.%i", index + 1);
		s->syscon = syscon_regmap_lookup_by_pdevname(syscon_name);
		if (IS_ERR(s->syscon))
			return PTR_ERR(s->syscon);

		s->use_ms = !index;
	} else {
		s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
		if (IS_ERR(s->syscon))
			return PTR_ERR(s->syscon);

		if (!index) {
			bool use_irda;

			s->use_ms = of_property_read_bool(np, "uart-use-ms");
			use_irda = of_property_read_bool(np, "uart-use-irda");
			regmap_update_bits(s->syscon, SYSCON_OFFSET,
					   SYSCON1_SIREN,
					   use_irda ? SYSCON1_SIREN : 0);
		}
	}

	s->port.line		= index;
	s->port.dev		= &pdev->dev;
	s->port.iotype		= UPIO_MEM32;
	s->port.mapbase		= res->start;
	s->port.type		= PORT_CLPS711X;
	s->port.fifosize	= 16;
	s->port.flags		= UPF_SKIP_TEST | UPF_FIXED_TYPE;
	s->port.uartclk		= clk_get_rate(uart_clk);
	s->port.ops		= &uart_clps711x_ops;

	platform_set_drvdata(pdev, s);

	ret = uart_add_one_port(&clps711x_uart, &s->port);
	if (ret)
		return ret;

	/* Disable port */
	if (!uart_console(&s->port))
		regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);

	s->tx_enabled = 1;

	ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0,
			       dev_name(&pdev->dev), &s->port);
	if (ret) {
		uart_remove_one_port(&clps711x_uart, &s->port);
		return ret;
	}

	ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0,
			       dev_name(&pdev->dev), &s->port);
	if (ret)
		uart_remove_one_port(&clps711x_uart, &s->port);

	return ret;
}

static int uart_clps711x_remove(struct platform_device *pdev)
{
	struct clps711x_port *s = platform_get_drvdata(pdev);

	return uart_remove_one_port(&clps711x_uart, &s->port);
}

static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = {
	{ .compatible = "cirrus,clps711x-uart", },
	{ }
};
MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids);

static struct platform_driver clps711x_uart_platform = {
	.driver = {
		.name		= "clps711x-uart",
		.owner		= THIS_MODULE,
		.of_match_table	= of_match_ptr(clps711x_uart_dt_ids),
	},
	.probe	= uart_clps711x_probe,
	.remove	= uart_clps711x_remove,
};

static int __init uart_clps711x_init(void)
{
	int ret;

#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
	clps711x_uart.cons = &clps711x_console;
	clps711x_console.data = &clps711x_uart;
#endif

	ret = uart_register_driver(&clps711x_uart);
	if (ret)
		return ret;

	return platform_driver_register(&clps711x_uart_platform);
}
module_init(uart_clps711x_init);

static void __exit uart_clps711x_exit(void)
{
	platform_driver_unregister(&clps711x_uart_platform);
	uart_unregister_driver(&clps711x_uart);
}
module_exit(uart_clps711x_exit);

MODULE_AUTHOR("Deep Blue Solutions Ltd");
MODULE_DESCRIPTION("CLPS711X serial driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Driver for CLPS711x serial ports
	3	*
	4	* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
	5	*
	6	* Copyright 1999 ARM Limited
	7	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
1da177e4	13	*/
1da177e4 LT	14
	15	#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
	16	#define SUPPORT_SYSRQ
	17	#endif
	18
	19	#include <linux/module.h>
1da177e4	20	#include <linux/device.h>
a1c25f2b	21	#include <linux/console.h>
1da177e4 LT	22	#include <linux/serial_core.h>
1da177e4 LT	23	#include <linux/serial.h>
c08f0153	24	#include <linux/clk.h>
bc000245	25	#include <linux/io.h>
a1c25f2b AS	26	#include <linux/tty.h>
	27	#include <linux/tty_flip.h>
	28	#include <linux/ioport.h>
bc000245	29	#include <linux/of.h>
95113728	30	#include <linux/platform_device.h>
bc000245	31	#include <linux/regmap.h>
1da177e4	32
bc000245 AS	33	#include <linux/mfd/syscon.h>
bc000245 AS	34	#include <linux/mfd/syscon/clps711x.h>
1da177e4	35
bc000245	36	#define UART_CLPS711X_DEVNAME "ttyCL"
117d5d42 AS	37	#define UART_CLPS711X_NR 2
	38	#define UART_CLPS711X_MAJOR 204
	39	#define UART_CLPS711X_MINOR 40
95113728	40
bc000245 AS	41	#define UARTDR_OFFSET (0x00)
	42	#define UBRLCR_OFFSET (0x40)
	43
	44	#define UARTDR_FRMERR (1 << 8)
	45	#define UARTDR_PARERR (1 << 9)
	46	#define UARTDR_OVERR (1 << 10)
	47
	48	#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
	49	#define UBRLCR_BREAK (1 << 12)
	50	#define UBRLCR_PRTEN (1 << 13)
	51	#define UBRLCR_EVENPRT (1 << 14)
	52	#define UBRLCR_XSTOP (1 << 15)
	53	#define UBRLCR_FIFOEN (1 << 16)
	54	#define UBRLCR_WRDLEN5 (0 << 17)
	55	#define UBRLCR_WRDLEN6 (1 << 17)
	56	#define UBRLCR_WRDLEN7 (2 << 17)
	57	#define UBRLCR_WRDLEN8 (3 << 17)
	58	#define UBRLCR_WRDLEN_MASK (3 << 17)
1da177e4	59
117d5d42	60	struct clps711x_port {
bc000245 AS	61	struct uart_port port;
	62	unsigned int tx_enabled;
	63	int rx_irq;
	64	struct regmap *syscon;
	65	bool use_ms;
	66	};
	67
	68	static struct uart_driver clps711x_uart = {
	69	.owner = THIS_MODULE,
	70	.driver_name = UART_CLPS711X_DEVNAME,
	71	.dev_name = UART_CLPS711X_DEVNAME,
	72	.major = UART_CLPS711X_MAJOR,
	73	.minor = UART_CLPS711X_MINOR,
	74	.nr = UART_CLPS711X_NR,
117d5d42 AS	75	};
117d5d42 AS	76
a1c25f2b	77	static void uart_clps711x_stop_tx(struct uart_port *port)
1da177e4	78	{
3c7e9eb1 AS	79	struct clps711x_port *s = dev_get_drvdata(port->dev);
3c7e9eb1 AS	80
bc000245 AS	81	if (s->tx_enabled) {
	82	disable_irq(port->irq);
	83	s->tx_enabled = 0;
1da177e4 LT	84	}
	85	}
	86
a1c25f2b	87	static void uart_clps711x_start_tx(struct uart_port *port)
1da177e4	88	{
3c7e9eb1 AS	89	struct clps711x_port *s = dev_get_drvdata(port->dev);
3c7e9eb1 AS	90
bc000245 AS	91	if (!s->tx_enabled) {
	92	s->tx_enabled = 1;
	93	enable_irq(port->irq);
1da177e4 LT	94	}
	95	}
	96
135cc790	97	static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id)
1da177e4 LT	98	{
1da177e4 LT	99	struct uart_port *port = dev_id;
bc000245 AS	100	struct clps711x_port *s = dev_get_drvdata(port->dev);
	101	unsigned int status, flg;
	102	u32 sysflg;
	103	u16 ch;
1da177e4	104
f27de95c	105	for (;;) {
bc000245 AS	106	regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
bc000245 AS	107	if (sysflg & SYSFLG_URXFE)
f27de95c	108	break;
1da177e4	109
bc000245	110	ch = readw_relaxed(port->membase + UARTDR_OFFSET);
f27de95c AS	111	status = ch & (UARTDR_FRMERR \| UARTDR_PARERR \| UARTDR_OVERR);
	112	ch &= 0xff;
	113
	114	port->icount.rx++;
1da177e4 LT	115	flg = TTY_NORMAL;
1da177e4 LT	116
f27de95c AS	117	if (unlikely(status)) {
f27de95c AS	118	if (status & UARTDR_PARERR)
2a9604b8	119	port->icount.parity++;
f27de95c	120	else if (status & UARTDR_FRMERR)
2a9604b8	121	port->icount.frame++;
f27de95c	122	else if (status & UARTDR_OVERR)
2a9604b8	123	port->icount.overrun++;
1da177e4	124
f27de95c	125	status &= port->read_status_mask;
1da177e4	126
f27de95c	127	if (status & UARTDR_PARERR)
2a9604b8	128	flg = TTY_PARITY;
f27de95c	129	else if (status & UARTDR_FRMERR)
2a9604b8	130	flg = TTY_FRAME;
f27de95c AS	131	else if (status & UARTDR_OVERR)
f27de95c AS	132	flg = TTY_OVERRUN;
2a9604b8	133	}
1da177e4	134
7d12e780	135	if (uart_handle_sysrq_char(port, ch))
f27de95c	136	continue;
1da177e4	137
f27de95c AS	138	if (status & port->ignore_status_mask)
f27de95c AS	139	continue;
2a9604b8	140
f27de95c	141	uart_insert_char(port, status, UARTDR_OVERR, ch, flg);
1da177e4	142	}
f27de95c	143
2e124b4a	144	tty_flip_buffer_push(&port->state->port);
f27de95c	145
2a9604b8	146	return IRQ_HANDLED;
1da177e4 LT	147	}
1da177e4 LT	148
135cc790	149	static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id)
1da177e4 LT	150	{
1da177e4 LT	151	struct uart_port *port = dev_id;
3c7e9eb1	152	struct clps711x_port *s = dev_get_drvdata(port->dev);
ebd2c8f6	153	struct circ_buf *xmit = &port->state->xmit;
bc000245	154	u32 sysflg;
1da177e4 LT	155
1da177e4 LT	156	if (port->x_char) {
bc000245	157	writew_relaxed(port->x_char, port->membase + UARTDR_OFFSET);
1da177e4 LT	158	port->icount.tx++;
	159	port->x_char = 0;
	160	return IRQ_HANDLED;
	161	}
7a6fbc9a	162
3c7e9eb1	163	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
bc000245 AS	164	if (s->tx_enabled) {
	165	disable_irq_nosync(port->irq);
	166	s->tx_enabled = 0;
	167	}
3c7e9eb1 AS	168	return IRQ_HANDLED;
3c7e9eb1 AS	169	}
1da177e4	170
cf03a884	171	while (!uart_circ_empty(xmit)) {
bc000245 AS	172	writew_relaxed(xmit->buf[xmit->tail],
bc000245 AS	173	port->membase + UARTDR_OFFSET);
1da177e4 LT	174	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1da177e4 LT	175	port->icount.tx++;
bc000245 AS	176
	177	regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
	178	if (sysflg & SYSFLG_UTXFF)
1da177e4	179	break;
cf03a884	180	}
1da177e4 LT	181
	182	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	183	uart_write_wakeup(port);
	184
1da177e4 LT	185	return IRQ_HANDLED;
	186	}
	187
a1c25f2b	188	static unsigned int uart_clps711x_tx_empty(struct uart_port *port)
1da177e4	189	{
bc000245 AS	190	struct clps711x_port *s = dev_get_drvdata(port->dev);
	191	u32 sysflg;
	192
	193	regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
	194
	195	return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT;
1da177e4 LT	196	}
1da177e4 LT	197
a1c25f2b	198	static unsigned int uart_clps711x_get_mctrl(struct uart_port *port)
1da177e4	199	{
bc000245 AS	200	struct clps711x_port *s = dev_get_drvdata(port->dev);
	201	unsigned int result = 0;
	202	u32 sysflg;
1da177e4	203
bc000245 AS	204	if (s->use_ms) {
	205	regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
	206	if (sysflg & SYSFLG1_DCD)
1da177e4	207	result \|= TIOCM_CAR;
bc000245	208	if (sysflg & SYSFLG1_DSR)
1da177e4	209	result \|= TIOCM_DSR;
bc000245	210	if (sysflg & SYSFLG1_CTS)
1da177e4	211	result \|= TIOCM_CTS;
1593daf9 AS	212	} else
1593daf9 AS	213	result = TIOCM_DSR \| TIOCM_CTS \| TIOCM_CAR;
1da177e4 LT	214
	215	return result;
	216	}
	217
a1c25f2b	218	static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4	219	{
a1c25f2b	220	/* Do nothing */
1da177e4 LT	221	}
1da177e4 LT	222
a1c25f2b	223	static void uart_clps711x_break_ctl(struct uart_port *port, int break_state)
1da177e4	224	{
1da177e4 LT	225	unsigned int ubrlcr;
1da177e4 LT	226
bc000245	227	ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET);
ec335526	228	if (break_state)
1da177e4 LT	229	ubrlcr \|= UBRLCR_BREAK;
	230	else
	231	ubrlcr &= ~UBRLCR_BREAK;
bc000245	232	writel_relaxed(ubrlcr, port->membase + UBRLCR_OFFSET);
1da177e4 LT	233	}
1da177e4 LT	234
a1c25f2b	235	static int uart_clps711x_startup(struct uart_port *port)
1da177e4	236	{
3c7e9eb1	237	struct clps711x_port *s = dev_get_drvdata(port->dev);
1da177e4	238
f52ede2a	239	/* Disable break */
bc000245 AS	240	writel_relaxed(readl_relaxed(port->membase + UBRLCR_OFFSET) &
bc000245 AS	241	~UBRLCR_BREAK, port->membase + UBRLCR_OFFSET);
f52ede2a AS	242
f52ede2a AS	243	/* Enable the port */
bc000245 AS	244	return regmap_update_bits(s->syscon, SYSCON_OFFSET,
bc000245 AS	245	SYSCON_UARTEN, SYSCON_UARTEN);
1da177e4 LT	246	}
1da177e4 LT	247
a1c25f2b	248	static void uart_clps711x_shutdown(struct uart_port *port)
1da177e4	249	{
bc000245	250	struct clps711x_port *s = dev_get_drvdata(port->dev);
1da177e4	251
f52ede2a	252	/* Disable the port */
bc000245	253	regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
1da177e4 LT	254	}
1da177e4 LT	255
a1c25f2b AS	256	static void uart_clps711x_set_termios(struct uart_port *port,
	257	struct ktermios *termios,
	258	struct ktermios *old)
1da177e4	259	{
bc000245 AS	260	u32 ubrlcr;
bc000245 AS	261	unsigned int baud, quot;
1da177e4	262
7ae75e94 AS	263	/* Mask termios capabilities we don't support */
	264	termios->c_cflag &= ~CMSPAR;
	265	termios->c_iflag &= ~(BRKINT \| IGNBRK);
1da177e4	266
c08f0153 AS	267	/* Ask the core to calculate the divisor for us */
	268	baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096,
	269	port->uartclk / 16);
1da177e4 LT	270	quot = uart_get_divisor(port, baud);
	271
	272	switch (termios->c_cflag & CSIZE) {
	273	case CS5:
	274	ubrlcr = UBRLCR_WRDLEN5;
	275	break;
	276	case CS6:
	277	ubrlcr = UBRLCR_WRDLEN6;
	278	break;
	279	case CS7:
	280	ubrlcr = UBRLCR_WRDLEN7;
	281	break;
a1c25f2b AS	282	case CS8:
a1c25f2b AS	283	default:
1da177e4 LT	284	ubrlcr = UBRLCR_WRDLEN8;
	285	break;
	286	}
7ae75e94	287
1da177e4 LT	288	if (termios->c_cflag & CSTOPB)
1da177e4 LT	289	ubrlcr \|= UBRLCR_XSTOP;
7ae75e94	290
1da177e4 LT	291	if (termios->c_cflag & PARENB) {
	292	ubrlcr \|= UBRLCR_PRTEN;
	293	if (!(termios->c_cflag & PARODD))
	294	ubrlcr \|= UBRLCR_EVENPRT;
	295	}
cf03a884 AS	296
	297	/* Enable FIFO */
	298	ubrlcr \|= UBRLCR_FIFOEN;
1da177e4	299
7ae75e94	300	/* Set read status mask */
1da177e4 LT	301	port->read_status_mask = UARTDR_OVERR;
	302	if (termios->c_iflag & INPCK)
	303	port->read_status_mask \|= UARTDR_PARERR \| UARTDR_FRMERR;
	304
7ae75e94	305	/* Set status ignore mask */
1da177e4	306	port->ignore_status_mask = 0;
7ae75e94 AS	307	if (!(termios->c_cflag & CREAD))
	308	port->ignore_status_mask \|= UARTDR_OVERR \| UARTDR_PARERR \|
	309	UARTDR_FRMERR;
1da177e4	310
7ae75e94	311	uart_update_timeout(port, termios->c_cflag, baud);
1da177e4	312
bc000245	313	writel_relaxed(ubrlcr \| (quot - 1), port->membase + UBRLCR_OFFSET);
1da177e4 LT	314	}
1da177e4 LT	315
a1c25f2b	316	static const char uart_clps711x_type(struct uart_port port)
1da177e4	317	{
a1c25f2b	318	return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL;
1da177e4 LT	319	}
1da177e4 LT	320
a1c25f2b	321	static void uart_clps711x_config_port(struct uart_port *port, int flags)
1da177e4 LT	322	{
	323	if (flags & UART_CONFIG_TYPE)
	324	port->type = PORT_CLPS711X;
	325	}
	326
bc000245	327	static void uart_clps711x_nop_void(struct uart_port *port)
1da177e4 LT	328	{
	329	}
	330
bc000245	331	static int uart_clps711x_nop_int(struct uart_port *port)
1da177e4 LT	332	{
	333	return 0;
	334	}
	335
a1c25f2b AS	336	static const struct uart_ops uart_clps711x_ops = {
	337	.tx_empty = uart_clps711x_tx_empty,
	338	.set_mctrl = uart_clps711x_set_mctrl,
	339	.get_mctrl = uart_clps711x_get_mctrl,
	340	.stop_tx = uart_clps711x_stop_tx,
	341	.start_tx = uart_clps711x_start_tx,
bc000245 AS	342	.stop_rx = uart_clps711x_nop_void,
bc000245 AS	343	.enable_ms = uart_clps711x_nop_void,
a1c25f2b AS	344	.break_ctl = uart_clps711x_break_ctl,
	345	.startup = uart_clps711x_startup,
	346	.shutdown = uart_clps711x_shutdown,
	347	.set_termios = uart_clps711x_set_termios,
	348	.type = uart_clps711x_type,
	349	.config_port = uart_clps711x_config_port,
bc000245 AS	350	.release_port = uart_clps711x_nop_void,
bc000245 AS	351	.request_port = uart_clps711x_nop_int,
1da177e4 LT	352	};
1da177e4 LT	353
1da177e4	354	#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
117d5d42	355	static void uart_clps711x_console_putchar(struct uart_port *port, int ch)
d358788f	356	{
bc000245 AS	357	struct clps711x_port *s = dev_get_drvdata(port->dev);
	358	u32 sysflg;
	359
	360	do {
	361	regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
	362	} while (sysflg & SYSFLG_UTXFF);
117d5d42	363
bc000245	364	writew_relaxed(ch, port->membase + UARTDR_OFFSET);
d358788f RK	365	}
d358788f RK	366
117d5d42 AS	367	static void uart_clps711x_console_write(struct console co, const char c,
117d5d42 AS	368	unsigned n)
1da177e4	369	{
bc000245 AS	370	struct uart_port *port = clps711x_uart.state[co->index].uart_port;
	371	struct clps711x_port *s = dev_get_drvdata(port->dev);
	372	u32 sysflg;
1da177e4	373
117d5d42	374	uart_console_write(port, c, n, uart_clps711x_console_putchar);
1da177e4	375
117d5d42	376	/* Wait for transmitter to become empty */
bc000245 AS	377	do {
	378	regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
	379	} while (sysflg & SYSFLG_UBUSY);
1da177e4 LT	380	}
1da177e4 LT	381
bc000245	382	static int uart_clps711x_console_setup(struct console co, char options)
1da177e4	383	{
bc000245 AS	384	int baud = 38400, bits = 8, parity = 'n', flow = 'n';
	385	int ret, index = co->index;
	386	struct clps711x_port *s;
	387	struct uart_port *port;
	388	u32 ubrlcr, syscon;
	389	unsigned int quot;
1da177e4	390
bc000245 AS	391	if (index < 0 \|\| index >= UART_CLPS711X_NR)
bc000245 AS	392	return -EINVAL;
1da177e4	393
bc000245 AS	394	port = clps711x_uart.state[index].uart_port;
	395	if (!port)
	396	return -ENODEV;
1da177e4	397
bc000245	398	s = dev_get_drvdata(port->dev);
1da177e4	399
bc000245 AS	400	if (!options) {
	401	regmap_read(s->syscon, SYSCON_OFFSET, &syscon);
	402	if (syscon & SYSCON_UARTEN) {
	403	ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET);
1da177e4	404
bc000245 AS	405	if (ubrlcr & UBRLCR_PRTEN) {
	406	if (ubrlcr & UBRLCR_EVENPRT)
	407	parity = 'e';
	408	else
	409	parity = 'o';
	410	}
1da177e4	411
bc000245 AS	412	if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
	413	bits = 7;
	414
	415	quot = ubrlcr & UBRLCR_BAUD_MASK;
	416	baud = port->uartclk / (16 * (quot + 1));
	417	}
	418	} else
1da177e4	419	uart_parse_options(options, &baud, &parity, &bits, &flow);
1da177e4	420
bc000245 AS	421	ret = uart_set_options(port, co, baud, parity, bits, flow);
	422	if (ret)
	423	return ret;
	424
	425	return regmap_update_bits(s->syscon, SYSCON_OFFSET,
	426	SYSCON_UARTEN, SYSCON_UARTEN);
1da177e4	427	}
bc000245 AS	428
	429	static struct console clps711x_console = {
	430	.name = UART_CLPS711X_DEVNAME,
	431	.device = uart_console_device,
	432	.write = uart_clps711x_console_write,
	433	.setup = uart_clps711x_console_setup,
	434	.flags = CON_PRINTBUFFER,
	435	.index = -1,
	436	};
1da177e4 LT	437	#endif
1da177e4 LT	438
9671f099	439	static int uart_clps711x_probe(struct platform_device *pdev)
1da177e4	440	{
bc000245 AS	441	struct device_node *np = pdev->dev.of_node;
bc000245 AS	442	int ret, index = np ? of_alias_get_id(np, "serial") : pdev->id;
117d5d42	443	struct clps711x_port *s;
bc000245 AS	444	struct resource *res;
bc000245 AS	445	struct clk *uart_clk;
1da177e4	446
bc000245 AS	447	if (index < 0 \|\| index >= UART_CLPS711X_NR)
	448	return -EINVAL;
	449
	450	s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
	451	if (!s)
117d5d42	452	return -ENOMEM;
bc000245 AS	453
	454	uart_clk = devm_clk_get(&pdev->dev, NULL);
	455	if (IS_ERR(uart_clk))
	456	return PTR_ERR(uart_clk);
	457
	458	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	459	s->port.membase = devm_ioremap_resource(&pdev->dev, res);
	460	if (IS_ERR(s->port.membase))
	461	return PTR_ERR(s->port.membase);
	462
	463	s->port.irq = platform_get_irq(pdev, 0);
	464	if (IS_ERR_VALUE(s->port.irq))
	465	return s->port.irq;
	466
	467	s->rx_irq = platform_get_irq(pdev, 1);
	468	if (IS_ERR_VALUE(s->rx_irq))
	469	return s->rx_irq;
	470
	471	if (!np) {
	472	char syscon_name[9];
	473
	474	sprintf(syscon_name, "syscon.%i", index + 1);
	475	s->syscon = syscon_regmap_lookup_by_pdevname(syscon_name);
	476	if (IS_ERR(s->syscon))
	477	return PTR_ERR(s->syscon);
	478
	479	s->use_ms = !index;
	480	} else {
	481	s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
	482	if (IS_ERR(s->syscon))
	483	return PTR_ERR(s->syscon);
	484
	485	if (!index) {
	486	bool use_irda;
	487
	488	s->use_ms = of_property_read_bool(np, "uart-use-ms");
	489	use_irda = of_property_read_bool(np, "uart-use-irda");
	490	regmap_update_bits(s->syscon, SYSCON_OFFSET,
	491	SYSCON1_SIREN,
	492	use_irda ? SYSCON1_SIREN : 0);
	493	}
117d5d42	494	}
bc000245 AS	495
	496	s->port.line = index;
	497	s->port.dev = &pdev->dev;
	498	s->port.iotype = UPIO_MEM32;
	499	s->port.mapbase = res->start;
	500	s->port.type = PORT_CLPS711X;
	501	s->port.fifosize = 16;
	502	s->port.flags = UPF_SKIP_TEST \| UPF_FIXED_TYPE;
	503	s->port.uartclk = clk_get_rate(uart_clk);
	504	s->port.ops = &uart_clps711x_ops;
	505
117d5d42	506	platform_set_drvdata(pdev, s);
1da177e4	507
bc000245 AS	508	ret = uart_add_one_port(&clps711x_uart, &s->port);
	509	if (ret)
	510	return ret;
c08f0153	511
bc000245 AS	512	/* Disable port */
	513	if (!uart_console(&s->port))
	514	regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
	515
	516	s->tx_enabled = 1;
	517
	518	ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0,
	519	dev_name(&pdev->dev), &s->port);
117d5d42	520	if (ret) {
bc000245	521	uart_remove_one_port(&clps711x_uart, &s->port);
43b829b3	522	return ret;
117d5d42	523	}
1da177e4	524
bc000245 AS	525	ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0,
	526	dev_name(&pdev->dev), &s->port);
	527	if (ret)
	528	uart_remove_one_port(&clps711x_uart, &s->port);
1da177e4	529
bc000245	530	return ret;
1da177e4 LT	531	}
1da177e4 LT	532
ae8d8a14	533	static int uart_clps711x_remove(struct platform_device *pdev)
1da177e4	534	{
117d5d42	535	struct clps711x_port *s = platform_get_drvdata(pdev);
95113728	536
bc000245	537	return uart_remove_one_port(&clps711x_uart, &s->port);
1da177e4 LT	538	}
1da177e4 LT	539
bc000245 AS	540	static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = {
	541	{ .compatible = "cirrus,clps711x-uart", },
	542	{ }
	543	};
	544	MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids);
	545
	546	static struct platform_driver clps711x_uart_platform = {
95113728	547	.driver = {
bc000245 AS	548	.name = "clps711x-uart",
	549	.owner = THIS_MODULE,
	550	.of_match_table = of_match_ptr(clps711x_uart_dt_ids),
95113728 AS	551	},
95113728 AS	552	.probe = uart_clps711x_probe,
2d47b716	553	.remove = uart_clps711x_remove,
95113728	554	};
95113728 AS	555
	556	static int __init uart_clps711x_init(void)
	557	{
bc000245 AS	558	int ret;
	559
	560	#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
	561	clps711x_uart.cons = &clps711x_console;
	562	clps711x_console.data = &clps711x_uart;
	563	#endif
	564
	565	ret = uart_register_driver(&clps711x_uart);
	566	if (ret)
	567	return ret;
	568
	569	return platform_driver_register(&clps711x_uart_platform);
95113728 AS	570	}
	571	module_init(uart_clps711x_init);
	572
	573	static void __exit uart_clps711x_exit(void)
	574	{
bc000245 AS	575	platform_driver_unregister(&clps711x_uart_platform);
bc000245 AS	576	uart_unregister_driver(&clps711x_uart);
95113728 AS	577	}
95113728 AS	578	module_exit(uart_clps711x_exit);
1da177e4 LT	579
1da177e4 LT	580	MODULE_AUTHOR("Deep Blue Solutions Ltd");
95113728	581	MODULE_DESCRIPTION("CLPS711X serial driver");
1da177e4	582	MODULE_LICENSE("GPL");