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Disintegrate asm/system.h for CRIS
[deliverable/linux.git] / drivers / tty / serial / crisv10.c
CommitLineData
77accbf5 1/*
1da177e4
LT		 2 * Serial port driver for the ETRAX 100LX chip
3 *
77accbf5 4 * Copyright (C) 1998-2007 Axis Communications AB
1da177e4
LT		 5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
1da177e4
LT		 8 */
9
10static char *serial_version = "$Revision: 1.25 $";
11
1da177e4
LT		 12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/major.h>
21#include <linux/string.h>
22#include <linux/fcntl.h>
23#include <linux/mm.h>
24#include <linux/slab.h>
25#include <linux/init.h>
1da177e4 26#include <linux/kernel.h>
f392ecfa 27#include <linux/mutex.h>
1977f032 28#include <linux/bitops.h>
9e040a3e
JN		 29#include <linux/seq_file.h>
30#include <linux/delay.h>
31#include <linux/module.h>
32#include <linux/uaccess.h>
33#include <linux/io.h>
1da177e4 34
1da177e4 35#include <asm/irq.h>
77accbf5 36#include <asm/dma.h>
1da177e4 37#include <asm/system.h>
1da177e4 38
556dcee7 39#include <arch/svinto.h>
b1a154db 40#include <arch/system.h>
1da177e4
LT		 41
42/* non-arch dependent serial structures are in linux/serial.h */
43#include <linux/serial.h>
44/* while we keep our own stuff (struct e100_serial) in a local .h file */
77accbf5 45#include "crisv10.h"
1da177e4 46#include <asm/fasttimer.h>
556dcee7 47#include <arch/io_interface_mux.h>
1da177e4
LT		 48
49#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
50#ifndef CONFIG_ETRAX_FAST_TIMER
51#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
52#endif
53#endif
54
55#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
56 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
57#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
58#endif
59
60#if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
61#error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
62#endif
63
64/*
65 * All of the compatibilty code so we can compile serial.c against
66 * older kernels is hidden in serial_compat.h
67 */
68#if defined(LOCAL_HEADERS)
69#include "serial_compat.h"
70#endif
71
1da177e4
LT		 72struct tty_driver *serial_driver;
73
1da177e4
LT		 74/* number of characters left in xmit buffer before we ask for more */
75#define WAKEUP_CHARS 256
76
77//#define SERIAL_DEBUG_INTR
78//#define SERIAL_DEBUG_OPEN
79//#define SERIAL_DEBUG_FLOW
80//#define SERIAL_DEBUG_DATA
81//#define SERIAL_DEBUG_THROTTLE
82//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
83//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
84
85/* Enable this to use serial interrupts to handle when you
86 expect the first received event on the serial port to
87 be an error, break or similar. Used to be able to flash IRMA
88 from eLinux */
89#define SERIAL_HANDLE_EARLY_ERRORS
90
1da177e4
LT		 91/* Currently 16 descriptors x 128 bytes = 2048 bytes */
92#define SERIAL_DESCR_BUF_SIZE 256
93
94#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
95#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
96
97/* We don't want to load the system with massive fast timer interrupt
98 * on high baudrates so limit it to 250 us (4kHz) */
99#define MIN_FLUSH_TIME_USEC 250
100
101/* Add an x here to log a lot of timer stuff */
102#define TIMERD(x)
103/* Debug details of interrupt handling */
104#define DINTR1(x) /* irq on/off, errors */
105#define DINTR2(x) /* tx and rx */
106/* Debug flip buffer stuff */
107#define DFLIP(x)
108/* Debug flow control and overview of data flow */
109#define DFLOW(x)
110#define DBAUD(x)
111#define DLOG_INT_TRIG(x)
112
113//#define DEBUG_LOG_INCLUDED
114#ifndef DEBUG_LOG_INCLUDED
115#define DEBUG_LOG(line, string, value)
116#else
117struct debug_log_info
118{
119 unsigned long time;
120 unsigned long timer_data;
121// int line;
122 const char *string;
123 int value;
124};
125#define DEBUG_LOG_SIZE 4096
126
127struct debug_log_info debug_log[DEBUG_LOG_SIZE];
128int debug_log_pos = 0;
129
130#define DEBUG_LOG(_line, _string, _value) do { \
131 if ((_line) == SERIAL_DEBUG_LINE) {\
132 debug_log_func(_line, _string, _value); \
133 }\
134}while(0)
135
136void debug_log_func(int line, const char *string, int value)
137{
138 if (debug_log_pos < DEBUG_LOG_SIZE) {
139 debug_log[debug_log_pos].time = jiffies;
140 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
141// debug_log[debug_log_pos].line = line;
142 debug_log[debug_log_pos].string = string;
143 debug_log[debug_log_pos].value = value;
144 debug_log_pos++;
145 }
146 /*printk(string, value);*/
147}
148#endif
149
150#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
151/* Default number of timer ticks before flushing rx fifo
152 * When using "little data, low latency applications: use 0
153 * When using "much data applications (PPP)" use ~5
154 */
155#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
156#endif
157
158unsigned long timer_data_to_ns(unsigned long timer_data);
159
160static void change_speed(struct e100_serial *info);
161static void rs_throttle(struct tty_struct * tty);
162static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
77accbf5
JN		 163static int rs_write(struct tty_struct *tty,
164 const unsigned char *buf, int count);
1da177e4 165#ifdef CONFIG_ETRAX_RS485
77accbf5
JN		 166static int e100_write_rs485(struct tty_struct *tty,
167 const unsigned char *buf, int count);
1da177e4 168#endif
77accbf5 169static int get_lsr_info(struct e100_serial *info, unsigned int *value);
1da177e4
LT		 170
171
172#define DEF_BAUD 115200 /* 115.2 kbit/s */
173#define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
174#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
175/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
176#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
177
178/* offsets from R_SERIALx_CTRL */
179
180#define REG_DATA 0
181#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
182#define REG_TR_DATA 0
183#define REG_STATUS 1
184#define REG_TR_CTRL 1
185#define REG_REC_CTRL 2
186#define REG_BAUD 3
187#define REG_XOFF 4 /* this is a 32 bit register */
188
189/* The bitfields are the same for all serial ports */
190#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
191#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
192#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
193#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
194#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
195
196#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
197
198/* Values for info->errorcode */
199#define ERRCODE_SET_BREAK (TTY_BREAK)
200#define ERRCODE_INSERT 0x100
201#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
202
203#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
204
205/*
206 * General note regarding the use of IO_* macros in this file:
207 *
208 * We will use the bits defined for DMA channel 6 when using various
209 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
210 * the same for all channels (which of course they are).
211 *
212 * We will also use the bits defined for serial port 0 when writing commands
213 * to the different ports, as these bits too are the same for all ports.
214 */
215
216
217/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
218static const unsigned long e100_ser_int_mask = 0
219#ifdef CONFIG_ETRAX_SERIAL_PORT0
220| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
221#endif
222#ifdef CONFIG_ETRAX_SERIAL_PORT1
223| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
224#endif
225#ifdef CONFIG_ETRAX_SERIAL_PORT2
226| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
227#endif
228#ifdef CONFIG_ETRAX_SERIAL_PORT3
229| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
230#endif
231;
232unsigned long r_alt_ser_baudrate_shadow = 0;
233
234/* this is the data for the four serial ports in the etrax100 */
235/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
236/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
237
238static struct e100_serial rs_table[] = {
239 { .baud = DEF_BAUD,
d7283353 240 .ioport = (unsigned char *)R_SERIAL0_CTRL,
1da177e4
LT		 241 .irq = 1U << 12, /* uses DMA 6 and 7 */
242 .oclrintradr = R_DMA_CH6_CLR_INTR,
243 .ofirstadr = R_DMA_CH6_FIRST,
244 .ocmdadr = R_DMA_CH6_CMD,
245 .ostatusadr = R_DMA_CH6_STATUS,
246 .iclrintradr = R_DMA_CH7_CLR_INTR,
247 .ifirstadr = R_DMA_CH7_FIRST,
248 .icmdadr = R_DMA_CH7_CMD,
249 .idescradr = R_DMA_CH7_DESCR,
250 .flags = STD_FLAGS,
251 .rx_ctrl = DEF_RX,
252 .tx_ctrl = DEF_TX,
253 .iseteop = 2,
77accbf5
JN		 254 .dma_owner = dma_ser0,
255 .io_if = if_serial_0,
1da177e4
LT		 256#ifdef CONFIG_ETRAX_SERIAL_PORT0
257 .enabled = 1,
258#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
259 .dma_out_enabled = 1,
77accbf5
JN		 260 .dma_out_nbr = SER0_TX_DMA_NBR,
261 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
9cfb5c05 262 .dma_out_irq_flags = 0,
77accbf5 263 .dma_out_irq_description = "serial 0 dma tr",
1da177e4
LT		 264#else
265 .dma_out_enabled = 0,
77accbf5
JN		 266 .dma_out_nbr = UINT_MAX,
267 .dma_out_irq_nbr = 0,
268 .dma_out_irq_flags = 0,
269 .dma_out_irq_description = NULL,
1da177e4
LT		 270#endif
271#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
272 .dma_in_enabled = 1,
77accbf5
JN		 273 .dma_in_nbr = SER0_RX_DMA_NBR,
274 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
9cfb5c05 275 .dma_in_irq_flags = 0,
77accbf5 276 .dma_in_irq_description = "serial 0 dma rec",
1da177e4 277#else
77accbf5
JN		 278 .dma_in_enabled = 0,
279 .dma_in_nbr = UINT_MAX,
280 .dma_in_irq_nbr = 0,
281 .dma_in_irq_flags = 0,
282 .dma_in_irq_description = NULL,
1da177e4
LT		 283#endif
284#else
285 .enabled = 0,
77accbf5 286 .io_if_description = NULL,
1da177e4
LT		 287 .dma_out_enabled = 0,
288 .dma_in_enabled = 0
289#endif
290
291}, /* ttyS0 */
292#ifndef CONFIG_SVINTO_SIM
293 { .baud = DEF_BAUD,
d7283353 294 .ioport = (unsigned char *)R_SERIAL1_CTRL,
1da177e4
LT		 295 .irq = 1U << 16, /* uses DMA 8 and 9 */
296 .oclrintradr = R_DMA_CH8_CLR_INTR,
297 .ofirstadr = R_DMA_CH8_FIRST,
298 .ocmdadr = R_DMA_CH8_CMD,
299 .ostatusadr = R_DMA_CH8_STATUS,
300 .iclrintradr = R_DMA_CH9_CLR_INTR,
301 .ifirstadr = R_DMA_CH9_FIRST,
302 .icmdadr = R_DMA_CH9_CMD,
303 .idescradr = R_DMA_CH9_DESCR,
304 .flags = STD_FLAGS,
305 .rx_ctrl = DEF_RX,
306 .tx_ctrl = DEF_TX,
307 .iseteop = 3,
77accbf5
JN		 308 .dma_owner = dma_ser1,
309 .io_if = if_serial_1,
1da177e4
LT		 310#ifdef CONFIG_ETRAX_SERIAL_PORT1
311 .enabled = 1,
77accbf5 312 .io_if_description = "ser1",
1da177e4
LT		 313#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
314 .dma_out_enabled = 1,
77accbf5
JN		 315 .dma_out_nbr = SER1_TX_DMA_NBR,
316 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
9cfb5c05 317 .dma_out_irq_flags = 0,
77accbf5 318 .dma_out_irq_description = "serial 1 dma tr",
1da177e4
LT		 319#else
320 .dma_out_enabled = 0,
77accbf5
JN		 321 .dma_out_nbr = UINT_MAX,
322 .dma_out_irq_nbr = 0,
323 .dma_out_irq_flags = 0,
324 .dma_out_irq_description = NULL,
1da177e4
LT		 325#endif
326#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
327 .dma_in_enabled = 1,
77accbf5
JN		 328 .dma_in_nbr = SER1_RX_DMA_NBR,
329 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
9cfb5c05 330 .dma_in_irq_flags = 0,
77accbf5 331 .dma_in_irq_description = "serial 1 dma rec",
1da177e4 332#else
77accbf5
JN		 333 .dma_in_enabled = 0,
334 .dma_in_enabled = 0,
335 .dma_in_nbr = UINT_MAX,
336 .dma_in_irq_nbr = 0,
337 .dma_in_irq_flags = 0,
338 .dma_in_irq_description = NULL,
1da177e4
LT		 339#endif
340#else
341 .enabled = 0,
77accbf5
JN		 342 .io_if_description = NULL,
343 .dma_in_irq_nbr = 0,
1da177e4
LT		 344 .dma_out_enabled = 0,
345 .dma_in_enabled = 0
346#endif
347}, /* ttyS1 */
348
349 { .baud = DEF_BAUD,
d7283353 350 .ioport = (unsigned char *)R_SERIAL2_CTRL,
1da177e4
LT		 351 .irq = 1U << 4, /* uses DMA 2 and 3 */
352 .oclrintradr = R_DMA_CH2_CLR_INTR,
353 .ofirstadr = R_DMA_CH2_FIRST,
354 .ocmdadr = R_DMA_CH2_CMD,
355 .ostatusadr = R_DMA_CH2_STATUS,
356 .iclrintradr = R_DMA_CH3_CLR_INTR,
357 .ifirstadr = R_DMA_CH3_FIRST,
358 .icmdadr = R_DMA_CH3_CMD,
359 .idescradr = R_DMA_CH3_DESCR,
360 .flags = STD_FLAGS,
361 .rx_ctrl = DEF_RX,
362 .tx_ctrl = DEF_TX,
363 .iseteop = 0,
77accbf5
JN		 364 .dma_owner = dma_ser2,
365 .io_if = if_serial_2,
1da177e4
LT		 366#ifdef CONFIG_ETRAX_SERIAL_PORT2
367 .enabled = 1,
77accbf5 368 .io_if_description = "ser2",
1da177e4
LT		 369#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
370 .dma_out_enabled = 1,
77accbf5
JN		 371 .dma_out_nbr = SER2_TX_DMA_NBR,
372 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
9cfb5c05 373 .dma_out_irq_flags = 0,
77accbf5 374 .dma_out_irq_description = "serial 2 dma tr",
1da177e4
LT		 375#else
376 .dma_out_enabled = 0,
77accbf5
JN		 377 .dma_out_nbr = UINT_MAX,
378 .dma_out_irq_nbr = 0,
379 .dma_out_irq_flags = 0,
380 .dma_out_irq_description = NULL,
1da177e4
LT		 381#endif
382#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
383 .dma_in_enabled = 1,
77accbf5
JN		 384 .dma_in_nbr = SER2_RX_DMA_NBR,
385 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
9cfb5c05 386 .dma_in_irq_flags = 0,
77accbf5 387 .dma_in_irq_description = "serial 2 dma rec",
1da177e4 388#else
77accbf5
JN		 389 .dma_in_enabled = 0,
390 .dma_in_nbr = UINT_MAX,
391 .dma_in_irq_nbr = 0,
392 .dma_in_irq_flags = 0,
393 .dma_in_irq_description = NULL,
1da177e4
LT		 394#endif
395#else
396 .enabled = 0,
77accbf5 397 .io_if_description = NULL,
1da177e4
LT		 398 .dma_out_enabled = 0,
399 .dma_in_enabled = 0
400#endif
401 }, /* ttyS2 */
402
403 { .baud = DEF_BAUD,
d7283353 404 .ioport = (unsigned char *)R_SERIAL3_CTRL,
1da177e4
LT		 405 .irq = 1U << 8, /* uses DMA 4 and 5 */
406 .oclrintradr = R_DMA_CH4_CLR_INTR,
407 .ofirstadr = R_DMA_CH4_FIRST,
408 .ocmdadr = R_DMA_CH4_CMD,
409 .ostatusadr = R_DMA_CH4_STATUS,
410 .iclrintradr = R_DMA_CH5_CLR_INTR,
411 .ifirstadr = R_DMA_CH5_FIRST,
412 .icmdadr = R_DMA_CH5_CMD,
413 .idescradr = R_DMA_CH5_DESCR,
414 .flags = STD_FLAGS,
415 .rx_ctrl = DEF_RX,
416 .tx_ctrl = DEF_TX,
417 .iseteop = 1,
77accbf5
JN		 418 .dma_owner = dma_ser3,
419 .io_if = if_serial_3,
1da177e4
LT		 420#ifdef CONFIG_ETRAX_SERIAL_PORT3
421 .enabled = 1,
77accbf5 422 .io_if_description = "ser3",
1da177e4
LT		 423#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
424 .dma_out_enabled = 1,
77accbf5
JN		 425 .dma_out_nbr = SER3_TX_DMA_NBR,
426 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
9cfb5c05 427 .dma_out_irq_flags = 0,
77accbf5 428 .dma_out_irq_description = "serial 3 dma tr",
1da177e4
LT		 429#else
430 .dma_out_enabled = 0,
77accbf5
JN		 431 .dma_out_nbr = UINT_MAX,
432 .dma_out_irq_nbr = 0,
433 .dma_out_irq_flags = 0,
434 .dma_out_irq_description = NULL,
1da177e4
LT		 435#endif
436#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
437 .dma_in_enabled = 1,
77accbf5
JN		 438 .dma_in_nbr = SER3_RX_DMA_NBR,
439 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
9cfb5c05 440 .dma_in_irq_flags = 0,
77accbf5 441 .dma_in_irq_description = "serial 3 dma rec",
1da177e4 442#else
77accbf5
JN		 443 .dma_in_enabled = 0,
444 .dma_in_nbr = UINT_MAX,
445 .dma_in_irq_nbr = 0,
446 .dma_in_irq_flags = 0,
447 .dma_in_irq_description = NULL
1da177e4
LT		 448#endif
449#else
450 .enabled = 0,
77accbf5 451 .io_if_description = NULL,
1da177e4
LT		 452 .dma_out_enabled = 0,
453 .dma_in_enabled = 0
454#endif
455 } /* ttyS3 */
456#endif
457};
458
459
460#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
461
1da177e4
LT		 462#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
463static struct fast_timer fast_timers[NR_PORTS];
464#endif
465
466#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
467#define PROCSTAT(x) x
468struct ser_statistics_type {
469 int overrun_cnt;
470 int early_errors_cnt;
471 int ser_ints_ok_cnt;
472 int errors_cnt;
473 unsigned long int processing_flip;
474 unsigned long processing_flip_still_room;
475 unsigned long int timeout_flush_cnt;
476 int rx_dma_ints;
477 int tx_dma_ints;
478 int rx_tot;
479 int tx_tot;
480};
481
482static struct ser_statistics_type ser_stat[NR_PORTS];
483
484#else
485
486#define PROCSTAT(x)
487
488#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
489
490/* RS-485 */
491#if defined(CONFIG_ETRAX_RS485)
492#ifdef CONFIG_ETRAX_FAST_TIMER
493static struct fast_timer fast_timers_rs485[NR_PORTS];
494#endif
495#if defined(CONFIG_ETRAX_RS485_ON_PA)
496static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
497#endif
498#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
499static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
500#endif
501#endif
502
503/* Info and macros needed for each ports extra control/status signals. */
504#define E100_STRUCT_PORT(line, pinname) \
505 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
506 (R_PORT_PA_DATA): ( \
507 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
508 (R_PORT_PB_DATA):&dummy_ser[line]))
509
510#define E100_STRUCT_SHADOW(line, pinname) \
511 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
512 (&port_pa_data_shadow): ( \
513 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
514 (&port_pb_data_shadow):&dummy_ser[line]))
515#define E100_STRUCT_MASK(line, pinname) \
516 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
517 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
518 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
519 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
520
521#define DUMMY_DTR_MASK 1
522#define DUMMY_RI_MASK 2
523#define DUMMY_DSR_MASK 4
524#define DUMMY_CD_MASK 8
525static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
526
527/* If not all status pins are used or disabled, use mixed mode */
528#ifdef CONFIG_ETRAX_SERIAL_PORT0
529
530#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
531
532#if SER0_PA_BITSUM != -4
533# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
534# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
535# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
536# endif
537# endif
538# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
539# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
540# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
541# endif
542# endif
543# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
544# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
545# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
546# endif
547# endif
548# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
549# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
550# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
551# endif
552# endif
553#endif
554
555#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
556
557#if SER0_PB_BITSUM != -4
558# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
559# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
560# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
561# endif
562# endif
563# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
564# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
565# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
566# endif
567# endif
568# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
569# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
570# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
571# endif
572# endif
573# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
574# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
575# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
576# endif
577# endif
578#endif
579
580#endif /* PORT0 */
581
582
583#ifdef CONFIG_ETRAX_SERIAL_PORT1
584
585#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
586
587#if SER1_PA_BITSUM != -4
588# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
589# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
590# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
591# endif
592# endif
593# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
594# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
595# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
596# endif
597# endif
598# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
599# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
600# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
601# endif
602# endif
603# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
604# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
605# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
606# endif
607# endif
608#endif
609
610#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
611
612#if SER1_PB_BITSUM != -4
613# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
614# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
615# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
616# endif
617# endif
618# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
619# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
620# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
621# endif
622# endif
623# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
624# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
625# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
626# endif
627# endif
628# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
629# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
630# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
631# endif
632# endif
633#endif
634
635#endif /* PORT1 */
636
637#ifdef CONFIG_ETRAX_SERIAL_PORT2
638
639#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
640
641#if SER2_PA_BITSUM != -4
642# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
643# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
644# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
645# endif
646# endif
647# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
648# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
649# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
650# endif
651# endif
652# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
653# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
654# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
655# endif
656# endif
657# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
658# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
659# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
660# endif
661# endif
662#endif
663
664#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
665
666#if SER2_PB_BITSUM != -4
667# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
668# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
669# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
670# endif
671# endif
672# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
673# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
674# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
675# endif
676# endif
677# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
678# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
679# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
680# endif
681# endif
682# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
683# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
684# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
685# endif
686# endif
687#endif
688
689#endif /* PORT2 */
690
691#ifdef CONFIG_ETRAX_SERIAL_PORT3
692
693#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
694
695#if SER3_PA_BITSUM != -4
696# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
697# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
698# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
699# endif
700# endif
701# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
702# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
703# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
704# endif
705# endif
706# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
707# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
708# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
709# endif
710# endif
711# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
712# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
713# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
714# endif
715# endif
716#endif
717
718#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
719
720#if SER3_PB_BITSUM != -4
721# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
722# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
723# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
724# endif
725# endif
726# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
727# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
728# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
729# endif
730# endif
731# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
732# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
733# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
734# endif
735# endif
736# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
737# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
738# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
739# endif
740# endif
741#endif
742
743#endif /* PORT3 */
744
745
746#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
747 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
748 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
749 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
750#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
751#endif
752
753#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
754/* The pins can be mixed on PA and PB */
755#define CONTROL_PINS_PORT_NOT_USED(line) \
756 &dummy_ser[line], &dummy_ser[line], \
757 &dummy_ser[line], &dummy_ser[line], \
758 &dummy_ser[line], &dummy_ser[line], \
759 &dummy_ser[line], &dummy_ser[line], \
760 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
761
762
763struct control_pins
764{
765 volatile unsigned char *dtr_port;
766 unsigned char *dtr_shadow;
767 volatile unsigned char *ri_port;
768 unsigned char *ri_shadow;
769 volatile unsigned char *dsr_port;
770 unsigned char *dsr_shadow;
771 volatile unsigned char *cd_port;
772 unsigned char *cd_shadow;
773
774 unsigned char dtr_mask;
775 unsigned char ri_mask;
776 unsigned char dsr_mask;
777 unsigned char cd_mask;
778};
779
780static const struct control_pins e100_modem_pins[NR_PORTS] =
781{
782 /* Ser 0 */
783 {
784#ifdef CONFIG_ETRAX_SERIAL_PORT0
785 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
786 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
787 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
788 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
789 E100_STRUCT_MASK(0,DTR),
790 E100_STRUCT_MASK(0,RI),
791 E100_STRUCT_MASK(0,DSR),
792 E100_STRUCT_MASK(0,CD)
793#else
794 CONTROL_PINS_PORT_NOT_USED(0)
795#endif
796 },
797
798 /* Ser 1 */
799 {
800#ifdef CONFIG_ETRAX_SERIAL_PORT1
801 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
802 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
803 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
804 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
805 E100_STRUCT_MASK(1,DTR),
806 E100_STRUCT_MASK(1,RI),
807 E100_STRUCT_MASK(1,DSR),
808 E100_STRUCT_MASK(1,CD)
809#else
810 CONTROL_PINS_PORT_NOT_USED(1)
811#endif
812 },
813
814 /* Ser 2 */
815 {
816#ifdef CONFIG_ETRAX_SERIAL_PORT2
817 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
818 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
819 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
820 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
821 E100_STRUCT_MASK(2,DTR),
822 E100_STRUCT_MASK(2,RI),
823 E100_STRUCT_MASK(2,DSR),
824 E100_STRUCT_MASK(2,CD)
825#else
826 CONTROL_PINS_PORT_NOT_USED(2)
827#endif
828 },
829
830 /* Ser 3 */
831 {
832#ifdef CONFIG_ETRAX_SERIAL_PORT3
833 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
834 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
835 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
836 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
837 E100_STRUCT_MASK(3,DTR),
838 E100_STRUCT_MASK(3,RI),
839 E100_STRUCT_MASK(3,DSR),
840 E100_STRUCT_MASK(3,CD)
841#else
842 CONTROL_PINS_PORT_NOT_USED(3)
843#endif
844 }
845};
846#else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
847
848/* All pins are on either PA or PB for each serial port */
849#define CONTROL_PINS_PORT_NOT_USED(line) \
850 &dummy_ser[line], &dummy_ser[line], \
851 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
852
853
854struct control_pins
855{
856 volatile unsigned char *port;
857 unsigned char *shadow;
858
859 unsigned char dtr_mask;
860 unsigned char ri_mask;
861 unsigned char dsr_mask;
862 unsigned char cd_mask;
863};
864
865#define dtr_port port
866#define dtr_shadow shadow
867#define ri_port port
868#define ri_shadow shadow
869#define dsr_port port
870#define dsr_shadow shadow
871#define cd_port port
872#define cd_shadow shadow
873
874static const struct control_pins e100_modem_pins[NR_PORTS] =
875{
876 /* Ser 0 */
877 {
878#ifdef CONFIG_ETRAX_SERIAL_PORT0
879 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
880 E100_STRUCT_MASK(0,DTR),
881 E100_STRUCT_MASK(0,RI),
882 E100_STRUCT_MASK(0,DSR),
883 E100_STRUCT_MASK(0,CD)
884#else
885 CONTROL_PINS_PORT_NOT_USED(0)
886#endif
887 },
888
889 /* Ser 1 */
890 {
891#ifdef CONFIG_ETRAX_SERIAL_PORT1
892 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
893 E100_STRUCT_MASK(1,DTR),
894 E100_STRUCT_MASK(1,RI),
895 E100_STRUCT_MASK(1,DSR),
896 E100_STRUCT_MASK(1,CD)
897#else
898 CONTROL_PINS_PORT_NOT_USED(1)
899#endif
900 },
901
902 /* Ser 2 */
903 {
904#ifdef CONFIG_ETRAX_SERIAL_PORT2
905 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
906 E100_STRUCT_MASK(2,DTR),
907 E100_STRUCT_MASK(2,RI),
908 E100_STRUCT_MASK(2,DSR),
909 E100_STRUCT_MASK(2,CD)
910#else
911 CONTROL_PINS_PORT_NOT_USED(2)
912#endif
913 },
914
915 /* Ser 3 */
916 {
917#ifdef CONFIG_ETRAX_SERIAL_PORT3
918 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
919 E100_STRUCT_MASK(3,DTR),
920 E100_STRUCT_MASK(3,RI),
921 E100_STRUCT_MASK(3,DSR),
922 E100_STRUCT_MASK(3,CD)
923#else
924 CONTROL_PINS_PORT_NOT_USED(3)
925#endif
926 }
927};
928#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
929
930#define E100_RTS_MASK 0x20
931#define E100_CTS_MASK 0x40
932
933/* All serial port signals are active low:
934 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
935 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
936 *
937 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
938 */
939
940/* Output */
941#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
942/* Input */
d7283353 943#define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
1da177e4
LT		 944
945/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
946/* Is an output */
947#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
948
949/* Normally inputs */
950#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
951#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
952
953/* Input */
954#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
955
956
957/*
958 * tmp_buf is used as a temporary buffer by serial_write. We need to
959 * lock it in case the memcpy_fromfs blocks while swapping in a page,
960 * and some other program tries to do a serial write at the same time.
961 * Since the lock will only come under contention when the system is
962 * swapping and available memory is low, it makes sense to share one
963 * buffer across all the serial ports, since it significantly saves
964 * memory if large numbers of serial ports are open.
965 */
966static unsigned char *tmp_buf;
f392ecfa 967static DEFINE_MUTEX(tmp_buf_mutex);
1da177e4
LT		 968
969/* Calculate the chartime depending on baudrate, numbor of bits etc. */
970static void update_char_time(struct e100_serial * info)
971{
a88487c7 972 tcflag_t cflags = info->port.tty->termios->c_cflag;
1da177e4
LT		 973 int bits;
974
975 /* calc. number of bits / data byte */
976 /* databits + startbit and 1 stopbit */
977 if ((cflags & CSIZE) == CS7)
978 bits = 9;
979 else
980 bits = 10;
981
982 if (cflags & CSTOPB) /* 2 stopbits ? */
983 bits++;
984
985 if (cflags & PARENB) /* parity bit ? */
986 bits++;
987
988 /* calc timeout */
989 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
990 info->flush_time_usec = 4*info->char_time_usec;
991 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
992 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
993
994}
995
996/*
997 * This function maps from the Bxxxx defines in asm/termbits.h into real
998 * baud rates.
999 */
1000
1001static int
1002cflag_to_baud(unsigned int cflag)
1003{
1004 static int baud_table[] = {
1005 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
1006 4800, 9600, 19200, 38400 };
1007
1008 static int ext_baud_table[] = {
1009 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
1010 0, 0, 0, 0, 0, 0, 0, 0 };
1011
1012 if (cflag & CBAUDEX)
1013 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1014 else
1015 return baud_table[cflag & CBAUD];
1016}
1017
1018/* and this maps to an etrax100 hardware baud constant */
1019
1020static unsigned char
1021cflag_to_etrax_baud(unsigned int cflag)
1022{
1023 char retval;
1024
1025 static char baud_table[] = {
1026 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1027
1028 static char ext_baud_table[] = {
1029 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1030
1031 if (cflag & CBAUDEX)
1032 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1033 else
1034 retval = baud_table[cflag & CBAUD];
1035
1036 if (retval < 0) {
1037 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1038 retval = 5; /* choose default 9600 instead */
1039 }
1040
1041 return retval | (retval << 4); /* choose same for both TX and RX */
1042}
1043
1044
1045/* Various static support functions */
1046
1047/* Functions to set or clear DTR/RTS on the requested line */
1048/* It is complicated by the fact that RTS is a serial port register, while
1049 * DTR might not be implemented in the HW at all, and if it is, it can be on
1050 * any general port.
1051 */
1052
1053
1054static inline void
1055e100_dtr(struct e100_serial *info, int set)
1056{
1057#ifndef CONFIG_SVINTO_SIM
1058 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1059
1060#ifdef SERIAL_DEBUG_IO
1061 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1062 printk("ser%i shadow before 0x%02X get: %i\n",
1063 info->line, *e100_modem_pins[info->line].dtr_shadow,
1064 E100_DTR_GET(info));
1065#endif
1066 /* DTR is active low */
1067 {
1068 unsigned long flags;
1069
77accbf5 1070 local_irq_save(flags);
1da177e4
LT		 1071 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1072 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1073 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
77accbf5 1074 local_irq_restore(flags);
1da177e4
LT		 1075 }
1076
1077#ifdef SERIAL_DEBUG_IO
1078 printk("ser%i shadow after 0x%02X get: %i\n",
1079 info->line, *e100_modem_pins[info->line].dtr_shadow,
1080 E100_DTR_GET(info));
1081#endif
1082#endif
1083}
1084
1085/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1086 * 0=0V , 1=3.3V
1087 */
1088static inline void
1089e100_rts(struct e100_serial *info, int set)
1090{
1091#ifndef CONFIG_SVINTO_SIM
1092 unsigned long flags;
77accbf5 1093 local_irq_save(flags);
1da177e4
LT		 1094 info->rx_ctrl &= ~E100_RTS_MASK;
1095 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
d7283353 1096 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
77accbf5 1097 local_irq_restore(flags);
1da177e4
LT		 1098#ifdef SERIAL_DEBUG_IO
1099 printk("ser%i rts %i\n", info->line, set);
1100#endif
1101#endif
1102}
1103
1104
1105/* If this behaves as a modem, RI and CD is an output */
1106static inline void
1107e100_ri_out(struct e100_serial *info, int set)
1108{
1109#ifndef CONFIG_SVINTO_SIM
1110 /* RI is active low */
1111 {
1112 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1113 unsigned long flags;
1114
77accbf5 1115 local_irq_save(flags);
1da177e4
LT		 1116 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1117 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1118 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
77accbf5 1119 local_irq_restore(flags);
1da177e4
LT		 1120 }
1121#endif
1122}
1123static inline void
1124e100_cd_out(struct e100_serial *info, int set)
1125{
1126#ifndef CONFIG_SVINTO_SIM
1127 /* CD is active low */
1128 {
1129 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1130 unsigned long flags;
1131
77accbf5 1132 local_irq_save(flags);
1da177e4
LT		 1133 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1134 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1135 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
77accbf5 1136 local_irq_restore(flags);
1da177e4
LT		 1137 }
1138#endif
1139}
1140
1141static inline void
1142e100_disable_rx(struct e100_serial *info)
1143{
1144#ifndef CONFIG_SVINTO_SIM
1145 /* disable the receiver */
d7283353 1146 info->ioport[REG_REC_CTRL] =
1da177e4
LT		 1147 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1148#endif
1149}
1150
1151static inline void
1152e100_enable_rx(struct e100_serial *info)
1153{
1154#ifndef CONFIG_SVINTO_SIM
1155 /* enable the receiver */
d7283353 1156 info->ioport[REG_REC_CTRL] =
1da177e4
LT		 1157 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1158#endif
1159}
1160
1161/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1162
1163static inline void
1164e100_disable_rxdma_irq(struct e100_serial *info)
1165{
1166#ifdef SERIAL_DEBUG_INTR
1167 printk("rxdma_irq(%d): 0\n",info->line);
1168#endif
1169 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1170 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1171}
1172
1173static inline void
1174e100_enable_rxdma_irq(struct e100_serial *info)
1175{
1176#ifdef SERIAL_DEBUG_INTR
1177 printk("rxdma_irq(%d): 1\n",info->line);
1178#endif
1179 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1180 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1181}
1182
1183/* the tx DMA uses only dma_descr interrupt */
1184
41c28ff1 1185static void e100_disable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1186{
1187#ifdef SERIAL_DEBUG_INTR
1188 printk("txdma_irq(%d): 0\n",info->line);
1189#endif
1190 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1191 *R_IRQ_MASK2_CLR = info->irq;
1192}
1193
41c28ff1 1194static void e100_enable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1195{
1196#ifdef SERIAL_DEBUG_INTR
1197 printk("txdma_irq(%d): 1\n",info->line);
1198#endif
1199 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1200 *R_IRQ_MASK2_SET = info->irq;
1201}
1202
41c28ff1 1203static void e100_disable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1204{
1205 unsigned long flags;
1206
1207 /* Disable output DMA channel for the serial port in question
025dfdaf 1208 * ( set to something other than serialX)
1da177e4 1209 */
77accbf5 1210 local_irq_save(flags);
1da177e4
LT		 1211 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1212 if (info->line == 0) {
1213 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1214 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1215 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1216 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1217 }
1218 } else if (info->line == 1) {
1219 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1220 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1221 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1222 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1223 }
1224 } else if (info->line == 2) {
1225 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1226 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1227 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1228 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1229 }
1230 } else if (info->line == 3) {
1231 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1232 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1233 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1234 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1235 }
1236 }
1237 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1238 local_irq_restore(flags);
1da177e4
LT		 1239}
1240
1241
41c28ff1 1242static void e100_enable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1243{
1244 unsigned long flags;
1245
77accbf5 1246 local_irq_save(flags);
1da177e4
LT		 1247 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1248 /* Enable output DMA channel for the serial port in question */
1249 if (info->line == 0) {
1250 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1251 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1252 } else if (info->line == 1) {
1253 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1254 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1255 } else if (info->line == 2) {
1256 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1257 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1258 } else if (info->line == 3) {
1259 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1260 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1261 }
1262 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1263 local_irq_restore(flags);
1da177e4
LT		 1264}
1265
41c28ff1 1266static void e100_disable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1267{
1268 unsigned long flags;
1269
1270 /* Disable input DMA channel for the serial port in question
025dfdaf 1271 * ( set to something other than serialX)
1da177e4 1272 */
77accbf5 1273 local_irq_save(flags);
1da177e4
LT		 1274 if (info->line == 0) {
1275 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1276 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1277 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1278 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1279 }
1280 } else if (info->line == 1) {
1281 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1282 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1283 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1284 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1285 }
1286 } else if (info->line == 2) {
1287 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1288 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1289 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1290 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1291 }
1292 } else if (info->line == 3) {
1293 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1294 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1295 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1296 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1297 }
1298 }
1299 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1300 local_irq_restore(flags);
1da177e4
LT		 1301}
1302
1303
41c28ff1 1304static void e100_enable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1305{
1306 unsigned long flags;
1307
77accbf5 1308 local_irq_save(flags);
1da177e4
LT		 1309 /* Enable input DMA channel for the serial port in question */
1310 if (info->line == 0) {
1311 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1312 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1313 } else if (info->line == 1) {
1314 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1315 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1316 } else if (info->line == 2) {
1317 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1318 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1319 } else if (info->line == 3) {
1320 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1321 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1322 }
1323 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1324 local_irq_restore(flags);
1da177e4
LT		 1325}
1326
1327#ifdef SERIAL_HANDLE_EARLY_ERRORS
1328/* in order to detect and fix errors on the first byte
1329 we have to use the serial interrupts as well. */
1330
1331static inline void
1332e100_disable_serial_data_irq(struct e100_serial *info)
1333{
1334#ifdef SERIAL_DEBUG_INTR
1335 printk("ser_irq(%d): 0\n",info->line);
1336#endif
1337 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1338 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1339}
1340
1341static inline void
1342e100_enable_serial_data_irq(struct e100_serial *info)
1343{
1344#ifdef SERIAL_DEBUG_INTR
1345 printk("ser_irq(%d): 1\n",info->line);
1346 printk("**** %d = %d\n",
1347 (8+2*info->line),
1348 (1U << (8+2*info->line)));
1349#endif
1350 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1351 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1352}
1353#endif
1354
1355static inline void
1356e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1357{
1358#ifdef SERIAL_DEBUG_INTR
1359 printk("ser_tx_irq(%d): 0\n",info->line);
1360#endif
1361 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1362 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1363}
1364
1365static inline void
1366e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1367{
1368#ifdef SERIAL_DEBUG_INTR
1369 printk("ser_tx_irq(%d): 1\n",info->line);
1370 printk("**** %d = %d\n",
1371 (8+1+2*info->line),
1372 (1U << (8+1+2*info->line)));
1373#endif
1374 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1375 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1376}
1377
1378static inline void e100_enable_rx_irq(struct e100_serial *info)
1379{
1380 if (info->uses_dma_in)
1381 e100_enable_rxdma_irq(info);
1382 else
1383 e100_enable_serial_data_irq(info);
1384}
1385static inline void e100_disable_rx_irq(struct e100_serial *info)
1386{
1387 if (info->uses_dma_in)
1388 e100_disable_rxdma_irq(info);
1389 else
1390 e100_disable_serial_data_irq(info);
1391}
1392
1393#if defined(CONFIG_ETRAX_RS485)
1394/* Enable RS-485 mode on selected port. This is UGLY. */
1395static int
6fd1af4c 1396e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1da177e4
LT		 1397{
1398 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1399
1400#if defined(CONFIG_ETRAX_RS485_ON_PA)
1401 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1402#endif
1403#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1404 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1405 rs485_port_g_bit, 1);
1406#endif
1407#if defined(CONFIG_ETRAX_RS485_LTC1387)
1408 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1409 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1410 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1411 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1412#endif
1413
c7213fc4
JN		 1414 info->rs485 = *r;
1415
1416 /* Maximum delay before RTS equal to 1000 */
1417 if (info->rs485.delay_rts_before_send >= 1000)
1da177e4 1418 info->rs485.delay_rts_before_send = 1000;
c7213fc4 1419
1da177e4
LT		 1420/* printk("rts: on send = %i, after = %i, enabled = %i",
1421 info->rs485.rts_on_send,
1422 info->rs485.rts_after_sent,
1423 info->rs485.enabled
1424 );
1425*/
1426 return 0;
1427}
1428
1429static int
77accbf5 1430e100_write_rs485(struct tty_struct *tty,
1da177e4
LT		 1431 const unsigned char *buf, int count)
1432{
1433 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
6fd1af4c 1434 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1da177e4
LT		 1435
1436 /* rs485 is always implicitly enabled if we're using the ioctl()
6fd1af4c 1437 * but it doesn't have to be set in the serial_rs485
1da177e4
LT		 1438 * (to be backward compatible with old apps)
1439 * So we store, set and restore it.
1440 */
6fd1af4c 1441 info->rs485.flags |= SER_RS485_ENABLED;
1da177e4 1442 /* rs_write now deals with RS485 if enabled */
77accbf5 1443 count = rs_write(tty, buf, count);
6fd1af4c
CS		 1444 if (!old_value)
1445 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 1446 return count;
1447}
1448
1449#ifdef CONFIG_ETRAX_FAST_TIMER
1450/* Timer function to toggle RTS when using FAST_TIMER */
1451static void rs485_toggle_rts_timer_function(unsigned long data)
1452{
1453 struct e100_serial *info = (struct e100_serial *)data;
1454
1455 fast_timers_rs485[info->line].function = NULL;
6fd1af4c 1456 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 1457#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1458 e100_enable_rx(info);
1459 e100_enable_rx_irq(info);
1460#endif
1461}
1462#endif
1463#endif /* CONFIG_ETRAX_RS485 */
1464
1465/*
1466 * ------------------------------------------------------------
1467 * rs_stop() and rs_start()
1468 *
1469 * This routines are called before setting or resetting tty->stopped.
1470 * They enable or disable transmitter using the XOFF registers, as necessary.
1471 * ------------------------------------------------------------
1472 */
1473
1474static void
1475rs_stop(struct tty_struct *tty)
1476{
1477 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1478 if (info) {
1479 unsigned long flags;
1480 unsigned long xoff;
1481
77accbf5 1482 local_irq_save(flags);
1da177e4
LT		 1483 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1484 CIRC_CNT(info->xmit.head,
1485 info->xmit.tail,SERIAL_XMIT_SIZE)));
1486
a88487c7
TI		 1487 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1488 STOP_CHAR(info->port.tty));
1da177e4
LT		 1489 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1490 if (tty->termios->c_iflag & IXON ) {
1491 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1492 }
1493
d7283353 1494 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 1495 local_irq_restore(flags);
1da177e4
LT		 1496 }
1497}
1498
1499static void
1500rs_start(struct tty_struct *tty)
1501{
1502 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1503 if (info) {
1504 unsigned long flags;
1505 unsigned long xoff;
1506
77accbf5 1507 local_irq_save(flags);
1da177e4
LT		 1508 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1509 CIRC_CNT(info->xmit.head,
1510 info->xmit.tail,SERIAL_XMIT_SIZE)));
1511 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1512 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1513 if (tty->termios->c_iflag & IXON ) {
1514 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1515 }
1516
d7283353 1517 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1da177e4
LT		 1518 if (!info->uses_dma_out &&
1519 info->xmit.head != info->xmit.tail && info->xmit.buf)
1520 e100_enable_serial_tx_ready_irq(info);
1521
77accbf5 1522 local_irq_restore(flags);
1da177e4
LT		 1523 }
1524}
1525
1526/*
1527 * ----------------------------------------------------------------------
1528 *
1529 * Here starts the interrupt handling routines. All of the following
1530 * subroutines are declared as inline and are folded into
1531 * rs_interrupt(). They were separated out for readability's sake.
1532 *
1533 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1534 * runs with interrupts turned off. People who may want to modify
1535 * rs_interrupt() should try to keep the interrupt handler as fast as
1536 * possible. After you are done making modifications, it is not a bad
1537 * idea to do:
1538 *
1539 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1540 *
1541 * and look at the resulting assemble code in serial.s.
1542 *
1543 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1544 * -----------------------------------------------------------------------
1545 */
1546
1547/*
1548 * This routine is used by the interrupt handler to schedule
1549 * processing in the software interrupt portion of the driver.
1550 */
41c28ff1 1551static void rs_sched_event(struct e100_serial *info, int event)
1da177e4
LT		 1552{
1553 if (info->event & (1 << event))
1554 return;
1555 info->event |= 1 << event;
1556 schedule_work(&info->work);
1557}
1558
1559/* The output DMA channel is free - use it to send as many chars as possible
1560 * NOTES:
1561 * We don't pay attention to info->x_char, which means if the TTY wants to
1562 * use XON/XOFF it will set info->x_char but we won't send any X char!
1563 *
1564 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1565 * buffer containing the X char, and skip updating xmit. We'd also have to
1566 * check if the last sent char was the X char when we enter this function
1567 * the next time, to avoid updating xmit with the sent X value.
1568 */
1569
1570static void
1571transmit_chars_dma(struct e100_serial *info)
1572{
1573 unsigned int c, sentl;
1574 struct etrax_dma_descr *descr;
1575
1576#ifdef CONFIG_SVINTO_SIM
1577 /* This will output too little if tail is not 0 always since
1578 * we don't reloop to send the other part. Anyway this SHOULD be a
1579 * no-op - transmit_chars_dma would never really be called during sim
1580 * since rs_write does not write into the xmit buffer then.
1581 */
1582 if (info->xmit.tail)
1583 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1584 if (info->xmit.head != info->xmit.tail) {
1585 SIMCOUT(info->xmit.buf + info->xmit.tail,
1586 CIRC_CNT(info->xmit.head,
1587 info->xmit.tail,
1588 SERIAL_XMIT_SIZE));
1589 info->xmit.head = info->xmit.tail; /* move back head */
1590 info->tr_running = 0;
1591 }
1592 return;
1593#endif
1594 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1595 *info->oclrintradr =
1596 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1597 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1598
1599#ifdef SERIAL_DEBUG_INTR
1600 if (info->line == SERIAL_DEBUG_LINE)
1601 printk("tc\n");
1602#endif
1603 if (!info->tr_running) {
1604 /* weirdo... we shouldn't get here! */
1605 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1606 return;
1607 }
1608
1609 descr = &info->tr_descr;
1610
1611 /* first get the amount of bytes sent during the last DMA transfer,
1612 and update xmit accordingly */
1613
1614 /* if the stop bit was not set, all data has been sent */
1615 if (!(descr->status & d_stop)) {
1616 sentl = descr->sw_len;
1617 } else
1618 /* otherwise we find the amount of data sent here */
1619 sentl = descr->hw_len;
1620
1621 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1622
1623 /* update stats */
1624 info->icount.tx += sentl;
1625
1626 /* update xmit buffer */
1627 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1628
1629 /* if there is only a few chars left in the buf, wake up the blocked
1630 write if any */
1631 if (CIRC_CNT(info->xmit.head,
1632 info->xmit.tail,
1633 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1634 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1635
1636 /* find out the largest amount of consecutive bytes we want to send now */
1637
1638 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1639
1640 /* Don't send all in one DMA transfer - divide it so we wake up
1641 * application before all is sent
1642 */
1643
1644 if (c >= 4*WAKEUP_CHARS)
1645 c = c/2;
1646
1647 if (c <= 0) {
1648 /* our job here is done, don't schedule any new DMA transfer */
1649 info->tr_running = 0;
1650
1651#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 1652 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 1653 /* Set a short timer to toggle RTS */
1654 start_one_shot_timer(&fast_timers_rs485[info->line],
1655 rs485_toggle_rts_timer_function,
1656 (unsigned long)info,
1657 info->char_time_usec*2,
1658 "RS-485");
1659 }
1660#endif /* RS485 */
1661 return;
1662 }
1663
1664 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1665 /* set up the descriptor correctly for output */
1666 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1667 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1668 descr->sw_len = c;
1669 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1670 descr->status = 0;
1671
1672 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1673 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1674
1675 /* DMA is now running (hopefully) */
1676} /* transmit_chars_dma */
1677
1678static void
1679start_transmit(struct e100_serial *info)
1680{
1681#if 0
1682 if (info->line == SERIAL_DEBUG_LINE)
1683 printk("x\n");
1684#endif
1685
1686 info->tr_descr.sw_len = 0;
1687 info->tr_descr.hw_len = 0;
1688 info->tr_descr.status = 0;
1689 info->tr_running = 1;
1690 if (info->uses_dma_out)
1691 transmit_chars_dma(info);
1692 else
1693 e100_enable_serial_tx_ready_irq(info);
1694} /* start_transmit */
1695
1696#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1697static int serial_fast_timer_started = 0;
1698static int serial_fast_timer_expired = 0;
1699static void flush_timeout_function(unsigned long data);
1700#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1701 unsigned long timer_flags; \
77accbf5 1702 local_irq_save(timer_flags); \
1da177e4
LT		 1703 if (fast_timers[info->line].function == NULL) { \
1704 serial_fast_timer_started++; \
1705 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1706 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1707 start_one_shot_timer(&fast_timers[info->line], \
1708 flush_timeout_function, \
1709 (unsigned long)info, \
1710 (usec), \
1711 string); \
1712 } \
1713 else { \
1714 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1715 } \
77accbf5 1716 local_irq_restore(timer_flags); \
1da177e4
LT		 1717}
1718#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1719
1720#else
1721#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1722#define START_FLUSH_FAST_TIMER(info, string)
1723#endif
1724
1725static struct etrax_recv_buffer *
1726alloc_recv_buffer(unsigned int size)
1727{
1728 struct etrax_recv_buffer *buffer;
1729
1730 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1731 return NULL;
1732
1733 buffer->next = NULL;
1734 buffer->length = 0;
1735 buffer->error = TTY_NORMAL;
1736
1737 return buffer;
1738}
1739
1740static void
1741append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1742{
1743 unsigned long flags;
1744
77accbf5 1745 local_irq_save(flags);
1da177e4
LT		 1746
1747 if (!info->first_recv_buffer)
1748 info->first_recv_buffer = buffer;
1749 else
1750 info->last_recv_buffer->next = buffer;
1751
1752 info->last_recv_buffer = buffer;
1753
1754 info->recv_cnt += buffer->length;
1755 if (info->recv_cnt > info->max_recv_cnt)
1756 info->max_recv_cnt = info->recv_cnt;
1757
77accbf5 1758 local_irq_restore(flags);
1da177e4
LT		 1759}
1760
1761static int
1762add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1763{
1764 struct etrax_recv_buffer *buffer;
1765 if (info->uses_dma_in) {
1766 if (!(buffer = alloc_recv_buffer(4)))
1767 return 0;
1768
1769 buffer->length = 1;
1770 buffer->error = flag;
1771 buffer->buffer[0] = data;
1772
1773 append_recv_buffer(info, buffer);
1774
1775 info->icount.rx++;
1776 } else {
a88487c7 1777 struct tty_struct *tty = info->port.tty;
77accbf5 1778 tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 1779 info->icount.rx++;
1780 }
1781
1782 return 1;
1783}
1784
41c28ff1
AB		 1785static unsigned int handle_descr_data(struct e100_serial *info,
1786 struct etrax_dma_descr *descr,
1787 unsigned int recvl)
1da177e4
LT		 1788{
1789 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1790
1791 if (info->recv_cnt + recvl > 65536) {
3d43b7d5 1792 printk(KERN_WARNING
71cc2c21 1793 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1da177e4
LT		 1794 return 0;
1795 }
1796
1797 buffer->length = recvl;
1798
1799 if (info->errorcode == ERRCODE_SET_BREAK)
1800 buffer->error = TTY_BREAK;
1801 info->errorcode = 0;
1802
1803 append_recv_buffer(info, buffer);
1804
1805 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
71cc2c21 1806 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1807
1808 descr->buf = virt_to_phys(buffer->buffer);
1809
1810 return recvl;
1811}
1812
41c28ff1 1813static unsigned int handle_all_descr_data(struct e100_serial *info)
1da177e4
LT		 1814{
1815 struct etrax_dma_descr *descr;
1816 unsigned int recvl;
1817 unsigned int ret = 0;
1818
1819 while (1)
1820 {
1821 descr = &info->rec_descr[info->cur_rec_descr];
1822
1823 if (descr == phys_to_virt(*info->idescradr))
1824 break;
1825
1826 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1827 info->cur_rec_descr = 0;
1828
1829 /* find out how many bytes were read */
1830
1831 /* if the eop bit was not set, all data has been received */
1832 if (!(descr->status & d_eop)) {
1833 recvl = descr->sw_len;
1834 } else {
1835 /* otherwise we find the amount of data received here */
1836 recvl = descr->hw_len;
1837 }
1838
1839 /* Reset the status information */
1840 descr->status = 0;
1841
1842 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
a88487c7 1843 if (info->port.tty->stopped) {
1da177e4
LT		 1844 unsigned char *buf = phys_to_virt(descr->buf);
1845 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1846 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1847 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1848 }
1849 );
1850
1851 /* update stats */
1852 info->icount.rx += recvl;
1853
1854 ret += handle_descr_data(info, descr, recvl);
1855 }
1856
1857 return ret;
1858}
1859
41c28ff1 1860static void receive_chars_dma(struct e100_serial *info)
1da177e4
LT		 1861{
1862 struct tty_struct *tty;
1863 unsigned char rstat;
1864
1865#ifdef CONFIG_SVINTO_SIM
1866 /* No receive in the simulator. Will probably be when the rest of
1867 * the serial interface works, and this piece will just be removed.
1868 */
1869 return;
1870#endif
1871
1872 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1873 *info->iclrintradr =
1874 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1875 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1876
a88487c7 1877 tty = info->port.tty;
1da177e4
LT		 1878 if (!tty) /* Something wrong... */
1879 return;
1880
1881#ifdef SERIAL_HANDLE_EARLY_ERRORS
1882 if (info->uses_dma_in)
1883 e100_enable_serial_data_irq(info);
1884#endif
1885
1886 if (info->errorcode == ERRCODE_INSERT_BREAK)
1887 add_char_and_flag(info, '\0', TTY_BREAK);
1888
1889 handle_all_descr_data(info);
1890
1891 /* Read the status register to detect errors */
d7283353 1892 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 1893 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1894 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1895 }
1896
1897 if (rstat & SER_ERROR_MASK) {
1898 /* If we got an error, we must reset it by reading the
1899 * data_in field
1900 */
d7283353 1901 unsigned char data = info->ioport[REG_DATA];
1da177e4
LT		 1902
1903 PROCSTAT(ser_stat[info->line].errors_cnt++);
1904 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1905 ((rstat & SER_ERROR_MASK) << 8) | data);
1906
1907 if (rstat & SER_PAR_ERR_MASK)
1908 add_char_and_flag(info, data, TTY_PARITY);
1909 else if (rstat & SER_OVERRUN_MASK)
1910 add_char_and_flag(info, data, TTY_OVERRUN);
1911 else if (rstat & SER_FRAMING_ERR_MASK)
1912 add_char_and_flag(info, data, TTY_FRAME);
1913 }
1914
1915 START_FLUSH_FAST_TIMER(info, "receive_chars");
1916
1917 /* Restart the receiving DMA */
1918 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1919}
1920
41c28ff1 1921static int start_recv_dma(struct e100_serial *info)
1da177e4
LT		 1922{
1923 struct etrax_dma_descr *descr = info->rec_descr;
1924 struct etrax_recv_buffer *buffer;
1925 int i;
1926
1927 /* Set up the receiving descriptors */
1928 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1929 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
71cc2c21 1930 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1931
1932 descr[i].ctrl = d_int;
1933 descr[i].buf = virt_to_phys(buffer->buffer);
1934 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1935 descr[i].hw_len = 0;
1936 descr[i].status = 0;
1937 descr[i].next = virt_to_phys(&descr[i+1]);
1938 }
1939
1940 /* Link the last descriptor to the first */
1941 descr[i-1].next = virt_to_phys(&descr[0]);
1942
1943 /* Start with the first descriptor in the list */
1944 info->cur_rec_descr = 0;
1945
1946 /* Start the DMA */
1947 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1948 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1949
1950 /* Input DMA should be running now */
1951 return 1;
1952}
1953
1954static void
1955start_receive(struct e100_serial *info)
1956{
1957#ifdef CONFIG_SVINTO_SIM
1958 /* No receive in the simulator. Will probably be when the rest of
1959 * the serial interface works, and this piece will just be removed.
1960 */
1961 return;
1962#endif
1da177e4
LT		 1963 if (info->uses_dma_in) {
1964 /* reset the input dma channel to be sure it works */
1965
1966 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1967 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1968 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1969
1970 start_recv_dma(info);
1971 }
1972}
1973
1974
1da177e4
LT		 1975/* the bits in the MASK2 register are laid out like this:
1976 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1977 where I is the input channel and O is the output channel for the port.
1978 info->irq is the bit number for the DMAO_DESCR so to check the others we
1979 shift info->irq to the left.
1980*/
1981
1982/* dma output channel interrupt handler
1983 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1984 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1985*/
1986
1987static irqreturn_t
7d12e780 1988tr_interrupt(int irq, void *dev_id)
1da177e4
LT		 1989{
1990 struct e100_serial *info;
1991 unsigned long ireg;
1992 int i;
1993 int handled = 0;
1994
1995#ifdef CONFIG_SVINTO_SIM
1996 /* No receive in the simulator. Will probably be when the rest of
1997 * the serial interface works, and this piece will just be removed.
1998 */
1999 {
2000 const char *s = "What? tr_interrupt in simulator??\n";
2001 SIMCOUT(s,strlen(s));
2002 }
2003 return IRQ_HANDLED;
2004#endif
2005
2006 /* find out the line that caused this irq and get it from rs_table */
2007
2008 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2009
2010 for (i = 0; i < NR_PORTS; i++) {
2011 info = rs_table + i;
2012 if (!info->enabled || !info->uses_dma_out)
2013 continue;
2014 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2015 if (ireg & info->irq) {
2016 handled = 1;
2017 /* we can send a new dma bunch. make it so. */
2018 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2019 /* Read jiffies_usec first,
2020 * we want this time to be as late as possible
2021 */
2022 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2023 info->last_tx_active_usec = GET_JIFFIES_USEC();
2024 info->last_tx_active = jiffies;
2025 transmit_chars_dma(info);
2026 }
2027
2028 /* FIXME: here we should really check for a change in the
2029 status lines and if so call status_handle(info) */
2030 }
2031 return IRQ_RETVAL(handled);
2032} /* tr_interrupt */
2033
2034/* dma input channel interrupt handler */
2035
2036static irqreturn_t
7d12e780 2037rec_interrupt(int irq, void *dev_id)
1da177e4
LT		 2038{
2039 struct e100_serial *info;
2040 unsigned long ireg;
2041 int i;
2042 int handled = 0;
2043
2044#ifdef CONFIG_SVINTO_SIM
2045 /* No receive in the simulator. Will probably be when the rest of
2046 * the serial interface works, and this piece will just be removed.
2047 */
2048 {
2049 const char *s = "What? rec_interrupt in simulator??\n";
2050 SIMCOUT(s,strlen(s));
2051 }
2052 return IRQ_HANDLED;
2053#endif
2054
2055 /* find out the line that caused this irq and get it from rs_table */
2056
2057 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2058
2059 for (i = 0; i < NR_PORTS; i++) {
2060 info = rs_table + i;
2061 if (!info->enabled || !info->uses_dma_in)
2062 continue;
2063 /* check for both dma_eop and dma_descr for the input dma channel */
2064 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2065 handled = 1;
2066 /* we have received something */
2067 receive_chars_dma(info);
2068 }
2069
2070 /* FIXME: here we should really check for a change in the
2071 status lines and if so call status_handle(info) */
2072 }
2073 return IRQ_RETVAL(handled);
2074} /* rec_interrupt */
2075
41c28ff1 2076static int force_eop_if_needed(struct e100_serial *info)
1da177e4
LT		 2077{
2078 /* We check data_avail bit to determine if data has
2079 * arrived since last time
2080 */
d7283353 2081 unsigned char rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2082
2083 /* error or datavail? */
2084 if (rstat & SER_ERROR_MASK) {
2085 /* Some error has occurred. If there has been valid data, an
2086 * EOP interrupt will be made automatically. If no data, the
2087 * normal ser_interrupt should be enabled and handle it.
2088 * So do nothing!
2089 */
2090 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2091 rstat | (info->line << 8));
2092 return 0;
2093 }
2094
2095 if (rstat & SER_DATA_AVAIL_MASK) {
2096 /* Ok data, no error, count it */
2097 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2098 rstat | (info->line << 8)));
2099 /* Read data to clear status flags */
d7283353 2100 (void)info->ioport[REG_DATA];
1da177e4
LT		 2101
2102 info->forced_eop = 0;
2103 START_FLUSH_FAST_TIMER(info, "magic");
2104 return 0;
2105 }
2106
2107 /* hit the timeout, force an EOP for the input
2108 * dma channel if we haven't already
2109 */
2110 if (!info->forced_eop) {
2111 info->forced_eop = 1;
2112 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2113 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2114 FORCE_EOP(info);
2115 }
2116
2117 return 1;
2118}
2119
41c28ff1 2120static void flush_to_flip_buffer(struct e100_serial *info)
1da177e4
LT		 2121{
2122 struct tty_struct *tty;
2123 struct etrax_recv_buffer *buffer;
1da177e4 2124 unsigned long flags;
1da177e4 2125
77accbf5 2126 local_irq_save(flags);
a88487c7 2127 tty = info->port.tty;
1da177e4 2128
77accbf5
JN		 2129 if (!tty) {
2130 local_irq_restore(flags);
1da177e4
LT		 2131 return;
2132 }
2133
2090ab05 2134 while ((buffer = info->first_recv_buffer) != NULL) {
1da177e4
LT		 2135 unsigned int count = buffer->length;
2136
77accbf5 2137 tty_insert_flip_string(tty, buffer->buffer, count);
1da177e4 2138 info->recv_cnt -= count;
1da177e4
LT		 2139
2140 if (count == buffer->length) {
2141 info->first_recv_buffer = buffer->next;
2142 kfree(buffer);
2143 } else {
2144 buffer->length -= count;
2145 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2146 buffer->error = TTY_NORMAL;
2147 }
2148 }
2149
2150 if (!info->first_recv_buffer)
2151 info->last_recv_buffer = NULL;
2152
77accbf5 2153 local_irq_restore(flags);
1da177e4 2154
77accbf5 2155 /* This includes a check for low-latency */
1da177e4
LT		 2156 tty_flip_buffer_push(tty);
2157}
2158
41c28ff1 2159static void check_flush_timeout(struct e100_serial *info)
1da177e4
LT		 2160{
2161 /* Flip what we've got (if we can) */
2162 flush_to_flip_buffer(info);
2163
2164 /* We might need to flip later, but not to fast
2165 * since the system is busy processing input... */
2166 if (info->first_recv_buffer)
2167 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2168
2169 /* Force eop last, since data might have come while we're processing
2170 * and if we started the slow timer above, we won't start a fast
2171 * below.
2172 */
2173 force_eop_if_needed(info);
2174}
2175
2176#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2177static void flush_timeout_function(unsigned long data)
2178{
2179 struct e100_serial *info = (struct e100_serial *)data;
2180
2181 fast_timers[info->line].function = NULL;
2182 serial_fast_timer_expired++;
2183 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2184 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2185 check_flush_timeout(info);
2186}
2187
2188#else
2189
2190/* dma fifo/buffer timeout handler
2191 forces an end-of-packet for the dma input channel if no chars
2192 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2193*/
2194
2195static struct timer_list flush_timer;
2196
2197static void
2198timed_flush_handler(unsigned long ptr)
2199{
2200 struct e100_serial *info;
2201 int i;
2202
2203#ifdef CONFIG_SVINTO_SIM
2204 return;
2205#endif
2206
2207 for (i = 0; i < NR_PORTS; i++) {
2208 info = rs_table + i;
2209 if (info->uses_dma_in)
2210 check_flush_timeout(info);
2211 }
2212
2213 /* restart flush timer */
2214 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2215}
2216#endif
2217
2218#ifdef SERIAL_HANDLE_EARLY_ERRORS
2219
2220/* If there is an error (ie break) when the DMA is running and
2221 * there are no bytes in the fifo the DMA is stopped and we get no
2222 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2223 * transfer, and if it is without error we can turn the serial
2224 * interrupts off.
2225 */
2226
2227/*
2228BREAK handling on ETRAX 100:
2229ETRAX will generate interrupt although there is no stop bit between the
2230characters.
2231
2232Depending on how long the break sequence is, the end of the breaksequence
2233will look differently:
2234| indicates start/end of a character.
2235
2236B= Break character (0x00) with framing error.
2237E= Error byte with parity error received after B characters.
2238F= "Faked" valid byte received immediately after B characters.
2239V= Valid byte
2240
22411.
2242 B BL ___________________________ V
2243.._|__________|__________| |valid data |
2244
2245Multiple frame errors with data == 0x00 (B),
2246the timing matches up "perfectly" so no extra ending char is detected.
2247The RXD pin is 1 in the last interrupt, in that case
2248we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2249know if another byte will come and this really is case 2. below
2250(e.g F=0xFF or 0xFE)
2251If RXD pin is 0 we can expect another character (see 2. below).
2252
2253
22542.
2255
2256 B B E or F__________________..__ V
2257.._|__________|__________|______ | |valid data
2258 "valid" or
2259 parity error
2260
2261Multiple frame errors with data == 0x00 (B),
2262but the part of the break trigs is interpreted as a start bit (and possibly
2263some 0 bits followed by a number of 1 bits and a stop bit).
2264Depending on parity settings etc. this last character can be either
2265a fake "valid" char (F) or have a parity error (E).
2266
2267If the character is valid it will be put in the buffer,
2268we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2269will set the flags so the tty will handle it,
2270if it's an error byte it will not be put in the buffer
2271and we set info->errorcode = ERRCODE_INSERT_BREAK.
2272
2273To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2274of the last faulty char (B) and compares it with the current time:
2275If the time elapsed time is less then 2*char_time_usec we will assume
2276it's a faked F char and not a Valid char and set
2277info->errorcode = ERRCODE_SET_BREAK.
2278
2279Flaws in the above solution:
2280~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2281We use the timer to distinguish a F character from a V character,
2282if a V character is to close after the break we might make the wrong decision.
2283
2284TODO: The break will be delayed until an F or V character is received.
2285
2286*/
2287
41c28ff1 2288static
1da177e4
LT		 2289struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2290{
2291 unsigned long data_read;
a88487c7 2292 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 2293
2294 if (!tty) {
2295 printk("!NO TTY!\n");
2296 return info;
2297 }
77accbf5 2298
1da177e4 2299 /* Read data and status at the same time */
d7283353 2300 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2301more_data:
2302 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2303 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2304 }
2305 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2306
2307 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2308 IO_MASK(R_SERIAL0_READ, par_err) |
2309 IO_MASK(R_SERIAL0_READ, overrun) )) {
2310 /* An error */
2311 info->last_rx_active_usec = GET_JIFFIES_USEC();
2312 info->last_rx_active = jiffies;
2313 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2314 DLOG_INT_TRIG(
2315 if (!log_int_trig1_pos) {
2316 log_int_trig1_pos = log_int_pos;
2317 log_int(rdpc(), 0, 0);
2318 }
2319 );
2320
2321
2322 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2323 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2324 /* Most likely a break, but we get interrupts over and
2325 * over again.
2326 */
2327
2328 if (!info->break_detected_cnt) {
2329 DEBUG_LOG(info->line, "#BRK start\n", 0);
2330 }
2331 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2332 /* The RX pin is high now, so the break
2333 * must be over, but....
2334 * we can't really know if we will get another
2335 * last byte ending the break or not.
2336 * And we don't know if the byte (if any) will
2337 * have an error or look valid.
2338 */
2339 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2340 info->errorcode = ERRCODE_INSERT_BREAK;
2341 }
2342 info->break_detected_cnt++;
2343 } else {
2344 /* The error does not look like a break, but could be
2345 * the end of one
2346 */
2347 if (info->break_detected_cnt) {
2348 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2349 info->errorcode = ERRCODE_INSERT_BREAK;
2350 } else {
77accbf5
JN		 2351 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2352 data_in, data_read);
2353 char flag = TTY_NORMAL;
1da177e4 2354 if (info->errorcode == ERRCODE_INSERT_BREAK) {
a88487c7 2355 struct tty_struct *tty = info->port.tty;
77accbf5 2356 tty_insert_flip_char(tty, 0, flag);
1da177e4
LT		 2357 info->icount.rx++;
2358 }
1da177e4
LT		 2359
2360 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2361 info->icount.parity++;
77accbf5 2362 flag = TTY_PARITY;
1da177e4
LT		 2363 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2364 info->icount.overrun++;
77accbf5 2365 flag = TTY_OVERRUN;
1da177e4
LT		 2366 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2367 info->icount.frame++;
77accbf5 2368 flag = TTY_FRAME;
1da177e4 2369 }
77accbf5 2370 tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 2371 info->errorcode = 0;
2372 }
2373 info->break_detected_cnt = 0;
2374 }
2375 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2376 /* No error */
2377 DLOG_INT_TRIG(
2378 if (!log_int_trig1_pos) {
2379 if (log_int_pos >= log_int_size) {
2380 log_int_pos = 0;
2381 }
2382 log_int_trig0_pos = log_int_pos;
2383 log_int(rdpc(), 0, 0);
2384 }
2385 );
77accbf5
JN		 2386 tty_insert_flip_char(tty,
2387 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2388 TTY_NORMAL);
1da177e4
LT		 2389 } else {
2390 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2391 }
2392
2393
1da177e4 2394 info->icount.rx++;
d7283353 2395 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2396 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2397 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2398 goto more_data;
2399 }
2400
a88487c7 2401 tty_flip_buffer_push(info->port.tty);
1da177e4
LT		 2402 return info;
2403}
2404
41c28ff1 2405static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
1da177e4
LT		 2406{
2407 unsigned char rstat;
2408
2409#ifdef SERIAL_DEBUG_INTR
2410 printk("Interrupt from serport %d\n", i);
2411#endif
2412/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2413 if (!info->uses_dma_in) {
2414 return handle_ser_rx_interrupt_no_dma(info);
2415 }
2416 /* DMA is used */
d7283353 2417 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2418 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2419 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2420 }
2421
2422 if (rstat & SER_ERROR_MASK) {
2423 unsigned char data;
2424
2425 info->last_rx_active_usec = GET_JIFFIES_USEC();
2426 info->last_rx_active = jiffies;
2427 /* If we got an error, we must reset it by reading the
2428 * data_in field
2429 */
d7283353 2430 data = info->ioport[REG_DATA];
1da177e4
LT		 2431 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2432 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2433 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2434 /* Most likely a break, but we get interrupts over and
2435 * over again.
2436 */
2437
2438 if (!info->break_detected_cnt) {
2439 DEBUG_LOG(info->line, "#BRK start\n", 0);
2440 }
2441 if (rstat & SER_RXD_MASK) {
2442 /* The RX pin is high now, so the break
2443 * must be over, but....
2444 * we can't really know if we will get another
2445 * last byte ending the break or not.
2446 * And we don't know if the byte (if any) will
2447 * have an error or look valid.
2448 */
2449 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2450 info->errorcode = ERRCODE_INSERT_BREAK;
2451 }
2452 info->break_detected_cnt++;
2453 } else {
2454 /* The error does not look like a break, but could be
2455 * the end of one
2456 */
2457 if (info->break_detected_cnt) {
2458 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2459 info->errorcode = ERRCODE_INSERT_BREAK;
2460 } else {
2461 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2462 info->icount.brk++;
2463 add_char_and_flag(info, '\0', TTY_BREAK);
2464 }
2465
2466 if (rstat & SER_PAR_ERR_MASK) {
2467 info->icount.parity++;
2468 add_char_and_flag(info, data, TTY_PARITY);
2469 } else if (rstat & SER_OVERRUN_MASK) {
2470 info->icount.overrun++;
2471 add_char_and_flag(info, data, TTY_OVERRUN);
2472 } else if (rstat & SER_FRAMING_ERR_MASK) {
2473 info->icount.frame++;
2474 add_char_and_flag(info, data, TTY_FRAME);
2475 }
2476
2477 info->errorcode = 0;
2478 }
2479 info->break_detected_cnt = 0;
2480 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2481 ((rstat & SER_ERROR_MASK) << 8) | data);
2482 }
2483 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2484 } else { /* It was a valid byte, now let the DMA do the rest */
2485 unsigned long curr_time_u = GET_JIFFIES_USEC();
2486 unsigned long curr_time = jiffies;
2487
2488 if (info->break_detected_cnt) {
2489 /* Detect if this character is a new valid char or the
2490 * last char in a break sequence: If LSBits are 0 and
2491 * MSBits are high AND the time is close to the
2492 * previous interrupt we should discard it.
2493 */
2494 long elapsed_usec =
2495 (curr_time - info->last_rx_active) * (1000000/HZ) +
2496 curr_time_u - info->last_rx_active_usec;
2497 if (elapsed_usec < 2*info->char_time_usec) {
2498 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2499 /* Report as BREAK (error) and let
2500 * receive_chars_dma() handle it
2501 */
2502 info->errorcode = ERRCODE_SET_BREAK;
2503 } else {
2504 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2505 }
2506 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2507 }
2508
2509#ifdef SERIAL_DEBUG_INTR
2510 printk("** OK, disabling ser_interrupts\n");
2511#endif
2512 e100_disable_serial_data_irq(info);
2513 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2514 info->break_detected_cnt = 0;
2515
2516 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2517 }
2518 /* Restarting the DMA never hurts */
2519 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2520 START_FLUSH_FAST_TIMER(info, "ser_int");
2521 return info;
2522} /* handle_ser_rx_interrupt */
2523
41c28ff1 2524static void handle_ser_tx_interrupt(struct e100_serial *info)
1da177e4
LT		 2525{
2526 unsigned long flags;
2527
2528 if (info->x_char) {
2529 unsigned char rstat;
2530 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
77accbf5 2531 local_irq_save(flags);
d7283353 2532 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2533 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2534
d7283353 2535 info->ioport[REG_TR_DATA] = info->x_char;
1da177e4
LT		 2536 info->icount.tx++;
2537 info->x_char = 0;
2538 /* We must enable since it is disabled in ser_interrupt */
2539 e100_enable_serial_tx_ready_irq(info);
77accbf5 2540 local_irq_restore(flags);
1da177e4
LT		 2541 return;
2542 }
2543 if (info->uses_dma_out) {
2544 unsigned char rstat;
2545 int i;
2546 /* We only use normal tx interrupt when sending x_char */
2547 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
77accbf5 2548 local_irq_save(flags);
d7283353 2549 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2550 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2551 e100_disable_serial_tx_ready_irq(info);
a88487c7
TI		 2552 if (info->port.tty->stopped)
2553 rs_stop(info->port.tty);
1da177e4
LT		 2554 /* Enable the DMA channel and tell it to continue */
2555 e100_enable_txdma_channel(info);
2556 /* Wait 12 cycles before doing the DMA command */
2557 for(i = 6; i > 0; i--)
2558 nop();
2559
2560 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
77accbf5 2561 local_irq_restore(flags);
1da177e4
LT		 2562 return;
2563 }
2564 /* Normal char-by-char interrupt */
2565 if (info->xmit.head == info->xmit.tail
a88487c7
TI		 2566 || info->port.tty->stopped
2567 || info->port.tty->hw_stopped) {
2568 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2569 info->port.tty->stopped));
1da177e4
LT		 2570 e100_disable_serial_tx_ready_irq(info);
2571 info->tr_running = 0;
2572 return;
2573 }
2574 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2575 /* Send a byte, rs485 timing is critical so turn of ints */
77accbf5 2576 local_irq_save(flags);
d7283353 2577 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
1da177e4
LT		 2578 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2579 info->icount.tx++;
2580 if (info->xmit.head == info->xmit.tail) {
2581#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 2582 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 2583 /* Set a short timer to toggle RTS */
2584 start_one_shot_timer(&fast_timers_rs485[info->line],
2585 rs485_toggle_rts_timer_function,
2586 (unsigned long)info,
2587 info->char_time_usec*2,
2588 "RS-485");
2589 }
2590#endif /* RS485 */
2591 info->last_tx_active_usec = GET_JIFFIES_USEC();
2592 info->last_tx_active = jiffies;
2593 e100_disable_serial_tx_ready_irq(info);
2594 info->tr_running = 0;
2595 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2596 } else {
2597 /* We must enable since it is disabled in ser_interrupt */
2598 e100_enable_serial_tx_ready_irq(info);
2599 }
77accbf5 2600 local_irq_restore(flags);
1da177e4
LT		 2601
2602 if (CIRC_CNT(info->xmit.head,
2603 info->xmit.tail,
2604 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2605 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2606
2607} /* handle_ser_tx_interrupt */
2608
2609/* result of time measurements:
2610 * RX duration 54-60 us when doing something, otherwise 6-9 us
2611 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2612 */
2613static irqreturn_t
7d12e780 2614ser_interrupt(int irq, void *dev_id)
1da177e4
LT		 2615{
2616 static volatile int tx_started = 0;
2617 struct e100_serial *info;
2618 int i;
2619 unsigned long flags;
2620 unsigned long irq_mask1_rd;
2621 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2622 int handled = 0;
2623 static volatile unsigned long reentered_ready_mask = 0;
2624
77accbf5 2625 local_irq_save(flags);
1da177e4
LT		 2626 irq_mask1_rd = *R_IRQ_MASK1_RD;
2627 /* First handle all rx interrupts with ints disabled */
2628 info = rs_table;
2629 irq_mask1_rd &= e100_ser_int_mask;
2630 for (i = 0; i < NR_PORTS; i++) {
2631 /* Which line caused the data irq? */
2632 if (irq_mask1_rd & data_mask) {
2633 handled = 1;
2634 handle_ser_rx_interrupt(info);
2635 }
2636 info += 1;
2637 data_mask <<= 2;
2638 }
2639 /* Handle tx interrupts with interrupts enabled so we
2640 * can take care of new data interrupts while transmitting
2641 * We protect the tx part with the tx_started flag.
2642 * We disable the tr_ready interrupts we are about to handle and
2643 * unblock the serial interrupt so new serial interrupts may come.
2644 *
2645 * If we get a new interrupt:
2646 * - it migth be due to synchronous serial ports.
2647 * - serial irq will be blocked by general irq handler.
2648 * - async data will be handled above (sync will be ignored).
2649 * - tx_started flag will prevent us from trying to send again and
2650 * we will exit fast - no need to unblock serial irq.
2651 * - Next (sync) serial interrupt handler will be runned with
2652 * disabled interrupt due to restore_flags() at end of function,
2653 * so sync handler will not be preempted or reentered.
2654 */
2655 if (!tx_started) {
2656 unsigned long ready_mask;
2657 unsigned long
2658 tx_started = 1;
2659 /* Only the tr_ready interrupts left */
2660 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2661 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2662 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2663 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2664 while (irq_mask1_rd) {
2665 /* Disable those we are about to handle */
2666 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2667 /* Unblock the serial interrupt */
2668 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2669
77accbf5 2670 local_irq_enable();
1da177e4
LT		 2671 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2672 info = rs_table;
2673 for (i = 0; i < NR_PORTS; i++) {
2674 /* Which line caused the ready irq? */
2675 if (irq_mask1_rd & ready_mask) {
2676 handled = 1;
2677 handle_ser_tx_interrupt(info);
2678 }
2679 info += 1;
2680 ready_mask <<= 2;
2681 }
2682 /* handle_ser_tx_interrupt enables tr_ready interrupts */
77accbf5 2683 local_irq_disable();
1da177e4
LT		 2684 /* Handle reentered TX interrupt */
2685 irq_mask1_rd = reentered_ready_mask;
2686 }
77accbf5 2687 local_irq_disable();
1da177e4
LT		 2688 tx_started = 0;
2689 } else {
2690 unsigned long ready_mask;
2691 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2692 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2693 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2694 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2695 if (ready_mask) {
2696 reentered_ready_mask |= ready_mask;
2697 /* Disable those we are about to handle */
2698 *R_IRQ_MASK1_CLR = ready_mask;
2699 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2700 }
2701 }
2702
77accbf5 2703 local_irq_restore(flags);
1da177e4
LT		 2704 return IRQ_RETVAL(handled);
2705} /* ser_interrupt */
2706#endif
2707
2708/*
2709 * -------------------------------------------------------------------
2710 * Here ends the serial interrupt routines.
2711 * -------------------------------------------------------------------
2712 */
2713
2714/*
2715 * This routine is used to handle the "bottom half" processing for the
2716 * serial driver, known also the "software interrupt" processing.
2717 * This processing is done at the kernel interrupt level, after the
2718 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2719 * is where time-consuming activities which can not be done in the
2720 * interrupt driver proper are done; the interrupt driver schedules
2721 * them using rs_sched_event(), and they get done here.
2722 */
2723static void
77accbf5 2724do_softint(struct work_struct *work)
1da177e4 2725{
77accbf5 2726 struct e100_serial *info;
1da177e4
LT		 2727 struct tty_struct *tty;
2728
77accbf5
JN		 2729 info = container_of(work, struct e100_serial, work);
2730
a88487c7 2731 tty = info->port.tty;
1da177e4
LT		 2732 if (!tty)
2733 return;
2734
b963a844
JS		 2735 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2736 tty_wakeup(tty);
1da177e4
LT		 2737}
2738
2739static int
2740startup(struct e100_serial * info)
2741{
2742 unsigned long flags;
2743 unsigned long xmit_page;
2744 int i;
2745
2746 xmit_page = get_zeroed_page(GFP_KERNEL);
2747 if (!xmit_page)
2748 return -ENOMEM;
2749
77accbf5 2750 local_irq_save(flags);
1da177e4
LT		 2751
2752 /* if it was already initialized, skip this */
2753
2754 if (info->flags & ASYNC_INITIALIZED) {
77accbf5 2755 local_irq_restore(flags);
1da177e4
LT		 2756 free_page(xmit_page);
2757 return 0;
2758 }
2759
2760 if (info->xmit.buf)
2761 free_page(xmit_page);
2762 else
2763 info->xmit.buf = (unsigned char *) xmit_page;
2764
2765#ifdef SERIAL_DEBUG_OPEN
2766 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2767#endif
2768
2769#ifdef CONFIG_SVINTO_SIM
2770 /* Bits and pieces collected from below. Better to have them
2771 in one ifdef:ed clause than to mix in a lot of ifdefs,
2772 right? */
a88487c7
TI		 2773 if (info->port.tty)
2774 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2775
2776 info->xmit.head = info->xmit.tail = 0;
2777 info->first_recv_buffer = info->last_recv_buffer = NULL;
2778 info->recv_cnt = info->max_recv_cnt = 0;
2779
2780 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2781 info->rec_descr[i].buf = NULL;
2782
2783 /* No real action in the simulator, but may set info important
2784 to ioctl. */
2785 change_speed(info);
2786#else
2787
2788 /*
2789 * Clear the FIFO buffers and disable them
2790 * (they will be reenabled in change_speed())
2791 */
2792
2793 /*
2794 * Reset the DMA channels and make sure their interrupts are cleared
2795 */
2796
2797 if (info->dma_in_enabled) {
2798 info->uses_dma_in = 1;
2799 e100_enable_rxdma_channel(info);
2800
2801 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2802
2803 /* Wait until reset cycle is complete */
2804 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2805 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2806
2807 /* Make sure the irqs are cleared */
2808 *info->iclrintradr =
2809 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2810 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2811 } else {
2812 e100_disable_rxdma_channel(info);
2813 }
2814
2815 if (info->dma_out_enabled) {
2816 info->uses_dma_out = 1;
2817 e100_enable_txdma_channel(info);
2818 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2819
2820 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2821 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2822
2823 /* Make sure the irqs are cleared */
2824 *info->oclrintradr =
2825 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2826 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2827 } else {
2828 e100_disable_txdma_channel(info);
2829 }
2830
a88487c7
TI		 2831 if (info->port.tty)
2832 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2833
2834 info->xmit.head = info->xmit.tail = 0;
2835 info->first_recv_buffer = info->last_recv_buffer = NULL;
2836 info->recv_cnt = info->max_recv_cnt = 0;
2837
2838 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2839 info->rec_descr[i].buf = 0;
2840
2841 /*
2842 * and set the speed and other flags of the serial port
2843 * this will start the rx/tx as well
2844 */
2845#ifdef SERIAL_HANDLE_EARLY_ERRORS
2846 e100_enable_serial_data_irq(info);
2847#endif
2848 change_speed(info);
2849
2850 /* dummy read to reset any serial errors */
2851
d7283353 2852 (void)info->ioport[REG_DATA];
1da177e4
LT		 2853
2854 /* enable the interrupts */
2855 if (info->uses_dma_out)
2856 e100_enable_txdma_irq(info);
2857
2858 e100_enable_rx_irq(info);
2859
2860 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2861
2862 /* setup the dma input descriptor and start dma */
2863
2864 start_receive(info);
2865
2866 /* for safety, make sure the descriptors last result is 0 bytes written */
2867
2868 info->tr_descr.sw_len = 0;
2869 info->tr_descr.hw_len = 0;
2870 info->tr_descr.status = 0;
2871
2872 /* enable RTS/DTR last */
2873
2874 e100_rts(info, 1);
2875 e100_dtr(info, 1);
2876
2877#endif /* CONFIG_SVINTO_SIM */
2878
2879 info->flags |= ASYNC_INITIALIZED;
2880
77accbf5 2881 local_irq_restore(flags);
1da177e4
LT		 2882 return 0;
2883}
2884
2885/*
2886 * This routine will shutdown a serial port; interrupts are disabled, and
2887 * DTR is dropped if the hangup on close termio flag is on.
2888 */
2889static void
2890shutdown(struct e100_serial * info)
2891{
2892 unsigned long flags;
2893 struct etrax_dma_descr *descr = info->rec_descr;
2894 struct etrax_recv_buffer *buffer;
2895 int i;
2896
2897#ifndef CONFIG_SVINTO_SIM
2898 /* shut down the transmitter and receiver */
2899 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2900 e100_disable_rx(info);
d7283353 2901 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
1da177e4
LT		 2902
2903 /* disable interrupts, reset dma channels */
2904 if (info->uses_dma_in) {
2905 e100_disable_rxdma_irq(info);
2906 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2907 info->uses_dma_in = 0;
2908 } else {
2909 e100_disable_serial_data_irq(info);
2910 }
2911
2912 if (info->uses_dma_out) {
2913 e100_disable_txdma_irq(info);
2914 info->tr_running = 0;
2915 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2916 info->uses_dma_out = 0;
2917 } else {
2918 e100_disable_serial_tx_ready_irq(info);
2919 info->tr_running = 0;
2920 }
2921
2922#endif /* CONFIG_SVINTO_SIM */
2923
2924 if (!(info->flags & ASYNC_INITIALIZED))
2925 return;
2926
2927#ifdef SERIAL_DEBUG_OPEN
2928 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2929 info->irq);
2930#endif
2931
77accbf5 2932 local_irq_save(flags);
1da177e4
LT		 2933
2934 if (info->xmit.buf) {
2935 free_page((unsigned long)info->xmit.buf);
2936 info->xmit.buf = NULL;
2937 }
2938
2939 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2940 if (descr[i].buf) {
2941 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2942 kfree(buffer);
2943 descr[i].buf = 0;
2944 }
2945
a88487c7 2946 if (!info->port.tty || (info->port.tty->termios->c_cflag & HUPCL)) {
1da177e4
LT		 2947 /* hang up DTR and RTS if HUPCL is enabled */
2948 e100_dtr(info, 0);
2949 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2950 }
2951
a88487c7
TI		 2952 if (info->port.tty)
2953 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2954
2955 info->flags &= ~ASYNC_INITIALIZED;
77accbf5 2956 local_irq_restore(flags);
1da177e4
LT		 2957}
2958
2959
2960/* change baud rate and other assorted parameters */
2961
2962static void
2963change_speed(struct e100_serial *info)
2964{
2965 unsigned int cflag;
2966 unsigned long xoff;
2967 unsigned long flags;
2968 /* first some safety checks */
2969
a88487c7 2970 if (!info->port.tty || !info->port.tty->termios)
1da177e4 2971 return;
d7283353 2972 if (!info->ioport)
1da177e4
LT		 2973 return;
2974
a88487c7 2975 cflag = info->port.tty->termios->c_cflag;
1da177e4
LT		 2976
2977 /* possibly, the tx/rx should be disabled first to do this safely */
2978
2979 /* change baud-rate and write it to the hardware */
2980 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2981 /* Special baudrate */
2982 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2983 unsigned long alt_source =
2984 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2985 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2986 /* R_ALT_SER_BAUDRATE selects the source */
2987 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2988 (unsigned long)info->baud_base, info->custom_divisor));
2989 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2990 /* 0, 2-65535 (0=65536) */
2991 u16 divisor = info->custom_divisor;
2992 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2993 /* baudrate is 3.125MHz/custom_divisor */
2994 alt_source =
2995 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2996 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2997 alt_source = 0x11;
2998 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2999 *R_SERIAL_PRESCALE = divisor;
3000 info->baud = SERIAL_PRESCALE_BASE/divisor;
3001 }
3002#ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
3003 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
3004 info->custom_divisor == 1) ||
3005 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
3006 info->custom_divisor == 8)) {
3007 /* ext_clk selected */
3008 alt_source =
3009 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
3010 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
3011 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
3012 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
3013 }
1da177e4
LT		 3014#endif
3015 else
3016 {
3017 /* Bad baudbase, we don't support using timer0
3018 * for baudrate.
3019 */
3020 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
3021 (unsigned long)info->baud_base, info->custom_divisor);
3022 }
3023 r_alt_ser_baudrate_shadow &= ~mask;
3024 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3025 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3026 } else {
3027 /* Normal baudrate */
3028 /* Make sure we use normal baudrate */
3029 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3030 unsigned long alt_source =
3031 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3032 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3033 r_alt_ser_baudrate_shadow &= ~mask;
3034 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3035#ifndef CONFIG_SVINTO_SIM
3036 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3037#endif /* CONFIG_SVINTO_SIM */
3038
3039 info->baud = cflag_to_baud(cflag);
3040#ifndef CONFIG_SVINTO_SIM
d7283353 3041 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
1da177e4
LT		 3042#endif /* CONFIG_SVINTO_SIM */
3043 }
3044
3045#ifndef CONFIG_SVINTO_SIM
3046 /* start with default settings and then fill in changes */
77accbf5 3047 local_irq_save(flags);
1da177e4
LT		 3048 /* 8 bit, no/even parity */
3049 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3050 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3051 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3052
3053 /* 8 bit, no/even parity, 1 stop bit, no cts */
3054 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3055 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3056 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3057 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3058 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3059
3060 if ((cflag & CSIZE) == CS7) {
3061 /* set 7 bit mode */
3062 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3063 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3064 }
3065
3066 if (cflag & CSTOPB) {
3067 /* set 2 stop bit mode */
3068 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3069 }
3070
3071 if (cflag & PARENB) {
3072 /* enable parity */
3073 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3074 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3075 }
3076
3077 if (cflag & CMSPAR) {
3078 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3079 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3080 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3081 }
3082 if (cflag & PARODD) {
3083 /* set odd parity (or Mark if CMSPAR) */
3084 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3085 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3086 }
3087
3088 if (cflag & CRTSCTS) {
3089 /* enable automatic CTS handling */
3090 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3091 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3092 }
3093
3094 /* make sure the tx and rx are enabled */
3095
3096 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3097 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3098
3099 /* actually write the control regs to the hardware */
3100
d7283353
AC		 3101 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3102 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
a88487c7 3103 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
1da177e4 3104 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
a88487c7
TI		 3105 if (info->port.tty->termios->c_iflag & IXON ) {
3106 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3107 STOP_CHAR(info->port.tty)));
1da177e4
LT		 3108 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3109 }
3110
d7283353 3111 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 3112 local_irq_restore(flags);
1da177e4
LT		 3113#endif /* !CONFIG_SVINTO_SIM */
3114
3115 update_char_time(info);
3116
3117} /* change_speed */
3118
3119/* start transmitting chars NOW */
3120
3121static void
3122rs_flush_chars(struct tty_struct *tty)
3123{
3124 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3125 unsigned long flags;
3126
3127 if (info->tr_running ||
3128 info->xmit.head == info->xmit.tail ||
3129 tty->stopped ||
3130 tty->hw_stopped ||
3131 !info->xmit.buf)
3132 return;
3133
3134#ifdef SERIAL_DEBUG_FLOW
3135 printk("rs_flush_chars\n");
3136#endif
3137
3138 /* this protection might not exactly be necessary here */
3139
77accbf5 3140 local_irq_save(flags);
1da177e4 3141 start_transmit(info);
77accbf5 3142 local_irq_restore(flags);
1da177e4
LT		 3143}
3144
77accbf5 3145static int rs_raw_write(struct tty_struct *tty,
41c28ff1 3146 const unsigned char *buf, int count)
1da177e4
LT		 3147{
3148 int c, ret = 0;
3149 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3150 unsigned long flags;
3151
3152 /* first some sanity checks */
3153
3154 if (!tty || !info->xmit.buf || !tmp_buf)
3155 return 0;
3156
3157#ifdef SERIAL_DEBUG_DATA
3158 if (info->line == SERIAL_DEBUG_LINE)
3159 printk("rs_raw_write (%d), status %d\n",
d7283353 3160 count, info->ioport[REG_STATUS]);
1da177e4
LT		 3161#endif
3162
3163#ifdef CONFIG_SVINTO_SIM
3164 /* Really simple. The output is here and now. */
3165 SIMCOUT(buf, count);
3166 return count;
3167#endif
77accbf5 3168 local_save_flags(flags);
1da177e4
LT		 3169 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3170 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3171
3172
77accbf5
JN		 3173 /* The local_irq_disable/restore_flags pairs below are needed
3174 * because the DMA interrupt handler moves the info->xmit values.
3175 * the memcpy needs to be in the critical region unfortunately,
3176 * because we need to read xmit values, memcpy, write xmit values
3177 * in one atomic operation... this could perhaps be avoided by
3178 * more clever design.
1da177e4 3179 */
77accbf5 3180 local_irq_disable();
1da177e4
LT		 3181 while (count) {
3182 c = CIRC_SPACE_TO_END(info->xmit.head,
3183 info->xmit.tail,
3184 SERIAL_XMIT_SIZE);
3185
3186 if (count < c)
3187 c = count;
3188 if (c <= 0)
3189 break;
3190
3191 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3192 info->xmit.head = (info->xmit.head + c) &
3193 (SERIAL_XMIT_SIZE-1);
3194 buf += c;
3195 count -= c;
3196 ret += c;
3197 }
77accbf5 3198 local_irq_restore(flags);
1da177e4
LT		 3199
3200 /* enable transmitter if not running, unless the tty is stopped
3201 * this does not need IRQ protection since if tr_running == 0
3202 * the IRQ's are not running anyway for this port.
3203 */
3204 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3205
3206 if (info->xmit.head != info->xmit.tail &&
3207 !tty->stopped &&
3208 !tty->hw_stopped &&
3209 !info->tr_running) {
3210 start_transmit(info);
3211 }
3212
3213 return ret;
3214} /* raw_raw_write() */
3215
3216static int
77accbf5 3217rs_write(struct tty_struct *tty,
1da177e4
LT		 3218 const unsigned char *buf, int count)
3219{
3220#if defined(CONFIG_ETRAX_RS485)
3221 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3222
6fd1af4c 3223 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3224 {
3225 /* If we are in RS-485 mode, we need to toggle RTS and disable
3226 * the receiver before initiating a DMA transfer
3227 */
3228#ifdef CONFIG_ETRAX_FAST_TIMER
3229 /* Abort any started timer */
3230 fast_timers_rs485[info->line].function = NULL;
3231 del_fast_timer(&fast_timers_rs485[info->line]);
3232#endif
6fd1af4c 3233 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
1da177e4
LT		 3234#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3235 e100_disable_rx(info);
3236 e100_enable_rx_irq(info);
3237#endif
93f3350c
CS		 3238 if (info->rs485.delay_rts_before_send > 0)
3239 msleep(info->rs485.delay_rts_before_send);
1da177e4
LT		 3240 }
3241#endif /* CONFIG_ETRAX_RS485 */
3242
77accbf5 3243 count = rs_raw_write(tty, buf, count);
1da177e4
LT		 3244
3245#if defined(CONFIG_ETRAX_RS485)
6fd1af4c 3246 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3247 {
3248 unsigned int val;
3249 /* If we are in RS-485 mode the following has to be done:
3250 * wait until DMA is ready
3251 * wait on transmit shift register
3252 * toggle RTS
3253 * enable the receiver
3254 */
3255
3256 /* Sleep until all sent */
3257 tty_wait_until_sent(tty, 0);
3258#ifdef CONFIG_ETRAX_FAST_TIMER
3259 /* Now sleep a little more so that shift register is empty */
3260 schedule_usleep(info->char_time_usec * 2);
3261#endif
3262 /* wait on transmit shift register */
3263 do{
3264 get_lsr_info(info, &val);
3265 }while (!(val & TIOCSER_TEMT));
3266
6fd1af4c 3267 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 3268
3269#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3270 e100_enable_rx(info);
3271 e100_enable_rxdma_irq(info);
3272#endif
3273 }
3274#endif /* CONFIG_ETRAX_RS485 */
3275
3276 return count;
3277} /* rs_write */
3278
3279
3280/* how much space is available in the xmit buffer? */
3281
3282static int
3283rs_write_room(struct tty_struct *tty)
3284{
3285 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3286
3287 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3288}
3289
3290/* How many chars are in the xmit buffer?
3291 * This does not include any chars in the transmitter FIFO.
3292 * Use wait_until_sent for waiting for FIFO drain.
3293 */
3294
3295static int
3296rs_chars_in_buffer(struct tty_struct *tty)
3297{
3298 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3299
3300 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3301}
3302
3303/* discard everything in the xmit buffer */
3304
3305static void
3306rs_flush_buffer(struct tty_struct *tty)
3307{
3308 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3309 unsigned long flags;
3310
77accbf5 3311 local_irq_save(flags);
1da177e4 3312 info->xmit.head = info->xmit.tail = 0;
77accbf5 3313 local_irq_restore(flags);
1da177e4 3314
b963a844 3315 tty_wakeup(tty);
1da177e4
LT		 3316}
3317
3318/*
3319 * This function is used to send a high-priority XON/XOFF character to
3320 * the device
3321 *
3322 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3323 * but we do it in handle_ser_tx_interrupt().
3324 * We disable DMA channel and enable tx ready interrupt and write the
3325 * character when possible.
3326 */
3327static void rs_send_xchar(struct tty_struct *tty, char ch)
3328{
3329 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3330 unsigned long flags;
77accbf5 3331 local_irq_save(flags);
1da177e4
LT		 3332 if (info->uses_dma_out) {
3333 /* Put the DMA on hold and disable the channel */
3334 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3335 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3336 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3337 e100_disable_txdma_channel(info);
3338 }
3339
3340 /* Must make sure transmitter is not stopped before we can transmit */
3341 if (tty->stopped)
3342 rs_start(tty);
3343
3344 /* Enable manual transmit interrupt and send from there */
3345 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3346 info->x_char = ch;
3347 e100_enable_serial_tx_ready_irq(info);
77accbf5 3348 local_irq_restore(flags);
1da177e4
LT		 3349}
3350
3351/*
3352 * ------------------------------------------------------------
3353 * rs_throttle()
3354 *
3355 * This routine is called by the upper-layer tty layer to signal that
3356 * incoming characters should be throttled.
3357 * ------------------------------------------------------------
3358 */
3359static void
3360rs_throttle(struct tty_struct * tty)
3361{
3362 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3363#ifdef SERIAL_DEBUG_THROTTLE
3364 char buf[64];
3365
3366 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3367 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3368#endif
3369 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3370
3371 /* Do RTS before XOFF since XOFF might take some time */
3372 if (tty->termios->c_cflag & CRTSCTS) {
3373 /* Turn off RTS line */
3374 e100_rts(info, 0);
3375 }
3376 if (I_IXOFF(tty))
3377 rs_send_xchar(tty, STOP_CHAR(tty));
3378
3379}
3380
3381static void
3382rs_unthrottle(struct tty_struct * tty)
3383{
3384 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3385#ifdef SERIAL_DEBUG_THROTTLE
3386 char buf[64];
3387
3388 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3389 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3390#endif
3391 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3392 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3393 /* Do RTS before XOFF since XOFF might take some time */
3394 if (tty->termios->c_cflag & CRTSCTS) {
3395 /* Assert RTS line */
3396 e100_rts(info, 1);
3397 }
3398
3399 if (I_IXOFF(tty)) {
3400 if (info->x_char)
3401 info->x_char = 0;
3402 else
3403 rs_send_xchar(tty, START_CHAR(tty));
3404 }
3405
3406}
3407
3408/*
3409 * ------------------------------------------------------------
3410 * rs_ioctl() and friends
3411 * ------------------------------------------------------------
3412 */
3413
3414static int
3415get_serial_info(struct e100_serial * info,
3416 struct serial_struct * retinfo)
3417{
3418 struct serial_struct tmp;
3419
3420 /* this is all probably wrong, there are a lot of fields
3421 * here that we don't have in e100_serial and maybe we
3422 * should set them to something else than 0.
3423 */
3424
3425 if (!retinfo)
3426 return -EFAULT;
3427 memset(&tmp, 0, sizeof(tmp));
3428 tmp.type = info->type;
3429 tmp.line = info->line;
d7283353 3430 tmp.port = (int)info->ioport;
1da177e4
LT		 3431 tmp.irq = info->irq;
3432 tmp.flags = info->flags;
3433 tmp.baud_base = info->baud_base;
3434 tmp.close_delay = info->close_delay;
3435 tmp.closing_wait = info->closing_wait;
3436 tmp.custom_divisor = info->custom_divisor;
3437 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3438 return -EFAULT;
3439 return 0;
3440}
3441
3442static int
3443set_serial_info(struct e100_serial *info,
3444 struct serial_struct *new_info)
3445{
3446 struct serial_struct new_serial;
3447 struct e100_serial old_info;
3448 int retval = 0;
3449
3450 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3451 return -EFAULT;
3452
3453 old_info = *info;
3454
3455 if (!capable(CAP_SYS_ADMIN)) {
3456 if ((new_serial.type != info->type) ||
3457 (new_serial.close_delay != info->close_delay) ||
3458 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3459 (info->flags & ~ASYNC_USR_MASK)))
3460 return -EPERM;
3461 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3462 (new_serial.flags & ASYNC_USR_MASK));
3463 goto check_and_exit;
3464 }
3465
3466 if (info->count > 1)
3467 return -EBUSY;
3468
3469 /*
3470 * OK, past this point, all the error checking has been done.
3471 * At this point, we start making changes.....
3472 */
3473
3474 info->baud_base = new_serial.baud_base;
3475 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3476 (new_serial.flags & ASYNC_FLAGS));
3477 info->custom_divisor = new_serial.custom_divisor;
3478 info->type = new_serial.type;
3479 info->close_delay = new_serial.close_delay;
3480 info->closing_wait = new_serial.closing_wait;
a88487c7 3481 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 3482
3483 check_and_exit:
3484 if (info->flags & ASYNC_INITIALIZED) {
3485 change_speed(info);
3486 } else
3487 retval = startup(info);
3488 return retval;
3489}
3490
3491/*
3492 * get_lsr_info - get line status register info
3493 *
3494 * Purpose: Let user call ioctl() to get info when the UART physically
3495 * is emptied. On bus types like RS485, the transmitter must
3496 * release the bus after transmitting. This must be done when
3497 * the transmit shift register is empty, not be done when the
3498 * transmit holding register is empty. This functionality
3499 * allows an RS485 driver to be written in user space.
3500 */
3501static int
3502get_lsr_info(struct e100_serial * info, unsigned int *value)
3503{
3504 unsigned int result = TIOCSER_TEMT;
3505#ifndef CONFIG_SVINTO_SIM
3506 unsigned long curr_time = jiffies;
3507 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3508 unsigned long elapsed_usec =
3509 (curr_time - info->last_tx_active) * 1000000/HZ +
3510 curr_time_usec - info->last_tx_active_usec;
3511
3512 if (info->xmit.head != info->xmit.tail ||
3513 elapsed_usec < 2*info->char_time_usec) {
3514 result = 0;
3515 }
3516#endif
3517
3518 if (copy_to_user(value, &result, sizeof(int)))
3519 return -EFAULT;
3520 return 0;
3521}
3522
3523#ifdef SERIAL_DEBUG_IO
3524struct state_str
3525{
3526 int state;
3527 const char *str;
3528};
3529
3530const struct state_str control_state_str[] = {
3531 {TIOCM_DTR, "DTR" },
3532 {TIOCM_RTS, "RTS"},
3533 {TIOCM_ST, "ST?" },
3534 {TIOCM_SR, "SR?" },
3535 {TIOCM_CTS, "CTS" },
3536 {TIOCM_CD, "CD" },
3537 {TIOCM_RI, "RI" },
3538 {TIOCM_DSR, "DSR" },
3539 {0, NULL }
3540};
3541
3542char *get_control_state_str(int MLines, char *s)
3543{
3544 int i = 0;
3545
3546 s[0]='\0';
3547 while (control_state_str[i].str != NULL) {
3548 if (MLines & control_state_str[i].state) {
3549 if (s[0] != '\0') {
3550 strcat(s, ", ");
3551 }
3552 strcat(s, control_state_str[i].str);
3553 }
3554 i++;
3555 }
3556 return s;
3557}
3558#endif
3559
d7283353 3560static int
77accbf5
JN		 3561rs_break(struct tty_struct *tty, int break_state)
3562{
3563 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3564 unsigned long flags;
3565
d7283353
AC		 3566 if (!info->ioport)
3567 return -EIO;
77accbf5
JN		 3568
3569 local_irq_save(flags);
3570 if (break_state == -1) {
3571 /* Go to manual mode and set the txd pin to 0 */
3572 /* Clear bit 7 (txd) and 6 (tr_enable) */
3573 info->tx_ctrl &= 0x3F;
3574 } else {
3575 /* Set bit 7 (txd) and 6 (tr_enable) */
3576 info->tx_ctrl |= (0x80 | 0x40);
3577 }
d7283353 3578 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
77accbf5 3579 local_irq_restore(flags);
d7283353 3580 return 0;
77accbf5
JN		 3581}
3582
1da177e4 3583static int
20b9d177 3584rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
1da177e4 3585{
77accbf5 3586 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
978e595f 3587 unsigned long flags;
1da177e4 3588
978e595f 3589 local_irq_save(flags);
032c17e8 3590
77accbf5
JN		 3591 if (clear & TIOCM_RTS)
3592 e100_rts(info, 0);
3593 if (clear & TIOCM_DTR)
3594 e100_dtr(info, 0);
3595 /* Handle FEMALE behaviour */
3596 if (clear & TIOCM_RI)
3597 e100_ri_out(info, 0);
3598 if (clear & TIOCM_CD)
3599 e100_cd_out(info, 0);
3600
3601 if (set & TIOCM_RTS)
3602 e100_rts(info, 1);
3603 if (set & TIOCM_DTR)
3604 e100_dtr(info, 1);
3605 /* Handle FEMALE behaviour */
3606 if (set & TIOCM_RI)
3607 e100_ri_out(info, 1);
3608 if (set & TIOCM_CD)
3609 e100_cd_out(info, 1);
032c17e8 3610
978e595f 3611 local_irq_restore(flags);
77accbf5
JN		 3612 return 0;
3613}
3614
3615static int
60b33c13 3616rs_tiocmget(struct tty_struct *tty)
77accbf5
JN		 3617{
3618 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3619 unsigned int result;
978e595f
AC		 3620 unsigned long flags;
3621
3622 local_irq_save(flags);
1da177e4
LT		 3623
3624 result =
3625 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3626 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3627 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3628 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3629 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3630 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3631
978e595f 3632 local_irq_restore(flags);
032c17e8 3633
1da177e4 3634#ifdef SERIAL_DEBUG_IO
77accbf5
JN		 3635 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3636 info->line, result, result);
1da177e4
LT		 3637 {
3638 char s[100];
3639
3640 get_control_state_str(result, s);
77accbf5 3641 printk(KERN_DEBUG "state: %s\n", s);
1da177e4
LT		 3642 }
3643#endif
77accbf5 3644 return result;
1da177e4 3645
1da177e4
LT		 3646}
3647
3648
1da177e4 3649static int
6caa76b7 3650rs_ioctl(struct tty_struct *tty,
1da177e4
LT		 3651 unsigned int cmd, unsigned long arg)
3652{
3653 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3654
3655 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3656 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3657 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3658 if (tty->flags & (1 << TTY_IO_ERROR))
3659 return -EIO;
3660 }
3661
3662 switch (cmd) {
77accbf5
JN		 3663 case TIOCGSERIAL:
3664 return get_serial_info(info,
3665 (struct serial_struct *) arg);
3666 case TIOCSSERIAL:
3667 return set_serial_info(info,
3668 (struct serial_struct *) arg);
3669 case TIOCSERGETLSR: /* Get line status register */
3670 return get_lsr_info(info, (unsigned int *) arg);
3671
3672 case TIOCSERGSTRUCT:
3673 if (copy_to_user((struct e100_serial *) arg,
3674 info, sizeof(struct e100_serial)))
3675 return -EFAULT;
3676 return 0;
1da177e4
LT		 3677
3678#if defined(CONFIG_ETRAX_RS485)
77accbf5
JN		 3679 case TIOCSERSETRS485:
3680 {
6fd1af4c
CS		 3681 /* In this ioctl we still use the old structure
3682 * rs485_control for backward compatibility
3683 * (if we use serial_rs485, then old user-level code
3684 * wouldn't work anymore...).
3685 * The use of this ioctl is deprecated: use TIOCSRS485
3686 * instead.*/
77accbf5 3687 struct rs485_control rs485ctrl;
6fd1af4c
CS		 3688 struct serial_rs485 rs485data;
3689 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
77accbf5
JN		 3690 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3691 sizeof(rs485ctrl)))
3692 return -EFAULT;
1da177e4 3693
6fd1af4c
CS		 3694 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3695 rs485data.flags = 0;
c7213fc4 3696
6fd1af4c
CS		 3697 if (rs485ctrl.enabled)
3698 rs485data.flags |= SER_RS485_ENABLED;
3699 else
3700 rs485data.flags &= ~(SER_RS485_ENABLED);
3701
3702 if (rs485ctrl.rts_on_send)
3703 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3704 else
3705 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3706
3707 if (rs485ctrl.rts_after_sent)
3708 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3709 else
3710 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3711
3712 return e100_enable_rs485(tty, &rs485data);
77accbf5 3713 }
1da177e4 3714
6fd1af4c
CS		 3715 case TIOCSRS485:
3716 {
3717 /* This is the new version of TIOCSRS485, with new
3718 * data structure serial_rs485 */
3719 struct serial_rs485 rs485data;
3720 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3721 sizeof(rs485data)))
3722 return -EFAULT;
3723
3724 return e100_enable_rs485(tty, &rs485data);
3725 }
3726
f1d23ed8
CS		 3727 case TIOCGRS485:
3728 {
3729 struct serial_rs485 *rs485data =
3730 &(((struct e100_serial *)tty->driver_data)->rs485);
3731 /* This is the ioctl to get RS485 data from user-space */
3732 if (copy_to_user((struct serial_rs485 *) arg,
3733 rs485data,
94479c01 3734 sizeof(struct serial_rs485)))
f1d23ed8
CS		 3735 return -EFAULT;
3736 break;
3737 }
6fd1af4c 3738
77accbf5
JN		 3739 case TIOCSERWRRS485:
3740 {
3741 struct rs485_write rs485wr;
3742 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3743 sizeof(rs485wr)))
3744 return -EFAULT;
1da177e4 3745
77accbf5
JN		 3746 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3747 }
1da177e4
LT		 3748#endif
3749
77accbf5
JN		 3750 default:
3751 return -ENOIOCTLCMD;
1da177e4
LT		 3752 }
3753 return 0;
3754}
3755
3756static void
606d099c 3757rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 3758{
3759 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3760
1da177e4
LT		 3761 change_speed(info);
3762
3763 /* Handle turning off CRTSCTS */
3764 if ((old_termios->c_cflag & CRTSCTS) &&
3765 !(tty->termios->c_cflag & CRTSCTS)) {
3766 tty->hw_stopped = 0;
3767 rs_start(tty);
3768 }
3769
3770}
3771
1da177e4
LT		 3772/*
3773 * ------------------------------------------------------------
3774 * rs_close()
3775 *
3776 * This routine is called when the serial port gets closed. First, we
3777 * wait for the last remaining data to be sent. Then, we unlink its
3778 * S structure from the interrupt chain if necessary, and we free
3779 * that IRQ if nothing is left in the chain.
3780 * ------------------------------------------------------------
3781 */
3782static void
3783rs_close(struct tty_struct *tty, struct file * filp)
3784{
3785 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3786 unsigned long flags;
3787
3788 if (!info)
3789 return;
3790
3791 /* interrupts are disabled for this entire function */
3792
77accbf5 3793 local_irq_save(flags);
1da177e4
LT		 3794
3795 if (tty_hung_up_p(filp)) {
77accbf5 3796 local_irq_restore(flags);
1da177e4
LT		 3797 return;
3798 }
3799
3800#ifdef SERIAL_DEBUG_OPEN
3801 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3802 info->line, info->count);
3803#endif
3804 if ((tty->count == 1) && (info->count != 1)) {
3805 /*
3806 * Uh, oh. tty->count is 1, which means that the tty
3807 * structure will be freed. Info->count should always
3808 * be one in these conditions. If it's greater than
3809 * one, we've got real problems, since it means the
3810 * serial port won't be shutdown.
3811 */
3d43b7d5 3812 printk(KERN_ERR
1da177e4
LT		 3813 "rs_close: bad serial port count; tty->count is 1, "
3814 "info->count is %d\n", info->count);
3815 info->count = 1;
3816 }
3817 if (--info->count < 0) {
3d43b7d5 3818 printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n",
1da177e4
LT		 3819 info->line, info->count);
3820 info->count = 0;
3821 }
3822 if (info->count) {
77accbf5 3823 local_irq_restore(flags);
1da177e4
LT		 3824 return;
3825 }
3826 info->flags |= ASYNC_CLOSING;
3827 /*
3828 * Save the termios structure, since this port may have
3829 * separate termios for callout and dialin.
3830 */
3831 if (info->flags & ASYNC_NORMAL_ACTIVE)
3832 info->normal_termios = *tty->termios;
3833 /*
3834 * Now we wait for the transmit buffer to clear; and we notify
3835 * the line discipline to only process XON/XOFF characters.
3836 */
3837 tty->closing = 1;
3838 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3839 tty_wait_until_sent(tty, info->closing_wait);
3840 /*
3841 * At this point we stop accepting input. To do this, we
3842 * disable the serial receiver and the DMA receive interrupt.
3843 */
3844#ifdef SERIAL_HANDLE_EARLY_ERRORS
3845 e100_disable_serial_data_irq(info);
3846#endif
3847
3848#ifndef CONFIG_SVINTO_SIM
3849 e100_disable_rx(info);
3850 e100_disable_rx_irq(info);
3851
3852 if (info->flags & ASYNC_INITIALIZED) {
3853 /*
3854 * Before we drop DTR, make sure the UART transmitter
3855 * has completely drained; this is especially
3856 * important as we have a transmit FIFO!
3857 */
3858 rs_wait_until_sent(tty, HZ);
3859 }
3860#endif
3861
3862 shutdown(info);
978e595f 3863 rs_flush_buffer(tty);
454aa389 3864 tty_ldisc_flush(tty);
1da177e4
LT		 3865 tty->closing = 0;
3866 info->event = 0;
a88487c7 3867 info->port.tty = NULL;
1da177e4 3868 if (info->blocked_open) {
3c76bc5b
NA		 3869 if (info->close_delay)
3870 schedule_timeout_interruptible(info->close_delay);
1da177e4
LT		 3871 wake_up_interruptible(&info->open_wait);
3872 }
3873 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3874 wake_up_interruptible(&info->close_wait);
77accbf5 3875 local_irq_restore(flags);
1da177e4
LT		 3876
3877 /* port closed */
3878
3879#if defined(CONFIG_ETRAX_RS485)
6fd1af4c
CS		 3880 if (info->rs485.flags & SER_RS485_ENABLED) {
3881 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 3882#if defined(CONFIG_ETRAX_RS485_ON_PA)
3883 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3884#endif
3885#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3886 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3887 rs485_port_g_bit, 0);
3888#endif
3889#if defined(CONFIG_ETRAX_RS485_LTC1387)
3890 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3891 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3892 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3893 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3894#endif
3895 }
3896#endif
77accbf5
JN		 3897
3898 /*
3899 * Release any allocated DMA irq's.
3900 */
3901 if (info->dma_in_enabled) {
3902 free_irq(info->dma_in_irq_nbr, info);
3903 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3904 info->uses_dma_in = 0;
3905#ifdef SERIAL_DEBUG_OPEN
3906 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3907 info->dma_in_irq_description);
3908#endif
3909 }
3910 if (info->dma_out_enabled) {
3911 free_irq(info->dma_out_irq_nbr, info);
3912 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3913 info->uses_dma_out = 0;
3914#ifdef SERIAL_DEBUG_OPEN
3915 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3916 info->dma_out_irq_description);
3917#endif
3918 }
1da177e4
LT		 3919}
3920
3921/*
3922 * rs_wait_until_sent() --- wait until the transmitter is empty
3923 */
3924static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3925{
3926 unsigned long orig_jiffies;
3927 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3928 unsigned long curr_time = jiffies;
3929 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3930 long elapsed_usec =
3931 (curr_time - info->last_tx_active) * (1000000/HZ) +
3932 curr_time_usec - info->last_tx_active_usec;
3933
3934 /*
3935 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3936 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3937 */
3938 orig_jiffies = jiffies;
3939 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3940 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3941 (elapsed_usec < 2*info->char_time_usec)) {
3c76bc5b 3942 schedule_timeout_interruptible(1);
1da177e4
LT		 3943 if (signal_pending(current))
3944 break;
3945 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3946 break;
3947 curr_time = jiffies;
3948 curr_time_usec = GET_JIFFIES_USEC();
3949 elapsed_usec =
3950 (curr_time - info->last_tx_active) * (1000000/HZ) +
3951 curr_time_usec - info->last_tx_active_usec;
3952 }
3953 set_current_state(TASK_RUNNING);
3954}
3955
3956/*
3957 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3958 */
3959void
3960rs_hangup(struct tty_struct *tty)
3961{
3962 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3963
3964 rs_flush_buffer(tty);
3965 shutdown(info);
3966 info->event = 0;
3967 info->count = 0;
3968 info->flags &= ~ASYNC_NORMAL_ACTIVE;
a88487c7 3969 info->port.tty = NULL;
1da177e4
LT		 3970 wake_up_interruptible(&info->open_wait);
3971}
3972
3973/*
3974 * ------------------------------------------------------------
3975 * rs_open() and friends
3976 * ------------------------------------------------------------
3977 */
3978static int
3979block_til_ready(struct tty_struct *tty, struct file * filp,
3980 struct e100_serial *info)
3981{
3982 DECLARE_WAITQUEUE(wait, current);
3983 unsigned long flags;
3984 int retval;
3985 int do_clocal = 0, extra_count = 0;
3986
3987 /*
3988 * If the device is in the middle of being closed, then block
3989 * until it's done, and then try again.
3990 */
3991 if (tty_hung_up_p(filp) ||
3992 (info->flags & ASYNC_CLOSING)) {
be1bc288 3993 wait_event_interruptible_tty(info->close_wait,
77accbf5 3994 !(info->flags & ASYNC_CLOSING));
1da177e4
LT		 3995#ifdef SERIAL_DO_RESTART
3996 if (info->flags & ASYNC_HUP_NOTIFY)
3997 return -EAGAIN;
3998 else
3999 return -ERESTARTSYS;
4000#else
4001 return -EAGAIN;
4002#endif
4003 }
4004
4005 /*
4006 * If non-blocking mode is set, or the port is not enabled,
4007 * then make the check up front and then exit.
4008 */
4009 if ((filp->f_flags & O_NONBLOCK) ||
4010 (tty->flags & (1 << TTY_IO_ERROR))) {
4011 info->flags |= ASYNC_NORMAL_ACTIVE;
4012 return 0;
4013 }
4014
4015 if (tty->termios->c_cflag & CLOCAL) {
4016 do_clocal = 1;
4017 }
4018
4019 /*
4020 * Block waiting for the carrier detect and the line to become
4021 * free (i.e., not in use by the callout). While we are in
4022 * this loop, info->count is dropped by one, so that
4023 * rs_close() knows when to free things. We restore it upon
4024 * exit, either normal or abnormal.
4025 */
4026 retval = 0;
4027 add_wait_queue(&info->open_wait, &wait);
4028#ifdef SERIAL_DEBUG_OPEN
4029 printk("block_til_ready before block: ttyS%d, count = %d\n",
4030 info->line, info->count);
4031#endif
77accbf5 4032 local_irq_save(flags);
1da177e4
LT		 4033 if (!tty_hung_up_p(filp)) {
4034 extra_count++;
4035 info->count--;
4036 }
77accbf5 4037 local_irq_restore(flags);
1da177e4
LT		 4038 info->blocked_open++;
4039 while (1) {
77accbf5 4040 local_irq_save(flags);
1da177e4
LT		 4041 /* assert RTS and DTR */
4042 e100_rts(info, 1);
4043 e100_dtr(info, 1);
77accbf5 4044 local_irq_restore(flags);
1da177e4
LT		 4045 set_current_state(TASK_INTERRUPTIBLE);
4046 if (tty_hung_up_p(filp) ||
4047 !(info->flags & ASYNC_INITIALIZED)) {
4048#ifdef SERIAL_DO_RESTART
4049 if (info->flags & ASYNC_HUP_NOTIFY)
4050 retval = -EAGAIN;
4051 else
4052 retval = -ERESTARTSYS;
4053#else
4054 retval = -EAGAIN;
4055#endif
4056 break;
4057 }
4058 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4059 /* && (do_clocal || DCD_IS_ASSERTED) */
4060 break;
4061 if (signal_pending(current)) {
4062 retval = -ERESTARTSYS;
4063 break;
4064 }
4065#ifdef SERIAL_DEBUG_OPEN
4066 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4067 info->line, info->count);
4068#endif
e142a31d 4069 tty_unlock();
1da177e4 4070 schedule();
e142a31d 4071 tty_lock();
1da177e4
LT		 4072 }
4073 set_current_state(TASK_RUNNING);
4074 remove_wait_queue(&info->open_wait, &wait);
4075 if (extra_count)
4076 info->count++;
4077 info->blocked_open--;
4078#ifdef SERIAL_DEBUG_OPEN
4079 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4080 info->line, info->count);
4081#endif
4082 if (retval)
4083 return retval;
4084 info->flags |= ASYNC_NORMAL_ACTIVE;
4085 return 0;
4086}
4087
77accbf5
JN		 4088static void
4089deinit_port(struct e100_serial *info)
4090{
4091 if (info->dma_out_enabled) {
4092 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4093 free_irq(info->dma_out_irq_nbr, info);
4094 }
4095 if (info->dma_in_enabled) {
4096 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4097 free_irq(info->dma_in_irq_nbr, info);
4098 }
4099}
4100
1da177e4
LT		 4101/*
4102 * This routine is called whenever a serial port is opened.
4103 * It performs the serial-specific initialization for the tty structure.
4104 */
4105static int
4106rs_open(struct tty_struct *tty, struct file * filp)
4107{
4108 struct e100_serial *info;
410235fd 4109 int retval;
1da177e4 4110 unsigned long page;
77accbf5 4111 int allocated_resources = 0;
1da177e4 4112
410235fd 4113 info = rs_table + tty->index;
1da177e4
LT		 4114 if (!info->enabled)
4115 return -ENODEV;
4116
4117#ifdef SERIAL_DEBUG_OPEN
4118 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4119 info->count);
4120#endif
4121
4122 info->count++;
4123 tty->driver_data = info;
a88487c7 4124 info->port.tty = tty;
1da177e4 4125
410235fd 4126 tty->low_latency = !!(info->flags & ASYNC_LOW_LATENCY);
1da177e4
LT		 4127
4128 if (!tmp_buf) {
4129 page = get_zeroed_page(GFP_KERNEL);
4130 if (!page) {
4131 return -ENOMEM;
4132 }
4133 if (tmp_buf)
4134 free_page(page);
4135 else
4136 tmp_buf = (unsigned char *) page;
4137 }
4138
4139 /*
4140 * If the port is in the middle of closing, bail out now
4141 */
4142 if (tty_hung_up_p(filp) ||
4143 (info->flags & ASYNC_CLOSING)) {
be1bc288 4144 wait_event_interruptible_tty(info->close_wait,
77accbf5 4145 !(info->flags & ASYNC_CLOSING));
1da177e4
LT		 4146#ifdef SERIAL_DO_RESTART
4147 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4148 -EAGAIN : -ERESTARTSYS);
4149#else
4150 return -EAGAIN;
4151#endif
4152 }
4153
77accbf5
JN		 4154 /*
4155 * If DMA is enabled try to allocate the irq's.
4156 */
4157 if (info->count == 1) {
4158 allocated_resources = 1;
4159 if (info->dma_in_enabled) {
4160 if (request_irq(info->dma_in_irq_nbr,
4161 rec_interrupt,
4162 info->dma_in_irq_flags,
4163 info->dma_in_irq_description,
4164 info)) {
4165 printk(KERN_WARNING "DMA irq '%s' busy; "
4166 "falling back to non-DMA mode\n",
4167 info->dma_in_irq_description);
4168 /* Make sure we never try to use DMA in */
4169 /* for the port again. */
4170 info->dma_in_enabled = 0;
4171 } else if (cris_request_dma(info->dma_in_nbr,
4172 info->dma_in_irq_description,
4173 DMA_VERBOSE_ON_ERROR,
4174 info->dma_owner)) {
4175 free_irq(info->dma_in_irq_nbr, info);
4176 printk(KERN_WARNING "DMA '%s' busy; "
4177 "falling back to non-DMA mode\n",
4178 info->dma_in_irq_description);
4179 /* Make sure we never try to use DMA in */
4180 /* for the port again. */
4181 info->dma_in_enabled = 0;
4182 }
4183#ifdef SERIAL_DEBUG_OPEN
4184 else
4185 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4186 info->dma_in_irq_description);
4187#endif
4188 }
4189 if (info->dma_out_enabled) {
4190 if (request_irq(info->dma_out_irq_nbr,
4191 tr_interrupt,
4192 info->dma_out_irq_flags,
4193 info->dma_out_irq_description,
4194 info)) {
4195 printk(KERN_WARNING "DMA irq '%s' busy; "
4196 "falling back to non-DMA mode\n",
4197 info->dma_out_irq_description);
4198 /* Make sure we never try to use DMA out */
4199 /* for the port again. */
4200 info->dma_out_enabled = 0;
4201 } else if (cris_request_dma(info->dma_out_nbr,
4202 info->dma_out_irq_description,
4203 DMA_VERBOSE_ON_ERROR,
4204 info->dma_owner)) {
4205 free_irq(info->dma_out_irq_nbr, info);
4206 printk(KERN_WARNING "DMA '%s' busy; "
4207 "falling back to non-DMA mode\n",
4208 info->dma_out_irq_description);
4209 /* Make sure we never try to use DMA out */
4210 /* for the port again. */
4211 info->dma_out_enabled = 0;
4212 }
4213#ifdef SERIAL_DEBUG_OPEN
4214 else
4215 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4216 info->dma_out_irq_description);
4217#endif
4218 }
4219 }
4220
1da177e4
LT		 4221 /*
4222 * Start up the serial port
4223 */
4224
4225 retval = startup(info);
77accbf5
JN		 4226 if (retval) {
4227 if (allocated_resources)
4228 deinit_port(info);
4229
4230 /* FIXME Decrease count info->count here too? */
1da177e4 4231 return retval;
77accbf5
JN		 4232 }
4233
1da177e4
LT		 4234
4235 retval = block_til_ready(tty, filp, info);
4236 if (retval) {
4237#ifdef SERIAL_DEBUG_OPEN
4238 printk("rs_open returning after block_til_ready with %d\n",
4239 retval);
4240#endif
77accbf5
JN		 4241 if (allocated_resources)
4242 deinit_port(info);
4243
1da177e4
LT		 4244 return retval;
4245 }
4246
4247 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4248 *tty->termios = info->normal_termios;
4249 change_speed(info);
4250 }
4251
4252#ifdef SERIAL_DEBUG_OPEN
4253 printk("rs_open ttyS%d successful...\n", info->line);
4254#endif
4255 DLOG_INT_TRIG( log_int_pos = 0);
4256
4257 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4258 info->icount.rx = 0;
4259 } );
4260
4261 return 0;
4262}
4263
9e040a3e 4264#ifdef CONFIG_PROC_FS
1da177e4
LT		 4265/*
4266 * /proc fs routines....
4267 */
4268
9e040a3e 4269static void seq_line_info(struct seq_file *m, struct e100_serial *info)
1da177e4 4270{
1da177e4
LT		 4271 unsigned long tmp;
4272
9e040a3e
JN		 4273 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4274 info->line, (unsigned long)info->ioport, info->irq);
1da177e4 4275
d7283353 4276 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
9e040a3e
JN		 4277 seq_printf(m, "\n");
4278 return;
1da177e4
LT		 4279 }
4280
9e040a3e
JN		 4281 seq_printf(m, " baud:%d", info->baud);
4282 seq_printf(m, " tx:%lu rx:%lu",
1da177e4
LT		 4283 (unsigned long)info->icount.tx,
4284 (unsigned long)info->icount.rx);
4285 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
9e040a3e
JN		 4286 if (tmp)
4287 seq_printf(m, " tx_pend:%lu/%lu",
4288 (unsigned long)tmp,
4289 (unsigned long)SERIAL_XMIT_SIZE);
1da177e4 4290
9e040a3e
JN		 4291 seq_printf(m, " rx_pend:%lu/%lu",
4292 (unsigned long)info->recv_cnt,
4293 (unsigned long)info->max_recv_cnt);
1da177e4
LT		 4294
4295#if 1
a88487c7 4296 if (info->port.tty) {
a88487c7 4297 if (info->port.tty->stopped)
9e040a3e
JN		 4298 seq_printf(m, " stopped:%i",
4299 (int)info->port.tty->stopped);
a88487c7 4300 if (info->port.tty->hw_stopped)
9e040a3e
JN		 4301 seq_printf(m, " hw_stopped:%i",
4302 (int)info->port.tty->hw_stopped);
1da177e4
LT		 4303 }
4304
4305 {
d7283353 4306 unsigned char rstat = info->ioport[REG_STATUS];
9e040a3e
JN		 4307 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4308 seq_printf(m, " xoff_detect:1");
1da177e4
LT		 4309 }
4310
4311#endif
4312
1da177e4 4313 if (info->icount.frame)
9e040a3e 4314 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
1da177e4
LT		 4315
4316 if (info->icount.parity)
9e040a3e 4317 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
1da177e4
LT		 4318
4319 if (info->icount.brk)
9e040a3e 4320 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
1da177e4
LT		 4321
4322 if (info->icount.overrun)
9e040a3e 4323 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
1da177e4
LT		 4324
4325 /*
4326 * Last thing is the RS-232 status lines
4327 */
9e040a3e
JN		 4328 if (!E100_RTS_GET(info))
4329 seq_puts(m, "|RTS");
4330 if (!E100_CTS_GET(info))
4331 seq_puts(m, "|CTS");
4332 if (!E100_DTR_GET(info))
4333 seq_puts(m, "|DTR");
4334 if (!E100_DSR_GET(info))
4335 seq_puts(m, "|DSR");
4336 if (!E100_CD_GET(info))
4337 seq_puts(m, "|CD");
4338 if (!E100_RI_GET(info))
4339 seq_puts(m, "|RI");
4340 seq_puts(m, "\n");
1da177e4
LT		 4341}
4342
9e040a3e
JN		 4343
4344static int crisv10_proc_show(struct seq_file *m, void *v)
1da177e4 4345{
9e040a3e 4346 int i;
1da177e4 4347
9e040a3e
JN		 4348 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4349
4350 for (i = 0; i < NR_PORTS; i++) {
1da177e4
LT		 4351 if (!rs_table[i].enabled)
4352 continue;
9e040a3e 4353 seq_line_info(m, &rs_table[i]);
1da177e4
LT		 4354 }
4355#ifdef DEBUG_LOG_INCLUDED
4356 for (i = 0; i < debug_log_pos; i++) {
9e040a3e
JN		 4357 seq_printf(m, "%-4i %lu.%lu ",
4358 i, debug_log[i].time,
4359 timer_data_to_ns(debug_log[i].timer_data));
4360 seq_printf(m, debug_log[i].string, debug_log[i].value);
1da177e4 4361 }
9e040a3e 4362 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
1da177e4
LT		 4363 debug_log_pos = 0;
4364#endif
9e040a3e
JN		 4365 return 0;
4366}
1da177e4 4367
9e040a3e
JN		 4368static int crisv10_proc_open(struct inode *inode, struct file *file)
4369{
4370 return single_open(file, crisv10_proc_show, NULL);
1da177e4
LT		 4371}
4372
9e040a3e
JN		 4373static const struct file_operations crisv10_proc_fops = {
4374 .owner = THIS_MODULE,
4375 .open = crisv10_proc_open,
4376 .read = seq_read,
4377 .llseek = seq_lseek,
4378 .release = single_release,
4379};
4380#endif
4381
4382
1da177e4
LT		 4383/* Finally, routines used to initialize the serial driver. */
4384
9e040a3e 4385static void show_serial_version(void)
1da177e4
LT		 4386{
4387 printk(KERN_INFO
9e040a3e
JN		 4388 "ETRAX 100LX serial-driver %s, "
4389 "(c) 2000-2004 Axis Communications AB\r\n",
1da177e4
LT		 4390 &serial_version[11]); /* "$Revision: x.yy" */
4391}
4392
4393/* rs_init inits the driver at boot (using the module_init chain) */
4394
b68e31d0 4395static const struct tty_operations rs_ops = {
1da177e4
LT		 4396 .open = rs_open,
4397 .close = rs_close,
4398 .write = rs_write,
4399 .flush_chars = rs_flush_chars,
4400 .write_room = rs_write_room,
4401 .chars_in_buffer = rs_chars_in_buffer,
4402 .flush_buffer = rs_flush_buffer,
4403 .ioctl = rs_ioctl,
4404 .throttle = rs_throttle,
4405 .unthrottle = rs_unthrottle,
4406 .set_termios = rs_set_termios,
4407 .stop = rs_stop,
4408 .start = rs_start,
4409 .hangup = rs_hangup,
4410 .break_ctl = rs_break,
4411 .send_xchar = rs_send_xchar,
4412 .wait_until_sent = rs_wait_until_sent,
77accbf5 4413 .tiocmget = rs_tiocmget,
9e040a3e
JN		 4414 .tiocmset = rs_tiocmset,
4415#ifdef CONFIG_PROC_FS
4416 .proc_fops = &crisv10_proc_fops,
4417#endif
1da177e4
LT		 4418};
4419
9e040a3e 4420static int __init rs_init(void)
1da177e4
LT		 4421{
4422 int i;
4423 struct e100_serial *info;
4424 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4425
4426 if (!driver)
4427 return -ENOMEM;
4428
4429 show_serial_version();
4430
4431 /* Setup the timed flush handler system */
4432
4433#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
77accbf5
JN		 4434 setup_timer(&flush_timer, timed_flush_handler, 0);
4435 mod_timer(&flush_timer, jiffies + 5);
4436#endif
4437
4438#if defined(CONFIG_ETRAX_RS485)
4439#if defined(CONFIG_ETRAX_RS485_ON_PA)
2f7861de 4440 if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit,
77accbf5 4441 rs485_pa_bit)) {
3d43b7d5 4442 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
77accbf5 4443 "RS485 pin\n");
41ca7322 4444 put_tty_driver(driver);
77accbf5
JN		 4445 return -EBUSY;
4446 }
4447#endif
4448#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
2f7861de 4449 if (cris_io_interface_allocate_pins(if_serial_0, 'g', rs485_pa_bit,
77accbf5 4450 rs485_port_g_bit)) {
3d43b7d5 4451 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
77accbf5 4452 "RS485 pin\n");
41ca7322 4453 put_tty_driver(driver);
77accbf5
JN		 4454 return -EBUSY;
4455 }
4456#endif
1da177e4
LT		 4457#endif
4458
4459 /* Initialize the tty_driver structure */
4460
4461 driver->driver_name = "serial";
4462 driver->name = "ttyS";
4463 driver->major = TTY_MAJOR;
4464 driver->minor_start = 64;
4465 driver->type = TTY_DRIVER_TYPE_SERIAL;
4466 driver->subtype = SERIAL_TYPE_NORMAL;
4467 driver->init_termios = tty_std_termios;
4468 driver->init_termios.c_cflag =
4469 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
606d099c
AC		 4470 driver->init_termios.c_ispeed = 115200;
4471 driver->init_termios.c_ospeed = 115200;
331b8319 4472 driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 4473
4474 tty_set_operations(driver, &rs_ops);
4475 serial_driver = driver;
4476 if (tty_register_driver(driver))
4477 panic("Couldn't register serial driver\n");
4478 /* do some initializing for the separate ports */
4479
4480 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
77accbf5
JN		 4481 if (info->enabled) {
4482 if (cris_request_io_interface(info->io_if,
4483 info->io_if_description)) {
3d43b7d5 4484 printk(KERN_ERR "ETRAX100LX async serial: "
77accbf5
JN		 4485 "Could not allocate IO pins for "
4486 "%s, port %d\n",
4487 info->io_if_description, i);
4488 info->enabled = 0;
4489 }
4490 }
1da177e4
LT		 4491 info->uses_dma_in = 0;
4492 info->uses_dma_out = 0;
4493 info->line = i;
a88487c7 4494 info->port.tty = NULL;
1da177e4
LT		 4495 info->type = PORT_ETRAX;
4496 info->tr_running = 0;
4497 info->forced_eop = 0;
4498 info->baud_base = DEF_BAUD_BASE;
4499 info->custom_divisor = 0;
4500 info->flags = 0;
4501 info->close_delay = 5*HZ/10;
4502 info->closing_wait = 30*HZ;
4503 info->x_char = 0;
4504 info->event = 0;
4505 info->count = 0;
4506 info->blocked_open = 0;
4507 info->normal_termios = driver->init_termios;
4508 init_waitqueue_head(&info->open_wait);
4509 init_waitqueue_head(&info->close_wait);
4510 info->xmit.buf = NULL;
4511 info->xmit.tail = info->xmit.head = 0;
4512 info->first_recv_buffer = info->last_recv_buffer = NULL;
4513 info->recv_cnt = info->max_recv_cnt = 0;
4514 info->last_tx_active_usec = 0;
4515 info->last_tx_active = 0;
4516
4517#if defined(CONFIG_ETRAX_RS485)
4518 /* Set sane defaults */
6fd1af4c
CS		 4519 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4520 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
1da177e4 4521 info->rs485.delay_rts_before_send = 0;
6fd1af4c 4522 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4 4523#endif
77accbf5 4524 INIT_WORK(&info->work, do_softint);
1da177e4
LT		 4525
4526 if (info->enabled) {
078dee2d
KV		 4527 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4528 serial_driver->name, info->line, info->ioport);
1da177e4
LT		 4529 }
4530 }
4531#ifdef CONFIG_ETRAX_FAST_TIMER
4532#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4533 memset(fast_timers, 0, sizeof(fast_timers));
4534#endif
4535#ifdef CONFIG_ETRAX_RS485
4536 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4537#endif
4538 fast_timer_init();
4539#endif
4540
4541#ifndef CONFIG_SVINTO_SIM
77accbf5 4542#ifndef CONFIG_ETRAX_KGDB
1da177e4
LT		 4543 /* Not needed in simulator. May only complicate stuff. */
4544 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4545
77accbf5 4546 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
9cfb5c05 4547 IRQF_SHARED, "serial ", driver))
71cc2c21 4548 panic("%s: Failed to request irq8", __func__);
1da177e4 4549
1da177e4
LT		 4550#endif
4551#endif /* CONFIG_SVINTO_SIM */
77accbf5 4552
1da177e4
LT		 4553 return 0;
4554}
4555
4556/* this makes sure that rs_init is called during kernel boot */
4557
4558module_init(rs_init);
Linux kernel - Deliverables
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