projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 44318feb | 1 | /* |
| 2 | * max3107.h - spi uart protocol driver header for Maxim 3107 | |
| 3 | * | |
| 4 | * Copyright (C) Aavamobile 2009 | |
| 5 | * Based on serial_max3100.h by Christian Pellegrin | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License as published by | |
| 9 | * the Free Software Foundation; either version 2 of the License, or | |
| 10 | * (at your option) any later version. | |
| 11 | */ | |
| 12 | ||
| 61fd1526 AC |
13 | #ifndef _MAX3107_H |
| 14 | #define _MAX3107_H | |
| 44318feb | 15 | |
| 16 | /* Serial error status definitions */ | |
| 17 | #define MAX3107_PARITY_ERROR 1 | |
| 18 | #define MAX3107_FRAME_ERROR 2 | |
| 19 | #define MAX3107_OVERRUN_ERROR 4 | |
| 20 | #define MAX3107_ALL_ERRORS (MAX3107_PARITY_ERROR | \ | |
| 21 | MAX3107_FRAME_ERROR | \ | |
| 22 | MAX3107_OVERRUN_ERROR) | |
| 23 | ||
| 24 | /* GPIO definitions */ | |
| 25 | #define MAX3107_GPIO_BASE 88 | |
| 26 | #define MAX3107_GPIO_COUNT 4 | |
| 27 | ||
| 28 | ||
| 29 | /* GPIO connected to chip's reset pin */ | |
| 30 | #define MAX3107_RESET_GPIO 87 | |
| 31 | ||
| 32 | ||
| 33 | /* Chip reset delay */ | |
| 34 | #define MAX3107_RESET_DELAY 10 | |
| 35 | ||
| 36 | /* Chip wakeup delay */ | |
| 37 | #define MAX3107_WAKEUP_DELAY 50 | |
| 38 | ||
| 39 | ||
| 40 | /* Sleep mode definitions */ | |
| 41 | #define MAX3107_DISABLE_FORCED_SLEEP 0 | |
| 42 | #define MAX3107_ENABLE_FORCED_SLEEP 1 | |
| 43 | #define MAX3107_DISABLE_AUTOSLEEP 2 | |
| 44 | #define MAX3107_ENABLE_AUTOSLEEP 3 | |
| 45 | ||
| 46 | ||
| 47 | /* Definitions for register access with SPI transfers | |
| 48 | * | |
| 49 | * SPI transfer format: | |
| 50 | * | |
| 51 | * Master to slave bits xzzzzzzzyyyyyyyy | |
| 52 | * Slave to master bits aaaaaaaabbbbbbbb | |
| 53 | * | |
| 54 | * where: | |
| 55 | * x = 0 for reads, 1 for writes | |
| 56 | * z = register address | |
| 57 | * y = new register value if write, 0 if read | |
| 58 | * a = unspecified | |
| 59 | * b = register value if read, unspecified if write | |
| 60 | */ | |
| 61 | ||
| 62 | /* SPI speed */ | |
| 63 | #define MAX3107_SPI_SPEED (3125000 * 2) | |
| 64 | ||
| 65 | /* Write bit */ | |
| 66 | #define MAX3107_WRITE_BIT (1 << 15) | |
| 67 | ||
| 68 | /* SPI TX data mask */ | |
| 69 | #define MAX3107_SPI_RX_DATA_MASK (0x00ff) | |
| 70 | ||
| 71 | /* SPI RX data mask */ | |
| 72 | #define MAX3107_SPI_TX_DATA_MASK (0x00ff) | |
| 73 | ||
| 74 | /* Register access masks */ | |
| 75 | #define MAX3107_RHR_REG (0x0000) /* RX FIFO */ | |
| 76 | #define MAX3107_THR_REG (0x0000) /* TX FIFO */ | |
| 77 | #define MAX3107_IRQEN_REG (0x0100) /* IRQ enable */ | |
| 78 | #define MAX3107_IRQSTS_REG (0x0200) /* IRQ status */ | |
| 79 | #define MAX3107_LSR_IRQEN_REG (0x0300) /* LSR IRQ enable */ | |
| 80 | #define MAX3107_LSR_IRQSTS_REG (0x0400) /* LSR IRQ status */ | |
| 81 | #define MAX3107_SPCHR_IRQEN_REG (0x0500) /* Special char IRQ enable */ | |
| 82 | #define MAX3107_SPCHR_IRQSTS_REG (0x0600) /* Special char IRQ status */ | |
| 83 | #define MAX3107_STS_IRQEN_REG (0x0700) /* Status IRQ enable */ | |
| 84 | #define MAX3107_STS_IRQSTS_REG (0x0800) /* Status IRQ status */ | |
| 85 | #define MAX3107_MODE1_REG (0x0900) /* MODE1 */ | |
| 86 | #define MAX3107_MODE2_REG (0x0a00) /* MODE2 */ | |
| 87 | #define MAX3107_LCR_REG (0x0b00) /* LCR */ | |
| 88 | #define MAX3107_RXTO_REG (0x0c00) /* RX timeout */ | |
| 89 | #define MAX3107_HDPIXDELAY_REG (0x0d00) /* Auto transceiver delays */ | |
| 90 | #define MAX3107_IRDA_REG (0x0e00) /* IRDA settings */ | |
| 91 | #define MAX3107_FLOWLVL_REG (0x0f00) /* Flow control levels */ | |
| 92 | #define MAX3107_FIFOTRIGLVL_REG (0x1000) /* FIFO IRQ trigger levels */ | |
| 93 | #define MAX3107_TXFIFOLVL_REG (0x1100) /* TX FIFO level */ | |
| 94 | #define MAX3107_RXFIFOLVL_REG (0x1200) /* RX FIFO level */ | |
| 95 | #define MAX3107_FLOWCTRL_REG (0x1300) /* Flow control */ | |
| 96 | #define MAX3107_XON1_REG (0x1400) /* XON1 character */ | |
| 97 | #define MAX3107_XON2_REG (0x1500) /* XON2 character */ | |
| 98 | #define MAX3107_XOFF1_REG (0x1600) /* XOFF1 character */ | |
| 99 | #define MAX3107_XOFF2_REG (0x1700) /* XOFF2 character */ | |
| 100 | #define MAX3107_GPIOCFG_REG (0x1800) /* GPIO config */ | |
| 101 | #define MAX3107_GPIODATA_REG (0x1900) /* GPIO data */ | |
| 102 | #define MAX3107_PLLCFG_REG (0x1a00) /* PLL config */ | |
| 103 | #define MAX3107_BRGCFG_REG (0x1b00) /* Baud rate generator conf */ | |
| 104 | #define MAX3107_BRGDIVLSB_REG (0x1c00) /* Baud rate divisor LSB */ | |
| 105 | #define MAX3107_BRGDIVMSB_REG (0x1d00) /* Baud rate divisor MSB */ | |
| 106 | #define MAX3107_CLKSRC_REG (0x1e00) /* Clock source */ | |
| 107 | #define MAX3107_REVID_REG (0x1f00) /* Revision identification */ | |
| 108 | ||
| 109 | /* IRQ register bits */ | |
| 110 | #define MAX3107_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ | |
| 111 | #define MAX3107_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ | |
| 112 | #define MAX3107_IRQ_STS_BIT (1 << 2) /* Status interrupt */ | |
| 113 | #define MAX3107_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ | |
| 114 | #define MAX3107_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ | |
| 115 | #define MAX3107_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ | |
| 116 | #define MAX3107_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ | |
| 117 | #define MAX3107_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ | |
| 118 | ||
| 119 | /* LSR register bits */ | |
| 120 | #define MAX3107_LSR_RXTO_BIT (1 << 0) /* RX timeout */ | |
| 121 | #define MAX3107_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ | |
| 122 | #define MAX3107_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ | |
| 123 | #define MAX3107_LSR_FRERR_BIT (1 << 3) /* Frame error */ | |
| 124 | #define MAX3107_LSR_RXBRK_BIT (1 << 4) /* RX break */ | |
| 125 | #define MAX3107_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ | |
| 126 | #define MAX3107_LSR_UNDEF6_BIT (1 << 6) /* Undefined/not used */ | |
| 127 | #define MAX3107_LSR_CTS_BIT (1 << 7) /* CTS pin state */ | |
| 128 | ||
| 129 | /* Special character register bits */ | |
| 130 | #define MAX3107_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ | |
| 131 | #define MAX3107_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ | |
| 132 | #define MAX3107_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ | |
| 133 | #define MAX3107_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ | |
| 134 | #define MAX3107_SPCHR_BREAK_BIT (1 << 4) /* RX break */ | |
| 135 | #define MAX3107_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ | |
| 136 | #define MAX3107_SPCHR_UNDEF6_BIT (1 << 6) /* Undefined/not used */ | |
| 137 | #define MAX3107_SPCHR_UNDEF7_BIT (1 << 7) /* Undefined/not used */ | |
| 138 | ||
| 139 | /* Status register bits */ | |
| 140 | #define MAX3107_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ | |
| 141 | #define MAX3107_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ | |
| 142 | #define MAX3107_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ | |
| 143 | #define MAX3107_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ | |
| 144 | #define MAX3107_STS_UNDEF4_BIT (1 << 4) /* Undefined/not used */ | |
| 145 | #define MAX3107_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ | |
| 146 | #define MAX3107_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ | |
| 147 | #define MAX3107_STS_UNDEF7_BIT (1 << 7) /* Undefined/not used */ | |
| 148 | ||
| 149 | /* MODE1 register bits */ | |
| 150 | #define MAX3107_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ | |
| 151 | #define MAX3107_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ | |
| 152 | #define MAX3107_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ | |
| 153 | #define MAX3107_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ | |
| 154 | #define MAX3107_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ | |
| 155 | #define MAX3107_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ | |
| 156 | #define MAX3107_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ | |
| 157 | #define MAX3107_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ | |
| 158 | ||
| 159 | /* MODE2 register bits */ | |
| 160 | #define MAX3107_MODE2_RST_BIT (1 << 0) /* Chip reset */ | |
| 161 | #define MAX3107_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ | |
| 162 | #define MAX3107_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ | |
| 163 | #define MAX3107_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ | |
| 164 | #define MAX3107_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ | |
| 165 | #define MAX3107_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ | |
| 166 | #define MAX3107_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ | |
| 167 | #define MAX3107_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ | |
| 168 | ||
| 169 | /* LCR register bits */ | |
| 170 | #define MAX3107_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ | |
| 171 | #define MAX3107_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 | |
| 172 | * | |
| 173 | * Word length bits table: | |
| 174 | * 00 -> 5 bit words | |
| 175 | * 01 -> 6 bit words | |
| 176 | * 10 -> 7 bit words | |
| 177 | * 11 -> 8 bit words | |
| 178 | */ | |
| 179 | #define MAX3107_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit | |
| 180 | * | |
| 181 | * STOP length bit table: | |
| 182 | * 0 -> 1 stop bit | |
| 183 | * 1 -> 1-1.5 stop bits if | |
| 184 | * word length is 5, | |
| 185 | * 2 stop bits otherwise | |
| 186 | */ | |
| 187 | #define MAX3107_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ | |
| 188 | #define MAX3107_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ | |
| 189 | #define MAX3107_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ | |
| 190 | #define MAX3107_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ | |
| 191 | #define MAX3107_LCR_RTS_BIT (1 << 7) /* RTS pin control */ | |
| 192 | #define MAX3107_LCR_WORD_LEN_5 (0x0000) | |
| 193 | #define MAX3107_LCR_WORD_LEN_6 (0x0001) | |
| 194 | #define MAX3107_LCR_WORD_LEN_7 (0x0002) | |
| 195 | #define MAX3107_LCR_WORD_LEN_8 (0x0003) | |
| 196 | ||
| 197 | ||
| 198 | /* IRDA register bits */ | |
| 199 | #define MAX3107_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ | |
| 200 | #define MAX3107_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ | |
| 201 | #define MAX3107_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */ | |
| 202 | #define MAX3107_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */ | |
| 203 | #define MAX3107_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */ | |
| 204 | #define MAX3107_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */ | |
| 205 | #define MAX3107_IRDA_UNDEF6_BIT (1 << 6) /* Undefined/not used */ | |
| 206 | #define MAX3107_IRDA_UNDEF7_BIT (1 << 7) /* Undefined/not used */ | |
| 207 | ||
| 208 | /* Flow control trigger level register masks */ | |
| 209 | #define MAX3107_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ | |
| 210 | #define MAX3107_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ | |
| 211 | #define MAX3107_FLOWLVL_HALT(words) ((words/8) & 0x000f) | |
| 212 | #define MAX3107_FLOWLVL_RES(words) (((words/8) & 0x000f) << 4) | |
| 213 | ||
| 214 | /* FIFO interrupt trigger level register masks */ | |
| 215 | #define MAX3107_FIFOTRIGLVL_TX_MASK (0x000f) /* TX FIFO trigger level */ | |
| 216 | #define MAX3107_FIFOTRIGLVL_RX_MASK (0x00f0) /* RX FIFO trigger level */ | |
| 217 | #define MAX3107_FIFOTRIGLVL_TX(words) ((words/8) & 0x000f) | |
| 218 | #define MAX3107_FIFOTRIGLVL_RX(words) (((words/8) & 0x000f) << 4) | |
| 219 | ||
| 220 | /* Flow control register bits */ | |
| 221 | #define MAX3107_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ | |
| 222 | #define MAX3107_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ | |
| 223 | #define MAX3107_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs | |
| 224 | * are used in conjunction with | |
| 225 | * XOFF2 for definition of | |
| 226 | * special character */ | |
| 227 | #define MAX3107_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ | |
| 228 | #define MAX3107_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ | |
| 229 | #define MAX3107_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 | |
| 230 | * | |
| 231 | * SWFLOW bits 1 & 0 table: | |
| 232 | * 00 -> no transmitter flow | |
| 233 | * control | |
| 234 | * 01 -> receiver compares | |
| 235 | * XON2 and XOFF2 | |
| 236 | * and controls | |
| 237 | * transmitter | |
| 238 | * 10 -> receiver compares | |
| 239 | * XON1 and XOFF1 | |
| 240 | * and controls | |
| 241 | * transmitter | |
| 242 | * 11 -> receiver compares | |
| 243 | * XON1, XON2, XOFF1 and | |
| 244 | * XOFF2 and controls | |
| 245 | * transmitter | |
| 246 | */ | |
| 247 | #define MAX3107_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ | |
| 248 | #define MAX3107_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 | |
| 249 | * | |
| 250 | * SWFLOW bits 3 & 2 table: | |
| 251 | * 00 -> no received flow | |
| 252 | * control | |
| 253 | * 01 -> transmitter generates | |
| 254 | * XON2 and XOFF2 | |
| 255 | * 10 -> transmitter generates | |
| 256 | * XON1 and XOFF1 | |
| 257 | * 11 -> transmitter generates | |
| 258 | * XON1, XON2, XOFF1 and | |
| 259 | * XOFF2 | |
| 260 | */ | |
| 261 | ||
| 262 | /* GPIO configuration register bits */ | |
| 263 | #define MAX3107_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */ | |
| 264 | #define MAX3107_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */ | |
| 265 | #define MAX3107_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */ | |
| 266 | #define MAX3107_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */ | |
| 267 | #define MAX3107_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */ | |
| 268 | #define MAX3107_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */ | |
| 269 | #define MAX3107_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */ | |
| 270 | #define MAX3107_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */ | |
| 271 | ||
| 272 | /* GPIO DATA register bits */ | |
| 273 | #define MAX3107_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */ | |
| 274 | #define MAX3107_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */ | |
| 275 | #define MAX3107_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */ | |
| 276 | #define MAX3107_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */ | |
| 277 | #define MAX3107_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */ | |
| 278 | #define MAX3107_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */ | |
| 279 | #define MAX3107_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */ | |
| 280 | #define MAX3107_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */ | |
| 281 | ||
| 282 | /* PLL configuration register masks */ | |
| 283 | #define MAX3107_PLLCFG_PREDIV_MASK (0x003f) /* PLL predivision value */ | |
| 284 | #define MAX3107_PLLCFG_PLLFACTOR_MASK (0x00c0) /* PLL multiplication factor */ | |
| 285 | ||
| 286 | /* Baud rate generator configuration register masks and bits */ | |
| 287 | #define MAX3107_BRGCFG_FRACT_MASK (0x000f) /* Fractional portion of | |
| 288 | * Baud rate generator divisor | |
| 289 | */ | |
| 290 | #define MAX3107_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ | |
| 291 | #define MAX3107_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ | |
| 292 | #define MAX3107_BRGCFG_UNDEF6_BIT (1 << 6) /* Undefined/not used */ | |
| 293 | #define MAX3107_BRGCFG_UNDEF7_BIT (1 << 7) /* Undefined/not used */ | |
| 294 | ||
| 295 | /* Clock source register bits */ | |
| 296 | #define MAX3107_CLKSRC_INTOSC_BIT (1 << 0) /* Internal osc enable */ | |
| 297 | #define MAX3107_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ | |
| 298 | #define MAX3107_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ | |
| 299 | #define MAX3107_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ | |
| 300 | #define MAX3107_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ | |
| 301 | #define MAX3107_CLKSRC_UNDEF5_BIT (1 << 5) /* Undefined/not used */ | |
| 302 | #define MAX3107_CLKSRC_UNDEF6_BIT (1 << 6) /* Undefined/not used */ | |
| 303 | #define MAX3107_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ | |
| 304 | ||
| 305 | ||
| 306 | /* HW definitions */ | |
| 307 | #define MAX3107_RX_FIFO_SIZE 128 | |
| 308 | #define MAX3107_TX_FIFO_SIZE 128 | |
| 309 | #define MAX3107_REVID1 0x00a0 | |
| 310 | #define MAX3107_REVID2 0x00a1 | |
| 311 | ||
| 312 | ||
| 313 | /* Baud rate generator configuration values for external clock 13MHz */ | |
| 314 | #define MAX3107_BRG13_B300 (0x0A9400 | 0x05) | |
| 315 | #define MAX3107_BRG13_B600 (0x054A00 | 0x03) | |
| 316 | #define MAX3107_BRG13_B1200 (0x02A500 | 0x01) | |
| 317 | #define MAX3107_BRG13_B2400 (0x015200 | 0x09) | |
| 318 | #define MAX3107_BRG13_B4800 (0x00A900 | 0x04) | |
| 319 | #define MAX3107_BRG13_B9600 (0x005400 | 0x0A) | |
| 320 | #define MAX3107_BRG13_B19200 (0x002A00 | 0x05) | |
| 321 | #define MAX3107_BRG13_B38400 (0x001500 | 0x03) | |
| 322 | #define MAX3107_BRG13_B57600 (0x000E00 | 0x02) | |
| 323 | #define MAX3107_BRG13_B115200 (0x000700 | 0x01) | |
| 324 | #define MAX3107_BRG13_B230400 (0x000300 | 0x08) | |
| 325 | #define MAX3107_BRG13_B460800 (0x000100 | 0x0c) | |
| 326 | #define MAX3107_BRG13_B921600 (0x000100 | 0x1c) | |
| 327 | ||
| 328 | /* Baud rate generator configuration values for external clock 26MHz */ | |
| 329 | #define MAX3107_BRG26_B300 (0x152800 | 0x0A) | |
| 330 | #define MAX3107_BRG26_B600 (0x0A9400 | 0x05) | |
| 331 | #define MAX3107_BRG26_B1200 (0x054A00 | 0x03) | |
| 332 | #define MAX3107_BRG26_B2400 (0x02A500 | 0x01) | |
| 333 | #define MAX3107_BRG26_B4800 (0x015200 | 0x09) | |
| 334 | #define MAX3107_BRG26_B9600 (0x00A900 | 0x04) | |
| 335 | #define MAX3107_BRG26_B19200 (0x005400 | 0x0A) | |
| 336 | #define MAX3107_BRG26_B38400 (0x002A00 | 0x05) | |
| 337 | #define MAX3107_BRG26_B57600 (0x001C00 | 0x03) | |
| 338 | #define MAX3107_BRG26_B115200 (0x000E00 | 0x02) | |
| 339 | #define MAX3107_BRG26_B230400 (0x000700 | 0x01) | |
| 340 | #define MAX3107_BRG26_B460800 (0x000300 | 0x08) | |
| 341 | #define MAX3107_BRG26_B921600 (0x000100 | 0x0C) | |
| 342 | ||
| 343 | /* Baud rate generator configuration values for internal clock */ | |
| 344 | #define MAX3107_BRG13_IB300 (0x008000 | 0x00) | |
| 345 | #define MAX3107_BRG13_IB600 (0x004000 | 0x00) | |
| 346 | #define MAX3107_BRG13_IB1200 (0x002000 | 0x00) | |
| 347 | #define MAX3107_BRG13_IB2400 (0x001000 | 0x00) | |
| 348 | #define MAX3107_BRG13_IB4800 (0x000800 | 0x00) | |
| 349 | #define MAX3107_BRG13_IB9600 (0x000400 | 0x00) | |
| 350 | #define MAX3107_BRG13_IB19200 (0x000200 | 0x00) | |
| 351 | #define MAX3107_BRG13_IB38400 (0x000100 | 0x00) | |
| 352 | #define MAX3107_BRG13_IB57600 (0x000000 | 0x0B) | |
| 353 | #define MAX3107_BRG13_IB115200 (0x000000 | 0x05) | |
| 354 | #define MAX3107_BRG13_IB230400 (0x000000 | 0x03) | |
| 355 | #define MAX3107_BRG13_IB460800 (0x000000 | 0x00) | |
| 356 | #define MAX3107_BRG13_IB921600 (0x000000 | 0x00) | |
| 357 | ||
| 61fd1526 AC |
358 | |
| 359 | struct baud_table { | |
| 360 | int baud; | |
| 361 | u32 new_brg; | |
| 362 | }; | |
| 363 | ||
| 364 | struct max3107_port { | |
| 365 | /* UART port structure */ | |
| 366 | struct uart_port port; | |
| 367 | ||
| 368 | /* SPI device structure */ | |
| 369 | struct spi_device *spi; | |
| 370 | ||
| e38018be | 371 | #if defined(CONFIG_GPIOLIB) |
| 61fd1526 AC |
372 | /* GPIO chip stucture */ |
| 373 | struct gpio_chip chip; | |
| e38018be | 374 | #endif |
| 61fd1526 AC |
375 | |
| 376 | /* Workqueue that does all the magic */ | |
| 377 | struct workqueue_struct *workqueue; | |
| 378 | struct work_struct work; | |
| 379 | ||
| 380 | /* Lock for shared data */ | |
| 381 | spinlock_t data_lock; | |
| 382 | ||
| 383 | /* Device configuration */ | |
| 384 | int ext_clk; /* 1 if external clock used */ | |
| 385 | int loopback; /* Current loopback mode state */ | |
| 386 | int baud; /* Current baud rate */ | |
| 387 | ||
| 388 | /* State flags */ | |
| 389 | int suspended; /* Indicates suspend mode */ | |
| 390 | int tx_fifo_empty; /* Flag for TX FIFO state */ | |
| 391 | int rx_enabled; /* Flag for receiver state */ | |
| 392 | int tx_enabled; /* Flag for transmitter state */ | |
| 393 | ||
| 394 | u16 irqen_reg; /* Current IRQ enable register value */ | |
| 395 | /* Shared data */ | |
| 396 | u16 mode1_reg; /* Current mode1 register value*/ | |
| 397 | int mode1_commit; /* Flag for setting new mode1 register value */ | |
| 398 | u16 lcr_reg; /* Current LCR register value */ | |
| 399 | int lcr_commit; /* Flag for setting new LCR register value */ | |
| 400 | u32 brg_cfg; /* Current Baud rate generator config */ | |
| 401 | int brg_commit; /* Flag for setting new baud rate generator | |
| 402 | * config | |
| 403 | */ | |
| 404 | struct baud_table *baud_tbl; | |
| 405 | int handle_irq; /* Indicates that IRQ should be handled */ | |
| 406 | ||
| 407 | /* Rx buffer and str*/ | |
| 408 | u16 *rxbuf; | |
| 409 | u8 *rxstr; | |
| 410 | /* Tx buffer*/ | |
| 411 | u16 *txbuf; | |
| 412 | ||
| 413 | struct max3107_plat *pdata; /* Platform data */ | |
| 414 | }; | |
| 415 | ||
| 416 | /* Platform data structure */ | |
| 417 | struct max3107_plat { | |
| 418 | /* Loopback mode enable */ | |
| 419 | int loopback; | |
| 420 | /* External clock enable */ | |
| 421 | int ext_clk; | |
| 422 | /* Called during the register initialisation */ | |
| 423 | void (*init)(struct max3107_port *s); | |
| 424 | /* Called when the port is found and configured */ | |
| 425 | int (*configure)(struct max3107_port *s); | |
| 426 | /* HW suspend function */ | |
| 427 | void (*hw_suspend) (struct max3107_port *s, int suspend); | |
| 428 | /* Polling mode enable */ | |
| 429 | int polled_mode; | |
| 430 | /* Polling period if polling mode enabled */ | |
| 431 | int poll_time; | |
| 432 | }; | |
| 433 | ||
| 434 | extern int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len); | |
| 435 | extern void max3107_hw_susp(struct max3107_port *s, int suspend); | |
| 436 | extern int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata); | |
| 437 | extern int max3107_remove(struct spi_device *spi); | |
| 438 | extern int max3107_suspend(struct spi_device *spi, pm_message_t state); | |
| 439 | extern int max3107_resume(struct spi_device *spi); | |
| 440 | ||
| 44318feb | 441 | #endif /* _LINUX_SERIAL_MAX3107_H */ |