Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. |
3 | * | |
4 | * FIXME According to the usermanual the status bits in the status register | |
5 | * are only updated when the peripherals access the FIFO and not when the | |
6 | * CPU access them. So since we use this bits to know when we stop writing | |
7 | * and reading, they may not be updated in-time and a race condition may | |
8 | * exists. But I haven't be able to prove this and I don't care. But if | |
9 | * any problem arises, it might worth checking. The TX/RX FIFO Stats | |
10 | * registers should be used in addition. | |
11 | * Update: Actually, they seem updated ... At least the bits we use. | |
12 | * | |
13 | * | |
14 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | |
9b9129e7 | 15 | * |
1da177e4 LT |
16 | * Some of the code has been inspired/copied from the 2.4 code written |
17 | * by Dale Farnsworth <dfarnsworth@mvista.com>. | |
9b9129e7 | 18 | * |
25ae3a07 JR |
19 | * Copyright (C) 2008 Freescale Semiconductor Inc. |
20 | * John Rigby <jrigby@gmail.com> | |
21 | * Added support for MPC5121 | |
b9272dfd GL |
22 | * Copyright (C) 2006 Secret Lab Technologies Ltd. |
23 | * Grant Likely <grant.likely@secretlab.ca> | |
24 | * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> | |
1da177e4 | 25 | * Copyright (C) 2003 MontaVista, Software, Inc. |
9b9129e7 | 26 | * |
1da177e4 LT |
27 | * This file is licensed under the terms of the GNU General Public License |
28 | * version 2. This program is licensed "as is" without any warranty of any | |
29 | * kind, whether express or implied. | |
30 | */ | |
9b9129e7 | 31 | |
b9272dfd GL |
32 | #undef DEBUG |
33 | ||
34 | #include <linux/device.h> | |
1da177e4 LT |
35 | #include <linux/module.h> |
36 | #include <linux/tty.h> | |
ee160a38 | 37 | #include <linux/tty_flip.h> |
1da177e4 LT |
38 | #include <linux/serial.h> |
39 | #include <linux/sysrq.h> | |
40 | #include <linux/console.h> | |
406b7d4f JR |
41 | #include <linux/delay.h> |
42 | #include <linux/io.h> | |
283029d1 GL |
43 | #include <linux/of.h> |
44 | #include <linux/of_platform.h> | |
6acc6833 | 45 | #include <linux/clk.h> |
b9272dfd | 46 | |
1da177e4 LT |
47 | #include <asm/mpc52xx.h> |
48 | #include <asm/mpc52xx_psc.h> | |
49 | ||
50 | #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
51 | #define SUPPORT_SYSRQ | |
52 | #endif | |
53 | ||
54 | #include <linux/serial_core.h> | |
55 | ||
56 | ||
d62de3aa SM |
57 | /* We've been assigned a range on the "Low-density serial ports" major */ |
58 | #define SERIAL_PSC_MAJOR 204 | |
59 | #define SERIAL_PSC_MINOR 148 | |
60 | ||
1da177e4 LT |
61 | |
62 | #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ | |
63 | ||
64 | ||
65 | static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; | |
66 | /* Rem: - We use the read_status_mask as a shadow of | |
67 | * psc->mpc52xx_psc_imr | |
68 | * - It's important that is array is all zero on start as we | |
69 | * use it to know if it's initialized or not ! If it's not sure | |
70 | * it's cleared, then a memset(...,0,...) should be added to | |
71 | * the console_init | |
72 | */ | |
8d1fb8cb | 73 | |
b9272dfd GL |
74 | /* lookup table for matching device nodes to index numbers */ |
75 | static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; | |
76 | ||
77 | static void mpc52xx_uart_of_enumerate(void); | |
1da177e4 | 78 | |
599f030c | 79 | |
1da177e4 LT |
80 | #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) |
81 | ||
82 | ||
83 | /* Forward declaration of the interruption handling routine */ | |
406b7d4f | 84 | static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); |
6acc6833 | 85 | static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port); |
1da177e4 LT |
86 | |
87 | ||
88 | /* Simple macro to test if a port is console or not. This one is taken | |
89 | * for serial_core.c and maybe should be moved to serial_core.h ? */ | |
90 | #ifdef CONFIG_SERIAL_CORE_CONSOLE | |
406b7d4f JR |
91 | #define uart_console(port) \ |
92 | ((port)->cons && (port)->cons->index == (port)->line) | |
1da177e4 LT |
93 | #else |
94 | #define uart_console(port) (0) | |
95 | #endif | |
96 | ||
599f030c JR |
97 | /* ======================================================================== */ |
98 | /* PSC fifo operations for isolating differences between 52xx and 512x */ | |
99 | /* ======================================================================== */ | |
100 | ||
101 | struct psc_ops { | |
102 | void (*fifo_init)(struct uart_port *port); | |
103 | int (*raw_rx_rdy)(struct uart_port *port); | |
104 | int (*raw_tx_rdy)(struct uart_port *port); | |
105 | int (*rx_rdy)(struct uart_port *port); | |
106 | int (*tx_rdy)(struct uart_port *port); | |
107 | int (*tx_empty)(struct uart_port *port); | |
108 | void (*stop_rx)(struct uart_port *port); | |
109 | void (*start_tx)(struct uart_port *port); | |
110 | void (*stop_tx)(struct uart_port *port); | |
111 | void (*rx_clr_irq)(struct uart_port *port); | |
112 | void (*tx_clr_irq)(struct uart_port *port); | |
113 | void (*write_char)(struct uart_port *port, unsigned char c); | |
114 | unsigned char (*read_char)(struct uart_port *port); | |
115 | void (*cw_disable_ints)(struct uart_port *port); | |
116 | void (*cw_restore_ints)(struct uart_port *port); | |
0d1f22e4 AD |
117 | unsigned int (*set_baudrate)(struct uart_port *port, |
118 | struct ktermios *new, | |
119 | struct ktermios *old); | |
6acc6833 AG |
120 | int (*clock)(struct uart_port *port, int enable); |
121 | int (*fifoc_init)(void); | |
122 | void (*fifoc_uninit)(void); | |
123 | void (*get_irq)(struct uart_port *, struct device_node *); | |
124 | irqreturn_t (*handle_irq)(struct uart_port *port); | |
599f030c JR |
125 | }; |
126 | ||
0d1f22e4 AD |
127 | /* setting the prescaler and divisor reg is common for all chips */ |
128 | static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, | |
129 | u16 prescaler, unsigned int divisor) | |
130 | { | |
131 | /* select prescaler */ | |
132 | out_be16(&psc->mpc52xx_psc_clock_select, prescaler); | |
133 | out_8(&psc->ctur, divisor >> 8); | |
134 | out_8(&psc->ctlr, divisor & 0xff); | |
135 | } | |
136 | ||
25ae3a07 | 137 | #ifdef CONFIG_PPC_MPC52xx |
599f030c JR |
138 | #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) |
139 | static void mpc52xx_psc_fifo_init(struct uart_port *port) | |
140 | { | |
141 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
142 | struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); | |
143 | ||
599f030c JR |
144 | out_8(&fifo->rfcntl, 0x00); |
145 | out_be16(&fifo->rfalarm, 0x1ff); | |
146 | out_8(&fifo->tfcntl, 0x07); | |
147 | out_be16(&fifo->tfalarm, 0x80); | |
148 | ||
149 | port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; | |
150 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
151 | } | |
152 | ||
153 | static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) | |
154 | { | |
155 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
156 | & MPC52xx_PSC_SR_RXRDY; | |
157 | } | |
158 | ||
159 | static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) | |
160 | { | |
161 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
162 | & MPC52xx_PSC_SR_TXRDY; | |
163 | } | |
164 | ||
165 | ||
166 | static int mpc52xx_psc_rx_rdy(struct uart_port *port) | |
167 | { | |
168 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
169 | & port->read_status_mask | |
170 | & MPC52xx_PSC_IMR_RXRDY; | |
171 | } | |
172 | ||
173 | static int mpc52xx_psc_tx_rdy(struct uart_port *port) | |
174 | { | |
175 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
176 | & port->read_status_mask | |
177 | & MPC52xx_PSC_IMR_TXRDY; | |
178 | } | |
179 | ||
180 | static int mpc52xx_psc_tx_empty(struct uart_port *port) | |
181 | { | |
182 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
183 | & MPC52xx_PSC_SR_TXEMP; | |
184 | } | |
185 | ||
186 | static void mpc52xx_psc_start_tx(struct uart_port *port) | |
187 | { | |
188 | port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; | |
189 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
190 | } | |
191 | ||
192 | static void mpc52xx_psc_stop_tx(struct uart_port *port) | |
193 | { | |
194 | port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; | |
195 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
196 | } | |
197 | ||
198 | static void mpc52xx_psc_stop_rx(struct uart_port *port) | |
199 | { | |
200 | port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; | |
201 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
202 | } | |
203 | ||
204 | static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) | |
205 | { | |
206 | } | |
207 | ||
208 | static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) | |
209 | { | |
210 | } | |
211 | ||
212 | static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) | |
213 | { | |
214 | out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); | |
215 | } | |
216 | ||
217 | static unsigned char mpc52xx_psc_read_char(struct uart_port *port) | |
218 | { | |
219 | return in_8(&PSC(port)->mpc52xx_psc_buffer_8); | |
220 | } | |
221 | ||
222 | static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) | |
223 | { | |
224 | out_be16(&PSC(port)->mpc52xx_psc_imr, 0); | |
225 | } | |
226 | ||
227 | static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) | |
228 | { | |
229 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
230 | } | |
231 | ||
0d1f22e4 AD |
232 | static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port, |
233 | struct ktermios *new, | |
234 | struct ktermios *old) | |
599f030c | 235 | { |
0d1f22e4 AD |
236 | unsigned int baud; |
237 | unsigned int divisor; | |
238 | ||
239 | /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */ | |
240 | baud = uart_get_baud_rate(port, new, old, | |
241 | port->uartclk / (32 * 0xffff) + 1, | |
242 | port->uartclk / 32); | |
243 | divisor = (port->uartclk + 16 * baud) / (32 * baud); | |
244 | ||
245 | /* enable the /32 prescaler and set the divisor */ | |
246 | mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); | |
247 | return baud; | |
248 | } | |
249 | ||
250 | static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port, | |
251 | struct ktermios *new, | |
252 | struct ktermios *old) | |
253 | { | |
254 | unsigned int baud; | |
255 | unsigned int divisor; | |
256 | u16 prescaler; | |
257 | ||
258 | /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the | |
259 | * ipb freq */ | |
260 | baud = uart_get_baud_rate(port, new, old, | |
261 | port->uartclk / (32 * 0xffff) + 1, | |
262 | port->uartclk / 4); | |
263 | divisor = (port->uartclk + 2 * baud) / (4 * baud); | |
264 | ||
e0955ace FB |
265 | /* select the proper prescaler and set the divisor |
266 | * prefer high prescaler for more tolerance on low baudrates */ | |
267 | if (divisor > 0xffff || baud <= 115200) { | |
0d1f22e4 AD |
268 | divisor = (divisor + 4) / 8; |
269 | prescaler = 0xdd00; /* /32 */ | |
270 | } else | |
271 | prescaler = 0xff00; /* /4 */ | |
272 | mpc52xx_set_divisor(PSC(port), prescaler, divisor); | |
273 | return baud; | |
599f030c JR |
274 | } |
275 | ||
6acc6833 AG |
276 | static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) |
277 | { | |
9cfb5c05 | 278 | port->irqflags = 0; |
6acc6833 AG |
279 | port->irq = irq_of_parse_and_map(np, 0); |
280 | } | |
281 | ||
282 | /* 52xx specific interrupt handler. The caller holds the port lock */ | |
283 | static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port) | |
284 | { | |
285 | return mpc5xxx_uart_process_int(port); | |
286 | } | |
287 | ||
599f030c JR |
288 | static struct psc_ops mpc52xx_psc_ops = { |
289 | .fifo_init = mpc52xx_psc_fifo_init, | |
290 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, | |
291 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, | |
292 | .rx_rdy = mpc52xx_psc_rx_rdy, | |
293 | .tx_rdy = mpc52xx_psc_tx_rdy, | |
294 | .tx_empty = mpc52xx_psc_tx_empty, | |
295 | .stop_rx = mpc52xx_psc_stop_rx, | |
296 | .start_tx = mpc52xx_psc_start_tx, | |
297 | .stop_tx = mpc52xx_psc_stop_tx, | |
298 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, | |
299 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, | |
300 | .write_char = mpc52xx_psc_write_char, | |
301 | .read_char = mpc52xx_psc_read_char, | |
302 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, | |
303 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, | |
0d1f22e4 AD |
304 | .set_baudrate = mpc5200_psc_set_baudrate, |
305 | .get_irq = mpc52xx_psc_get_irq, | |
306 | .handle_irq = mpc52xx_psc_handle_irq, | |
307 | }; | |
308 | ||
309 | static struct psc_ops mpc5200b_psc_ops = { | |
310 | .fifo_init = mpc52xx_psc_fifo_init, | |
311 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, | |
312 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, | |
313 | .rx_rdy = mpc52xx_psc_rx_rdy, | |
314 | .tx_rdy = mpc52xx_psc_tx_rdy, | |
315 | .tx_empty = mpc52xx_psc_tx_empty, | |
316 | .stop_rx = mpc52xx_psc_stop_rx, | |
317 | .start_tx = mpc52xx_psc_start_tx, | |
318 | .stop_tx = mpc52xx_psc_stop_tx, | |
319 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, | |
320 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, | |
321 | .write_char = mpc52xx_psc_write_char, | |
322 | .read_char = mpc52xx_psc_read_char, | |
323 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, | |
324 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, | |
325 | .set_baudrate = mpc5200b_psc_set_baudrate, | |
6acc6833 AG |
326 | .get_irq = mpc52xx_psc_get_irq, |
327 | .handle_irq = mpc52xx_psc_handle_irq, | |
599f030c JR |
328 | }; |
329 | ||
25ae3a07 JR |
330 | #endif /* CONFIG_MPC52xx */ |
331 | ||
332 | #ifdef CONFIG_PPC_MPC512x | |
333 | #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) | |
6acc6833 AG |
334 | |
335 | /* PSC FIFO Controller for mpc512x */ | |
336 | struct psc_fifoc { | |
337 | u32 fifoc_cmd; | |
338 | u32 fifoc_int; | |
339 | u32 fifoc_dma; | |
340 | u32 fifoc_axe; | |
341 | u32 fifoc_debug; | |
342 | }; | |
343 | ||
344 | static struct psc_fifoc __iomem *psc_fifoc; | |
345 | static unsigned int psc_fifoc_irq; | |
346 | ||
25ae3a07 JR |
347 | static void mpc512x_psc_fifo_init(struct uart_port *port) |
348 | { | |
6acc6833 AG |
349 | /* /32 prescaler */ |
350 | out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); | |
351 | ||
25ae3a07 JR |
352 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); |
353 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
354 | out_be32(&FIFO_512x(port)->txalarm, 1); | |
355 | out_be32(&FIFO_512x(port)->tximr, 0); | |
356 | ||
357 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); | |
358 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
359 | out_be32(&FIFO_512x(port)->rxalarm, 1); | |
360 | out_be32(&FIFO_512x(port)->rximr, 0); | |
361 | ||
362 | out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); | |
363 | out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); | |
364 | } | |
365 | ||
366 | static int mpc512x_psc_raw_rx_rdy(struct uart_port *port) | |
367 | { | |
368 | return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); | |
369 | } | |
370 | ||
371 | static int mpc512x_psc_raw_tx_rdy(struct uart_port *port) | |
372 | { | |
373 | return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); | |
374 | } | |
375 | ||
376 | static int mpc512x_psc_rx_rdy(struct uart_port *port) | |
377 | { | |
378 | return in_be32(&FIFO_512x(port)->rxsr) | |
379 | & in_be32(&FIFO_512x(port)->rximr) | |
380 | & MPC512x_PSC_FIFO_ALARM; | |
381 | } | |
382 | ||
383 | static int mpc512x_psc_tx_rdy(struct uart_port *port) | |
384 | { | |
385 | return in_be32(&FIFO_512x(port)->txsr) | |
386 | & in_be32(&FIFO_512x(port)->tximr) | |
387 | & MPC512x_PSC_FIFO_ALARM; | |
388 | } | |
389 | ||
390 | static int mpc512x_psc_tx_empty(struct uart_port *port) | |
391 | { | |
392 | return in_be32(&FIFO_512x(port)->txsr) | |
393 | & MPC512x_PSC_FIFO_EMPTY; | |
394 | } | |
395 | ||
396 | static void mpc512x_psc_stop_rx(struct uart_port *port) | |
397 | { | |
398 | unsigned long rx_fifo_imr; | |
399 | ||
400 | rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); | |
401 | rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
402 | out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); | |
403 | } | |
404 | ||
405 | static void mpc512x_psc_start_tx(struct uart_port *port) | |
406 | { | |
407 | unsigned long tx_fifo_imr; | |
408 | ||
409 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
410 | tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; | |
411 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
412 | } | |
413 | ||
414 | static void mpc512x_psc_stop_tx(struct uart_port *port) | |
415 | { | |
416 | unsigned long tx_fifo_imr; | |
417 | ||
418 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
419 | tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
420 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
421 | } | |
422 | ||
423 | static void mpc512x_psc_rx_clr_irq(struct uart_port *port) | |
424 | { | |
425 | out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); | |
426 | } | |
427 | ||
428 | static void mpc512x_psc_tx_clr_irq(struct uart_port *port) | |
429 | { | |
430 | out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); | |
431 | } | |
432 | ||
433 | static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) | |
434 | { | |
435 | out_8(&FIFO_512x(port)->txdata_8, c); | |
436 | } | |
437 | ||
438 | static unsigned char mpc512x_psc_read_char(struct uart_port *port) | |
439 | { | |
440 | return in_8(&FIFO_512x(port)->rxdata_8); | |
441 | } | |
442 | ||
443 | static void mpc512x_psc_cw_disable_ints(struct uart_port *port) | |
444 | { | |
445 | port->read_status_mask = | |
446 | in_be32(&FIFO_512x(port)->tximr) << 16 | | |
447 | in_be32(&FIFO_512x(port)->rximr); | |
448 | out_be32(&FIFO_512x(port)->tximr, 0); | |
449 | out_be32(&FIFO_512x(port)->rximr, 0); | |
450 | } | |
451 | ||
452 | static void mpc512x_psc_cw_restore_ints(struct uart_port *port) | |
453 | { | |
454 | out_be32(&FIFO_512x(port)->tximr, | |
455 | (port->read_status_mask >> 16) & 0x7f); | |
456 | out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); | |
457 | } | |
458 | ||
0d1f22e4 AD |
459 | static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port, |
460 | struct ktermios *new, | |
461 | struct ktermios *old) | |
25ae3a07 | 462 | { |
0d1f22e4 AD |
463 | unsigned int baud; |
464 | unsigned int divisor; | |
465 | ||
466 | /* | |
467 | * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on | |
468 | * pg. 30-10 that the chip supports a /32 and a /10 prescaler. | |
469 | * Furthermore, it states that "After reset, the prescaler by 10 | |
470 | * for the UART mode is selected", but the reset register value is | |
471 | * 0x0000 which means a /32 prescaler. This is wrong. | |
472 | * | |
473 | * In reality using /32 prescaler doesn't work, as it is not supported! | |
474 | * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide", | |
475 | * Chapter 4.1 PSC in UART Mode. | |
476 | * Calculate with a /16 prescaler here. | |
477 | */ | |
478 | ||
479 | /* uartclk contains the ips freq */ | |
480 | baud = uart_get_baud_rate(port, new, old, | |
481 | port->uartclk / (16 * 0xffff) + 1, | |
482 | port->uartclk / 16); | |
483 | divisor = (port->uartclk + 8 * baud) / (16 * baud); | |
484 | ||
485 | /* enable the /16 prescaler and set the divisor */ | |
486 | mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); | |
487 | return baud; | |
25ae3a07 JR |
488 | } |
489 | ||
6acc6833 AG |
490 | /* Init PSC FIFO Controller */ |
491 | static int __init mpc512x_psc_fifoc_init(void) | |
492 | { | |
493 | struct device_node *np; | |
6acc6833 AG |
494 | |
495 | np = of_find_compatible_node(NULL, NULL, | |
496 | "fsl,mpc5121-psc-fifo"); | |
497 | if (!np) { | |
498 | pr_err("%s: Can't find FIFOC node\n", __func__); | |
499 | return -ENODEV; | |
500 | } | |
501 | ||
502 | psc_fifoc = of_iomap(np, 0); | |
503 | if (!psc_fifoc) { | |
504 | pr_err("%s: Can't map FIFOC\n", __func__); | |
05f25abc | 505 | of_node_put(np); |
6acc6833 AG |
506 | return -ENODEV; |
507 | } | |
508 | ||
509 | psc_fifoc_irq = irq_of_parse_and_map(np, 0); | |
510 | of_node_put(np); | |
d4e33fac | 511 | if (psc_fifoc_irq == 0) { |
6acc6833 AG |
512 | pr_err("%s: Can't get FIFOC irq\n", __func__); |
513 | iounmap(psc_fifoc); | |
514 | return -ENODEV; | |
515 | } | |
516 | ||
6acc6833 AG |
517 | return 0; |
518 | } | |
519 | ||
520 | static void __exit mpc512x_psc_fifoc_uninit(void) | |
521 | { | |
522 | iounmap(psc_fifoc); | |
523 | } | |
524 | ||
525 | /* 512x specific interrupt handler. The caller holds the port lock */ | |
526 | static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port) | |
527 | { | |
528 | unsigned long fifoc_int; | |
529 | int psc_num; | |
530 | ||
531 | /* Read pending PSC FIFOC interrupts */ | |
532 | fifoc_int = in_be32(&psc_fifoc->fifoc_int); | |
533 | ||
534 | /* Check if it is an interrupt for this port */ | |
535 | psc_num = (port->mapbase & 0xf00) >> 8; | |
536 | if (test_bit(psc_num, &fifoc_int) || | |
537 | test_bit(psc_num + 16, &fifoc_int)) | |
538 | return mpc5xxx_uart_process_int(port); | |
539 | ||
540 | return IRQ_NONE; | |
541 | } | |
542 | ||
543 | static int mpc512x_psc_clock(struct uart_port *port, int enable) | |
544 | { | |
545 | struct clk *psc_clk; | |
546 | int psc_num; | |
547 | char clk_name[10]; | |
548 | ||
549 | if (uart_console(port)) | |
550 | return 0; | |
551 | ||
552 | psc_num = (port->mapbase & 0xf00) >> 8; | |
553 | snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num); | |
554 | psc_clk = clk_get(port->dev, clk_name); | |
555 | if (IS_ERR(psc_clk)) { | |
556 | dev_err(port->dev, "Failed to get PSC clock entry!\n"); | |
557 | return -ENODEV; | |
558 | } | |
559 | ||
560 | dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis"); | |
561 | ||
562 | if (enable) | |
563 | clk_enable(psc_clk); | |
564 | else | |
565 | clk_disable(psc_clk); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) | |
571 | { | |
572 | port->irqflags = IRQF_SHARED; | |
573 | port->irq = psc_fifoc_irq; | |
574 | } | |
575 | ||
25ae3a07 JR |
576 | static struct psc_ops mpc512x_psc_ops = { |
577 | .fifo_init = mpc512x_psc_fifo_init, | |
578 | .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, | |
579 | .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, | |
580 | .rx_rdy = mpc512x_psc_rx_rdy, | |
581 | .tx_rdy = mpc512x_psc_tx_rdy, | |
582 | .tx_empty = mpc512x_psc_tx_empty, | |
583 | .stop_rx = mpc512x_psc_stop_rx, | |
584 | .start_tx = mpc512x_psc_start_tx, | |
585 | .stop_tx = mpc512x_psc_stop_tx, | |
586 | .rx_clr_irq = mpc512x_psc_rx_clr_irq, | |
587 | .tx_clr_irq = mpc512x_psc_tx_clr_irq, | |
588 | .write_char = mpc512x_psc_write_char, | |
589 | .read_char = mpc512x_psc_read_char, | |
590 | .cw_disable_ints = mpc512x_psc_cw_disable_ints, | |
591 | .cw_restore_ints = mpc512x_psc_cw_restore_ints, | |
0d1f22e4 | 592 | .set_baudrate = mpc512x_psc_set_baudrate, |
6acc6833 AG |
593 | .clock = mpc512x_psc_clock, |
594 | .fifoc_init = mpc512x_psc_fifoc_init, | |
595 | .fifoc_uninit = mpc512x_psc_fifoc_uninit, | |
596 | .get_irq = mpc512x_psc_get_irq, | |
597 | .handle_irq = mpc512x_psc_handle_irq, | |
25ae3a07 JR |
598 | }; |
599 | #endif | |
600 | ||
601 | static struct psc_ops *psc_ops; | |
1da177e4 LT |
602 | |
603 | /* ======================================================================== */ | |
604 | /* UART operations */ | |
605 | /* ======================================================================== */ | |
606 | ||
9b9129e7 | 607 | static unsigned int |
1da177e4 LT |
608 | mpc52xx_uart_tx_empty(struct uart_port *port) |
609 | { | |
599f030c | 610 | return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; |
1da177e4 LT |
611 | } |
612 | ||
9b9129e7 | 613 | static void |
1da177e4 LT |
614 | mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
615 | { | |
aec739e0 WS |
616 | if (mctrl & TIOCM_RTS) |
617 | out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); | |
618 | else | |
619 | out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); | |
1da177e4 LT |
620 | } |
621 | ||
9b9129e7 | 622 | static unsigned int |
1da177e4 LT |
623 | mpc52xx_uart_get_mctrl(struct uart_port *port) |
624 | { | |
aec739e0 WS |
625 | unsigned int ret = TIOCM_DSR; |
626 | u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr); | |
627 | ||
628 | if (!(status & MPC52xx_PSC_CTS)) | |
629 | ret |= TIOCM_CTS; | |
630 | if (!(status & MPC52xx_PSC_DCD)) | |
631 | ret |= TIOCM_CAR; | |
632 | ||
633 | return ret; | |
1da177e4 LT |
634 | } |
635 | ||
9b9129e7 | 636 | static void |
b129a8cc | 637 | mpc52xx_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
638 | { |
639 | /* port->lock taken by caller */ | |
599f030c | 640 | psc_ops->stop_tx(port); |
1da177e4 LT |
641 | } |
642 | ||
9b9129e7 | 643 | static void |
b129a8cc | 644 | mpc52xx_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
645 | { |
646 | /* port->lock taken by caller */ | |
599f030c | 647 | psc_ops->start_tx(port); |
1da177e4 LT |
648 | } |
649 | ||
9b9129e7 | 650 | static void |
1da177e4 LT |
651 | mpc52xx_uart_send_xchar(struct uart_port *port, char ch) |
652 | { | |
653 | unsigned long flags; | |
654 | spin_lock_irqsave(&port->lock, flags); | |
9b9129e7 | 655 | |
1da177e4 LT |
656 | port->x_char = ch; |
657 | if (ch) { | |
658 | /* Make sure tx interrupts are on */ | |
659 | /* Truly necessary ??? They should be anyway */ | |
599f030c | 660 | psc_ops->start_tx(port); |
1da177e4 | 661 | } |
9b9129e7 | 662 | |
1da177e4 LT |
663 | spin_unlock_irqrestore(&port->lock, flags); |
664 | } | |
665 | ||
666 | static void | |
667 | mpc52xx_uart_stop_rx(struct uart_port *port) | |
668 | { | |
669 | /* port->lock taken by caller */ | |
599f030c | 670 | psc_ops->stop_rx(port); |
1da177e4 LT |
671 | } |
672 | ||
673 | static void | |
674 | mpc52xx_uart_enable_ms(struct uart_port *port) | |
675 | { | |
aec739e0 WS |
676 | struct mpc52xx_psc __iomem *psc = PSC(port); |
677 | ||
678 | /* clear D_*-bits by reading them */ | |
679 | in_8(&psc->mpc52xx_psc_ipcr); | |
680 | /* enable CTS and DCD as IPC interrupts */ | |
681 | out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); | |
682 | ||
683 | port->read_status_mask |= MPC52xx_PSC_IMR_IPC; | |
684 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
1da177e4 LT |
685 | } |
686 | ||
687 | static void | |
688 | mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) | |
689 | { | |
690 | unsigned long flags; | |
691 | spin_lock_irqsave(&port->lock, flags); | |
692 | ||
406b7d4f JR |
693 | if (ctl == -1) |
694 | out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK); | |
1da177e4 | 695 | else |
406b7d4f | 696 | out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK); |
9b9129e7 | 697 | |
1da177e4 LT |
698 | spin_unlock_irqrestore(&port->lock, flags); |
699 | } | |
700 | ||
701 | static int | |
702 | mpc52xx_uart_startup(struct uart_port *port) | |
703 | { | |
704 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
705 | int ret; | |
706 | ||
6acc6833 AG |
707 | if (psc_ops->clock) { |
708 | ret = psc_ops->clock(port, 1); | |
709 | if (ret) | |
710 | return ret; | |
711 | } | |
712 | ||
1da177e4 LT |
713 | /* Request IRQ */ |
714 | ret = request_irq(port->irq, mpc52xx_uart_int, | |
6acc6833 | 715 | port->irqflags, "mpc52xx_psc_uart", port); |
1da177e4 LT |
716 | if (ret) |
717 | return ret; | |
718 | ||
719 | /* Reset/activate the port, clear and enable interrupts */ | |
406b7d4f JR |
720 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
721 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
9b9129e7 | 722 | |
406b7d4f | 723 | out_be32(&psc->sicr, 0); /* UART mode DCD ignored */ |
1da177e4 | 724 | |
599f030c | 725 | psc_ops->fifo_init(port); |
9b9129e7 | 726 | |
406b7d4f JR |
727 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE); |
728 | out_8(&psc->command, MPC52xx_PSC_RX_ENABLE); | |
9b9129e7 | 729 | |
1da177e4 LT |
730 | return 0; |
731 | } | |
732 | ||
733 | static void | |
734 | mpc52xx_uart_shutdown(struct uart_port *port) | |
735 | { | |
736 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
9b9129e7 | 737 | |
a3481197 | 738 | /* Shut down the port. Leave TX active if on a console port */ |
406b7d4f | 739 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
a3481197 | 740 | if (!uart_console(port)) |
406b7d4f | 741 | out_8(&psc->command, MPC52xx_PSC_RST_TX); |
9b9129e7 GL |
742 | |
743 | port->read_status_mask = 0; | |
406b7d4f | 744 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); |
1da177e4 | 745 | |
6acc6833 AG |
746 | if (psc_ops->clock) |
747 | psc_ops->clock(port, 0); | |
748 | ||
1da177e4 LT |
749 | /* Release interrupt */ |
750 | free_irq(port->irq, port); | |
751 | } | |
752 | ||
9b9129e7 | 753 | static void |
606d099c | 754 | mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, |
406b7d4f | 755 | struct ktermios *old) |
1da177e4 LT |
756 | { |
757 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
758 | unsigned long flags; | |
759 | unsigned char mr1, mr2; | |
0d1f22e4 AD |
760 | unsigned int j; |
761 | unsigned int baud; | |
9b9129e7 | 762 | |
1da177e4 LT |
763 | /* Prepare what we're gonna write */ |
764 | mr1 = 0; | |
9b9129e7 | 765 | |
1da177e4 | 766 | switch (new->c_cflag & CSIZE) { |
406b7d4f JR |
767 | case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; |
768 | break; | |
769 | case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; | |
770 | break; | |
771 | case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; | |
772 | break; | |
773 | case CS8: | |
774 | default: mr1 |= MPC52xx_PSC_MODE_8_BITS; | |
1da177e4 LT |
775 | } |
776 | ||
777 | if (new->c_cflag & PARENB) { | |
778 | mr1 |= (new->c_cflag & PARODD) ? | |
779 | MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; | |
780 | } else | |
781 | mr1 |= MPC52xx_PSC_MODE_PARNONE; | |
9b9129e7 GL |
782 | |
783 | ||
1da177e4 LT |
784 | mr2 = 0; |
785 | ||
786 | if (new->c_cflag & CSTOPB) | |
787 | mr2 |= MPC52xx_PSC_MODE_TWO_STOP; | |
788 | else | |
789 | mr2 |= ((new->c_cflag & CSIZE) == CS5) ? | |
790 | MPC52xx_PSC_MODE_ONE_STOP_5_BITS : | |
791 | MPC52xx_PSC_MODE_ONE_STOP; | |
792 | ||
aec739e0 WS |
793 | if (new->c_cflag & CRTSCTS) { |
794 | mr1 |= MPC52xx_PSC_MODE_RXRTS; | |
795 | mr2 |= MPC52xx_PSC_MODE_TXCTS; | |
796 | } | |
1da177e4 | 797 | |
1da177e4 LT |
798 | /* Get the lock */ |
799 | spin_lock_irqsave(&port->lock, flags); | |
800 | ||
c4f01240 NA |
801 | /* Do our best to flush TX & RX, so we don't lose anything */ |
802 | /* But we don't wait indefinitely ! */ | |
1da177e4 LT |
803 | j = 5000000; /* Maximum wait */ |
804 | /* FIXME Can't receive chars since set_termios might be called at early | |
805 | * boot for the console, all stuff is not yet ready to receive at that | |
806 | * time and that just makes the kernel oops */ | |
807 | /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ | |
599f030c | 808 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
809 | udelay(1); |
810 | ||
811 | if (!j) | |
406b7d4f | 812 | printk(KERN_ERR "mpc52xx_uart.c: " |
1da177e4 | 813 | "Unable to flush RX & TX fifos in-time in set_termios." |
406b7d4f | 814 | "Some chars may have been lost.\n"); |
1da177e4 LT |
815 | |
816 | /* Reset the TX & RX */ | |
406b7d4f JR |
817 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
818 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
1da177e4 LT |
819 | |
820 | /* Send new mode settings */ | |
406b7d4f JR |
821 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
822 | out_8(&psc->mode, mr1); | |
823 | out_8(&psc->mode, mr2); | |
0d1f22e4 AD |
824 | baud = psc_ops->set_baudrate(port, new, old); |
825 | ||
826 | /* Update the per-port timeout */ | |
827 | uart_update_timeout(port, new->c_cflag, baud); | |
9b9129e7 | 828 | |
aec739e0 WS |
829 | if (UART_ENABLE_MS(port, new->c_cflag)) |
830 | mpc52xx_uart_enable_ms(port); | |
831 | ||
1da177e4 | 832 | /* Reenable TX & RX */ |
406b7d4f JR |
833 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE); |
834 | out_8(&psc->command, MPC52xx_PSC_RX_ENABLE); | |
1da177e4 LT |
835 | |
836 | /* We're all set, release the lock */ | |
837 | spin_unlock_irqrestore(&port->lock, flags); | |
838 | } | |
839 | ||
840 | static const char * | |
841 | mpc52xx_uart_type(struct uart_port *port) | |
842 | { | |
e44dcb6c WS |
843 | /* |
844 | * We keep using PORT_MPC52xx for historic reasons although it applies | |
845 | * for MPC512x, too, but print "MPC5xxx" to not irritate users | |
846 | */ | |
847 | return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL; | |
1da177e4 LT |
848 | } |
849 | ||
850 | static void | |
851 | mpc52xx_uart_release_port(struct uart_port *port) | |
852 | { | |
406b7d4f JR |
853 | /* remapped by us ? */ |
854 | if (port->flags & UPF_IOREMAP) { | |
1da177e4 LT |
855 | iounmap(port->membase); |
856 | port->membase = NULL; | |
857 | } | |
858 | ||
b9272dfd | 859 | release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
860 | } |
861 | ||
862 | static int | |
863 | mpc52xx_uart_request_port(struct uart_port *port) | |
864 | { | |
be618f55 AL |
865 | int err; |
866 | ||
1da177e4 | 867 | if (port->flags & UPF_IOREMAP) /* Need to remap ? */ |
b9272dfd | 868 | port->membase = ioremap(port->mapbase, |
406b7d4f | 869 | sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
870 | |
871 | if (!port->membase) | |
872 | return -EINVAL; | |
873 | ||
b9272dfd | 874 | err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), |
1da177e4 | 875 | "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; |
be618f55 AL |
876 | |
877 | if (err && (port->flags & UPF_IOREMAP)) { | |
878 | iounmap(port->membase); | |
879 | port->membase = NULL; | |
880 | } | |
881 | ||
882 | return err; | |
1da177e4 LT |
883 | } |
884 | ||
885 | static void | |
886 | mpc52xx_uart_config_port(struct uart_port *port, int flags) | |
887 | { | |
406b7d4f JR |
888 | if ((flags & UART_CONFIG_TYPE) |
889 | && (mpc52xx_uart_request_port(port) == 0)) | |
890 | port->type = PORT_MPC52xx; | |
1da177e4 LT |
891 | } |
892 | ||
893 | static int | |
894 | mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
895 | { | |
406b7d4f | 896 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) |
1da177e4 LT |
897 | return -EINVAL; |
898 | ||
406b7d4f | 899 | if ((ser->irq != port->irq) || |
b7a8212c | 900 | (ser->io_type != UPIO_MEM) || |
406b7d4f JR |
901 | (ser->baud_base != port->uartclk) || |
902 | (ser->iomem_base != (void *)port->mapbase) || | |
903 | (ser->hub6 != 0)) | |
1da177e4 LT |
904 | return -EINVAL; |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
909 | ||
910 | static struct uart_ops mpc52xx_uart_ops = { | |
911 | .tx_empty = mpc52xx_uart_tx_empty, | |
912 | .set_mctrl = mpc52xx_uart_set_mctrl, | |
913 | .get_mctrl = mpc52xx_uart_get_mctrl, | |
914 | .stop_tx = mpc52xx_uart_stop_tx, | |
915 | .start_tx = mpc52xx_uart_start_tx, | |
916 | .send_xchar = mpc52xx_uart_send_xchar, | |
917 | .stop_rx = mpc52xx_uart_stop_rx, | |
918 | .enable_ms = mpc52xx_uart_enable_ms, | |
919 | .break_ctl = mpc52xx_uart_break_ctl, | |
920 | .startup = mpc52xx_uart_startup, | |
921 | .shutdown = mpc52xx_uart_shutdown, | |
922 | .set_termios = mpc52xx_uart_set_termios, | |
923 | /* .pm = mpc52xx_uart_pm, Not supported yet */ | |
924 | /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */ | |
925 | .type = mpc52xx_uart_type, | |
926 | .release_port = mpc52xx_uart_release_port, | |
927 | .request_port = mpc52xx_uart_request_port, | |
928 | .config_port = mpc52xx_uart_config_port, | |
929 | .verify_port = mpc52xx_uart_verify_port | |
930 | }; | |
931 | ||
9b9129e7 | 932 | |
1da177e4 LT |
933 | /* ======================================================================== */ |
934 | /* Interrupt handling */ | |
935 | /* ======================================================================== */ | |
9b9129e7 | 936 | |
1da177e4 | 937 | static inline int |
7d12e780 | 938 | mpc52xx_uart_int_rx_chars(struct uart_port *port) |
1da177e4 | 939 | { |
ebd2c8f6 | 940 | struct tty_struct *tty = port->state->port.tty; |
33f0f88f | 941 | unsigned char ch, flag; |
1da177e4 LT |
942 | unsigned short status; |
943 | ||
944 | /* While we can read, do so ! */ | |
599f030c | 945 | while (psc_ops->raw_rx_rdy(port)) { |
1da177e4 | 946 | /* Get the char */ |
599f030c | 947 | ch = psc_ops->read_char(port); |
1da177e4 LT |
948 | |
949 | /* Handle sysreq char */ | |
950 | #ifdef SUPPORT_SYSRQ | |
7d12e780 | 951 | if (uart_handle_sysrq_char(port, ch)) { |
1da177e4 LT |
952 | port->sysrq = 0; |
953 | continue; | |
954 | } | |
955 | #endif | |
956 | ||
957 | /* Store it */ | |
33f0f88f AC |
958 | |
959 | flag = TTY_NORMAL; | |
1da177e4 | 960 | port->icount.rx++; |
9b9129e7 | 961 | |
599f030c JR |
962 | status = in_be16(&PSC(port)->mpc52xx_psc_status); |
963 | ||
406b7d4f JR |
964 | if (status & (MPC52xx_PSC_SR_PE | |
965 | MPC52xx_PSC_SR_FE | | |
966 | MPC52xx_PSC_SR_RB)) { | |
9b9129e7 | 967 | |
1da177e4 | 968 | if (status & MPC52xx_PSC_SR_RB) { |
33f0f88f | 969 | flag = TTY_BREAK; |
1da177e4 | 970 | uart_handle_break(port); |
b6514988 RB |
971 | port->icount.brk++; |
972 | } else if (status & MPC52xx_PSC_SR_PE) { | |
33f0f88f | 973 | flag = TTY_PARITY; |
b6514988 RB |
974 | port->icount.parity++; |
975 | } | |
976 | else if (status & MPC52xx_PSC_SR_FE) { | |
33f0f88f | 977 | flag = TTY_FRAME; |
b6514988 RB |
978 | port->icount.frame++; |
979 | } | |
1da177e4 LT |
980 | |
981 | /* Clear error condition */ | |
406b7d4f | 982 | out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT); |
1da177e4 LT |
983 | |
984 | } | |
33f0f88f AC |
985 | tty_insert_flip_char(tty, ch, flag); |
986 | if (status & MPC52xx_PSC_SR_OE) { | |
987 | /* | |
988 | * Overrun is special, since it's | |
989 | * reported immediately, and doesn't | |
990 | * affect the current character | |
991 | */ | |
992 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
b6514988 | 993 | port->icount.overrun++; |
33f0f88f | 994 | } |
1da177e4 LT |
995 | } |
996 | ||
fbe543b4 | 997 | spin_unlock(&port->lock); |
1da177e4 | 998 | tty_flip_buffer_push(tty); |
fbe543b4 | 999 | spin_lock(&port->lock); |
9b9129e7 | 1000 | |
599f030c | 1001 | return psc_ops->raw_rx_rdy(port); |
1da177e4 LT |
1002 | } |
1003 | ||
1004 | static inline int | |
1005 | mpc52xx_uart_int_tx_chars(struct uart_port *port) | |
1006 | { | |
ebd2c8f6 | 1007 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
1008 | |
1009 | /* Process out of band chars */ | |
1010 | if (port->x_char) { | |
599f030c | 1011 | psc_ops->write_char(port, port->x_char); |
1da177e4 LT |
1012 | port->icount.tx++; |
1013 | port->x_char = 0; | |
1014 | return 1; | |
1015 | } | |
1016 | ||
1017 | /* Nothing to do ? */ | |
1018 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 1019 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
1020 | return 0; |
1021 | } | |
1022 | ||
1023 | /* Send chars */ | |
599f030c JR |
1024 | while (psc_ops->raw_tx_rdy(port)) { |
1025 | psc_ops->write_char(port, xmit->buf[xmit->tail]); | |
1da177e4 LT |
1026 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1027 | port->icount.tx++; | |
1028 | if (uart_circ_empty(xmit)) | |
1029 | break; | |
1030 | } | |
1031 | ||
1032 | /* Wake up */ | |
1033 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1034 | uart_write_wakeup(port); | |
1035 | ||
1036 | /* Maybe we're done after all */ | |
1037 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 1038 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
1039 | return 0; |
1040 | } | |
1041 | ||
1042 | return 1; | |
1043 | } | |
1044 | ||
9b9129e7 | 1045 | static irqreturn_t |
6acc6833 | 1046 | mpc5xxx_uart_process_int(struct uart_port *port) |
1da177e4 | 1047 | { |
1da177e4 LT |
1048 | unsigned long pass = ISR_PASS_LIMIT; |
1049 | unsigned int keepgoing; | |
aec739e0 | 1050 | u8 status; |
9b9129e7 | 1051 | |
1da177e4 LT |
1052 | /* While we have stuff to do, we continue */ |
1053 | do { | |
1054 | /* If we don't find anything to do, we stop */ | |
9b9129e7 GL |
1055 | keepgoing = 0; |
1056 | ||
599f030c JR |
1057 | psc_ops->rx_clr_irq(port); |
1058 | if (psc_ops->rx_rdy(port)) | |
7d12e780 | 1059 | keepgoing |= mpc52xx_uart_int_rx_chars(port); |
1da177e4 | 1060 | |
599f030c JR |
1061 | psc_ops->tx_clr_irq(port); |
1062 | if (psc_ops->tx_rdy(port)) | |
1da177e4 | 1063 | keepgoing |= mpc52xx_uart_int_tx_chars(port); |
9b9129e7 | 1064 | |
aec739e0 WS |
1065 | status = in_8(&PSC(port)->mpc52xx_psc_ipcr); |
1066 | if (status & MPC52xx_PSC_D_DCD) | |
1067 | uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); | |
1068 | ||
1069 | if (status & MPC52xx_PSC_D_CTS) | |
1070 | uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); | |
1071 | ||
1da177e4 | 1072 | /* Limit number of iteration */ |
406b7d4f | 1073 | if (!(--pass)) |
1da177e4 LT |
1074 | keepgoing = 0; |
1075 | ||
1076 | } while (keepgoing); | |
9b9129e7 | 1077 | |
1da177e4 LT |
1078 | return IRQ_HANDLED; |
1079 | } | |
1080 | ||
6acc6833 AG |
1081 | static irqreturn_t |
1082 | mpc52xx_uart_int(int irq, void *dev_id) | |
1083 | { | |
1084 | struct uart_port *port = dev_id; | |
1085 | irqreturn_t ret; | |
1086 | ||
1087 | spin_lock(&port->lock); | |
1088 | ||
1089 | ret = psc_ops->handle_irq(port); | |
1090 | ||
1091 | spin_unlock(&port->lock); | |
1092 | ||
1093 | return ret; | |
1094 | } | |
1da177e4 LT |
1095 | |
1096 | /* ======================================================================== */ | |
1097 | /* Console ( if applicable ) */ | |
1098 | /* ======================================================================== */ | |
1099 | ||
1100 | #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE | |
1101 | ||
1102 | static void __init | |
1103 | mpc52xx_console_get_options(struct uart_port *port, | |
406b7d4f | 1104 | int *baud, int *parity, int *bits, int *flow) |
1da177e4 LT |
1105 | { |
1106 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
1107 | unsigned char mr1; | |
1108 | ||
b9272dfd GL |
1109 | pr_debug("mpc52xx_console_get_options(port=%p)\n", port); |
1110 | ||
1da177e4 | 1111 | /* Read the mode registers */ |
406b7d4f | 1112 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
1da177e4 | 1113 | mr1 = in_8(&psc->mode); |
9b9129e7 | 1114 | |
1da177e4 | 1115 | /* CT{U,L}R are write-only ! */ |
b9272dfd | 1116 | *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; |
1da177e4 LT |
1117 | |
1118 | /* Parse them */ | |
1119 | switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { | |
406b7d4f JR |
1120 | case MPC52xx_PSC_MODE_5_BITS: |
1121 | *bits = 5; | |
1122 | break; | |
1123 | case MPC52xx_PSC_MODE_6_BITS: | |
1124 | *bits = 6; | |
1125 | break; | |
1126 | case MPC52xx_PSC_MODE_7_BITS: | |
1127 | *bits = 7; | |
1128 | break; | |
1129 | case MPC52xx_PSC_MODE_8_BITS: | |
1130 | default: | |
1131 | *bits = 8; | |
1da177e4 | 1132 | } |
9b9129e7 | 1133 | |
1da177e4 LT |
1134 | if (mr1 & MPC52xx_PSC_MODE_PARNONE) |
1135 | *parity = 'n'; | |
1136 | else | |
1137 | *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; | |
1138 | } | |
1139 | ||
9b9129e7 | 1140 | static void |
1da177e4 LT |
1141 | mpc52xx_console_write(struct console *co, const char *s, unsigned int count) |
1142 | { | |
1143 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
1da177e4 | 1144 | unsigned int i, j; |
9b9129e7 | 1145 | |
1da177e4 | 1146 | /* Disable interrupts */ |
599f030c | 1147 | psc_ops->cw_disable_ints(port); |
1da177e4 LT |
1148 | |
1149 | /* Wait the TX buffer to be empty */ | |
9b9129e7 | 1150 | j = 5000000; /* Maximum wait */ |
599f030c | 1151 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
1152 | udelay(1); |
1153 | ||
1154 | /* Write all the chars */ | |
d358788f | 1155 | for (i = 0; i < count; i++, s++) { |
1da177e4 | 1156 | /* Line return handling */ |
d358788f | 1157 | if (*s == '\n') |
599f030c | 1158 | psc_ops->write_char(port, '\r'); |
9b9129e7 | 1159 | |
d358788f | 1160 | /* Send the char */ |
599f030c | 1161 | psc_ops->write_char(port, *s); |
d358788f | 1162 | |
1da177e4 | 1163 | /* Wait the TX buffer to be empty */ |
9b9129e7 | 1164 | j = 20000; /* Maximum wait */ |
599f030c | 1165 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
1166 | udelay(1); |
1167 | } | |
1168 | ||
1169 | /* Restore interrupt state */ | |
599f030c | 1170 | psc_ops->cw_restore_ints(port); |
1da177e4 LT |
1171 | } |
1172 | ||
b9272dfd GL |
1173 | |
1174 | static int __init | |
1175 | mpc52xx_console_setup(struct console *co, char *options) | |
1176 | { | |
1177 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
1178 | struct device_node *np = mpc52xx_uart_nodes[co->index]; | |
599f030c | 1179 | unsigned int uartclk; |
b9272dfd GL |
1180 | struct resource res; |
1181 | int ret; | |
1182 | ||
1183 | int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; | |
1184 | int bits = 8; | |
1185 | int parity = 'n'; | |
1186 | int flow = 'n'; | |
1187 | ||
1188 | pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", | |
1189 | co, co->index, options); | |
1190 | ||
b898f4f8 | 1191 | if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { |
b9272dfd GL |
1192 | pr_debug("PSC%x out of range\n", co->index); |
1193 | return -EINVAL; | |
1194 | } | |
1195 | ||
1196 | if (!np) { | |
1197 | pr_debug("PSC%x not found in device tree\n", co->index); | |
1198 | return -EINVAL; | |
1199 | } | |
1200 | ||
1201 | pr_debug("Console on ttyPSC%x is %s\n", | |
406b7d4f | 1202 | co->index, mpc52xx_uart_nodes[co->index]->full_name); |
b9272dfd GL |
1203 | |
1204 | /* Fetch register locations */ | |
406b7d4f JR |
1205 | ret = of_address_to_resource(np, 0, &res); |
1206 | if (ret) { | |
b9272dfd GL |
1207 | pr_debug("Could not get resources for PSC%x\n", co->index); |
1208 | return ret; | |
1209 | } | |
1210 | ||
0d1f22e4 | 1211 | uartclk = mpc5xxx_get_bus_frequency(np); |
599f030c JR |
1212 | if (uartclk == 0) { |
1213 | pr_debug("Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1214 | return -EINVAL; |
1215 | } | |
1216 | ||
1217 | /* Basic port init. Needed since we use some uart_??? func before | |
1218 | * real init for early access */ | |
1219 | spin_lock_init(&port->lock); | |
599f030c | 1220 | port->uartclk = uartclk; |
b9272dfd GL |
1221 | port->ops = &mpc52xx_uart_ops; |
1222 | port->mapbase = res.start; | |
1223 | port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); | |
1224 | port->irq = irq_of_parse_and_map(np, 0); | |
1225 | ||
1226 | if (port->membase == NULL) | |
1227 | return -EINVAL; | |
1228 | ||
5dd80d5d | 1229 | pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", |
406b7d4f JR |
1230 | (void *)port->mapbase, port->membase, |
1231 | port->irq, port->uartclk); | |
b9272dfd GL |
1232 | |
1233 | /* Setup the port parameters accoding to options */ | |
1234 | if (options) | |
1235 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1236 | else | |
1237 | mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); | |
1238 | ||
1239 | pr_debug("Setting console parameters: %i %i%c1 flow=%c\n", | |
406b7d4f | 1240 | baud, bits, parity, flow); |
b9272dfd GL |
1241 | |
1242 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1243 | } | |
b9272dfd | 1244 | |
1da177e4 | 1245 | |
2d8179c0 | 1246 | static struct uart_driver mpc52xx_uart_driver; |
1da177e4 LT |
1247 | |
1248 | static struct console mpc52xx_console = { | |
d62de3aa | 1249 | .name = "ttyPSC", |
1da177e4 LT |
1250 | .write = mpc52xx_console_write, |
1251 | .device = uart_console_device, | |
1252 | .setup = mpc52xx_console_setup, | |
1253 | .flags = CON_PRINTBUFFER, | |
406b7d4f | 1254 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ |
1da177e4 LT |
1255 | .data = &mpc52xx_uart_driver, |
1256 | }; | |
1257 | ||
9b9129e7 GL |
1258 | |
1259 | static int __init | |
1da177e4 LT |
1260 | mpc52xx_console_init(void) |
1261 | { | |
b9272dfd | 1262 | mpc52xx_uart_of_enumerate(); |
1da177e4 LT |
1263 | register_console(&mpc52xx_console); |
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | console_initcall(mpc52xx_console_init); | |
1268 | ||
1269 | #define MPC52xx_PSC_CONSOLE &mpc52xx_console | |
1270 | #else | |
1271 | #define MPC52xx_PSC_CONSOLE NULL | |
1272 | #endif | |
1273 | ||
1274 | ||
1275 | /* ======================================================================== */ | |
1276 | /* UART Driver */ | |
1277 | /* ======================================================================== */ | |
1278 | ||
1279 | static struct uart_driver mpc52xx_uart_driver = { | |
1da177e4 | 1280 | .driver_name = "mpc52xx_psc_uart", |
d62de3aa | 1281 | .dev_name = "ttyPSC", |
d62de3aa SM |
1282 | .major = SERIAL_PSC_MAJOR, |
1283 | .minor = SERIAL_PSC_MINOR, | |
1da177e4 LT |
1284 | .nr = MPC52xx_PSC_MAXNUM, |
1285 | .cons = MPC52xx_PSC_CONSOLE, | |
1286 | }; | |
1287 | ||
b9272dfd GL |
1288 | /* ======================================================================== */ |
1289 | /* OF Platform Driver */ | |
1290 | /* ======================================================================== */ | |
1291 | ||
52b80482 GL |
1292 | static struct of_device_id mpc52xx_uart_of_match[] = { |
1293 | #ifdef CONFIG_PPC_MPC52xx | |
0d1f22e4 | 1294 | { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, }, |
52b80482 GL |
1295 | { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, |
1296 | /* binding used by old lite5200 device trees: */ | |
1297 | { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, | |
1298 | /* binding used by efika: */ | |
1299 | { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, | |
1300 | #endif | |
1301 | #ifdef CONFIG_PPC_MPC512x | |
1302 | { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, | |
52b80482 | 1303 | #endif |
bc775eac | 1304 | {}, |
52b80482 GL |
1305 | }; |
1306 | ||
793218df | 1307 | static int __devinit mpc52xx_uart_of_probe(struct platform_device *op) |
b9272dfd GL |
1308 | { |
1309 | int idx = -1; | |
599f030c | 1310 | unsigned int uartclk; |
b9272dfd GL |
1311 | struct uart_port *port = NULL; |
1312 | struct resource res; | |
1313 | int ret; | |
1314 | ||
b9272dfd GL |
1315 | /* Check validity & presence */ |
1316 | for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) | |
61c7a080 | 1317 | if (mpc52xx_uart_nodes[idx] == op->dev.of_node) |
b9272dfd GL |
1318 | break; |
1319 | if (idx >= MPC52xx_PSC_MAXNUM) | |
1320 | return -EINVAL; | |
1321 | pr_debug("Found %s assigned to ttyPSC%x\n", | |
406b7d4f | 1322 | mpc52xx_uart_nodes[idx]->full_name, idx); |
b9272dfd | 1323 | |
0d1f22e4 AD |
1324 | /* set the uart clock to the input clock of the psc, the different |
1325 | * prescalers are taken into account in the set_baudrate() methods | |
1326 | * of the respective chip */ | |
1327 | uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node); | |
599f030c JR |
1328 | if (uartclk == 0) { |
1329 | dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1330 | return -EINVAL; |
1331 | } | |
1332 | ||
1333 | /* Init the port structure */ | |
1334 | port = &mpc52xx_uart_ports[idx]; | |
1335 | ||
1336 | spin_lock_init(&port->lock); | |
599f030c | 1337 | port->uartclk = uartclk; |
b9272dfd GL |
1338 | port->fifosize = 512; |
1339 | port->iotype = UPIO_MEM; | |
1340 | port->flags = UPF_BOOT_AUTOCONF | | |
406b7d4f | 1341 | (uart_console(port) ? 0 : UPF_IOREMAP); |
b9272dfd GL |
1342 | port->line = idx; |
1343 | port->ops = &mpc52xx_uart_ops; | |
1344 | port->dev = &op->dev; | |
1345 | ||
1346 | /* Search for IRQ and mapbase */ | |
61c7a080 | 1347 | ret = of_address_to_resource(op->dev.of_node, 0, &res); |
406b7d4f | 1348 | if (ret) |
b9272dfd GL |
1349 | return ret; |
1350 | ||
1351 | port->mapbase = res.start; | |
418441d9 WS |
1352 | if (!port->mapbase) { |
1353 | dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); | |
1354 | return -EINVAL; | |
1355 | } | |
1356 | ||
61c7a080 | 1357 | psc_ops->get_irq(port, op->dev.of_node); |
d4e33fac | 1358 | if (port->irq == 0) { |
418441d9 WS |
1359 | dev_dbg(&op->dev, "Could not get irq\n"); |
1360 | return -EINVAL; | |
1361 | } | |
b9272dfd | 1362 | |
5dd80d5d | 1363 | dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", |
406b7d4f | 1364 | (void *)port->mapbase, port->irq, port->uartclk); |
b9272dfd | 1365 | |
b9272dfd GL |
1366 | /* Add the port to the uart sub-system */ |
1367 | ret = uart_add_one_port(&mpc52xx_uart_driver, port); | |
6acc6833 | 1368 | if (ret) |
418441d9 | 1369 | return ret; |
b9272dfd | 1370 | |
418441d9 WS |
1371 | dev_set_drvdata(&op->dev, (void *)port); |
1372 | return 0; | |
b9272dfd GL |
1373 | } |
1374 | ||
1375 | static int | |
2dc11581 | 1376 | mpc52xx_uart_of_remove(struct platform_device *op) |
b9272dfd GL |
1377 | { |
1378 | struct uart_port *port = dev_get_drvdata(&op->dev); | |
1379 | dev_set_drvdata(&op->dev, NULL); | |
1380 | ||
6acc6833 | 1381 | if (port) |
b9272dfd GL |
1382 | uart_remove_one_port(&mpc52xx_uart_driver, port); |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | #ifdef CONFIG_PM | |
1388 | static int | |
2dc11581 | 1389 | mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state) |
b9272dfd GL |
1390 | { |
1391 | struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev); | |
1392 | ||
1393 | if (port) | |
1394 | uart_suspend_port(&mpc52xx_uart_driver, port); | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
1399 | static int | |
2dc11581 | 1400 | mpc52xx_uart_of_resume(struct platform_device *op) |
b9272dfd GL |
1401 | { |
1402 | struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev); | |
1403 | ||
1404 | if (port) | |
1405 | uart_resume_port(&mpc52xx_uart_driver, port); | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | #endif | |
1410 | ||
1411 | static void | |
3b5ebf8e | 1412 | mpc52xx_uart_of_assign(struct device_node *np) |
b9272dfd | 1413 | { |
b9272dfd GL |
1414 | int i; |
1415 | ||
3b5ebf8e | 1416 | /* Find the first free PSC number */ |
b9272dfd GL |
1417 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { |
1418 | if (mpc52xx_uart_nodes[i] == NULL) { | |
3b5ebf8e GL |
1419 | of_node_get(np); |
1420 | mpc52xx_uart_nodes[i] = np; | |
1421 | return; | |
b9272dfd GL |
1422 | } |
1423 | } | |
b9272dfd GL |
1424 | } |
1425 | ||
1426 | static void | |
1427 | mpc52xx_uart_of_enumerate(void) | |
1428 | { | |
406b7d4f | 1429 | static int enum_done; |
b9272dfd | 1430 | struct device_node *np; |
25ae3a07 | 1431 | const struct of_device_id *match; |
b9272dfd GL |
1432 | int i; |
1433 | ||
1434 | if (enum_done) | |
1435 | return; | |
1436 | ||
3b5ebf8e GL |
1437 | /* Assign index to each PSC in device tree */ |
1438 | for_each_matching_node(np, mpc52xx_uart_of_match) { | |
25ae3a07 | 1439 | match = of_match_node(mpc52xx_uart_of_match, np); |
25ae3a07 | 1440 | psc_ops = match->data; |
3b5ebf8e | 1441 | mpc52xx_uart_of_assign(np); |
b9272dfd GL |
1442 | } |
1443 | ||
1444 | enum_done = 1; | |
1445 | ||
1446 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { | |
1447 | if (mpc52xx_uart_nodes[i]) | |
1448 | pr_debug("%s assigned to ttyPSC%x\n", | |
406b7d4f | 1449 | mpc52xx_uart_nodes[i]->full_name, i); |
b9272dfd GL |
1450 | } |
1451 | } | |
1452 | ||
1453 | MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); | |
1454 | ||
793218df | 1455 | static struct platform_driver mpc52xx_uart_of_driver = { |
b9272dfd GL |
1456 | .probe = mpc52xx_uart_of_probe, |
1457 | .remove = mpc52xx_uart_of_remove, | |
1458 | #ifdef CONFIG_PM | |
1459 | .suspend = mpc52xx_uart_of_suspend, | |
1460 | .resume = mpc52xx_uart_of_resume, | |
1461 | #endif | |
4018294b GL |
1462 | .driver = { |
1463 | .name = "mpc52xx-psc-uart", | |
1464 | .owner = THIS_MODULE, | |
1465 | .of_match_table = mpc52xx_uart_of_match, | |
b9272dfd GL |
1466 | }, |
1467 | }; | |
1da177e4 LT |
1468 | |
1469 | ||
1470 | /* ======================================================================== */ | |
1471 | /* Module */ | |
1472 | /* ======================================================================== */ | |
1473 | ||
1474 | static int __init | |
1475 | mpc52xx_uart_init(void) | |
1476 | { | |
1477 | int ret; | |
1478 | ||
b9272dfd | 1479 | printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); |
1da177e4 | 1480 | |
406b7d4f JR |
1481 | ret = uart_register_driver(&mpc52xx_uart_driver); |
1482 | if (ret) { | |
b9272dfd GL |
1483 | printk(KERN_ERR "%s: uart_register_driver failed (%i)\n", |
1484 | __FILE__, ret); | |
1485 | return ret; | |
1da177e4 LT |
1486 | } |
1487 | ||
b9272dfd GL |
1488 | mpc52xx_uart_of_enumerate(); |
1489 | ||
6acc6833 AG |
1490 | /* |
1491 | * Map the PSC FIFO Controller and init if on MPC512x. | |
1492 | */ | |
e6114fa1 | 1493 | if (psc_ops && psc_ops->fifoc_init) { |
6acc6833 AG |
1494 | ret = psc_ops->fifoc_init(); |
1495 | if (ret) | |
1496 | return ret; | |
1497 | } | |
1498 | ||
793218df | 1499 | ret = platform_driver_register(&mpc52xx_uart_of_driver); |
b9272dfd | 1500 | if (ret) { |
793218df | 1501 | printk(KERN_ERR "%s: platform_driver_register failed (%i)\n", |
b9272dfd GL |
1502 | __FILE__, ret); |
1503 | uart_unregister_driver(&mpc52xx_uart_driver); | |
1504 | return ret; | |
1505 | } | |
b9272dfd GL |
1506 | |
1507 | return 0; | |
1da177e4 LT |
1508 | } |
1509 | ||
1510 | static void __exit | |
1511 | mpc52xx_uart_exit(void) | |
1512 | { | |
6acc6833 AG |
1513 | if (psc_ops->fifoc_uninit) |
1514 | psc_ops->fifoc_uninit(); | |
1515 | ||
793218df | 1516 | platform_driver_unregister(&mpc52xx_uart_of_driver); |
1da177e4 LT |
1517 | uart_unregister_driver(&mpc52xx_uart_driver); |
1518 | } | |
1519 | ||
1520 | ||
1521 | module_init(mpc52xx_uart_init); | |
1522 | module_exit(mpc52xx_uart_exit); | |
1523 | ||
1524 | MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); | |
1525 | MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); | |
1526 | MODULE_LICENSE("GPL"); |