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ARM: S3C2440: move handling of fclk/n clock to platform code
[deliverable/linux.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/delay.h>
43#include <linux/clk.h>
30555476 44#include <linux/cpufreq.h>
b497549a
BD		 45
46#include <asm/irq.h>
47
a09e64fb 48#include <mach/hardware.h>
b690ace5 49#include <mach/map.h>
b497549a 50
a2b7ba9c 51#include <plat/regs-serial.h>
b497549a
BD		 52
53#include "samsung.h"
54
55/* UART name and device definitions */
56
57#define S3C24XX_SERIAL_NAME "ttySAC"
58#define S3C24XX_SERIAL_MAJOR 204
59#define S3C24XX_SERIAL_MINOR 64
60
b497549a
BD		 61/* macros to change one thing to another */
62
63#define tx_enabled(port) ((port)->unused[0])
64#define rx_enabled(port) ((port)->unused[1])
65
25985edc 66/* flag to ignore all characters coming in */
b497549a
BD		 67#define RXSTAT_DUMMY_READ (0x10000000)
68
69static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
70{
71 return container_of(port, struct s3c24xx_uart_port, port);
72}
73
74/* translate a port to the device name */
75
76static inline const char *s3c24xx_serial_portname(struct uart_port *port)
77{
78 return to_platform_device(port->dev)->name;
79}
80
81static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
82{
83 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
84}
85
88bb4ea1
TA		 86/*
87 * s3c64xx and later SoC's include the interrupt mask and status registers in
88 * the controller itself, unlike the s3c24xx SoC's which have these registers
89 * in the interrupt controller. Check if the port type is s3c64xx or higher.
90 */
91static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
92{
93 return to_ourport(port)->info->type == PORT_S3C6400;
94}
95
b497549a
BD		 96static void s3c24xx_serial_rx_enable(struct uart_port *port)
97{
98 unsigned long flags;
99 unsigned int ucon, ufcon;
100 int count = 10000;
101
102 spin_lock_irqsave(&port->lock, flags);
103
104 while (--count && !s3c24xx_serial_txempty_nofifo(port))
105 udelay(100);
106
107 ufcon = rd_regl(port, S3C2410_UFCON);
108 ufcon |= S3C2410_UFCON_RESETRX;
109 wr_regl(port, S3C2410_UFCON, ufcon);
110
111 ucon = rd_regl(port, S3C2410_UCON);
112 ucon |= S3C2410_UCON_RXIRQMODE;
113 wr_regl(port, S3C2410_UCON, ucon);
114
115 rx_enabled(port) = 1;
116 spin_unlock_irqrestore(&port->lock, flags);
117}
118
119static void s3c24xx_serial_rx_disable(struct uart_port *port)
120{
121 unsigned long flags;
122 unsigned int ucon;
123
124 spin_lock_irqsave(&port->lock, flags);
125
126 ucon = rd_regl(port, S3C2410_UCON);
127 ucon &= ~S3C2410_UCON_RXIRQMODE;
128 wr_regl(port, S3C2410_UCON, ucon);
129
130 rx_enabled(port) = 0;
131 spin_unlock_irqrestore(&port->lock, flags);
132}
133
134static void s3c24xx_serial_stop_tx(struct uart_port *port)
135{
b73c289c
BD		 136 struct s3c24xx_uart_port *ourport = to_ourport(port);
137
b497549a 138 if (tx_enabled(port)) {
88bb4ea1
TA		 139 if (s3c24xx_serial_has_interrupt_mask(port))
140 __set_bit(S3C64XX_UINTM_TXD,
141 portaddrl(port, S3C64XX_UINTM));
142 else
143 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 144 tx_enabled(port) = 0;
145 if (port->flags & UPF_CONS_FLOW)
146 s3c24xx_serial_rx_enable(port);
147 }
148}
149
150static void s3c24xx_serial_start_tx(struct uart_port *port)
151{
b73c289c
BD		 152 struct s3c24xx_uart_port *ourport = to_ourport(port);
153
b497549a
BD		 154 if (!tx_enabled(port)) {
155 if (port->flags & UPF_CONS_FLOW)
156 s3c24xx_serial_rx_disable(port);
157
88bb4ea1
TA		 158 if (s3c24xx_serial_has_interrupt_mask(port))
159 __clear_bit(S3C64XX_UINTM_TXD,
160 portaddrl(port, S3C64XX_UINTM));
161 else
162 enable_irq(ourport->tx_irq);
b497549a
BD		 163 tx_enabled(port) = 1;
164 }
165}
166
b497549a
BD		 167static void s3c24xx_serial_stop_rx(struct uart_port *port)
168{
b73c289c
BD		 169 struct s3c24xx_uart_port *ourport = to_ourport(port);
170
b497549a
BD		 171 if (rx_enabled(port)) {
172 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 173 if (s3c24xx_serial_has_interrupt_mask(port))
174 __set_bit(S3C64XX_UINTM_RXD,
175 portaddrl(port, S3C64XX_UINTM));
176 else
177 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 178 rx_enabled(port) = 0;
179 }
180}
181
182static void s3c24xx_serial_enable_ms(struct uart_port *port)
183{
184}
185
186static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
187{
188 return to_ourport(port)->info;
189}
190
191static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
192{
4d84e970
TA		 193 struct s3c24xx_uart_port *ourport;
194
b497549a
BD		 195 if (port->dev == NULL)
196 return NULL;
197
4d84e970
TA		 198 ourport = container_of(port, struct s3c24xx_uart_port, port);
199 return ourport->cfg;
b497549a
BD		 200}
201
202static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
203 unsigned long ufstat)
204{
205 struct s3c24xx_uart_info *info = ourport->info;
206
207 if (ufstat & info->rx_fifofull)
208 return info->fifosize;
209
210 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
211}
212
213
214/* ? - where has parity gone?? */
215#define S3C2410_UERSTAT_PARITY (0x1000)
216
217static irqreturn_t
218s3c24xx_serial_rx_chars(int irq, void *dev_id)
219{
220 struct s3c24xx_uart_port *ourport = dev_id;
221 struct uart_port *port = &ourport->port;
ebd2c8f6 222 struct tty_struct *tty = port->state->port.tty;
b497549a
BD		 223 unsigned int ufcon, ch, flag, ufstat, uerstat;
224 int max_count = 64;
225
226 while (max_count-- > 0) {
227 ufcon = rd_regl(port, S3C2410_UFCON);
228 ufstat = rd_regl(port, S3C2410_UFSTAT);
229
230 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
231 break;
232
233 uerstat = rd_regl(port, S3C2410_UERSTAT);
234 ch = rd_regb(port, S3C2410_URXH);
235
236 if (port->flags & UPF_CONS_FLOW) {
237 int txe = s3c24xx_serial_txempty_nofifo(port);
238
239 if (rx_enabled(port)) {
240 if (!txe) {
241 rx_enabled(port) = 0;
242 continue;
243 }
244 } else {
245 if (txe) {
246 ufcon |= S3C2410_UFCON_RESETRX;
247 wr_regl(port, S3C2410_UFCON, ufcon);
248 rx_enabled(port) = 1;
249 goto out;
250 }
251 continue;
252 }
253 }
254
255 /* insert the character into the buffer */
256
257 flag = TTY_NORMAL;
258 port->icount.rx++;
259
260 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
261 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
262 ch, uerstat);
263
264 /* check for break */
265 if (uerstat & S3C2410_UERSTAT_BREAK) {
266 dbg("break!\n");
267 port->icount.brk++;
268 if (uart_handle_break(port))
269 goto ignore_char;
270 }
271
272 if (uerstat & S3C2410_UERSTAT_FRAME)
273 port->icount.frame++;
274 if (uerstat & S3C2410_UERSTAT_OVERRUN)
275 port->icount.overrun++;
276
277 uerstat &= port->read_status_mask;
278
279 if (uerstat & S3C2410_UERSTAT_BREAK)
280 flag = TTY_BREAK;
281 else if (uerstat & S3C2410_UERSTAT_PARITY)
282 flag = TTY_PARITY;
283 else if (uerstat & (S3C2410_UERSTAT_FRAME |
284 S3C2410_UERSTAT_OVERRUN))
285 flag = TTY_FRAME;
286 }
287
288 if (uart_handle_sysrq_char(port, ch))
289 goto ignore_char;
290
291 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
292 ch, flag);
293
294 ignore_char:
295 continue;
296 }
297 tty_flip_buffer_push(tty);
298
299 out:
300 return IRQ_HANDLED;
301}
302
303static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
304{
305 struct s3c24xx_uart_port *ourport = id;
306 struct uart_port *port = &ourport->port;
ebd2c8f6 307 struct circ_buf *xmit = &port->state->xmit;
b497549a
BD		 308 int count = 256;
309
310 if (port->x_char) {
311 wr_regb(port, S3C2410_UTXH, port->x_char);
312 port->icount.tx++;
313 port->x_char = 0;
314 goto out;
315 }
316
25985edc 317 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 318 * stopped, disable the uart and exit
319 */
320
321 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
322 s3c24xx_serial_stop_tx(port);
323 goto out;
324 }
325
326 /* try and drain the buffer... */
327
328 while (!uart_circ_empty(xmit) && count-- > 0) {
329 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
330 break;
331
332 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
333 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
334 port->icount.tx++;
335 }
336
337 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
338 uart_write_wakeup(port);
339
340 if (uart_circ_empty(xmit))
341 s3c24xx_serial_stop_tx(port);
342
343 out:
344 return IRQ_HANDLED;
345}
346
88bb4ea1
TA		 347/* interrupt handler for s3c64xx and later SoC's.*/
348static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
349{
350 struct s3c24xx_uart_port *ourport = id;
351 struct uart_port *port = &ourport->port;
352 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
353 unsigned long flags;
354 irqreturn_t ret = IRQ_HANDLED;
355
356 spin_lock_irqsave(&port->lock, flags);
357 if (pend & S3C64XX_UINTM_RXD_MSK) {
358 ret = s3c24xx_serial_rx_chars(irq, id);
359 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
360 }
361 if (pend & S3C64XX_UINTM_TXD_MSK) {
362 ret = s3c24xx_serial_tx_chars(irq, id);
363 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
364 }
365 spin_unlock_irqrestore(&port->lock, flags);
366 return ret;
367}
368
b497549a
BD		 369static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
370{
371 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
372 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
373 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
374
375 if (ufcon & S3C2410_UFCON_FIFOMODE) {
376 if ((ufstat & info->tx_fifomask) != 0 ||
377 (ufstat & info->tx_fifofull))
378 return 0;
379
380 return 1;
381 }
382
383 return s3c24xx_serial_txempty_nofifo(port);
384}
385
386/* no modem control lines */
387static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
388{
389 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
390
391 if (umstat & S3C2410_UMSTAT_CTS)
392 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
393 else
394 return TIOCM_CAR | TIOCM_DSR;
395}
396
397static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
398{
399 /* todo - possibly remove AFC and do manual CTS */
400}
401
402static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
403{
404 unsigned long flags;
405 unsigned int ucon;
406
407 spin_lock_irqsave(&port->lock, flags);
408
409 ucon = rd_regl(port, S3C2410_UCON);
410
411 if (break_state)
412 ucon |= S3C2410_UCON_SBREAK;
413 else
414 ucon &= ~S3C2410_UCON_SBREAK;
415
416 wr_regl(port, S3C2410_UCON, ucon);
417
418 spin_unlock_irqrestore(&port->lock, flags);
419}
420
421static void s3c24xx_serial_shutdown(struct uart_port *port)
422{
423 struct s3c24xx_uart_port *ourport = to_ourport(port);
424
425 if (ourport->tx_claimed) {
88bb4ea1
TA		 426 if (!s3c24xx_serial_has_interrupt_mask(port))
427 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 428 tx_enabled(port) = 0;
429 ourport->tx_claimed = 0;
430 }
431
432 if (ourport->rx_claimed) {
88bb4ea1
TA		 433 if (!s3c24xx_serial_has_interrupt_mask(port))
434 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 435 ourport->rx_claimed = 0;
436 rx_enabled(port) = 0;
437 }
b497549a 438
88bb4ea1
TA		 439 /* Clear pending interrupts and mask all interrupts */
440 if (s3c24xx_serial_has_interrupt_mask(port)) {
441 wr_regl(port, S3C64XX_UINTP, 0xf);
442 wr_regl(port, S3C64XX_UINTM, 0xf);
443 }
444}
b497549a
BD		 445
446static int s3c24xx_serial_startup(struct uart_port *port)
447{
448 struct s3c24xx_uart_port *ourport = to_ourport(port);
449 int ret;
450
451 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
452 port->mapbase, port->membase);
453
454 rx_enabled(port) = 1;
455
b73c289c 456 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 457 s3c24xx_serial_portname(port), ourport);
458
459 if (ret != 0) {
b73c289c 460 printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 461 return ret;
462 }
463
464 ourport->rx_claimed = 1;
465
466 dbg("requesting tx irq...\n");
467
468 tx_enabled(port) = 1;
469
b73c289c 470 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 471 s3c24xx_serial_portname(port), ourport);
472
473 if (ret) {
b73c289c 474 printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 475 goto err;
476 }
477
478 ourport->tx_claimed = 1;
479
480 dbg("s3c24xx_serial_startup ok\n");
481
482 /* the port reset code should have done the correct
483 * register setup for the port controls */
484
485 return ret;
486
487 err:
488 s3c24xx_serial_shutdown(port);
489 return ret;
490}
491
88bb4ea1
TA		 492static int s3c64xx_serial_startup(struct uart_port *port)
493{
494 struct s3c24xx_uart_port *ourport = to_ourport(port);
495 int ret;
496
497 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
498 port->mapbase, port->membase);
499
500 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
501 s3c24xx_serial_portname(port), ourport);
502 if (ret) {
503 printk(KERN_ERR "cannot get irq %d\n", port->irq);
504 return ret;
505 }
506
507 /* For compatibility with s3c24xx Soc's */
508 rx_enabled(port) = 1;
509 ourport->rx_claimed = 1;
510 tx_enabled(port) = 0;
511 ourport->tx_claimed = 1;
512
513 /* Enable Rx Interrupt */
514 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
515 dbg("s3c64xx_serial_startup ok\n");
516 return ret;
517}
518
b497549a
BD		 519/* power power management control */
520
521static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
522 unsigned int old)
523{
524 struct s3c24xx_uart_port *ourport = to_ourport(port);
525
30555476
BD		 526 ourport->pm_level = level;
527
b497549a
BD		 528 switch (level) {
529 case 3:
530 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
531 clk_disable(ourport->baudclk);
532
533 clk_disable(ourport->clk);
534 break;
535
536 case 0:
537 clk_enable(ourport->clk);
538
539 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
540 clk_enable(ourport->baudclk);
541
542 break;
543 default:
544 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
545 }
546}
547
548/* baud rate calculation
549 *
550 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
551 * of different sources, including the peripheral clock ("pclk") and an
552 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
553 * with a programmable extra divisor.
554 *
555 * The following code goes through the clock sources, and calculates the
556 * baud clocks (and the resultant actual baud rates) and then tries to
557 * pick the closest one and select that.
558 *
559*/
560
561
562#define MAX_CLKS (8)
563
564static struct s3c24xx_uart_clksrc tmp_clksrc = {
565 .name = "pclk",
566 .min_baud = 0,
567 .max_baud = 0,
568 .divisor = 1,
569};
570
571static inline int
572s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
573{
574 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
575
576 return (info->get_clksrc)(port, c);
577}
578
579static inline int
580s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
581{
582 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
583
584 return (info->set_clksrc)(port, c);
585}
586
587struct baud_calc {
588 struct s3c24xx_uart_clksrc *clksrc;
589 unsigned int calc;
090f848d 590 unsigned int divslot;
b497549a
BD		 591 unsigned int quot;
592 struct clk *src;
593};
594
595static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
596 struct uart_port *port,
597 struct s3c24xx_uart_clksrc *clksrc,
598 unsigned int baud)
599{
090f848d 600 struct s3c24xx_uart_port *ourport = to_ourport(port);
b497549a
BD		 601 unsigned long rate;
602
603 calc->src = clk_get(port->dev, clksrc->name);
604 if (calc->src == NULL || IS_ERR(calc->src))
605 return 0;
606
607 rate = clk_get_rate(calc->src);
608 rate /= clksrc->divisor;
609
610 calc->clksrc = clksrc;
090f848d
BD		 611
612 if (ourport->info->has_divslot) {
613 unsigned long div = rate / baud;
614
615 /* The UDIVSLOT register on the newer UARTs allows us to
616 * get a divisor adjustment of 1/16th on the baud clock.
617 *
618 * We don't keep the UDIVSLOT value (the 16ths we calculated
619 * by not multiplying the baud by 16) as it is easy enough
620 * to recalculate.
621 */
622
623 calc->quot = div / 16;
624 calc->calc = rate / div;
625 } else {
626 calc->quot = (rate + (8 * baud)) / (16 * baud);
627 calc->calc = (rate / (calc->quot * 16));
628 }
b497549a
BD		 629
630 calc->quot--;
631 return 1;
632}
633
634static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
635 struct s3c24xx_uart_clksrc **clksrc,
636 struct clk **clk,
637 unsigned int baud)
638{
639 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
640 struct s3c24xx_uart_clksrc *clkp;
641 struct baud_calc res[MAX_CLKS];
642 struct baud_calc *resptr, *best, *sptr;
643 int i;
644
645 clkp = cfg->clocks;
646 best = NULL;
647
648 if (cfg->clocks_size < 2) {
649 if (cfg->clocks_size == 0)
650 clkp = &tmp_clksrc;
651
b497549a
BD		 652 s3c24xx_serial_calcbaud(res, port, clkp, baud);
653 best = res;
654 resptr = best + 1;
655 } else {
656 resptr = res;
657
658 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
659 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
660 resptr++;
661 }
662 }
663
664 /* ok, we now need to select the best clock we found */
665
666 if (!best) {
667 unsigned int deviation = (1<<30)|((1<<30)-1);
668 int calc_deviation;
669
670 for (sptr = res; sptr < resptr; sptr++) {
671 calc_deviation = baud - sptr->calc;
672 if (calc_deviation < 0)
673 calc_deviation = -calc_deviation;
674
675 if (calc_deviation < deviation) {
676 best = sptr;
677 deviation = calc_deviation;
678 }
679 }
680 }
681
682 /* store results to pass back */
683
684 *clksrc = best->clksrc;
685 *clk = best->src;
686
687 return best->quot;
688}
689
090f848d
BD		 690/* udivslot_table[]
691 *
692 * This table takes the fractional value of the baud divisor and gives
693 * the recommended setting for the UDIVSLOT register.
694 */
695static u16 udivslot_table[16] = {
696 [0] = 0x0000,
697 [1] = 0x0080,
698 [2] = 0x0808,
699 [3] = 0x0888,
700 [4] = 0x2222,
701 [5] = 0x4924,
702 [6] = 0x4A52,
703 [7] = 0x54AA,
704 [8] = 0x5555,
705 [9] = 0xD555,
706 [10] = 0xD5D5,
707 [11] = 0xDDD5,
708 [12] = 0xDDDD,
709 [13] = 0xDFDD,
710 [14] = 0xDFDF,
711 [15] = 0xFFDF,
712};
713
b497549a
BD		 714static void s3c24xx_serial_set_termios(struct uart_port *port,
715 struct ktermios *termios,
716 struct ktermios *old)
717{
718 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
719 struct s3c24xx_uart_port *ourport = to_ourport(port);
720 struct s3c24xx_uart_clksrc *clksrc = NULL;
721 struct clk *clk = NULL;
722 unsigned long flags;
723 unsigned int baud, quot;
724 unsigned int ulcon;
725 unsigned int umcon;
090f848d 726 unsigned int udivslot = 0;
b497549a
BD		 727
728 /*
729 * We don't support modem control lines.
730 */
731 termios->c_cflag &= ~(HUPCL | CMSPAR);
732 termios->c_cflag |= CLOCAL;
733
734 /*
735 * Ask the core to calculate the divisor for us.
736 */
737
738 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
739
740 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
741 quot = port->custom_divisor;
742 else
743 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
744
745 /* check to see if we need to change clock source */
746
747 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
090f848d 748 dbg("selecting clock %p\n", clk);
b497549a
BD		 749 s3c24xx_serial_setsource(port, clksrc);
750
751 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
752 clk_disable(ourport->baudclk);
753 ourport->baudclk = NULL;
754 }
755
756 clk_enable(clk);
757
758 ourport->clksrc = clksrc;
759 ourport->baudclk = clk;
30555476 760 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 761 }
762
090f848d
BD		 763 if (ourport->info->has_divslot) {
764 unsigned int div = ourport->baudclk_rate / baud;
765
8b526ae4
JL		 766 if (cfg->has_fracval) {
767 udivslot = (div & 15);
768 dbg("fracval = %04x\n", udivslot);
769 } else {
770 udivslot = udivslot_table[div & 15];
771 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
772 }
090f848d
BD		 773 }
774
b497549a
BD		 775 switch (termios->c_cflag & CSIZE) {
776 case CS5:
777 dbg("config: 5bits/char\n");
778 ulcon = S3C2410_LCON_CS5;
779 break;
780 case CS6:
781 dbg("config: 6bits/char\n");
782 ulcon = S3C2410_LCON_CS6;
783 break;
784 case CS7:
785 dbg("config: 7bits/char\n");
786 ulcon = S3C2410_LCON_CS7;
787 break;
788 case CS8:
789 default:
790 dbg("config: 8bits/char\n");
791 ulcon = S3C2410_LCON_CS8;
792 break;
793 }
794
795 /* preserve original lcon IR settings */
796 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
797
798 if (termios->c_cflag & CSTOPB)
799 ulcon |= S3C2410_LCON_STOPB;
800
801 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
802
803 if (termios->c_cflag & PARENB) {
804 if (termios->c_cflag & PARODD)
805 ulcon |= S3C2410_LCON_PODD;
806 else
807 ulcon |= S3C2410_LCON_PEVEN;
808 } else {
809 ulcon |= S3C2410_LCON_PNONE;
810 }
811
812 spin_lock_irqsave(&port->lock, flags);
813
090f848d
BD		 814 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
815 ulcon, quot, udivslot);
b497549a
BD		 816
817 wr_regl(port, S3C2410_ULCON, ulcon);
818 wr_regl(port, S3C2410_UBRDIV, quot);
819 wr_regl(port, S3C2410_UMCON, umcon);
820
090f848d
BD		 821 if (ourport->info->has_divslot)
822 wr_regl(port, S3C2443_DIVSLOT, udivslot);
823
b497549a
BD		 824 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
825 rd_regl(port, S3C2410_ULCON),
826 rd_regl(port, S3C2410_UCON),
827 rd_regl(port, S3C2410_UFCON));
828
829 /*
830 * Update the per-port timeout.
831 */
832 uart_update_timeout(port, termios->c_cflag, baud);
833
834 /*
835 * Which character status flags are we interested in?
836 */
837 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
838 if (termios->c_iflag & INPCK)
839 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
840
841 /*
842 * Which character status flags should we ignore?
843 */
844 port->ignore_status_mask = 0;
845 if (termios->c_iflag & IGNPAR)
846 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
847 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
848 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
849
850 /*
851 * Ignore all characters if CREAD is not set.
852 */
853 if ((termios->c_cflag & CREAD) == 0)
854 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
855
856 spin_unlock_irqrestore(&port->lock, flags);
857}
858
859static const char *s3c24xx_serial_type(struct uart_port *port)
860{
861 switch (port->type) {
862 case PORT_S3C2410:
863 return "S3C2410";
864 case PORT_S3C2440:
865 return "S3C2440";
866 case PORT_S3C2412:
867 return "S3C2412";
b690ace5
BD		 868 case PORT_S3C6400:
869 return "S3C6400/10";
b497549a
BD		 870 default:
871 return NULL;
872 }
873}
874
875#define MAP_SIZE (0x100)
876
877static void s3c24xx_serial_release_port(struct uart_port *port)
878{
879 release_mem_region(port->mapbase, MAP_SIZE);
880}
881
882static int s3c24xx_serial_request_port(struct uart_port *port)
883{
884 const char *name = s3c24xx_serial_portname(port);
885 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
886}
887
888static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
889{
890 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
891
892 if (flags & UART_CONFIG_TYPE &&
893 s3c24xx_serial_request_port(port) == 0)
894 port->type = info->type;
895}
896
897/*
898 * verify the new serial_struct (for TIOCSSERIAL).
899 */
900static int
901s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
902{
903 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
904
905 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
906 return -EINVAL;
907
908 return 0;
909}
910
911
912#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
913
914static struct console s3c24xx_serial_console;
915
916#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
917#else
918#define S3C24XX_SERIAL_CONSOLE NULL
919#endif
920
921static struct uart_ops s3c24xx_serial_ops = {
922 .pm = s3c24xx_serial_pm,
923 .tx_empty = s3c24xx_serial_tx_empty,
924 .get_mctrl = s3c24xx_serial_get_mctrl,
925 .set_mctrl = s3c24xx_serial_set_mctrl,
926 .stop_tx = s3c24xx_serial_stop_tx,
927 .start_tx = s3c24xx_serial_start_tx,
928 .stop_rx = s3c24xx_serial_stop_rx,
929 .enable_ms = s3c24xx_serial_enable_ms,
930 .break_ctl = s3c24xx_serial_break_ctl,
931 .startup = s3c24xx_serial_startup,
932 .shutdown = s3c24xx_serial_shutdown,
933 .set_termios = s3c24xx_serial_set_termios,
934 .type = s3c24xx_serial_type,
935 .release_port = s3c24xx_serial_release_port,
936 .request_port = s3c24xx_serial_request_port,
937 .config_port = s3c24xx_serial_config_port,
938 .verify_port = s3c24xx_serial_verify_port,
939};
940
b497549a
BD		 941static struct uart_driver s3c24xx_uart_drv = {
942 .owner = THIS_MODULE,
2cf0c58e 943 .driver_name = "s3c2410_serial",
bdd4915a 944 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 945 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 946 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 947 .major = S3C24XX_SERIAL_MAJOR,
948 .minor = S3C24XX_SERIAL_MINOR,
949};
950
03d5e77b 951static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 952 [0] = {
953 .port = {
954 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
955 .iotype = UPIO_MEM,
b497549a
BD		 956 .uartclk = 0,
957 .fifosize = 16,
958 .ops = &s3c24xx_serial_ops,
959 .flags = UPF_BOOT_AUTOCONF,
960 .line = 0,
961 }
962 },
963 [1] = {
964 .port = {
965 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
966 .iotype = UPIO_MEM,
b497549a
BD		 967 .uartclk = 0,
968 .fifosize = 16,
969 .ops = &s3c24xx_serial_ops,
970 .flags = UPF_BOOT_AUTOCONF,
971 .line = 1,
972 }
973 },
03d5e77b 974#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 975
976 [2] = {
977 .port = {
978 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
979 .iotype = UPIO_MEM,
b497549a
BD		 980 .uartclk = 0,
981 .fifosize = 16,
982 .ops = &s3c24xx_serial_ops,
983 .flags = UPF_BOOT_AUTOCONF,
984 .line = 2,
985 }
03d5e77b
BD		 986 },
987#endif
988#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
989 [3] = {
990 .port = {
991 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
992 .iotype = UPIO_MEM,
03d5e77b
BD		 993 .uartclk = 0,
994 .fifosize = 16,
995 .ops = &s3c24xx_serial_ops,
996 .flags = UPF_BOOT_AUTOCONF,
997 .line = 3,
998 }
b497549a
BD		 999 }
1000#endif
1001};
1002
1003/* s3c24xx_serial_resetport
1004 *
1005 * wrapper to call the specific reset for this port (reset the fifos
1006 * and the settings)
1007*/
1008
1009static inline int s3c24xx_serial_resetport(struct uart_port *port,
1010 struct s3c2410_uartcfg *cfg)
1011{
1012 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1013
1014 return (info->reset_port)(port, cfg);
1015}
1016
30555476
BD		 1017
1018#ifdef CONFIG_CPU_FREQ
1019
1020static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1021 unsigned long val, void *data)
1022{
1023 struct s3c24xx_uart_port *port;
1024 struct uart_port *uport;
1025
1026 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1027 uport = &port->port;
1028
1029 /* check to see if port is enabled */
1030
1031 if (port->pm_level != 0)
1032 return 0;
1033
1034 /* try and work out if the baudrate is changing, we can detect
1035 * a change in rate, but we do not have support for detecting
1036 * a disturbance in the clock-rate over the change.
1037 */
1038
1039 if (IS_ERR(port->clk))
1040 goto exit;
1041
1042 if (port->baudclk_rate == clk_get_rate(port->clk))
1043 goto exit;
1044
1045 if (val == CPUFREQ_PRECHANGE) {
1046 /* we should really shut the port down whilst the
1047 * frequency change is in progress. */
1048
1049 } else if (val == CPUFREQ_POSTCHANGE) {
1050 struct ktermios *termios;
1051 struct tty_struct *tty;
1052
ebd2c8f6 1053 if (uport->state == NULL)
30555476 1054 goto exit;
30555476 1055
ebd2c8f6 1056 tty = uport->state->port.tty;
30555476 1057
7de40c21 1058 if (tty == NULL)
30555476 1059 goto exit;
30555476
BD		 1060
1061 termios = tty->termios;
1062
1063 if (termios == NULL) {
1064 printk(KERN_WARNING "%s: no termios?\n", __func__);
1065 goto exit;
1066 }
1067
1068 s3c24xx_serial_set_termios(uport, termios, NULL);
1069 }
1070
1071 exit:
1072 return 0;
1073}
1074
1075static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1076{
1077 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1078
1079 return cpufreq_register_notifier(&port->freq_transition,
1080 CPUFREQ_TRANSITION_NOTIFIER);
1081}
1082
1083static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1084{
1085 cpufreq_unregister_notifier(&port->freq_transition,
1086 CPUFREQ_TRANSITION_NOTIFIER);
1087}
1088
1089#else
1090static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1091{
1092 return 0;
1093}
1094
1095static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1096{
1097}
1098#endif
1099
b497549a
BD		 1100/* s3c24xx_serial_init_port
1101 *
1102 * initialise a single serial port from the platform device given
1103 */
1104
1105static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1106 struct s3c24xx_uart_info *info,
1107 struct platform_device *platdev)
1108{
1109 struct uart_port *port = &ourport->port;
4d84e970 1110 struct s3c2410_uartcfg *cfg = platdev->dev.platform_data;
b497549a
BD		 1111 struct resource *res;
1112 int ret;
1113
1114 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1115
1116 if (platdev == NULL)
1117 return -ENODEV;
1118
b497549a
BD		 1119 if (port->mapbase != 0)
1120 return 0;
1121
4d84e970
TA		 1122 /*
1123 * If platform data is supplied, keep a copy of the location of
1124 * platform data in the driver's private data.
1125 */
1126 if (cfg)
1127 ourport->cfg = cfg;
1128
bdd4915a
BD		 1129 if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
1130 printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
1131 cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
1132 return -ERANGE;
1133 }
b497549a
BD		 1134
1135 /* setup info for port */
1136 port->dev = &platdev->dev;
1137 ourport->info = info;
1138
88bb4ea1
TA		 1139 /* Startup sequence is different for s3c64xx and higher SoC's */
1140 if (s3c24xx_serial_has_interrupt_mask(port))
1141 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1142
b497549a
BD		 1143 /* copy the info in from provided structure */
1144 ourport->port.fifosize = info->fifosize;
1145
1146 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1147
1148 port->uartclk = 1;
1149
1150 if (cfg->uart_flags & UPF_CONS_FLOW) {
1151 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1152 port->flags |= UPF_CONS_FLOW;
1153 }
1154
1155 /* sort our the physical and virtual addresses for each UART */
1156
1157 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1158 if (res == NULL) {
1159 printk(KERN_ERR "failed to find memory resource for uart\n");
1160 return -EINVAL;
1161 }
1162
1163 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1164
b690ace5 1165 port->mapbase = res->start;
2555e663 1166 port->membase = S3C_VA_UART + (res->start & 0xfffff);
b497549a
BD		 1167 ret = platform_get_irq(platdev, 0);
1168 if (ret < 0)
1169 port->irq = 0;
b73c289c 1170 else {
b497549a 1171 port->irq = ret;
b73c289c
BD		 1172 ourport->rx_irq = ret;
1173 ourport->tx_irq = ret + 1;
1174 }
1175
1176 ret = platform_get_irq(platdev, 1);
1177 if (ret > 0)
1178 ourport->tx_irq = ret;
b497549a
BD		 1179
1180 ourport->clk = clk_get(&platdev->dev, "uart");
1181
88bb4ea1
TA		 1182 /* Keep all interrupts masked and cleared */
1183 if (s3c24xx_serial_has_interrupt_mask(port)) {
1184 wr_regl(port, S3C64XX_UINTM, 0xf);
1185 wr_regl(port, S3C64XX_UINTP, 0xf);
1186 wr_regl(port, S3C64XX_UINTSP, 0xf);
1187 }
1188
b73c289c
BD		 1189 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1190 port->mapbase, port->membase, port->irq,
1191 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1192
1193 /* reset the fifos (and setup the uart) */
1194 s3c24xx_serial_resetport(port, cfg);
1195 return 0;
1196}
1197
1198static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1199 struct device_attribute *attr,
1200 char *buf)
1201{
1202 struct uart_port *port = s3c24xx_dev_to_port(dev);
1203 struct s3c24xx_uart_port *ourport = to_ourport(port);
1204
1205 return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
1206}
1207
1208static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1209
1210/* Device driver serial port probe */
1211
1212static int probe_index;
1213
1214int s3c24xx_serial_probe(struct platform_device *dev,
1215 struct s3c24xx_uart_info *info)
1216{
1217 struct s3c24xx_uart_port *ourport;
1218 int ret;
1219
1220 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1221
1222 ourport = &s3c24xx_serial_ports[probe_index];
1223 probe_index++;
1224
1225 dbg("%s: initialising port %p...\n", __func__, ourport);
1226
1227 ret = s3c24xx_serial_init_port(ourport, info, dev);
1228 if (ret < 0)
1229 goto probe_err;
1230
1231 dbg("%s: adding port\n", __func__);
1232 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1233 platform_set_drvdata(dev, &ourport->port);
1234
1235 ret = device_create_file(&dev->dev, &dev_attr_clock_source);
1236 if (ret < 0)
1237 printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
1238
30555476
BD		 1239 ret = s3c24xx_serial_cpufreq_register(ourport);
1240 if (ret < 0)
1241 dev_err(&dev->dev, "failed to add cpufreq notifier\n");
1242
b497549a
BD		 1243 return 0;
1244
1245 probe_err:
1246 return ret;
1247}
1248
1249EXPORT_SYMBOL_GPL(s3c24xx_serial_probe);
1250
90ceb964 1251int __devexit s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1252{
1253 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1254
1255 if (port) {
30555476 1256 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1257 device_remove_file(&dev->dev, &dev_attr_clock_source);
1258 uart_remove_one_port(&s3c24xx_uart_drv, port);
1259 }
1260
1261 return 0;
1262}
1263
1264EXPORT_SYMBOL_GPL(s3c24xx_serial_remove);
1265
1266/* UART power management code */
aef7fe52
MH		 1267#ifdef CONFIG_PM_SLEEP
1268static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1269{
aef7fe52 1270 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1271
1272 if (port)
1273 uart_suspend_port(&s3c24xx_uart_drv, port);
1274
1275 return 0;
1276}
1277
aef7fe52 1278static int s3c24xx_serial_resume(struct device *dev)
b497549a 1279{
aef7fe52 1280 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1281 struct s3c24xx_uart_port *ourport = to_ourport(port);
1282
1283 if (port) {
1284 clk_enable(ourport->clk);
1285 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1286 clk_disable(ourport->clk);
1287
1288 uart_resume_port(&s3c24xx_uart_drv, port);
1289 }
1290
1291 return 0;
1292}
aef7fe52
MH		 1293
1294static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1295 .suspend = s3c24xx_serial_suspend,
1296 .resume = s3c24xx_serial_resume,
1297};
b882fc1b
KK		 1298#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1299
aef7fe52 1300#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1301
1302#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1303#endif /* CONFIG_PM_SLEEP */
b497549a
BD		 1304
1305int s3c24xx_serial_init(struct platform_driver *drv,
1306 struct s3c24xx_uart_info *info)
1307{
1308 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
b882fc1b
KK		 1309
1310 drv->driver.pm = SERIAL_SAMSUNG_PM_OPS;
b497549a
BD		 1311
1312 return platform_driver_register(drv);
1313}
1314
1315EXPORT_SYMBOL_GPL(s3c24xx_serial_init);
1316
1317/* module initialisation code */
1318
1319static int __init s3c24xx_serial_modinit(void)
1320{
1321 int ret;
1322
1323 ret = uart_register_driver(&s3c24xx_uart_drv);
1324 if (ret < 0) {
1325 printk(KERN_ERR "failed to register UART driver\n");
1326 return -1;
1327 }
1328
1329 return 0;
1330}
1331
1332static void __exit s3c24xx_serial_modexit(void)
1333{
1334 uart_unregister_driver(&s3c24xx_uart_drv);
1335}
1336
1337module_init(s3c24xx_serial_modinit);
1338module_exit(s3c24xx_serial_modexit);
1339
1340/* Console code */
1341
1342#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1343
1344static struct uart_port *cons_uart;
1345
1346static int
1347s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1348{
1349 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1350 unsigned long ufstat, utrstat;
1351
1352 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1353 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1354
1355 ufstat = rd_regl(port, S3C2410_UFSTAT);
1356 return (ufstat & info->tx_fifofull) ? 0 : 1;
1357 }
1358
1359 /* in non-fifo mode, we go and use the tx buffer empty */
1360
1361 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1362 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1363}
1364
1365static void
1366s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1367{
1368 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1369 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1370 barrier();
1371 wr_regb(cons_uart, S3C2410_UTXH, ch);
1372}
1373
1374static void
1375s3c24xx_serial_console_write(struct console *co, const char *s,
1376 unsigned int count)
1377{
1378 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1379}
1380
1381static void __init
1382s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1383 int *parity, int *bits)
1384{
1385 struct s3c24xx_uart_clksrc clksrc;
1386 struct clk *clk;
1387 unsigned int ulcon;
1388 unsigned int ucon;
1389 unsigned int ubrdiv;
1390 unsigned long rate;
1391
1392 ulcon = rd_regl(port, S3C2410_ULCON);
1393 ucon = rd_regl(port, S3C2410_UCON);
1394 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1395
1396 dbg("s3c24xx_serial_get_options: port=%p\n"
1397 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1398 port, ulcon, ucon, ubrdiv);
1399
1400 if ((ucon & 0xf) != 0) {
1401 /* consider the serial port configured if the tx/rx mode set */
1402
1403 switch (ulcon & S3C2410_LCON_CSMASK) {
1404 case S3C2410_LCON_CS5:
1405 *bits = 5;
1406 break;
1407 case S3C2410_LCON_CS6:
1408 *bits = 6;
1409 break;
1410 case S3C2410_LCON_CS7:
1411 *bits = 7;
1412 break;
1413 default:
1414 case S3C2410_LCON_CS8:
1415 *bits = 8;
1416 break;
1417 }
1418
1419 switch (ulcon & S3C2410_LCON_PMASK) {
1420 case S3C2410_LCON_PEVEN:
1421 *parity = 'e';
1422 break;
1423
1424 case S3C2410_LCON_PODD:
1425 *parity = 'o';
1426 break;
1427
1428 case S3C2410_LCON_PNONE:
1429 default:
1430 *parity = 'n';
1431 }
1432
1433 /* now calculate the baud rate */
1434
1435 s3c24xx_serial_getsource(port, &clksrc);
1436
1437 clk = clk_get(port->dev, clksrc.name);
1438 if (!IS_ERR(clk) && clk != NULL)
1439 rate = clk_get_rate(clk) / clksrc.divisor;
1440 else
1441 rate = 1;
1442
1443
1444 *baud = rate / (16 * (ubrdiv + 1));
1445 dbg("calculated baud %d\n", *baud);
1446 }
1447
1448}
1449
1450/* s3c24xx_serial_init_ports
1451 *
1452 * initialise the serial ports from the machine provided initialisation
1453 * data.
1454*/
1455
51fe5222 1456static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info)
b497549a
BD		 1457{
1458 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1459 struct platform_device **platdev_ptr;
1460 int i;
1461
1462 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1463
1464 platdev_ptr = s3c24xx_uart_devs;
1465
03d5e77b 1466 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
51fe5222 1467 s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr);
b497549a
BD		 1468 }
1469
1470 return 0;
1471}
1472
1473static int __init
1474s3c24xx_serial_console_setup(struct console *co, char *options)
1475{
1476 struct uart_port *port;
1477 int baud = 9600;
1478 int bits = 8;
1479 int parity = 'n';
1480 int flow = 'n';
1481
1482 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1483 co, co->index, options);
1484
1485 /* is this a valid port */
1486
03d5e77b 1487 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1488 co->index = 0;
1489
1490 port = &s3c24xx_serial_ports[co->index].port;
1491
1492 /* is the port configured? */
1493
ee430f16
TA		 1494 if (port->mapbase == 0x0)
1495 return -ENODEV;
b497549a
BD		 1496
1497 cons_uart = port;
1498
1499 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1500
1501 /*
1502 * Check whether an invalid uart number has been specified, and
1503 * if so, search for the first available port that does have
1504 * console support.
1505 */
1506 if (options)
1507 uart_parse_options(options, &baud, &parity, &bits, &flow);
1508 else
1509 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1510
1511 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1512
1513 return uart_set_options(port, co, baud, parity, bits, flow);
1514}
1515
1516/* s3c24xx_serial_initconsole
1517 *
1518 * initialise the console from one of the uart drivers
1519*/
1520
1521static struct console s3c24xx_serial_console = {
1522 .name = S3C24XX_SERIAL_NAME,
1523 .device = uart_console_device,
1524 .flags = CON_PRINTBUFFER,
1525 .index = -1,
1526 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1527 .setup = s3c24xx_serial_console_setup,
1528 .data = &s3c24xx_uart_drv,
b497549a
BD		 1529};
1530
1531int s3c24xx_serial_initconsole(struct platform_driver *drv,
51fe5222 1532 struct s3c24xx_uart_info **info)
b497549a
BD		 1533
1534{
1535 struct platform_device *dev = s3c24xx_uart_devs[0];
1536
1537 dbg("s3c24xx_serial_initconsole\n");
1538
1539 /* select driver based on the cpu */
1540
1541 if (dev == NULL) {
1542 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1543 return 0;
1544 }
1545
1546 if (strcmp(dev->name, drv->driver.name) != 0)
1547 return 0;
1548
1549 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1550 s3c24xx_serial_init_ports(info);
1551
1552 register_console(&s3c24xx_serial_console);
1553 return 0;
1554}
1555
1556#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1557
1558MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1559MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1560MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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