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uart: pl011: Add support to ZTE ZX296702 uart
[deliverable/linux.git] / drivers / tty / serial / sc16is7xx.c
CommitLineData
dfeae619
JR		 1/*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/regmap.h>
24#include <linux/serial_core.h>
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
2c837a8a 28#include <linux/spi/spi.h>
d952795d 29#include <linux/uaccess.h>
dfeae619
JR		 30
31#define SC16IS7XX_NAME "sc16is7xx"
32
33/* SC16IS7XX register definitions */
34#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
47 * - only on 75x/76x
48 */
49#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
50 * - only on 75x/76x
51 */
52#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
53 * - only on 75x/76x
54 */
55#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
56 * - only on 75x/76x
57 */
58#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59
60/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63
64/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67
68/* Enhanced Register set: Only if (LCR == 0xBF) */
69#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74
75/* IER register bits */
76#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 * interrupt */
79#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 * interrupt */
81#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
82 * interrupt */
83
84/* IER register bits - write only if (EFR[4] == 1) */
85#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89
90/* FCR register bits */
91#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96
97/* FCR register bits - write only if (EFR[4] == 1) */
98#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100
101/* IIR register bits */
102#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
109 * - only on 75x/76x
110 */
111#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
112 * - only on 75x/76x
113 */
114#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
116 * from active (LOW)
117 * to inactive (HIGH)
118 */
119/* LCR register bits */
120#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 *
123 * Word length bits table:
124 * 00 -> 5 bit words
125 * 01 -> 6 bit words
126 * 10 -> 7 bit words
127 * 11 -> 8 bit words
128 */
129#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 *
131 * STOP length bit table:
132 * 0 -> 1 stop bit
133 * 1 -> 1-1.5 stop bits if
134 * word length is 5,
135 * 2 stop bits otherwise
136 */
137#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 * reg set */
148#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
149 * reg set */
150
151/* MCR register bits */
152#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
153 * - only on 75x/76x
154 */
155#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
159 * - write enabled
160 * if (EFR[4] == 1)
161 */
162#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
163 * - write enabled
164 * if (EFR[4] == 1)
165 */
166#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
167 * - write enabled
168 * if (EFR[4] == 1)
169 */
170
171/* LSR register bits */
172#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181
182/* MSR register bits */
183#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
185 * or (IO4)
186 * - only on 75x/76x
187 */
188#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
189 * or (IO7)
190 * - only on 75x/76x
191 */
192#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
193 * or (IO6)
194 * - only on 75x/76x
195 */
196#define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
197#define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
198 * - only on 75x/76x
199 */
200#define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
201 * - only on 75x/76x
202 */
203#define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
204 * - only on 75x/76x
205 */
206#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
207
208/*
209 * TCR register bits
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * of four.
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
216 */
217#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
219
220/*
221 * TLR register bits
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
226 *
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
231 *
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
234 */
235#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237
238/* IOControl register bits (Only 750/760) */
239#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240#define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
241#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242
243/* EFCR register bits */
244#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 * mode (RS485) */
246#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
247#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
248#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
249#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
250#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * 0 = rate upto 115.2 kbit/s
252 * - Only 750/760
253 * 1 = rate upto 1.152 Mbit/s
254 * - Only 760
255 */
256
257/* EFR register bits */
258#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
259#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
260#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
261#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
262 * and writing to IER[7:4],
263 * FCR[5:4], MCR[7:5]
264 */
265#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
266#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 *
268 * SWFLOW bits 3 & 2 table:
269 * 00 -> no transmitter flow
270 * control
271 * 01 -> transmitter generates
272 * XON2 and XOFF2
273 * 10 -> transmitter generates
274 * XON1 and XOFF1
275 * 11 -> transmitter generates
276 * XON1, XON2, XOFF1 and
277 * XOFF2
278 */
279#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
280#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 *
282 * SWFLOW bits 3 & 2 table:
283 * 00 -> no received flow
284 * control
285 * 01 -> receiver compares
286 * XON2 and XOFF2
287 * 10 -> receiver compares
288 * XON1 and XOFF1
289 * 11 -> receiver compares
290 * XON1, XON2, XOFF1 and
291 * XOFF2
292 */
293
294/* Misc definitions */
295#define SC16IS7XX_FIFO_SIZE (64)
296#define SC16IS7XX_REG_SHIFT 2
297
298struct sc16is7xx_devtype {
299 char name[10];
300 int nr_gpio;
301 int nr_uart;
302};
303
a0104085 304#define SC16IS7XX_RECONF_MD (1 << 0)
059d5815 305#define SC16IS7XX_RECONF_IER (1 << 1)
478d1051 306#define SC16IS7XX_RECONF_RS485 (1 << 2)
a0104085
JK		 307
308struct sc16is7xx_one_config {
309 unsigned int flags;
059d5815 310 u8 ier_clear;
a0104085
JK		 311};
312
dfeae619
JR		 313struct sc16is7xx_one {
314 struct uart_port port;
9e6f4ca3 315 struct kthread_work tx_work;
a0104085
JK		 316 struct kthread_work reg_work;
317 struct sc16is7xx_one_config config;
dfeae619
JR		 318};
319
320struct sc16is7xx_port {
321 struct uart_driver uart;
322 struct sc16is7xx_devtype *devtype;
323 struct regmap *regmap;
dfeae619
JR		 324 struct clk *clk;
325#ifdef CONFIG_GPIOLIB
326 struct gpio_chip gpio;
327#endif
beb04a9f 328 unsigned char buf[SC16IS7XX_FIFO_SIZE];
9e6f4ca3
JK		 329 struct kthread_worker kworker;
330 struct task_struct *kworker_task;
331 struct kthread_work irq_work;
dfeae619
JR		 332 struct sc16is7xx_one p[0];
333};
334
9e6f4ca3 335#define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
dfeae619
JR		 336#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
337
338static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
339{
340 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
341 unsigned int val = 0;
342
343 regmap_read(s->regmap,
344 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val);
345
346 return val;
347}
348
349static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
350{
351 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
352
353 regmap_write(s->regmap,
354 (reg << SC16IS7XX_REG_SHIFT) | port->line, val);
355}
356
dec273ec
BS		 357static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
358{
359 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
360 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | port->line;
361
362 regcache_cache_bypass(s->regmap, true);
363 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
364 regcache_cache_bypass(s->regmap, false);
365}
366
367static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
368{
369 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
370 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | port->line;
371
372 regcache_cache_bypass(s->regmap, true);
373 regmap_raw_write(s->regmap, addr, s->buf, to_send);
374 regcache_cache_bypass(s->regmap, false);
375}
376
dfeae619
JR		 377static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
378 u8 mask, u8 val)
379{
380 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
381
382 regmap_update_bits(s->regmap,
383 (reg << SC16IS7XX_REG_SHIFT) | port->line,
384 mask, val);
385}
386
387
388static void sc16is7xx_power(struct uart_port *port, int on)
389{
390 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
391 SC16IS7XX_IER_SLEEP_BIT,
392 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
393}
394
395static const struct sc16is7xx_devtype sc16is74x_devtype = {
396 .name = "SC16IS74X",
397 .nr_gpio = 0,
398 .nr_uart = 1,
399};
400
401static const struct sc16is7xx_devtype sc16is750_devtype = {
402 .name = "SC16IS750",
403 .nr_gpio = 8,
404 .nr_uart = 1,
405};
406
407static const struct sc16is7xx_devtype sc16is752_devtype = {
408 .name = "SC16IS752",
409 .nr_gpio = 8,
410 .nr_uart = 2,
411};
412
413static const struct sc16is7xx_devtype sc16is760_devtype = {
414 .name = "SC16IS760",
415 .nr_gpio = 8,
416 .nr_uart = 1,
417};
418
419static const struct sc16is7xx_devtype sc16is762_devtype = {
420 .name = "SC16IS762",
421 .nr_gpio = 8,
422 .nr_uart = 2,
423};
424
425static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
426{
427 switch (reg >> SC16IS7XX_REG_SHIFT) {
428 case SC16IS7XX_RHR_REG:
429 case SC16IS7XX_IIR_REG:
430 case SC16IS7XX_LSR_REG:
431 case SC16IS7XX_MSR_REG:
432 case SC16IS7XX_TXLVL_REG:
433 case SC16IS7XX_RXLVL_REG:
434 case SC16IS7XX_IOSTATE_REG:
435 return true;
436 default:
437 break;
438 }
439
440 return false;
441}
442
443static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
444{
445 switch (reg >> SC16IS7XX_REG_SHIFT) {
446 case SC16IS7XX_RHR_REG:
447 return true;
448 default:
449 break;
450 }
451
452 return false;
453}
454
455static int sc16is7xx_set_baud(struct uart_port *port, int baud)
456{
457 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
458 u8 lcr;
459 u8 prescaler = 0;
460 unsigned long clk = port->uartclk, div = clk / 16 / baud;
461
462 if (div > 0xffff) {
463 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
464 div /= 4;
465 }
466
467 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
468
469 /* Open the LCR divisors for configuration */
470 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
471 SC16IS7XX_LCR_CONF_MODE_B);
472
473 /* Enable enhanced features */
474 regcache_cache_bypass(s->regmap, true);
475 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
476 SC16IS7XX_EFR_ENABLE_BIT);
477 regcache_cache_bypass(s->regmap, false);
478
479 /* Put LCR back to the normal mode */
480 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
481
482 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
483 SC16IS7XX_MCR_CLKSEL_BIT,
484 prescaler);
485
486 /* Open the LCR divisors for configuration */
487 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
488 SC16IS7XX_LCR_CONF_MODE_A);
489
490 /* Write the new divisor */
491 regcache_cache_bypass(s->regmap, true);
492 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
493 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
494 regcache_cache_bypass(s->regmap, false);
495
496 /* Put LCR back to the normal mode */
497 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
498
499 return DIV_ROUND_CLOSEST(clk / 16, div);
500}
501
502static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
503 unsigned int iir)
504{
505 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
506 unsigned int lsr = 0, ch, flag, bytes_read, i;
dfeae619
JR		 507 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
508
beb04a9f 509 if (unlikely(rxlen >= sizeof(s->buf))) {
dfeae619
JR		 510 dev_warn_ratelimited(port->dev,
511 "Port %i: Possible RX FIFO overrun: %d\n",
512 port->line, rxlen);
513 port->icount.buf_overrun++;
514 /* Ensure sanity of RX level */
beb04a9f 515 rxlen = sizeof(s->buf);
dfeae619
JR		 516 }
517
518 while (rxlen) {
519 /* Only read lsr if there are possible errors in FIFO */
520 if (read_lsr) {
521 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
522 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
523 read_lsr = false; /* No errors left in FIFO */
524 } else
525 lsr = 0;
526
527 if (read_lsr) {
beb04a9f 528 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
dfeae619
JR		 529 bytes_read = 1;
530 } else {
dec273ec 531 sc16is7xx_fifo_read(port, rxlen);
dfeae619
JR		 532 bytes_read = rxlen;
533 }
534
535 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
536
537 port->icount.rx++;
538 flag = TTY_NORMAL;
539
540 if (unlikely(lsr)) {
541 if (lsr & SC16IS7XX_LSR_BI_BIT) {
542 port->icount.brk++;
543 if (uart_handle_break(port))
544 continue;
545 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
546 port->icount.parity++;
547 else if (lsr & SC16IS7XX_LSR_FE_BIT)
548 port->icount.frame++;
549 else if (lsr & SC16IS7XX_LSR_OE_BIT)
550 port->icount.overrun++;
551
552 lsr &= port->read_status_mask;
553 if (lsr & SC16IS7XX_LSR_BI_BIT)
554 flag = TTY_BREAK;
555 else if (lsr & SC16IS7XX_LSR_PE_BIT)
556 flag = TTY_PARITY;
557 else if (lsr & SC16IS7XX_LSR_FE_BIT)
558 flag = TTY_FRAME;
559 else if (lsr & SC16IS7XX_LSR_OE_BIT)
560 flag = TTY_OVERRUN;
561 }
562
563 for (i = 0; i < bytes_read; ++i) {
beb04a9f 564 ch = s->buf[i];
dfeae619
JR		 565 if (uart_handle_sysrq_char(port, ch))
566 continue;
567
568 if (lsr & port->ignore_status_mask)
569 continue;
570
571 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
572 flag);
573 }
574 rxlen -= bytes_read;
575 }
576
577 tty_flip_buffer_push(&port->state->port);
578}
579
580static void sc16is7xx_handle_tx(struct uart_port *port)
581{
582 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
583 struct circ_buf *xmit = &port->state->xmit;
584 unsigned int txlen, to_send, i;
dfeae619
JR		 585
586 if (unlikely(port->x_char)) {
587 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
588 port->icount.tx++;
589 port->x_char = 0;
590 return;
591 }
592
593 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
594 return;
595
596 /* Get length of data pending in circular buffer */
597 to_send = uart_circ_chars_pending(xmit);
598 if (likely(to_send)) {
599 /* Limit to size of TX FIFO */
600 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
601 to_send = (to_send > txlen) ? txlen : to_send;
602
603 /* Add data to send */
604 port->icount.tx += to_send;
605
606 /* Convert to linear buffer */
607 for (i = 0; i < to_send; ++i) {
beb04a9f 608 s->buf[i] = xmit->buf[xmit->tail];
dfeae619
JR		 609 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
610 }
dec273ec
BS		 611
612 sc16is7xx_fifo_write(port, to_send);
dfeae619
JR		 613 }
614
615 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
616 uart_write_wakeup(port);
617}
618
619static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
620{
621 struct uart_port *port = &s->p[portno].port;
622
623 do {
624 unsigned int iir, msr, rxlen;
625
626 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
627 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
628 break;
629
630 iir &= SC16IS7XX_IIR_ID_MASK;
631
632 switch (iir) {
633 case SC16IS7XX_IIR_RDI_SRC:
634 case SC16IS7XX_IIR_RLSE_SRC:
635 case SC16IS7XX_IIR_RTOI_SRC:
636 case SC16IS7XX_IIR_XOFFI_SRC:
637 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
638 if (rxlen)
639 sc16is7xx_handle_rx(port, rxlen, iir);
640 break;
641
642 case SC16IS7XX_IIR_CTSRTS_SRC:
643 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
644 uart_handle_cts_change(port,
645 !!(msr & SC16IS7XX_MSR_CTS_BIT));
646 break;
647 case SC16IS7XX_IIR_THRI_SRC:
dfeae619 648 sc16is7xx_handle_tx(port);
dfeae619
JR		 649 break;
650 default:
651 dev_err_ratelimited(port->dev,
652 "Port %i: Unexpected interrupt: %x",
653 port->line, iir);
654 break;
655 }
656 } while (1);
657}
658
9e6f4ca3 659static void sc16is7xx_ist(struct kthread_work *ws)
dfeae619 660{
9e6f4ca3 661 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
dfeae619
JR		 662 int i;
663
664 for (i = 0; i < s->uart.nr; ++i)
665 sc16is7xx_port_irq(s, i);
9e6f4ca3
JK		 666}
667
668static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
669{
670 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
671
672 queue_kthread_work(&s->kworker, &s->irq_work);
dfeae619
JR		 673
674 return IRQ_HANDLED;
675}
676
9e6f4ca3 677static void sc16is7xx_tx_proc(struct kthread_work *ws)
dfeae619 678{
dbe5a40c 679 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
dfeae619 680
dbe5a40c
JK		 681 if ((port->rs485.flags & SER_RS485_ENABLED) &&
682 (port->rs485.delay_rts_before_send > 0))
683 msleep(port->rs485.delay_rts_before_send);
684
685 sc16is7xx_handle_tx(port);
dfeae619
JR		 686}
687
478d1051
JK		 688static void sc16is7xx_reconf_rs485(struct uart_port *port)
689{
690 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
691 SC16IS7XX_EFCR_RTS_INVERT_BIT;
692 u32 efcr = 0;
693 struct serial_rs485 *rs485 = &port->rs485;
694 unsigned long irqflags;
695
696 spin_lock_irqsave(&port->lock, irqflags);
697 if (rs485->flags & SER_RS485_ENABLED) {
698 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
699
700 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
701 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
702 }
703 spin_unlock_irqrestore(&port->lock, irqflags);
704
705 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
706}
707
a0104085
JK		 708static void sc16is7xx_reg_proc(struct kthread_work *ws)
709{
710 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
711 struct sc16is7xx_one_config config;
712 unsigned long irqflags;
713
714 spin_lock_irqsave(&one->port.lock, irqflags);
715 config = one->config;
716 memset(&one->config, 0, sizeof(one->config));
717 spin_unlock_irqrestore(&one->port.lock, irqflags);
718
719 if (config.flags & SC16IS7XX_RECONF_MD)
720 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
721 SC16IS7XX_MCR_LOOP_BIT,
722 (one->port.mctrl & TIOCM_LOOP) ?
723 SC16IS7XX_MCR_LOOP_BIT : 0);
059d5815
JK		 724
725 if (config.flags & SC16IS7XX_RECONF_IER)
726 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
727 config.ier_clear, 0);
478d1051
JK		 728
729 if (config.flags & SC16IS7XX_RECONF_RS485)
730 sc16is7xx_reconf_rs485(&one->port);
a0104085
JK		 731}
732
059d5815 733static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
dfeae619 734{
059d5815
JK		 735 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
736 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
737
738 one->config.flags |= SC16IS7XX_RECONF_IER;
739 one->config.ier_clear |= bit;
740 queue_kthread_work(&s->kworker, &one->reg_work);
dfeae619
JR		 741}
742
059d5815 743static void sc16is7xx_stop_tx(struct uart_port *port)
dfeae619 744{
059d5815
JK		 745 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
746}
dfeae619 747
059d5815
JK		 748static void sc16is7xx_stop_rx(struct uart_port *port)
749{
750 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
dfeae619
JR		 751}
752
753static void sc16is7xx_start_tx(struct uart_port *port)
754{
9e6f4ca3 755 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
dfeae619
JR		 756 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
757
9e6f4ca3 758 queue_kthread_work(&s->kworker, &one->tx_work);
dfeae619
JR		 759}
760
761static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
762{
4ae82e5d 763 unsigned int lsr;
dfeae619 764
dfeae619
JR		 765 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
766
4ae82e5d 767 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
dfeae619
JR		 768}
769
770static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
771{
772 /* DCD and DSR are not wired and CTS/RTS is handled automatically
773 * so just indicate DSR and CAR asserted
774 */
775 return TIOCM_DSR | TIOCM_CAR;
776}
777
dfeae619
JR		 778static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
779{
a0104085 780 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
dfeae619
JR		 781 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
782
a0104085
JK		 783 one->config.flags |= SC16IS7XX_RECONF_MD;
784 queue_kthread_work(&s->kworker, &one->reg_work);
dfeae619
JR		 785}
786
787static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
788{
789 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
790 SC16IS7XX_LCR_TXBREAK_BIT,
791 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
792}
793
794static void sc16is7xx_set_termios(struct uart_port *port,
795 struct ktermios *termios,
796 struct ktermios *old)
797{
798 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
799 unsigned int lcr, flow = 0;
800 int baud;
801
802 /* Mask termios capabilities we don't support */
803 termios->c_cflag &= ~CMSPAR;
804
805 /* Word size */
806 switch (termios->c_cflag & CSIZE) {
807 case CS5:
808 lcr = SC16IS7XX_LCR_WORD_LEN_5;
809 break;
810 case CS6:
811 lcr = SC16IS7XX_LCR_WORD_LEN_6;
812 break;
813 case CS7:
814 lcr = SC16IS7XX_LCR_WORD_LEN_7;
815 break;
816 case CS8:
817 lcr = SC16IS7XX_LCR_WORD_LEN_8;
818 break;
819 default:
820 lcr = SC16IS7XX_LCR_WORD_LEN_8;
821 termios->c_cflag &= ~CSIZE;
822 termios->c_cflag |= CS8;
823 break;
824 }
825
826 /* Parity */
827 if (termios->c_cflag & PARENB) {
828 lcr |= SC16IS7XX_LCR_PARITY_BIT;
829 if (!(termios->c_cflag & PARODD))
830 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
831 }
832
833 /* Stop bits */
834 if (termios->c_cflag & CSTOPB)
835 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
836
837 /* Set read status mask */
838 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
839 if (termios->c_iflag & INPCK)
840 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
841 SC16IS7XX_LSR_FE_BIT;
842 if (termios->c_iflag & (BRKINT | PARMRK))
843 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
844
845 /* Set status ignore mask */
846 port->ignore_status_mask = 0;
847 if (termios->c_iflag & IGNBRK)
848 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
849 if (!(termios->c_cflag & CREAD))
850 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
851
852 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
853 SC16IS7XX_LCR_CONF_MODE_B);
854
855 /* Configure flow control */
856 regcache_cache_bypass(s->regmap, true);
857 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
858 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
859 if (termios->c_cflag & CRTSCTS)
860 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
861 SC16IS7XX_EFR_AUTORTS_BIT;
862 if (termios->c_iflag & IXON)
863 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
864 if (termios->c_iflag & IXOFF)
865 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
866
867 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
868 regcache_cache_bypass(s->regmap, false);
869
870 /* Update LCR register */
871 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
872
873 /* Get baud rate generator configuration */
874 baud = uart_get_baud_rate(port, termios, old,
875 port->uartclk / 16 / 4 / 0xffff,
876 port->uartclk / 16);
877
878 /* Setup baudrate generator */
879 baud = sc16is7xx_set_baud(port, baud);
880
881 /* Update timeout according to new baud rate */
882 uart_update_timeout(port, termios->c_cflag, baud);
883}
884
b57d15fe 885static int sc16is7xx_config_rs485(struct uart_port *port,
f0e38115 886 struct serial_rs485 *rs485)
dfeae619 887{
478d1051
JK		 888 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
889 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
f0e38115
JK		 890
891 if (rs485->flags & SER_RS485_ENABLED) {
892 bool rts_during_rx, rts_during_tx;
893
894 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
895 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
896
478d1051 897 if (rts_during_rx == rts_during_tx)
f0e38115
JK		 898 dev_err(port->dev,
899 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
900 rts_during_tx, rts_during_rx);
5451bb29
JK		 901
902 /*
903 * RTS signal is handled by HW, it's timing can't be influenced.
904 * However, it's sometimes useful to delay TX even without RTS
905 * control therefore we try to handle .delay_rts_before_send.
906 */
907 if (rs485->delay_rts_after_send)
908 return -EINVAL;
f0e38115
JK		 909 }
910
b57d15fe 911 port->rs485 = *rs485;
478d1051
JK		 912 one->config.flags |= SC16IS7XX_RECONF_RS485;
913 queue_kthread_work(&s->kworker, &one->reg_work);
dfeae619 914
b57d15fe 915 return 0;
dfeae619
JR		 916}
917
918static int sc16is7xx_startup(struct uart_port *port)
919{
920 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
921 unsigned int val;
922
923 sc16is7xx_power(port, 1);
924
925 /* Reset FIFOs*/
926 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
927 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
928 udelay(5);
929 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
930 SC16IS7XX_FCR_FIFO_BIT);
931
932 /* Enable EFR */
933 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
934 SC16IS7XX_LCR_CONF_MODE_B);
935
936 regcache_cache_bypass(s->regmap, true);
937
938 /* Enable write access to enhanced features and internal clock div */
939 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
940 SC16IS7XX_EFR_ENABLE_BIT);
941
942 /* Enable TCR/TLR */
943 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
944 SC16IS7XX_MCR_TCRTLR_BIT,
945 SC16IS7XX_MCR_TCRTLR_BIT);
946
947 /* Configure flow control levels */
948 /* Flow control halt level 48, resume level 24 */
949 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
950 SC16IS7XX_TCR_RX_RESUME(24) |
951 SC16IS7XX_TCR_RX_HALT(48));
952
953 regcache_cache_bypass(s->regmap, false);
954
955 /* Now, initialize the UART */
956 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
957
958 /* Enable the Rx and Tx FIFO */
959 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
960 SC16IS7XX_EFCR_RXDISABLE_BIT |
961 SC16IS7XX_EFCR_TXDISABLE_BIT,
962 0);
963
964 /* Enable RX, TX, CTS change interrupts */
965 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
966 SC16IS7XX_IER_CTSI_BIT;
967 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
968
969 return 0;
970}
971
972static void sc16is7xx_shutdown(struct uart_port *port)
973{
9e6f4ca3
JK		 974 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
975
dfeae619
JR		 976 /* Disable all interrupts */
977 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
978 /* Disable TX/RX */
9764e7a0
JK		 979 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
980 SC16IS7XX_EFCR_RXDISABLE_BIT |
981 SC16IS7XX_EFCR_TXDISABLE_BIT,
982 SC16IS7XX_EFCR_RXDISABLE_BIT |
983 SC16IS7XX_EFCR_TXDISABLE_BIT);
dfeae619
JR		 984
985 sc16is7xx_power(port, 0);
9e6f4ca3
JK		 986
987 flush_kthread_worker(&s->kworker);
dfeae619
JR		 988}
989
990static const char *sc16is7xx_type(struct uart_port *port)
991{
992 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
993
994 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
995}
996
997static int sc16is7xx_request_port(struct uart_port *port)
998{
999 /* Do nothing */
1000 return 0;
1001}
1002
1003static void sc16is7xx_config_port(struct uart_port *port, int flags)
1004{
1005 if (flags & UART_CONFIG_TYPE)
1006 port->type = PORT_SC16IS7XX;
1007}
1008
1009static int sc16is7xx_verify_port(struct uart_port *port,
1010 struct serial_struct *s)
1011{
1012 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1013 return -EINVAL;
1014 if (s->irq != port->irq)
1015 return -EINVAL;
1016
1017 return 0;
1018}
1019
1020static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1021 unsigned int oldstate)
1022{
1023 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1024}
1025
1026static void sc16is7xx_null_void(struct uart_port *port)
1027{
1028 /* Do nothing */
1029}
1030
1031static const struct uart_ops sc16is7xx_ops = {
1032 .tx_empty = sc16is7xx_tx_empty,
1033 .set_mctrl = sc16is7xx_set_mctrl,
1034 .get_mctrl = sc16is7xx_get_mctrl,
1035 .stop_tx = sc16is7xx_stop_tx,
1036 .start_tx = sc16is7xx_start_tx,
1037 .stop_rx = sc16is7xx_stop_rx,
dfeae619
JR		 1038 .break_ctl = sc16is7xx_break_ctl,
1039 .startup = sc16is7xx_startup,
1040 .shutdown = sc16is7xx_shutdown,
1041 .set_termios = sc16is7xx_set_termios,
1042 .type = sc16is7xx_type,
1043 .request_port = sc16is7xx_request_port,
1044 .release_port = sc16is7xx_null_void,
1045 .config_port = sc16is7xx_config_port,
1046 .verify_port = sc16is7xx_verify_port,
dfeae619
JR		 1047 .pm = sc16is7xx_pm,
1048};
1049
1050#ifdef CONFIG_GPIOLIB
1051static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1052{
1053 unsigned int val;
1054 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1055 gpio);
1056 struct uart_port *port = &s->p[0].port;
1057
1058 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1059
1060 return !!(val & BIT(offset));
1061}
1062
1063static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1064{
1065 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1066 gpio);
1067 struct uart_port *port = &s->p[0].port;
1068
1069 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1070 val ? BIT(offset) : 0);
1071}
1072
1073static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1074 unsigned offset)
1075{
1076 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1077 gpio);
1078 struct uart_port *port = &s->p[0].port;
1079
1080 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1081
1082 return 0;
1083}
1084
1085static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1086 unsigned offset, int val)
1087{
1088 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1089 gpio);
1090 struct uart_port *port = &s->p[0].port;
1091
1092 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1093 val ? BIT(offset) : 0);
1094 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1095 BIT(offset));
1096
1097 return 0;
1098}
1099#endif
1100
1101static int sc16is7xx_probe(struct device *dev,
1102 struct sc16is7xx_devtype *devtype,
1103 struct regmap *regmap, int irq, unsigned long flags)
1104{
9e6f4ca3 1105 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
dfeae619 1106 unsigned long freq, *pfreq = dev_get_platdata(dev);
dfeae619
JR		 1107 int i, ret;
1108 struct sc16is7xx_port *s;
1109
1110 if (IS_ERR(regmap))
1111 return PTR_ERR(regmap);
1112
1113 /* Alloc port structure */
1114 s = devm_kzalloc(dev, sizeof(*s) +
1115 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1116 GFP_KERNEL);
1117 if (!s) {
1118 dev_err(dev, "Error allocating port structure\n");
1119 return -ENOMEM;
1120 }
1121
dc824ebe
JR		 1122 s->clk = devm_clk_get(dev, NULL);
1123 if (IS_ERR(s->clk)) {
dfeae619
JR		 1124 if (pfreq)
1125 freq = *pfreq;
1126 else
dc824ebe 1127 return PTR_ERR(s->clk);
dfeae619 1128 } else {
0814e8d5 1129 clk_prepare_enable(s->clk);
dc824ebe 1130 freq = clk_get_rate(s->clk);
dfeae619
JR		 1131 }
1132
1133 s->regmap = regmap;
1134 s->devtype = devtype;
1135 dev_set_drvdata(dev, s);
1136
1137 /* Register UART driver */
1138 s->uart.owner = THIS_MODULE;
1139 s->uart.dev_name = "ttySC";
1140 s->uart.nr = devtype->nr_uart;
1141 ret = uart_register_driver(&s->uart);
1142 if (ret) {
1143 dev_err(dev, "Registering UART driver failed\n");
1144 goto out_clk;
1145 }
1146
9e6f4ca3
JK		 1147 init_kthread_worker(&s->kworker);
1148 init_kthread_work(&s->irq_work, sc16is7xx_ist);
1149 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1150 "sc16is7xx");
1151 if (IS_ERR(s->kworker_task)) {
1152 ret = PTR_ERR(s->kworker_task);
1153 goto out_uart;
1154 }
1155 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1156
dfeae619
JR		 1157#ifdef CONFIG_GPIOLIB
1158 if (devtype->nr_gpio) {
1159 /* Setup GPIO cotroller */
1160 s->gpio.owner = THIS_MODULE;
1161 s->gpio.dev = dev;
1162 s->gpio.label = dev_name(dev);
1163 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1164 s->gpio.get = sc16is7xx_gpio_get;
1165 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1166 s->gpio.set = sc16is7xx_gpio_set;
1167 s->gpio.base = -1;
1168 s->gpio.ngpio = devtype->nr_gpio;
1169 s->gpio.can_sleep = 1;
1170 ret = gpiochip_add(&s->gpio);
1171 if (ret)
9e6f4ca3 1172 goto out_thread;
dfeae619
JR		 1173 }
1174#endif
1175
dfeae619
JR		 1176 for (i = 0; i < devtype->nr_uart; ++i) {
1177 /* Initialize port data */
1178 s->p[i].port.line = i;
1179 s->p[i].port.dev = dev;
1180 s->p[i].port.irq = irq;
1181 s->p[i].port.type = PORT_SC16IS7XX;
1182 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1183 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1184 s->p[i].port.iotype = UPIO_PORT;
1185 s->p[i].port.uartclk = freq;
b57d15fe 1186 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
dfeae619
JR		 1187 s->p[i].port.ops = &sc16is7xx_ops;
1188 /* Disable all interrupts */
1189 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1190 /* Disable TX/RX */
1191 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1192 SC16IS7XX_EFCR_RXDISABLE_BIT |
1193 SC16IS7XX_EFCR_TXDISABLE_BIT);
a0104085 1194 /* Initialize kthread work structs */
9e6f4ca3 1195 init_kthread_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
a0104085 1196 init_kthread_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
dfeae619
JR		 1197 /* Register port */
1198 uart_add_one_port(&s->uart, &s->p[i].port);
1199 /* Go to suspend mode */
1200 sc16is7xx_power(&s->p[i].port, 0);
1201 }
1202
1203 /* Setup interrupt */
9e6f4ca3
JK		 1204 ret = devm_request_irq(dev, irq, sc16is7xx_irq,
1205 IRQF_ONESHOT | flags, dev_name(dev), s);
dfeae619
JR		 1206 if (!ret)
1207 return 0;
1208
11b03ea0
JK		 1209 for (i = 0; i < s->uart.nr; i++)
1210 uart_remove_one_port(&s->uart, &s->p[i].port);
1211
dfeae619
JR		 1212#ifdef CONFIG_GPIOLIB
1213 if (devtype->nr_gpio)
e27e2786 1214 gpiochip_remove(&s->gpio);
dfeae619 1215
9e6f4ca3 1216out_thread:
dfeae619 1217#endif
9e6f4ca3
JK		 1218 kthread_stop(s->kworker_task);
1219
1220out_uart:
dfeae619
JR		 1221 uart_unregister_driver(&s->uart);
1222
1223out_clk:
1224 if (!IS_ERR(s->clk))
1225 clk_disable_unprepare(s->clk);
1226
1227 return ret;
1228}
1229
1230static int sc16is7xx_remove(struct device *dev)
1231{
1232 struct sc16is7xx_port *s = dev_get_drvdata(dev);
e27e2786 1233 int i;
dfeae619
JR		 1234
1235#ifdef CONFIG_GPIOLIB
e27e2786
LW		 1236 if (s->devtype->nr_gpio)
1237 gpiochip_remove(&s->gpio);
dfeae619
JR		 1238#endif
1239
1240 for (i = 0; i < s->uart.nr; i++) {
dfeae619
JR		 1241 uart_remove_one_port(&s->uart, &s->p[i].port);
1242 sc16is7xx_power(&s->p[i].port, 0);
1243 }
1244
9e6f4ca3
JK		 1245 flush_kthread_worker(&s->kworker);
1246 kthread_stop(s->kworker_task);
1247
dfeae619
JR		 1248 uart_unregister_driver(&s->uart);
1249 if (!IS_ERR(s->clk))
1250 clk_disable_unprepare(s->clk);
1251
e27e2786 1252 return 0;
dfeae619
JR		 1253}
1254
1255static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1256 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1257 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1258 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1259 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1260 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1261 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1262 { }
1263};
1264MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1265
1266static struct regmap_config regcfg = {
1267 .reg_bits = 7,
1268 .pad_bits = 1,
1269 .val_bits = 8,
1270 .cache_type = REGCACHE_RBTREE,
1271 .volatile_reg = sc16is7xx_regmap_volatile,
1272 .precious_reg = sc16is7xx_regmap_precious,
1273};
1274
2c837a8a
RKKI		 1275#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1276static int sc16is7xx_spi_probe(struct spi_device *spi)
1277{
1278 struct sc16is7xx_devtype *devtype;
1279 unsigned long flags = 0;
1280 struct regmap *regmap;
1281 int ret;
1282
1283 /* Setup SPI bus */
1284 spi->bits_per_word = 8;
1285 /* only supports mode 0 on SC16IS762 */
1286 spi->mode = spi->mode ? : SPI_MODE_0;
1287 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1288 ret = spi_setup(spi);
1289 if (ret)
1290 return ret;
1291
1292 if (spi->dev.of_node) {
1293 const struct of_device_id *of_id =
1294 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1295
1296 devtype = (struct sc16is7xx_devtype *)of_id->data;
1297 } else {
1298 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1299
1300 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1301 flags = IRQF_TRIGGER_FALLING;
1302 }
1303
1304 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1305 (devtype->nr_uart - 1);
1306 regmap = devm_regmap_init_spi(spi, &regcfg);
1307
1308 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1309}
1310
1311static int sc16is7xx_spi_remove(struct spi_device *spi)
1312{
1313 return sc16is7xx_remove(&spi->dev);
1314}
1315
1316static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1317 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1318 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1319 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
2c837a8a
RKKI		 1320 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1321 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1322 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1323 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1324 { }
1325};
1326
1327MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1328
1329static struct spi_driver sc16is7xx_spi_uart_driver = {
1330 .driver = {
1331 .name = SC16IS7XX_NAME,
1332 .owner = THIS_MODULE,
1333 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1334 },
1335 .probe = sc16is7xx_spi_probe,
1336 .remove = sc16is7xx_spi_remove,
1337 .id_table = sc16is7xx_spi_id_table,
1338};
1339
1340MODULE_ALIAS("spi:sc16is7xx");
1341#endif
1342
1343#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
dfeae619
JR		 1344static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1345 const struct i2c_device_id *id)
1346{
1347 struct sc16is7xx_devtype *devtype;
1348 unsigned long flags = 0;
1349 struct regmap *regmap;
1350
1351 if (i2c->dev.of_node) {
1352 const struct of_device_id *of_id =
1353 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1354
1355 devtype = (struct sc16is7xx_devtype *)of_id->data;
1356 } else {
1357 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1358 flags = IRQF_TRIGGER_FALLING;
1359 }
1360
1361 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1362 (devtype->nr_uart - 1);
1363 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1364
1365 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1366}
1367
1368static int sc16is7xx_i2c_remove(struct i2c_client *client)
1369{
1370 return sc16is7xx_remove(&client->dev);
1371}
1372
1373static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1374 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1375 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1376 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
dfeae619
JR		 1377 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1378 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1379 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1380 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1381 { }
1382};
1383MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1384
1385static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1386 .driver = {
1387 .name = SC16IS7XX_NAME,
dfeae619
JR		 1388 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1389 },
1390 .probe = sc16is7xx_i2c_probe,
1391 .remove = sc16is7xx_i2c_remove,
1392 .id_table = sc16is7xx_i2c_id_table,
1393};
2c837a8a 1394
dfeae619 1395MODULE_ALIAS("i2c:sc16is7xx");
2c837a8a
RKKI		 1396#endif
1397
1398static int __init sc16is7xx_init(void)
1399{
1400 int ret = 0;
1401#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1402 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1403 if (ret < 0) {
1404 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1405 return ret;
1406 }
1407#endif
1408
1409#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1410 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1411 if (ret < 0) {
1412 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1413 return ret;
1414 }
1415#endif
1416 return ret;
1417}
1418module_init(sc16is7xx_init);
1419
1420static void __exit sc16is7xx_exit(void)
1421{
1422#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1423 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1424#endif
1425
1426#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1427 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1428#endif
1429}
1430module_exit(sc16is7xx_exit);
dfeae619
JR		 1431
1432MODULE_LICENSE("GPL");
1433MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1434MODULE_DESCRIPTION("SC16IS7XX serial driver");
Linux kernel - Deliverables
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