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serial: sh-sci: Remove unused GPIO request code
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
8fb9631c 42#include <linux/platform_device.h>
5e50d2d6 43#include <linux/pm_runtime.h>
73a19e4c 44#include <linux/scatterlist.h>
8fb9631c
LP		 45#include <linux/serial.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
5a0e3ad6 48#include <linux/slab.h>
8fb9631c
LP		 49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
1da177e4
LT		 59#include "sh-sci.h"
60
e108b2ca
PM		 61struct sci_port {
62 struct uart_port port;
63
ce6738b6
PM		 64 /* Platform configuration */
65 struct plat_sci_port *cfg;
3ae988d9
LP		 66 int overrun_bit;
67 unsigned int error_mask;
68
e108b2ca 69
e108b2ca
PM		 70 /* Break timer */
71 struct timer_list break_timer;
72 int break_flag;
1534a3b3 73
501b825d
MD		 74 /* Interface clock */
75 struct clk *iclk;
c7ed1ab3
PM		 76 /* Function clock */
77 struct clk *fclk;
edad1f20 78
1fcc91a6 79 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 80 char *irqstr[SCIx_NR_IRQS];
81
73a19e4c
GL		 82 struct dma_chan *chan_tx;
83 struct dma_chan *chan_rx;
f43dc23d 84
73a19e4c 85#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 86 struct dma_async_tx_descriptor *desc_tx;
87 struct dma_async_tx_descriptor *desc_rx[2];
88 dma_cookie_t cookie_tx;
89 dma_cookie_t cookie_rx[2];
90 dma_cookie_t active_rx;
91 struct scatterlist sg_tx;
92 unsigned int sg_len_tx;
93 struct scatterlist sg_rx[2];
94 size_t buf_len_rx;
95 struct sh_dmae_slave param_tx;
96 struct sh_dmae_slave param_rx;
97 struct work_struct work_tx;
98 struct work_struct work_rx;
99 struct timer_list rx_timer;
3089f381 100 unsigned int rx_timeout;
73a19e4c 101#endif
e552de24 102
d535a230 103 struct notifier_block freq_transition;
e108b2ca
PM		 104};
105
1da177e4 106/* Function prototypes */
d535a230 107static void sci_start_tx(struct uart_port *port);
b129a8cc 108static void sci_stop_tx(struct uart_port *port);
d535a230 109static void sci_start_rx(struct uart_port *port);
1da177e4 110
e108b2ca 111#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 112
e108b2ca
PM		 113static struct sci_port sci_ports[SCI_NPORTS];
114static struct uart_driver sci_uart_driver;
1da177e4 115
e7c98dc7
MT		 116static inline struct sci_port *
117to_sci_port(struct uart_port *uart)
118{
119 return container_of(uart, struct sci_port, port);
120}
121
61a6976b
PM		 122struct plat_sci_reg {
123 u8 offset, size;
124};
125
126/* Helper for invalidating specific entries of an inherited map. */
127#define sci_reg_invalid { .offset = 0, .size = 0 }
128
129static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
130 [SCIx_PROBE_REGTYPE] = {
131 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
132 },
133
134 /*
135 * Common SCI definitions, dependent on the port's regshift
136 * value.
137 */
138 [SCIx_SCI_REGTYPE] = {
139 [SCSMR] = { 0x00, 8 },
140 [SCBRR] = { 0x01, 8 },
141 [SCSCR] = { 0x02, 8 },
142 [SCxTDR] = { 0x03, 8 },
143 [SCxSR] = { 0x04, 8 },
144 [SCxRDR] = { 0x05, 8 },
145 [SCFCR] = sci_reg_invalid,
146 [SCFDR] = sci_reg_invalid,
147 [SCTFDR] = sci_reg_invalid,
148 [SCRFDR] = sci_reg_invalid,
149 [SCSPTR] = sci_reg_invalid,
150 [SCLSR] = sci_reg_invalid,
f303b364 151 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 152 },
153
154 /*
155 * Common definitions for legacy IrDA ports, dependent on
156 * regshift value.
157 */
158 [SCIx_IRDA_REGTYPE] = {
159 [SCSMR] = { 0x00, 8 },
160 [SCBRR] = { 0x01, 8 },
161 [SCSCR] = { 0x02, 8 },
162 [SCxTDR] = { 0x03, 8 },
163 [SCxSR] = { 0x04, 8 },
164 [SCxRDR] = { 0x05, 8 },
165 [SCFCR] = { 0x06, 8 },
166 [SCFDR] = { 0x07, 16 },
167 [SCTFDR] = sci_reg_invalid,
168 [SCRFDR] = sci_reg_invalid,
169 [SCSPTR] = sci_reg_invalid,
170 [SCLSR] = sci_reg_invalid,
f303b364 171 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 172 },
173
174 /*
175 * Common SCIFA definitions.
176 */
177 [SCIx_SCIFA_REGTYPE] = {
178 [SCSMR] = { 0x00, 16 },
179 [SCBRR] = { 0x04, 8 },
180 [SCSCR] = { 0x08, 16 },
181 [SCxTDR] = { 0x20, 8 },
182 [SCxSR] = { 0x14, 16 },
183 [SCxRDR] = { 0x24, 8 },
184 [SCFCR] = { 0x18, 16 },
185 [SCFDR] = { 0x1c, 16 },
186 [SCTFDR] = sci_reg_invalid,
187 [SCRFDR] = sci_reg_invalid,
188 [SCSPTR] = sci_reg_invalid,
189 [SCLSR] = sci_reg_invalid,
f303b364 190 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 191 },
192
193 /*
194 * Common SCIFB definitions.
195 */
196 [SCIx_SCIFB_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x40, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x60, 8 },
203 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 204 [SCFDR] = sci_reg_invalid,
205 [SCTFDR] = { 0x38, 16 },
206 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
f303b364 209 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 210 },
211
3af1f8a4
PE		 212 /*
213 * Common SH-2(A) SCIF definitions for ports with FIFO data
214 * count registers.
215 */
216 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
217 [SCSMR] = { 0x00, 16 },
218 [SCBRR] = { 0x04, 8 },
219 [SCSCR] = { 0x08, 16 },
220 [SCxTDR] = { 0x0c, 8 },
221 [SCxSR] = { 0x10, 16 },
222 [SCxRDR] = { 0x14, 8 },
223 [SCFCR] = { 0x18, 16 },
224 [SCFDR] = { 0x1c, 16 },
225 [SCTFDR] = sci_reg_invalid,
226 [SCRFDR] = sci_reg_invalid,
227 [SCSPTR] = { 0x20, 16 },
228 [SCLSR] = { 0x24, 16 },
f303b364 229 [HSSRR] = sci_reg_invalid,
3af1f8a4
PE		 230 },
231
61a6976b
PM		 232 /*
233 * Common SH-3 SCIF definitions.
234 */
235 [SCIx_SH3_SCIF_REGTYPE] = {
236 [SCSMR] = { 0x00, 8 },
237 [SCBRR] = { 0x02, 8 },
238 [SCSCR] = { 0x04, 8 },
239 [SCxTDR] = { 0x06, 8 },
240 [SCxSR] = { 0x08, 16 },
241 [SCxRDR] = { 0x0a, 8 },
242 [SCFCR] = { 0x0c, 8 },
243 [SCFDR] = { 0x0e, 16 },
244 [SCTFDR] = sci_reg_invalid,
245 [SCRFDR] = sci_reg_invalid,
246 [SCSPTR] = sci_reg_invalid,
247 [SCLSR] = sci_reg_invalid,
f303b364 248 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 249 },
250
251 /*
252 * Common SH-4(A) SCIF(B) definitions.
253 */
254 [SCIx_SH4_SCIF_REGTYPE] = {
255 [SCSMR] = { 0x00, 16 },
256 [SCBRR] = { 0x04, 8 },
257 [SCSCR] = { 0x08, 16 },
258 [SCxTDR] = { 0x0c, 8 },
259 [SCxSR] = { 0x10, 16 },
260 [SCxRDR] = { 0x14, 8 },
261 [SCFCR] = { 0x18, 16 },
262 [SCFDR] = { 0x1c, 16 },
263 [SCTFDR] = sci_reg_invalid,
264 [SCRFDR] = sci_reg_invalid,
265 [SCSPTR] = { 0x20, 16 },
266 [SCLSR] = { 0x24, 16 },
f303b364
UH		 267 [HSSRR] = sci_reg_invalid,
268 },
269
270 /*
271 * Common HSCIF definitions.
272 */
273 [SCIx_HSCIF_REGTYPE] = {
274 [SCSMR] = { 0x00, 16 },
275 [SCBRR] = { 0x04, 8 },
276 [SCSCR] = { 0x08, 16 },
277 [SCxTDR] = { 0x0c, 8 },
278 [SCxSR] = { 0x10, 16 },
279 [SCxRDR] = { 0x14, 8 },
280 [SCFCR] = { 0x18, 16 },
281 [SCFDR] = { 0x1c, 16 },
282 [SCTFDR] = sci_reg_invalid,
283 [SCRFDR] = sci_reg_invalid,
284 [SCSPTR] = { 0x20, 16 },
285 [SCLSR] = { 0x24, 16 },
286 [HSSRR] = { 0x40, 16 },
61a6976b
PM		 287 },
288
289 /*
290 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
291 * register.
292 */
293 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
294 [SCSMR] = { 0x00, 16 },
295 [SCBRR] = { 0x04, 8 },
296 [SCSCR] = { 0x08, 16 },
297 [SCxTDR] = { 0x0c, 8 },
298 [SCxSR] = { 0x10, 16 },
299 [SCxRDR] = { 0x14, 8 },
300 [SCFCR] = { 0x18, 16 },
301 [SCFDR] = { 0x1c, 16 },
302 [SCTFDR] = sci_reg_invalid,
303 [SCRFDR] = sci_reg_invalid,
304 [SCSPTR] = sci_reg_invalid,
305 [SCLSR] = { 0x24, 16 },
f303b364 306 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 307 },
308
309 /*
310 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
311 * count registers.
312 */
313 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
314 [SCSMR] = { 0x00, 16 },
315 [SCBRR] = { 0x04, 8 },
316 [SCSCR] = { 0x08, 16 },
317 [SCxTDR] = { 0x0c, 8 },
318 [SCxSR] = { 0x10, 16 },
319 [SCxRDR] = { 0x14, 8 },
320 [SCFCR] = { 0x18, 16 },
321 [SCFDR] = { 0x1c, 16 },
322 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
323 [SCRFDR] = { 0x20, 16 },
324 [SCSPTR] = { 0x24, 16 },
325 [SCLSR] = { 0x28, 16 },
f303b364 326 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 327 },
328
329 /*
330 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
331 * registers.
332 */
333 [SCIx_SH7705_SCIF_REGTYPE] = {
334 [SCSMR] = { 0x00, 16 },
335 [SCBRR] = { 0x04, 8 },
336 [SCSCR] = { 0x08, 16 },
337 [SCxTDR] = { 0x20, 8 },
338 [SCxSR] = { 0x14, 16 },
339 [SCxRDR] = { 0x24, 8 },
340 [SCFCR] = { 0x18, 16 },
341 [SCFDR] = { 0x1c, 16 },
342 [SCTFDR] = sci_reg_invalid,
343 [SCRFDR] = sci_reg_invalid,
344 [SCSPTR] = sci_reg_invalid,
345 [SCLSR] = sci_reg_invalid,
f303b364 346 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 347 },
348};
349
72b294cf
PM		 350#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
351
61a6976b
PM		 352/*
353 * The "offset" here is rather misleading, in that it refers to an enum
354 * value relative to the port mapping rather than the fixed offset
355 * itself, which needs to be manually retrieved from the platform's
356 * register map for the given port.
357 */
358static unsigned int sci_serial_in(struct uart_port *p, int offset)
359{
72b294cf 360 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 361
362 if (reg->size == 8)
363 return ioread8(p->membase + (reg->offset << p->regshift));
364 else if (reg->size == 16)
365 return ioread16(p->membase + (reg->offset << p->regshift));
366 else
367 WARN(1, "Invalid register access\n");
368
369 return 0;
370}
371
372static void sci_serial_out(struct uart_port *p, int offset, int value)
373{
72b294cf 374 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 375
376 if (reg->size == 8)
377 iowrite8(value, p->membase + (reg->offset << p->regshift));
378 else if (reg->size == 16)
379 iowrite16(value, p->membase + (reg->offset << p->regshift));
380 else
381 WARN(1, "Invalid register access\n");
382}
383
61a6976b
PM		 384static int sci_probe_regmap(struct plat_sci_port *cfg)
385{
386 switch (cfg->type) {
387 case PORT_SCI:
388 cfg->regtype = SCIx_SCI_REGTYPE;
389 break;
390 case PORT_IRDA:
391 cfg->regtype = SCIx_IRDA_REGTYPE;
392 break;
393 case PORT_SCIFA:
394 cfg->regtype = SCIx_SCIFA_REGTYPE;
395 break;
396 case PORT_SCIFB:
397 cfg->regtype = SCIx_SCIFB_REGTYPE;
398 break;
399 case PORT_SCIF:
400 /*
401 * The SH-4 is a bit of a misnomer here, although that's
402 * where this particular port layout originated. This
403 * configuration (or some slight variation thereof)
404 * remains the dominant model for all SCIFs.
405 */
406 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
407 break;
f303b364
UH		 408 case PORT_HSCIF:
409 cfg->regtype = SCIx_HSCIF_REGTYPE;
410 break;
61a6976b
PM		 411 default:
412 printk(KERN_ERR "Can't probe register map for given port\n");
413 return -EINVAL;
414 }
415
416 return 0;
417}
418
23241d43
PM		 419static void sci_port_enable(struct sci_port *sci_port)
420{
421 if (!sci_port->port.dev)
422 return;
423
424 pm_runtime_get_sync(sci_port->port.dev);
425
b016b646 426 clk_prepare_enable(sci_port->iclk);
23241d43 427 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 428 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 429}
430
431static void sci_port_disable(struct sci_port *sci_port)
432{
433 if (!sci_port->port.dev)
434 return;
435
caec7038
LP		 436 /* Cancel the break timer to ensure that the timer handler will not try
437 * to access the hardware with clocks and power disabled. Reset the
438 * break flag to make the break debouncing state machine ready for the
439 * next break.
440 */
441 del_timer_sync(&sci_port->break_timer);
442 sci_port->break_flag = 0;
443
b016b646
LP		 444 clk_disable_unprepare(sci_port->fclk);
445 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 446
447 pm_runtime_put_sync(sci_port->port.dev);
448}
449
07d2a1a1 450#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 451
452#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 453static int sci_poll_get_char(struct uart_port *port)
1da177e4 454{
1da177e4
LT		 455 unsigned short status;
456 int c;
457
e108b2ca 458 do {
b12bb29f 459 status = serial_port_in(port, SCxSR);
1da177e4 460 if (status & SCxSR_ERRORS(port)) {
b12bb29f 461 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 462 continue;
463 }
3f255eb3
JW		 464 break;
465 } while (1);
466
467 if (!(status & SCxSR_RDxF(port)))
468 return NO_POLL_CHAR;
07d2a1a1 469
b12bb29f 470 c = serial_port_in(port, SCxRDR);
07d2a1a1 471
e7c98dc7 472 /* Dummy read */
b12bb29f
PM		 473 serial_port_in(port, SCxSR);
474 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 475
476 return c;
477}
1f6fd5c9 478#endif
1da177e4 479
07d2a1a1 480static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 481{
1da177e4
LT		 482 unsigned short status;
483
1da177e4 484 do {
b12bb29f 485 status = serial_port_in(port, SCxSR);
1da177e4
LT		 486 } while (!(status & SCxSR_TDxE(port)));
487
b12bb29f
PM		 488 serial_port_out(port, SCxTDR, c);
489 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 490}
07d2a1a1 491#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 492
61a6976b 493static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 494{
61a6976b
PM		 495 struct sci_port *s = to_sci_port(port);
496 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 497
61a6976b
PM		 498 /*
499 * Use port-specific handler if provided.
500 */
501 if (s->cfg->ops && s->cfg->ops->init_pins) {
502 s->cfg->ops->init_pins(port, cflag);
503 return;
1da177e4 504 }
41504c39 505
61a6976b
PM		 506 /*
507 * For the generic path SCSPTR is necessary. Bail out if that's
508 * unavailable, too.
509 */
510 if (!reg->size)
511 return;
41504c39 512
faf02f8f
PM		 513 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
514 ((!(cflag & CRTSCTS)))) {
515 unsigned short status;
516
b12bb29f 517 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 518 status &= ~SCSPTR_CTSIO;
519 status |= SCSPTR_RTSIO;
b12bb29f 520 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 521 }
d5701647 522}
e108b2ca 523
72b294cf 524static int sci_txfill(struct uart_port *port)
e108b2ca 525{
72b294cf 526 struct plat_sci_reg *reg;
e108b2ca 527
72b294cf
PM		 528 reg = sci_getreg(port, SCTFDR);
529 if (reg->size)
63f7ad11 530 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 531
72b294cf
PM		 532 reg = sci_getreg(port, SCFDR);
533 if (reg->size)
b12bb29f 534 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 535
b12bb29f 536 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 537}
538
73a19e4c
GL		 539static int sci_txroom(struct uart_port *port)
540{
72b294cf 541 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 542}
543
544static int sci_rxfill(struct uart_port *port)
e108b2ca 545{
72b294cf
PM		 546 struct plat_sci_reg *reg;
547
548 reg = sci_getreg(port, SCRFDR);
549 if (reg->size)
63f7ad11 550 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 551
552 reg = sci_getreg(port, SCFDR);
553 if (reg->size)
b12bb29f 554 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 555
b12bb29f 556 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 557}
558
514820eb
PM		 559/*
560 * SCI helper for checking the state of the muxed port/RXD pins.
561 */
562static inline int sci_rxd_in(struct uart_port *port)
563{
564 struct sci_port *s = to_sci_port(port);
565
566 if (s->cfg->port_reg <= 0)
567 return 1;
568
0dd4d5cb 569 /* Cast for ARM damage */
e2afca69 570 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 571}
572
1da177e4
LT		 573/* ********************************************************************** *
574 * the interrupt related routines *
575 * ********************************************************************** */
576
577static void sci_transmit_chars(struct uart_port *port)
578{
ebd2c8f6 579 struct circ_buf *xmit = &port->state->xmit;
1da177e4 580 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 581 unsigned short status;
582 unsigned short ctrl;
e108b2ca 583 int count;
1da177e4 584
b12bb29f 585 status = serial_port_in(port, SCxSR);
1da177e4 586 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 587 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 588 if (uart_circ_empty(xmit))
8e698614 589 ctrl &= ~SCSCR_TIE;
e7c98dc7 590 else
8e698614 591 ctrl |= SCSCR_TIE;
b12bb29f 592 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 593 return;
594 }
595
72b294cf 596 count = sci_txroom(port);
1da177e4
LT		 597
598 do {
599 unsigned char c;
600
601 if (port->x_char) {
602 c = port->x_char;
603 port->x_char = 0;
604 } else if (!uart_circ_empty(xmit) && !stopped) {
605 c = xmit->buf[xmit->tail];
606 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
607 } else {
608 break;
609 }
610
b12bb29f 611 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 612
613 port->icount.tx++;
614 } while (--count > 0);
615
b12bb29f 616 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 617
618 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
619 uart_write_wakeup(port);
620 if (uart_circ_empty(xmit)) {
b129a8cc 621 sci_stop_tx(port);
1da177e4 622 } else {
b12bb29f 623 ctrl = serial_port_in(port, SCSCR);
1da177e4 624
1a22f08d 625 if (port->type != PORT_SCI) {
b12bb29f
PM		 626 serial_port_in(port, SCxSR); /* Dummy read */
627 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 628 }
1da177e4 629
8e698614 630 ctrl |= SCSCR_TIE;
b12bb29f 631 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 632 }
633}
634
635/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 636#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 637
94c8b6db 638static void sci_receive_chars(struct uart_port *port)
1da177e4 639{
e7c98dc7 640 struct sci_port *sci_port = to_sci_port(port);
227434f8 641 struct tty_port *tport = &port->state->port;
1da177e4
LT		 642 int i, count, copied = 0;
643 unsigned short status;
33f0f88f 644 unsigned char flag;
1da177e4 645
b12bb29f 646 status = serial_port_in(port, SCxSR);
1da177e4
LT		 647 if (!(status & SCxSR_RDxF(port)))
648 return;
649
650 while (1) {
1da177e4 651 /* Don't copy more bytes than there is room for in the buffer */
227434f8 652 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 653
654 /* If for any reason we can't copy more data, we're done! */
655 if (count == 0)
656 break;
657
658 if (port->type == PORT_SCI) {
b12bb29f 659 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 660 if (uart_handle_sysrq_char(port, c) ||
661 sci_port->break_flag)
1da177e4 662 count = 0;
e7c98dc7 663 else
92a19f9c 664 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 665 } else {
e7c98dc7 666 for (i = 0; i < count; i++) {
b12bb29f 667 char c = serial_port_in(port, SCxRDR);
d97fbbed 668
b12bb29f 669 status = serial_port_in(port, SCxSR);
1da177e4
LT		 670#if defined(CONFIG_CPU_SH3)
671 /* Skip "chars" during break */
e108b2ca 672 if (sci_port->break_flag) {
1da177e4
LT		 673 if ((c == 0) &&
674 (status & SCxSR_FER(port))) {
675 count--; i--;
676 continue;
677 }
e108b2ca 678
1da177e4 679 /* Nonzero => end-of-break */
762c69e3 680 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 681 sci_port->break_flag = 0;
682
1da177e4
LT		 683 if (STEPFN(c)) {
684 count--; i--;
685 continue;
686 }
687 }
688#endif /* CONFIG_CPU_SH3 */
7d12e780 689 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 690 count--; i--;
691 continue;
692 }
693
694 /* Store data and status */
73a19e4c 695 if (status & SCxSR_FER(port)) {
33f0f88f 696 flag = TTY_FRAME;
d97fbbed 697 port->icount.frame++;
762c69e3 698 dev_notice(port->dev, "frame error\n");
73a19e4c 699 } else if (status & SCxSR_PER(port)) {
33f0f88f 700 flag = TTY_PARITY;
d97fbbed 701 port->icount.parity++;
762c69e3 702 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 703 } else
704 flag = TTY_NORMAL;
762c69e3 705
92a19f9c 706 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 707 }
708 }
709
b12bb29f
PM		 710 serial_port_in(port, SCxSR); /* dummy read */
711 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 712
1da177e4
LT		 713 copied += count;
714 port->icount.rx += count;
715 }
716
717 if (copied) {
718 /* Tell the rest of the system the news. New characters! */
2e124b4a 719 tty_flip_buffer_push(tport);
1da177e4 720 } else {
b12bb29f
PM		 721 serial_port_in(port, SCxSR); /* dummy read */
722 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 723 }
724}
725
726#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 727
728/*
729 * The sci generates interrupts during the break,
1da177e4
LT		 730 * 1 per millisecond or so during the break period, for 9600 baud.
731 * So dont bother disabling interrupts.
732 * But dont want more than 1 break event.
733 * Use a kernel timer to periodically poll the rx line until
734 * the break is finished.
735 */
94c8b6db 736static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 737{
bc9b3f5c 738 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 739}
94c8b6db 740
1da177e4
LT		 741/* Ensure that two consecutive samples find the break over. */
742static void sci_break_timer(unsigned long data)
743{
e108b2ca
PM		 744 struct sci_port *port = (struct sci_port *)data;
745
746 if (sci_rxd_in(&port->port) == 0) {
1da177e4 747 port->break_flag = 1;
e108b2ca
PM		 748 sci_schedule_break_timer(port);
749 } else if (port->break_flag == 1) {
1da177e4
LT		 750 /* break is over. */
751 port->break_flag = 2;
e108b2ca
PM		 752 sci_schedule_break_timer(port);
753 } else
754 port->break_flag = 0;
1da177e4
LT		 755}
756
94c8b6db 757static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 758{
759 int copied = 0;
b12bb29f 760 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 761 struct tty_port *tport = &port->state->port;
debf9507 762 struct sci_port *s = to_sci_port(port);
1da177e4 763
3ae988d9
LP		 764 /* Handle overruns */
765 if (status & (1 << s->overrun_bit)) {
766 port->icount.overrun++;
d97fbbed 767
3ae988d9
LP		 768 /* overrun error */
769 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
770 copied++;
762c69e3 771
3ae988d9 772 dev_notice(port->dev, "overrun error");
1da177e4
LT		 773 }
774
e108b2ca 775 if (status & SCxSR_FER(port)) {
1da177e4
LT		 776 if (sci_rxd_in(port) == 0) {
777 /* Notify of BREAK */
e7c98dc7 778 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 779
780 if (!sci_port->break_flag) {
d97fbbed
PM		 781 port->icount.brk++;
782
e108b2ca
PM		 783 sci_port->break_flag = 1;
784 sci_schedule_break_timer(sci_port);
785
1da177e4 786 /* Do sysrq handling. */
e108b2ca 787 if (uart_handle_break(port))
1da177e4 788 return 0;
762c69e3
PM		 789
790 dev_dbg(port->dev, "BREAK detected\n");
791
92a19f9c 792 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 793 copied++;
794 }
795
e108b2ca 796 } else {
1da177e4 797 /* frame error */
d97fbbed
PM		 798 port->icount.frame++;
799
92a19f9c 800 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 801 copied++;
762c69e3
PM		 802
803 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 804 }
805 }
806
e108b2ca 807 if (status & SCxSR_PER(port)) {
1da177e4 808 /* parity error */
d97fbbed
PM		 809 port->icount.parity++;
810
92a19f9c 811 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 812 copied++;
762c69e3
PM		 813
814 dev_notice(port->dev, "parity error");
1da177e4
LT		 815 }
816
33f0f88f 817 if (copied)
2e124b4a 818 tty_flip_buffer_push(tport);
1da177e4
LT		 819
820 return copied;
821}
822
94c8b6db 823static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 824{
92a19f9c 825 struct tty_port *tport = &port->state->port;
debf9507 826 struct sci_port *s = to_sci_port(port);
4b8c59a3 827 struct plat_sci_reg *reg;
d830fa45
PM		 828 int copied = 0;
829
4b8c59a3
PM		 830 reg = sci_getreg(port, SCLSR);
831 if (!reg->size)
d830fa45
PM		 832 return 0;
833
3ae988d9 834 if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) {
b12bb29f 835 serial_port_out(port, SCLSR, 0);
d830fa45 836
d97fbbed
PM		 837 port->icount.overrun++;
838
92a19f9c 839 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 840 tty_flip_buffer_push(tport);
d830fa45
PM		 841
842 dev_notice(port->dev, "overrun error\n");
843 copied++;
844 }
845
846 return copied;
847}
848
94c8b6db 849static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 850{
851 int copied = 0;
b12bb29f 852 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 853 struct tty_port *tport = &port->state->port;
a5660ada 854 struct sci_port *s = to_sci_port(port);
1da177e4 855
0b3d4ef6
PM		 856 if (uart_handle_break(port))
857 return 0;
858
b7a76e4b 859 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 860#if defined(CONFIG_CPU_SH3)
861 /* Debounce break */
862 s->break_flag = 1;
863#endif
d97fbbed
PM		 864
865 port->icount.brk++;
866
1da177e4 867 /* Notify of BREAK */
92a19f9c 868 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 869 copied++;
762c69e3
PM		 870
871 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 872 }
873
33f0f88f 874 if (copied)
2e124b4a 875 tty_flip_buffer_push(tport);
e108b2ca 876
d830fa45
PM		 877 copied += sci_handle_fifo_overrun(port);
878
1da177e4
LT		 879 return copied;
880}
881
73a19e4c 882static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 883{
73a19e4c
GL		 884#ifdef CONFIG_SERIAL_SH_SCI_DMA
885 struct uart_port *port = ptr;
886 struct sci_port *s = to_sci_port(port);
887
888 if (s->chan_rx) {
b12bb29f
PM		 889 u16 scr = serial_port_in(port, SCSCR);
890 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 891
892 /* Disable future Rx interrupts */
d1d4b10c 893 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 894 disable_irq_nosync(irq);
895 scr |= 0x4000;
896 } else {
f43dc23d 897 scr &= ~SCSCR_RIE;
3089f381 898 }
b12bb29f 899 serial_port_out(port, SCSCR, scr);
73a19e4c 900 /* Clear current interrupt */
b12bb29f 901 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 902 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
903 jiffies, s->rx_timeout);
904 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 905
906 return IRQ_HANDLED;
907 }
908#endif
909
1da177e4
LT		 910 /* I think sci_receive_chars has to be called irrespective
911 * of whether the I_IXOFF is set, otherwise, how is the interrupt
912 * to be disabled?
913 */
73a19e4c 914 sci_receive_chars(ptr);
1da177e4
LT		 915
916 return IRQ_HANDLED;
917}
918
7d12e780 919static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 920{
921 struct uart_port *port = ptr;
fd78a76a 922 unsigned long flags;
1da177e4 923
fd78a76a 924 spin_lock_irqsave(&port->lock, flags);
1da177e4 925 sci_transmit_chars(port);
fd78a76a 926 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 927
928 return IRQ_HANDLED;
929}
930
7d12e780 931static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 932{
933 struct uart_port *port = ptr;
934
935 /* Handle errors */
936 if (port->type == PORT_SCI) {
937 if (sci_handle_errors(port)) {
938 /* discard character in rx buffer */
b12bb29f
PM		 939 serial_port_in(port, SCxSR);
940 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 941 }
942 } else {
d830fa45 943 sci_handle_fifo_overrun(port);
7d12e780 944 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 945 }
946
b12bb29f 947 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 948
949 /* Kick the transmission */
7d12e780 950 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 951
952 return IRQ_HANDLED;
953}
954
7d12e780 955static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 956{
957 struct uart_port *port = ptr;
958
959 /* Handle BREAKs */
960 sci_handle_breaks(port);
b12bb29f 961 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 962
963 return IRQ_HANDLED;
964}
965
f43dc23d
PM		 966static inline unsigned long port_rx_irq_mask(struct uart_port *port)
967{
968 /*
969 * Not all ports (such as SCIFA) will support REIE. Rather than
970 * special-casing the port type, we check the port initialization
971 * IRQ enable mask to see whether the IRQ is desired at all. If
972 * it's unset, it's logically inferred that there's no point in
973 * testing for it.
974 */
ce6738b6 975 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 976}
977
7d12e780 978static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 979{
44e18e9e 980 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 981 struct uart_port *port = ptr;
73a19e4c 982 struct sci_port *s = to_sci_port(port);
a8884e34 983 irqreturn_t ret = IRQ_NONE;
1da177e4 984
b12bb29f
PM		 985 ssr_status = serial_port_in(port, SCxSR);
986 scr_status = serial_port_in(port, SCSCR);
f43dc23d 987 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 988
989 /* Tx Interrupt */
f43dc23d 990 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 991 !s->chan_tx)
a8884e34 992 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 993
73a19e4c
GL		 994 /*
995 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
996 * DR flags
997 */
998 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 999 (scr_status & SCSCR_RIE))
a8884e34 1000 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 1001
1da177e4 1002 /* Error Interrupt */
dd4da3a5 1003 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1004 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1005
1da177e4 1006 /* Break Interrupt */
dd4da3a5 1007 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1008 ret = sci_br_interrupt(irq, ptr);
1da177e4 1009
a8884e34 1010 return ret;
1da177e4
LT		 1011}
1012
1da177e4 1013/*
25985edc 1014 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1015 * ports' baud rate when the peripheral clock changes.
1016 */
e108b2ca
PM		 1017static int sci_notifier(struct notifier_block *self,
1018 unsigned long phase, void *p)
1da177e4 1019{
e552de24
MD		 1020 struct sci_port *sci_port;
1021 unsigned long flags;
1da177e4 1022
d535a230
PM		 1023 sci_port = container_of(self, struct sci_port, freq_transition);
1024
1da177e4 1025 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 1026 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 1027 struct uart_port *port = &sci_port->port;
073e84c9 1028
d535a230
PM		 1029 spin_lock_irqsave(&port->lock, flags);
1030 port->uartclk = clk_get_rate(sci_port->iclk);
1031 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1032 }
1da177e4 1033
1da177e4
LT		 1034 return NOTIFY_OK;
1035}
501b825d 1036
9174fc8f
PM		 1037static struct sci_irq_desc {
1038 const char *desc;
1039 irq_handler_t handler;
1040} sci_irq_desc[] = {
1041 /*
1042 * Split out handlers, the default case.
1043 */
1044 [SCIx_ERI_IRQ] = {
1045 .desc = "rx err",
1046 .handler = sci_er_interrupt,
1047 },
1048
1049 [SCIx_RXI_IRQ] = {
1050 .desc = "rx full",
1051 .handler = sci_rx_interrupt,
1052 },
1053
1054 [SCIx_TXI_IRQ] = {
1055 .desc = "tx empty",
1056 .handler = sci_tx_interrupt,
1057 },
1058
1059 [SCIx_BRI_IRQ] = {
1060 .desc = "break",
1061 .handler = sci_br_interrupt,
1062 },
1063
1064 /*
1065 * Special muxed handler.
1066 */
1067 [SCIx_MUX_IRQ] = {
1068 .desc = "mux",
1069 .handler = sci_mpxed_interrupt,
1070 },
1071};
1072
1da177e4
LT		 1073static int sci_request_irq(struct sci_port *port)
1074{
9174fc8f
PM		 1075 struct uart_port *up = &port->port;
1076 int i, j, ret = 0;
1077
1078 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1079 struct sci_irq_desc *desc;
1fcc91a6 1080 int irq;
9174fc8f
PM		 1081
1082 if (SCIx_IRQ_IS_MUXED(port)) {
1083 i = SCIx_MUX_IRQ;
1084 irq = up->irq;
0e8963de 1085 } else {
1fcc91a6 1086 irq = port->irqs[i];
9174fc8f 1087
0e8963de
PM		 1088 /*
1089 * Certain port types won't support all of the
1090 * available interrupt sources.
1091 */
1fcc91a6 1092 if (unlikely(irq < 0))
0e8963de
PM		 1093 continue;
1094 }
1095
9174fc8f
PM		 1096 desc = sci_irq_desc + i;
1097 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1098 dev_name(up->dev), desc->desc);
1099 if (!port->irqstr[j]) {
1100 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1101 desc->desc);
1102 goto out_nomem;
1da177e4 1103 }
9174fc8f
PM		 1104
1105 ret = request_irq(irq, desc->handler, up->irqflags,
1106 port->irqstr[j], port);
1107 if (unlikely(ret)) {
1108 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1109 goto out_noirq;
1da177e4
LT		 1110 }
1111 }
1112
1113 return 0;
9174fc8f
PM		 1114
1115out_noirq:
1116 while (--i >= 0)
1fcc91a6 1117 free_irq(port->irqs[i], port);
9174fc8f
PM		 1118
1119out_nomem:
1120 while (--j >= 0)
1121 kfree(port->irqstr[j]);
1122
1123 return ret;
1da177e4
LT		 1124}
1125
1126static void sci_free_irq(struct sci_port *port)
1127{
1128 int i;
1129
9174fc8f
PM		 1130 /*
1131 * Intentionally in reverse order so we iterate over the muxed
1132 * IRQ first.
1133 */
1134 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1135 int irq = port->irqs[i];
0e8963de
PM		 1136
1137 /*
1138 * Certain port types won't support all of the available
1139 * interrupt sources.
1140 */
1fcc91a6 1141 if (unlikely(irq < 0))
0e8963de
PM		 1142 continue;
1143
1fcc91a6 1144 free_irq(port->irqs[i], port);
9174fc8f 1145 kfree(port->irqstr[i]);
1da177e4 1146
9174fc8f
PM		 1147 if (SCIx_IRQ_IS_MUXED(port)) {
1148 /* If there's only one IRQ, we're done. */
1149 return;
1da177e4
LT		 1150 }
1151 }
1152}
1153
1154static unsigned int sci_tx_empty(struct uart_port *port)
1155{
b12bb29f 1156 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1157 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1158
1159 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1160}
1161
cdf7c42f
PM		 1162/*
1163 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1164 * CTS/RTS is supported in hardware by at least one port and controlled
1165 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1166 * handled via the ->init_pins() op, which is a bit of a one-way street,
1167 * lacking any ability to defer pin control -- this will later be
1168 * converted over to the GPIO framework).
dc7e3ef7
PM		 1169 *
1170 * Other modes (such as loopback) are supported generically on certain
1171 * port types, but not others. For these it's sufficient to test for the
1172 * existence of the support register and simply ignore the port type.
cdf7c42f 1173 */
1da177e4
LT		 1174static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1175{
dc7e3ef7
PM		 1176 if (mctrl & TIOCM_LOOP) {
1177 struct plat_sci_reg *reg;
1178
1179 /*
1180 * Standard loopback mode for SCFCR ports.
1181 */
1182 reg = sci_getreg(port, SCFCR);
1183 if (reg->size)
b12bb29f 1184 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1185 }
1da177e4
LT		 1186}
1187
1188static unsigned int sci_get_mctrl(struct uart_port *port)
1189{
cdf7c42f
PM		 1190 /*
1191 * CTS/RTS is handled in hardware when supported, while nothing
1192 * else is wired up. Keep it simple and simply assert DSR/CAR.
1193 */
1194 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1195}
1196
73a19e4c
GL		 1197#ifdef CONFIG_SERIAL_SH_SCI_DMA
1198static void sci_dma_tx_complete(void *arg)
1199{
1200 struct sci_port *s = arg;
1201 struct uart_port *port = &s->port;
1202 struct circ_buf *xmit = &port->state->xmit;
1203 unsigned long flags;
1204
1205 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1206
1207 spin_lock_irqsave(&port->lock, flags);
1208
f354a381 1209 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1210 xmit->tail &= UART_XMIT_SIZE - 1;
1211
f354a381 1212 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1213
1214 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1215 s->desc_tx = NULL;
1216
73a19e4c
GL		 1217 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1218 uart_write_wakeup(port);
1219
3089f381 1220 if (!uart_circ_empty(xmit)) {
49d4bcad 1221 s->cookie_tx = 0;
73a19e4c 1222 schedule_work(&s->work_tx);
49d4bcad
YT		 1223 } else {
1224 s->cookie_tx = -EINVAL;
1225 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1226 u16 ctrl = serial_port_in(port, SCSCR);
1227 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1228 }
3089f381
GL		 1229 }
1230
1231 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1232}
1233
1234/* Locking: called with port lock held */
92a19f9c 1235static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1236{
1237 struct uart_port *port = &s->port;
227434f8 1238 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1239 int i, active, room;
1240
227434f8 1241 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1242
1243 if (s->active_rx == s->cookie_rx[0]) {
1244 active = 0;
1245 } else if (s->active_rx == s->cookie_rx[1]) {
1246 active = 1;
1247 } else {
1248 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1249 return 0;
1250 }
1251
1252 if (room < count)
e2afca69 1253 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1254 count - room);
1255 if (!room)
1256 return room;
1257
1258 for (i = 0; i < room; i++)
92a19f9c 1259 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1260 TTY_NORMAL);
1261
1262 port->icount.rx += room;
1263
1264 return room;
1265}
1266
1267static void sci_dma_rx_complete(void *arg)
1268{
1269 struct sci_port *s = arg;
1270 struct uart_port *port = &s->port;
73a19e4c
GL		 1271 unsigned long flags;
1272 int count;
1273
3089f381 1274 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1275
1276 spin_lock_irqsave(&port->lock, flags);
1277
92a19f9c 1278 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1279
3089f381 1280 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1281
1282 spin_unlock_irqrestore(&port->lock, flags);
1283
1284 if (count)
2e124b4a 1285 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1286
1287 schedule_work(&s->work_rx);
1288}
1289
73a19e4c
GL		 1290static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1291{
1292 struct dma_chan *chan = s->chan_rx;
1293 struct uart_port *port = &s->port;
73a19e4c
GL		 1294
1295 s->chan_rx = NULL;
1296 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1297 dma_release_channel(chan);
85b8e3ff
GL		 1298 if (sg_dma_address(&s->sg_rx[0]))
1299 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1300 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1301 if (enable_pio)
1302 sci_start_rx(port);
1303}
1304
1305static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1306{
1307 struct dma_chan *chan = s->chan_tx;
1308 struct uart_port *port = &s->port;
73a19e4c
GL		 1309
1310 s->chan_tx = NULL;
1311 s->cookie_tx = -EINVAL;
1312 dma_release_channel(chan);
1313 if (enable_pio)
1314 sci_start_tx(port);
1315}
1316
1317static void sci_submit_rx(struct sci_port *s)
1318{
1319 struct dma_chan *chan = s->chan_rx;
1320 int i;
1321
1322 for (i = 0; i < 2; i++) {
1323 struct scatterlist *sg = &s->sg_rx[i];
1324 struct dma_async_tx_descriptor *desc;
1325
16052827 1326 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1327 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1328
1329 if (desc) {
1330 s->desc_rx[i] = desc;
1331 desc->callback = sci_dma_rx_complete;
1332 desc->callback_param = s;
1333 s->cookie_rx[i] = desc->tx_submit(desc);
1334 }
1335
1336 if (!desc || s->cookie_rx[i] < 0) {
1337 if (i) {
1338 async_tx_ack(s->desc_rx[0]);
1339 s->cookie_rx[0] = -EINVAL;
1340 }
1341 if (desc) {
1342 async_tx_ack(desc);
1343 s->cookie_rx[i] = -EINVAL;
1344 }
1345 dev_warn(s->port.dev,
1346 "failed to re-start DMA, using PIO\n");
1347 sci_rx_dma_release(s, true);
1348 return;
1349 }
3089f381
GL		 1350 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1351 s->cookie_rx[i], i);
73a19e4c
GL		 1352 }
1353
1354 s->active_rx = s->cookie_rx[0];
1355
1356 dma_async_issue_pending(chan);
1357}
1358
1359static void work_fn_rx(struct work_struct *work)
1360{
1361 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1362 struct uart_port *port = &s->port;
1363 struct dma_async_tx_descriptor *desc;
1364 int new;
1365
1366 if (s->active_rx == s->cookie_rx[0]) {
1367 new = 0;
1368 } else if (s->active_rx == s->cookie_rx[1]) {
1369 new = 1;
1370 } else {
1371 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1372 return;
1373 }
1374 desc = s->desc_rx[new];
1375
1376 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1377 DMA_COMPLETE) {
73a19e4c 1378 /* Handle incomplete DMA receive */
73a19e4c 1379 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1380 struct shdma_desc *sh_desc = container_of(desc,
1381 struct shdma_desc, async_tx);
73a19e4c
GL		 1382 unsigned long flags;
1383 int count;
1384
05827630 1385 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
e2afca69 1386 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
73a19e4c
GL		 1387 sh_desc->partial, sh_desc->cookie);
1388
1389 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1390 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1391 spin_unlock_irqrestore(&port->lock, flags);
1392
1393 if (count)
2e124b4a 1394 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1395
1396 sci_submit_rx(s);
1397
1398 return;
1399 }
1400
1401 s->cookie_rx[new] = desc->tx_submit(desc);
1402 if (s->cookie_rx[new] < 0) {
1403 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1404 sci_rx_dma_release(s, true);
1405 return;
1406 }
1407
73a19e4c 1408 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1409
1410 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1411 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1412}
1413
1414static void work_fn_tx(struct work_struct *work)
1415{
1416 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1417 struct dma_async_tx_descriptor *desc;
1418 struct dma_chan *chan = s->chan_tx;
1419 struct uart_port *port = &s->port;
1420 struct circ_buf *xmit = &port->state->xmit;
1421 struct scatterlist *sg = &s->sg_tx;
1422
1423 /*
1424 * DMA is idle now.
1425 * Port xmit buffer is already mapped, and it is one page... Just adjust
1426 * offsets and lengths. Since it is a circular buffer, we have to
1427 * transmit till the end, and then the rest. Take the port lock to get a
1428 * consistent xmit buffer state.
1429 */
1430 spin_lock_irq(&port->lock);
1431 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1432 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1433 sg->offset;
f354a381 1434 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1435 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1436 spin_unlock_irq(&port->lock);
1437
f354a381 1438 BUG_ON(!sg_dma_len(sg));
73a19e4c 1439
16052827 1440 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1441 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1442 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1443 if (!desc) {
1444 /* switch to PIO */
1445 sci_tx_dma_release(s, true);
1446 return;
1447 }
1448
1449 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1450
1451 spin_lock_irq(&port->lock);
1452 s->desc_tx = desc;
1453 desc->callback = sci_dma_tx_complete;
1454 desc->callback_param = s;
1455 spin_unlock_irq(&port->lock);
1456 s->cookie_tx = desc->tx_submit(desc);
1457 if (s->cookie_tx < 0) {
1458 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1459 /* switch to PIO */
1460 sci_tx_dma_release(s, true);
1461 return;
1462 }
1463
1464 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1465 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1466
1467 dma_async_issue_pending(chan);
1468}
1469#endif
1470
b129a8cc 1471static void sci_start_tx(struct uart_port *port)
1da177e4 1472{
3089f381 1473 struct sci_port *s = to_sci_port(port);
e108b2ca 1474 unsigned short ctrl;
1da177e4 1475
73a19e4c 1476#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1477 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1478 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1479 if (s->chan_tx)
1480 new = scr | 0x8000;
1481 else
1482 new = scr & ~0x8000;
1483 if (new != scr)
b12bb29f 1484 serial_port_out(port, SCSCR, new);
73a19e4c 1485 }
f43dc23d 1486
3089f381 1487 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1488 s->cookie_tx < 0) {
1489 s->cookie_tx = 0;
3089f381 1490 schedule_work(&s->work_tx);
49d4bcad 1491 }
73a19e4c 1492#endif
f43dc23d 1493
d1d4b10c 1494 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1495 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1496 ctrl = serial_port_in(port, SCSCR);
1497 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1498 }
1da177e4
LT		 1499}
1500
b129a8cc 1501static void sci_stop_tx(struct uart_port *port)
1da177e4 1502{
1da177e4
LT		 1503 unsigned short ctrl;
1504
1505 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1506 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1507
d1d4b10c 1508 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1509 ctrl &= ~0x8000;
f43dc23d 1510
8e698614 1511 ctrl &= ~SCSCR_TIE;
f43dc23d 1512
b12bb29f 1513 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1514}
1515
73a19e4c 1516static void sci_start_rx(struct uart_port *port)
1da177e4 1517{
1da177e4
LT		 1518 unsigned short ctrl;
1519
b12bb29f 1520 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1521
d1d4b10c 1522 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1523 ctrl &= ~0x4000;
f43dc23d 1524
b12bb29f 1525 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1526}
1527
1528static void sci_stop_rx(struct uart_port *port)
1529{
1da177e4
LT		 1530 unsigned short ctrl;
1531
b12bb29f 1532 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1533
d1d4b10c 1534 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1535 ctrl &= ~0x4000;
f43dc23d
PM		 1536
1537 ctrl &= ~port_rx_irq_mask(port);
1538
b12bb29f 1539 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1540}
1541
1542static void sci_enable_ms(struct uart_port *port)
1543{
d39ec6ce
PM		 1544 /*
1545 * Not supported by hardware, always a nop.
1546 */
1da177e4
LT		 1547}
1548
1549static void sci_break_ctl(struct uart_port *port, int break_state)
1550{
bbb4ce50 1551 struct sci_port *s = to_sci_port(port);
a4e02f6d 1552 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1553 unsigned short scscr, scsptr;
1554
a4e02f6d
SY		 1555 /* check wheter the port has SCSPTR */
1556 if (!reg->size) {
bbb4ce50
SY		 1557 /*
1558 * Not supported by hardware. Most parts couple break and rx
1559 * interrupts together, with break detection always enabled.
1560 */
a4e02f6d 1561 return;
bbb4ce50 1562 }
a4e02f6d
SY		 1563
1564 scsptr = serial_port_in(port, SCSPTR);
1565 scscr = serial_port_in(port, SCSCR);
1566
1567 if (break_state == -1) {
1568 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1569 scscr &= ~SCSCR_TE;
1570 } else {
1571 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1572 scscr |= SCSCR_TE;
1573 }
1574
1575 serial_port_out(port, SCSPTR, scsptr);
1576 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1577}
1578
73a19e4c
GL		 1579#ifdef CONFIG_SERIAL_SH_SCI_DMA
1580static bool filter(struct dma_chan *chan, void *slave)
1581{
1582 struct sh_dmae_slave *param = slave;
1583
1584 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
d6fa5a4e 1585 param->shdma_slave.slave_id);
73a19e4c 1586
d6fa5a4e 1587 chan->private = &param->shdma_slave;
937bb6e4 1588 return true;
73a19e4c
GL		 1589}
1590
1591static void rx_timer_fn(unsigned long arg)
1592{
1593 struct sci_port *s = (struct sci_port *)arg;
1594 struct uart_port *port = &s->port;
b12bb29f 1595 u16 scr = serial_port_in(port, SCSCR);
3089f381 1596
d1d4b10c 1597 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1598 scr &= ~0x4000;
1fcc91a6 1599 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1600 }
b12bb29f 1601 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1602 dev_dbg(port->dev, "DMA Rx timed out\n");
1603 schedule_work(&s->work_rx);
1604}
1605
1606static void sci_request_dma(struct uart_port *port)
1607{
1608 struct sci_port *s = to_sci_port(port);
1609 struct sh_dmae_slave *param;
1610 struct dma_chan *chan;
1611 dma_cap_mask_t mask;
1612 int nent;
1613
937bb6e4
GL		 1614 dev_dbg(port->dev, "%s: port %d\n", __func__,
1615 port->line);
73a19e4c 1616
937bb6e4 1617 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1618 return;
1619
1620 dma_cap_zero(mask);
1621 dma_cap_set(DMA_SLAVE, mask);
1622
1623 param = &s->param_tx;
1624
1625 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1626 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1627
1628 s->cookie_tx = -EINVAL;
1629 chan = dma_request_channel(mask, filter, param);
1630 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1631 if (chan) {
1632 s->chan_tx = chan;
1633 sg_init_table(&s->sg_tx, 1);
1634 /* UART circular tx buffer is an aligned page. */
e2afca69 1635 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c 1636 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
e2afca69
LP		 1637 UART_XMIT_SIZE,
1638 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c
GL		 1639 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1640 if (!nent)
1641 sci_tx_dma_release(s, false);
1642 else
e2afca69
LP		 1643 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1644 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1645 &sg_dma_address(&s->sg_tx));
73a19e4c
GL		 1646
1647 s->sg_len_tx = nent;
1648
1649 INIT_WORK(&s->work_tx, work_fn_tx);
1650 }
1651
1652 param = &s->param_rx;
1653
1654 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1655 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1656
1657 chan = dma_request_channel(mask, filter, param);
1658 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1659 if (chan) {
1660 dma_addr_t dma[2];
1661 void *buf[2];
1662 int i;
1663
1664 s->chan_rx = chan;
1665
1666 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1667 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1668 &dma[0], GFP_KERNEL);
1669
1670 if (!buf[0]) {
1671 dev_warn(port->dev,
1672 "failed to allocate dma buffer, using PIO\n");
1673 sci_rx_dma_release(s, true);
1674 return;
1675 }
1676
1677 buf[1] = buf[0] + s->buf_len_rx;
1678 dma[1] = dma[0] + s->buf_len_rx;
1679
1680 for (i = 0; i < 2; i++) {
1681 struct scatterlist *sg = &s->sg_rx[i];
1682
1683 sg_init_table(sg, 1);
1684 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1685 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1686 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1687 }
1688
1689 INIT_WORK(&s->work_rx, work_fn_rx);
1690 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1691
1692 sci_submit_rx(s);
1693 }
1694}
1695
1696static void sci_free_dma(struct uart_port *port)
1697{
1698 struct sci_port *s = to_sci_port(port);
1699
73a19e4c
GL		 1700 if (s->chan_tx)
1701 sci_tx_dma_release(s, false);
1702 if (s->chan_rx)
1703 sci_rx_dma_release(s, false);
1704}
27bd1075
PM		 1705#else
1706static inline void sci_request_dma(struct uart_port *port)
1707{
1708}
1709
1710static inline void sci_free_dma(struct uart_port *port)
1711{
1712}
73a19e4c
GL		 1713#endif
1714
1da177e4
LT		 1715static int sci_startup(struct uart_port *port)
1716{
a5660ada 1717 struct sci_port *s = to_sci_port(port);
33b48e16 1718 unsigned long flags;
073e84c9 1719 int ret;
1da177e4 1720
73a19e4c
GL		 1721 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1722
073e84c9
PM		 1723 ret = sci_request_irq(s);
1724 if (unlikely(ret < 0))
1725 return ret;
1726
73a19e4c 1727 sci_request_dma(port);
073e84c9 1728
33b48e16 1729 spin_lock_irqsave(&port->lock, flags);
d656901b 1730 sci_start_tx(port);
73a19e4c 1731 sci_start_rx(port);
33b48e16 1732 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1733
1734 return 0;
1735}
1736
1737static void sci_shutdown(struct uart_port *port)
1738{
a5660ada 1739 struct sci_port *s = to_sci_port(port);
33b48e16 1740 unsigned long flags;
1da177e4 1741
73a19e4c
GL		 1742 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1743
33b48e16 1744 spin_lock_irqsave(&port->lock, flags);
1da177e4 1745 sci_stop_rx(port);
b129a8cc 1746 sci_stop_tx(port);
33b48e16 1747 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1748
73a19e4c 1749 sci_free_dma(port);
1da177e4 1750 sci_free_irq(s);
1da177e4
LT		 1751}
1752
26c92f37
PM		 1753static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1754 unsigned long freq)
1755{
1756 switch (algo_id) {
1757 case SCBRR_ALGO_1:
6557b1f6 1758 return freq / (16 * bps);
26c92f37 1759 case SCBRR_ALGO_2:
6557b1f6 1760 return DIV_ROUND_CLOSEST(freq, 32 * bps) - 1;
26c92f37 1761 case SCBRR_ALGO_3:
6557b1f6 1762 return freq / (8 * bps);
26c92f37 1763 case SCBRR_ALGO_4:
6557b1f6 1764 return DIV_ROUND_CLOSEST(freq, 16 * bps) - 1;
26c92f37
PM		 1765 }
1766
1767 /* Warn, but use a safe default */
1768 WARN_ON(1);
e8183a6c 1769
26c92f37
PM		 1770 return ((freq + 16 * bps) / (32 * bps) - 1);
1771}
1772
f303b364
UH		 1773/* calculate sample rate, BRR, and clock select for HSCIF */
1774static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1775 int *brr, unsigned int *srr,
1776 unsigned int *cks)
1777{
1778 int sr, c, br, err;
1779 int min_err = 1000; /* 100% */
1780
1781 /* Find the combination of sample rate and clock select with the
1782 smallest deviation from the desired baud rate. */
1783 for (sr = 8; sr <= 32; sr++) {
1784 for (c = 0; c <= 3; c++) {
1785 /* integerized formulas from HSCIF documentation */
1786 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1787 if (br < 0 || br > 255)
1788 continue;
1789 err = freq / ((br + 1) * bps * sr *
1790 (1 << (2 * c + 1)) / 1000) - 1000;
1791 if (min_err > err) {
1792 min_err = err;
1793 *brr = br;
1794 *srr = sr - 1;
1795 *cks = c;
1796 }
1797 }
1798 }
1799
1800 if (min_err == 1000) {
1801 WARN_ON(1);
1802 /* use defaults */
1803 *brr = 255;
1804 *srr = 15;
1805 *cks = 0;
1806 }
1807}
1808
1ba76220
MD		 1809static void sci_reset(struct uart_port *port)
1810{
0979e0e6 1811 struct plat_sci_reg *reg;
1ba76220
MD		 1812 unsigned int status;
1813
1814 do {
b12bb29f 1815 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1816 } while (!(status & SCxSR_TEND(port)));
1817
b12bb29f 1818 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1819
0979e0e6
PM		 1820 reg = sci_getreg(port, SCFCR);
1821 if (reg->size)
b12bb29f 1822 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1823}
1824
606d099c
AC		 1825static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1826 struct ktermios *old)
1da177e4 1827{
00b9de9c 1828 struct sci_port *s = to_sci_port(port);
0979e0e6 1829 struct plat_sci_reg *reg;
d4759ded 1830 unsigned int baud, smr_val, max_baud, cks = 0;
a2159b52 1831 int t = -1;
d4759ded 1832 unsigned int srr = 15;
1da177e4 1833
154280fd
MD		 1834 /*
1835 * earlyprintk comes here early on with port->uartclk set to zero.
1836 * the clock framework is not up and running at this point so here
1837 * we assume that 115200 is the maximum baud rate. please note that
1838 * the baud rate is not programmed during earlyprintk - it is assumed
1839 * that the previous boot loader has enabled required clocks and
1840 * setup the baud rate generator hardware for us already.
1841 */
1842 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1843
154280fd 1844 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364
UH		 1845 if (likely(baud && port->uartclk)) {
1846 if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) {
1847 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1848 &cks);
1849 } else {
1850 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud,
1851 port->uartclk);
1852 for (cks = 0; t >= 256 && cks <= 3; cks++)
1853 t >>= 2;
1854 }
1855 }
e108b2ca 1856
23241d43 1857 sci_port_enable(s);
36003386 1858
1ba76220 1859 sci_reset(port);
1da177e4 1860
b12bb29f 1861 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1862
1da177e4
LT		 1863 if ((termios->c_cflag & CSIZE) == CS7)
1864 smr_val |= 0x40;
1865 if (termios->c_cflag & PARENB)
1866 smr_val |= 0x20;
1867 if (termios->c_cflag & PARODD)
1868 smr_val |= 0x30;
1869 if (termios->c_cflag & CSTOPB)
1870 smr_val |= 0x08;
1871
1872 uart_update_timeout(port, termios->c_cflag, baud);
1873
9d482cc3
TY		 1874 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1875 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1876
4ffc3cdb 1877 if (t >= 0) {
9d482cc3 1878 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
b12bb29f 1879 serial_port_out(port, SCBRR, t);
f303b364
UH		 1880 reg = sci_getreg(port, HSSRR);
1881 if (reg->size)
1882 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1883 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1884 } else
1885 serial_port_out(port, SCSMR, smr_val);
1da177e4 1886
d5701647 1887 sci_init_pins(port, termios->c_cflag);
0979e0e6 1888
73c3d53f
PM		 1889 reg = sci_getreg(port, SCFCR);
1890 if (reg->size) {
b12bb29f 1891 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1892
73c3d53f 1893 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1894 if (termios->c_cflag & CRTSCTS)
1895 ctrl |= SCFCR_MCE;
1896 else
1897 ctrl &= ~SCFCR_MCE;
faf02f8f 1898 }
73c3d53f
PM		 1899
1900 /*
1901 * As we've done a sci_reset() above, ensure we don't
1902 * interfere with the FIFOs while toggling MCE. As the
1903 * reset values could still be set, simply mask them out.
1904 */
1905 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1906
b12bb29f 1907 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1908 }
b7a76e4b 1909
b12bb29f 1910 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1911
3089f381
GL		 1912#ifdef CONFIG_SERIAL_SH_SCI_DMA
1913 /*
1914 * Calculate delay for 1.5 DMA buffers: see
1915 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1916 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1917 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1918 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1919 * sizes), but it has been found out experimentally, that this is not
1920 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1921 * as a minimum seem to work perfectly.
1922 */
1923 if (s->chan_rx) {
1924 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1925 port->fifosize / 2;
1926 dev_dbg(port->dev,
1927 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1928 s->rx_timeout * 1000 / HZ, port->timeout);
1929 if (s->rx_timeout < msecs_to_jiffies(20))
1930 s->rx_timeout = msecs_to_jiffies(20);
1931 }
1932#endif
1933
1da177e4 1934 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1935 sci_start_rx(port);
36003386 1936
23241d43 1937 sci_port_disable(s);
1da177e4
LT		 1938}
1939
0174e5ca
TK		 1940static void sci_pm(struct uart_port *port, unsigned int state,
1941 unsigned int oldstate)
1942{
1943 struct sci_port *sci_port = to_sci_port(port);
1944
1945 switch (state) {
1946 case 3:
1947 sci_port_disable(sci_port);
1948 break;
1949 default:
1950 sci_port_enable(sci_port);
1951 break;
1952 }
1953}
1954
1da177e4
LT		 1955static const char *sci_type(struct uart_port *port)
1956{
1957 switch (port->type) {
e7c98dc7
MT		 1958 case PORT_IRDA:
1959 return "irda";
1960 case PORT_SCI:
1961 return "sci";
1962 case PORT_SCIF:
1963 return "scif";
1964 case PORT_SCIFA:
1965 return "scifa";
d1d4b10c
GL		 1966 case PORT_SCIFB:
1967 return "scifb";
f303b364
UH		 1968 case PORT_HSCIF:
1969 return "hscif";
1da177e4
LT		 1970 }
1971
fa43972f 1972 return NULL;
1da177e4
LT		 1973}
1974
e2651647 1975static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1976{
e2651647
PM		 1977 /*
1978 * Pick an arbitrary size that encapsulates all of the base
1979 * registers by default. This can be optimized later, or derived
1980 * from platform resource data at such a time that ports begin to
1981 * behave more erratically.
1982 */
f303b364
UH		 1983 if (port->type == PORT_HSCIF)
1984 return 96;
1985 else
1986 return 64;
1da177e4
LT		 1987}
1988
f6e9495d
PM		 1989static int sci_remap_port(struct uart_port *port)
1990{
1991 unsigned long size = sci_port_size(port);
1992
1993 /*
1994 * Nothing to do if there's already an established membase.
1995 */
1996 if (port->membase)
1997 return 0;
1998
1999 if (port->flags & UPF_IOREMAP) {
2000 port->membase = ioremap_nocache(port->mapbase, size);
2001 if (unlikely(!port->membase)) {
2002 dev_err(port->dev, "can't remap port#%d\n", port->line);
2003 return -ENXIO;
2004 }
2005 } else {
2006 /*
2007 * For the simple (and majority of) cases where we don't
2008 * need to do any remapping, just cast the cookie
2009 * directly.
2010 */
2011 port->membase = (void __iomem *)port->mapbase;
2012 }
2013
2014 return 0;
2015}
2016
e2651647 2017static void sci_release_port(struct uart_port *port)
1da177e4 2018{
e2651647
PM		 2019 if (port->flags & UPF_IOREMAP) {
2020 iounmap(port->membase);
2021 port->membase = NULL;
2022 }
2023
2024 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 2025}
2026
e2651647 2027static int sci_request_port(struct uart_port *port)
1da177e4 2028{
e2651647
PM		 2029 unsigned long size = sci_port_size(port);
2030 struct resource *res;
f6e9495d 2031 int ret;
1da177e4 2032
1020520e 2033 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2034 if (unlikely(res == NULL))
2035 return -EBUSY;
1da177e4 2036
f6e9495d
PM		 2037 ret = sci_remap_port(port);
2038 if (unlikely(ret != 0)) {
2039 release_resource(res);
2040 return ret;
7ff731ae 2041 }
e2651647
PM		 2042
2043 return 0;
2044}
2045
2046static void sci_config_port(struct uart_port *port, int flags)
2047{
2048 if (flags & UART_CONFIG_TYPE) {
2049 struct sci_port *sport = to_sci_port(port);
2050
2051 port->type = sport->cfg->type;
2052 sci_request_port(port);
2053 }
1da177e4
LT		 2054}
2055
2056static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2057{
1da177e4
LT		 2058 if (ser->baud_base < 2400)
2059 /* No paper tape reader for Mitch.. */
2060 return -EINVAL;
2061
2062 return 0;
2063}
2064
2065static struct uart_ops sci_uart_ops = {
2066 .tx_empty = sci_tx_empty,
2067 .set_mctrl = sci_set_mctrl,
2068 .get_mctrl = sci_get_mctrl,
2069 .start_tx = sci_start_tx,
2070 .stop_tx = sci_stop_tx,
2071 .stop_rx = sci_stop_rx,
2072 .enable_ms = sci_enable_ms,
2073 .break_ctl = sci_break_ctl,
2074 .startup = sci_startup,
2075 .shutdown = sci_shutdown,
2076 .set_termios = sci_set_termios,
0174e5ca 2077 .pm = sci_pm,
1da177e4
LT		 2078 .type = sci_type,
2079 .release_port = sci_release_port,
2080 .request_port = sci_request_port,
2081 .config_port = sci_config_port,
2082 .verify_port = sci_verify_port,
07d2a1a1
PM		 2083#ifdef CONFIG_CONSOLE_POLL
2084 .poll_get_char = sci_poll_get_char,
2085 .poll_put_char = sci_poll_put_char,
2086#endif
1da177e4
LT		 2087};
2088
9671f099 2089static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2090 struct sci_port *sci_port, unsigned int index,
2091 struct plat_sci_port *p, bool early)
e108b2ca 2092{
73a19e4c 2093 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2094 const struct resource *res;
2095 unsigned int i;
3127c6b2 2096 int ret;
e108b2ca 2097
50f0959a
PM		 2098 sci_port->cfg = p;
2099
73a19e4c
GL		 2100 port->ops = &sci_uart_ops;
2101 port->iotype = UPIO_MEM;
2102 port->line = index;
75136d48 2103
1fcc91a6
LP		 2104 if (dev->num_resources) {
2105 /* Device has resources, use them. */
2106 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2107 if (res == NULL)
2108 return -ENOMEM;
2109
2110 port->mapbase = res->start;
2111
2112 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2113 sci_port->irqs[i] = platform_get_irq(dev, i);
2114
2115 /* The SCI generates several interrupts. They can be muxed
2116 * together or connected to different interrupt lines. In the
2117 * muxed case only one interrupt resource is specified. In the
2118 * non-muxed case three or four interrupt resources are
2119 * specified, as the BRI interrupt is optional.
2120 */
2121 if (sci_port->irqs[0] < 0)
2122 return -ENXIO;
2123
2124 if (sci_port->irqs[1] < 0) {
2125 sci_port->irqs[1] = sci_port->irqs[0];
2126 sci_port->irqs[2] = sci_port->irqs[0];
2127 sci_port->irqs[3] = sci_port->irqs[0];
2128 }
2129 } else {
2130 /* No resources, use old-style platform data. */
2131 port->mapbase = p->mapbase;
2132 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2133 sci_port->irqs[i] = p->irqs[i] ? p->irqs[i] : -ENXIO;
2134 }
2135
75136d48 2136 switch (p->type) {
d1d4b10c
GL		 2137 case PORT_SCIFB:
2138 port->fifosize = 256;
2139 break;
f303b364
UH		 2140 case PORT_HSCIF:
2141 port->fifosize = 128;
2142 break;
75136d48 2143 case PORT_SCIFA:
73a19e4c 2144 port->fifosize = 64;
75136d48
MP		 2145 break;
2146 case PORT_SCIF:
73a19e4c 2147 port->fifosize = 16;
75136d48
MP		 2148 break;
2149 default:
73a19e4c 2150 port->fifosize = 1;
75136d48
MP		 2151 break;
2152 }
7b6fd3bf 2153
3127c6b2
PM		 2154 if (p->regtype == SCIx_PROBE_REGTYPE) {
2155 ret = sci_probe_regmap(p);
fc97114b 2156 if (unlikely(ret))
3127c6b2
PM		 2157 return ret;
2158 }
61a6976b 2159
1fcc91a6 2160 if (!early) {
c7ed1ab3
PM		 2161 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2162 if (IS_ERR(sci_port->iclk)) {
2163 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2164 if (IS_ERR(sci_port->iclk)) {
2165 dev_err(&dev->dev, "can't get iclk\n");
2166 return PTR_ERR(sci_port->iclk);
2167 }
2168 }
2169
2170 /*
2171 * The function clock is optional, ignore it if we can't
2172 * find it.
2173 */
2174 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2175 if (IS_ERR(sci_port->fclk))
2176 sci_port->fclk = NULL;
2177
73a19e4c 2178 port->dev = &dev->dev;
5e50d2d6
MD		 2179
2180 pm_runtime_enable(&dev->dev);
7b6fd3bf 2181 }
e108b2ca 2182
7ed7e071
MD		 2183 sci_port->break_timer.data = (unsigned long)sci_port;
2184 sci_port->break_timer.function = sci_break_timer;
2185 init_timer(&sci_port->break_timer);
2186
debf9507
PM		 2187 /*
2188 * Establish some sensible defaults for the error detection.
2189 */
3ae988d9 2190 sci_port->error_mask = (p->type == PORT_SCI) ?
debf9507
PM		 2191 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2192
2193 /*
2194 * Establish sensible defaults for the overrun detection, unless
2195 * the part has explicitly disabled support for it.
2196 */
3ae988d9
LP		 2197 if (p->type == PORT_SCI)
2198 sci_port->overrun_bit = 5;
2199 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2200 sci_port->overrun_bit = 9;
2201 else
2202 sci_port->overrun_bit = 0;
debf9507 2203
3ae988d9
LP		 2204 /*
2205 * Make the error mask inclusive of overrun detection, if
2206 * supported.
2207 */
2208 sci_port->error_mask |= 1 << sci_port->overrun_bit;
debf9507 2209
ce6738b6 2210 port->type = p->type;
b6e4a3f1 2211 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2212 port->regshift = p->regshift;
73a19e4c 2213
ce6738b6 2214 /*
61a6976b 2215 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2216 * for the multi-IRQ ports, which is where we are primarily
2217 * concerned with the shutdown path synchronization.
2218 *
2219 * For the muxed case there's nothing more to do.
2220 */
1fcc91a6 2221 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2222 port->irqflags = 0;
73a19e4c 2223
61a6976b
PM		 2224 port->serial_in = sci_serial_in;
2225 port->serial_out = sci_serial_out;
2226
937bb6e4
GL		 2227 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2228 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2229 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2230
c7ed1ab3 2231 return 0;
e108b2ca
PM		 2232}
2233
6dae1421
LP		 2234static void sci_cleanup_single(struct sci_port *port)
2235{
6dae1421
LP		 2236 clk_put(port->iclk);
2237 clk_put(port->fclk);
2238
2239 pm_runtime_disable(port->port.dev);
2240}
2241
1da177e4 2242#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2243static void serial_console_putchar(struct uart_port *port, int ch)
2244{
2245 sci_poll_put_char(port, ch);
2246}
2247
1da177e4
LT		 2248/*
2249 * Print a string to the serial port trying not to disturb
2250 * any possible real use of the port...
2251 */
2252static void serial_console_write(struct console *co, const char *s,
2253 unsigned count)
2254{
906b17dc
PM		 2255 struct sci_port *sci_port = &sci_ports[co->index];
2256 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2257 unsigned short bits, ctrl;
2258 unsigned long flags;
2259 int locked = 1;
2260
2261 local_irq_save(flags);
2262 if (port->sysrq)
2263 locked = 0;
2264 else if (oops_in_progress)
2265 locked = spin_trylock(&port->lock);
2266 else
2267 spin_lock(&port->lock);
2268
2269 /* first save the SCSCR then disable the interrupts */
2270 ctrl = serial_port_in(port, SCSCR);
2271 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2272
501b825d 2273 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2274
2275 /* wait until fifo is empty and last bit has been transmitted */
2276 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2277 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2278 cpu_relax();
40f70c03
SK		 2279
2280 /* restore the SCSCR */
2281 serial_port_out(port, SCSCR, ctrl);
2282
2283 if (locked)
2284 spin_unlock(&port->lock);
2285 local_irq_restore(flags);
1da177e4
LT		 2286}
2287
9671f099 2288static int serial_console_setup(struct console *co, char *options)
1da177e4 2289{
dc8e6f5b 2290 struct sci_port *sci_port;
1da177e4
LT		 2291 struct uart_port *port;
2292 int baud = 115200;
2293 int bits = 8;
2294 int parity = 'n';
2295 int flow = 'n';
2296 int ret;
2297
e108b2ca 2298 /*
906b17dc 2299 * Refuse to handle any bogus ports.
1da177e4 2300 */
906b17dc 2301 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2302 return -ENODEV;
e108b2ca 2303
906b17dc
PM		 2304 sci_port = &sci_ports[co->index];
2305 port = &sci_port->port;
2306
b2267a6b
AC		 2307 /*
2308 * Refuse to handle uninitialized ports.
2309 */
2310 if (!port->ops)
2311 return -ENODEV;
2312
f6e9495d
PM		 2313 ret = sci_remap_port(port);
2314 if (unlikely(ret != 0))
2315 return ret;
e108b2ca 2316
1da177e4
LT		 2317 if (options)
2318 uart_parse_options(options, &baud, &parity, &bits, &flow);
2319
ab7cfb55 2320 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2321}
2322
2323static struct console serial_console = {
2324 .name = "ttySC",
906b17dc 2325 .device = uart_console_device,
1da177e4
LT		 2326 .write = serial_console_write,
2327 .setup = serial_console_setup,
fa5da2f7 2328 .flags = CON_PRINTBUFFER,
1da177e4 2329 .index = -1,
906b17dc 2330 .data = &sci_uart_driver,
1da177e4
LT		 2331};
2332
7b6fd3bf
MD		 2333static struct console early_serial_console = {
2334 .name = "early_ttySC",
2335 .write = serial_console_write,
2336 .flags = CON_PRINTBUFFER,
906b17dc 2337 .index = -1,
7b6fd3bf 2338};
ecdf8a46 2339
7b6fd3bf
MD		 2340static char early_serial_buf[32];
2341
9671f099 2342static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2343{
574de559 2344 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2345
2346 if (early_serial_console.data)
2347 return -EEXIST;
2348
2349 early_serial_console.index = pdev->id;
ecdf8a46 2350
1fcc91a6 2351 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2352
2353 serial_console_setup(&early_serial_console, early_serial_buf);
2354
2355 if (!strstr(early_serial_buf, "keep"))
2356 early_serial_console.flags |= CON_BOOT;
2357
2358 register_console(&early_serial_console);
2359 return 0;
2360}
6a8c9799
NI		 2361
2362#define SCI_CONSOLE (&serial_console)
2363
ecdf8a46 2364#else
9671f099 2365static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2366{
2367 return -EINVAL;
2368}
1da177e4 2369
6a8c9799
NI		 2370#define SCI_CONSOLE NULL
2371
2372#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2373
2374static char banner[] __initdata =
f303b364 2375 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
1da177e4
LT		 2376
2377static struct uart_driver sci_uart_driver = {
2378 .owner = THIS_MODULE,
2379 .driver_name = "sci",
1da177e4
LT		 2380 .dev_name = "ttySC",
2381 .major = SCI_MAJOR,
2382 .minor = SCI_MINOR_START,
e108b2ca 2383 .nr = SCI_NPORTS,
1da177e4
LT		 2384 .cons = SCI_CONSOLE,
2385};
2386
54507f6e 2387static int sci_remove(struct platform_device *dev)
e552de24 2388{
d535a230 2389 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2390
d535a230
PM		 2391 cpufreq_unregister_notifier(&port->freq_transition,
2392 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2393
d535a230
PM		 2394 uart_remove_one_port(&sci_uart_driver, &port->port);
2395
6dae1421 2396 sci_cleanup_single(port);
e552de24 2397
e552de24
MD		 2398 return 0;
2399}
2400
9671f099 2401static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2402 unsigned int index,
2403 struct plat_sci_port *p,
2404 struct sci_port *sciport)
2405{
0ee70712
MD		 2406 int ret;
2407
2408 /* Sanity check */
2409 if (unlikely(index >= SCI_NPORTS)) {
2410 dev_notice(&dev->dev, "Attempting to register port "
2411 "%d when only %d are available.\n",
2412 index+1, SCI_NPORTS);
2413 dev_notice(&dev->dev, "Consider bumping "
2414 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2415 return -EINVAL;
0ee70712
MD		 2416 }
2417
1fcc91a6 2418 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2419 if (ret)
2420 return ret;
0ee70712 2421
6dae1421
LP		 2422 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2423 if (ret) {
2424 sci_cleanup_single(sciport);
2425 return ret;
2426 }
2427
2428 return 0;
0ee70712
MD		 2429}
2430
9671f099 2431static int sci_probe(struct platform_device *dev)
1da177e4 2432{
3ba35baa 2433 struct plat_sci_port *p = dev_get_platdata(&dev->dev);
d535a230 2434 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2435 int ret;
d535a230 2436
ecdf8a46
PM		 2437 /*
2438 * If we've come here via earlyprintk initialization, head off to
2439 * the special early probe. We don't have sufficient device state
2440 * to make it beyond this yet.
2441 */
2442 if (is_early_platform_device(dev))
2443 return sci_probe_earlyprintk(dev);
7b6fd3bf 2444
d535a230 2445 platform_set_drvdata(dev, sp);
e552de24 2446
906b17dc 2447 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2448 if (ret)
6dae1421 2449 return ret;
e552de24 2450
d535a230 2451 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2452
d535a230
PM		 2453 ret = cpufreq_register_notifier(&sp->freq_transition,
2454 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2455 if (unlikely(ret < 0)) {
2456 sci_cleanup_single(sp);
2457 return ret;
2458 }
1da177e4
LT		 2459
2460#ifdef CONFIG_SH_STANDARD_BIOS
2461 sh_bios_gdb_detach();
2462#endif
2463
e108b2ca 2464 return 0;
1da177e4
LT		 2465}
2466
6daa79b3 2467static int sci_suspend(struct device *dev)
1da177e4 2468{
d535a230 2469 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2470
d535a230
PM		 2471 if (sport)
2472 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2473
e108b2ca
PM		 2474 return 0;
2475}
1da177e4 2476
6daa79b3 2477static int sci_resume(struct device *dev)
e108b2ca 2478{
d535a230 2479 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2480
d535a230
PM		 2481 if (sport)
2482 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2483
2484 return 0;
2485}
2486
47145210 2487static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2488 .suspend = sci_suspend,
2489 .resume = sci_resume,
2490};
2491
e108b2ca
PM		 2492static struct platform_driver sci_driver = {
2493 .probe = sci_probe,
b9e39c89 2494 .remove = sci_remove,
e108b2ca
PM		 2495 .driver = {
2496 .name = "sh-sci",
2497 .owner = THIS_MODULE,
6daa79b3 2498 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2499 },
2500};
2501
2502static int __init sci_init(void)
2503{
2504 int ret;
2505
2506 printk(banner);
2507
e108b2ca
PM		 2508 ret = uart_register_driver(&sci_uart_driver);
2509 if (likely(ret == 0)) {
2510 ret = platform_driver_register(&sci_driver);
2511 if (unlikely(ret))
2512 uart_unregister_driver(&sci_uart_driver);
2513 }
2514
2515 return ret;
2516}
2517
2518static void __exit sci_exit(void)
2519{
2520 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2521 uart_unregister_driver(&sci_uart_driver);
2522}
2523
7b6fd3bf
MD		 2524#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2525early_platform_init_buffer("earlyprintk", &sci_driver,
2526 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2527#endif
1da177e4
LT		 2528module_init(sci_init);
2529module_exit(sci_exit);
2530
e108b2ca 2531MODULE_LICENSE("GPL");
e169c139 2532MODULE_ALIAS("platform:sh-sci");
7f405f9c 2533MODULE_AUTHOR("Paul Mundt");
f303b364 2534MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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