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serial: sh-sci: Shuffle functions around
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
501b825d
MD		 95 /* Interface clock */
96 struct clk *iclk;
c7ed1ab3
PM		 97 /* Function clock */
98 struct clk *fclk;
edad1f20 99
1fcc91a6 100 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 101 char *irqstr[SCIx_NR_IRQS];
102
73a19e4c
GL		 103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
f43dc23d 105
73a19e4c 106#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
79904420
GU		 110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
73a19e4c 112 struct scatterlist sg_rx[2];
7b39d901 113 void *rx_buf[2];
73a19e4c
GL		 114 size_t buf_len_rx;
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
118 struct work_struct work_rx;
119 struct timer_list rx_timer;
3089f381 120 unsigned int rx_timeout;
73a19e4c 121#endif
e552de24 122
d535a230 123 struct notifier_block freq_transition;
e108b2ca
PM		 124};
125
e108b2ca 126#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 127
e108b2ca
PM		 128static struct sci_port sci_ports[SCI_NPORTS];
129static struct uart_driver sci_uart_driver;
1da177e4 130
e7c98dc7
MT		 131static inline struct sci_port *
132to_sci_port(struct uart_port *uart)
133{
134 return container_of(uart, struct sci_port, port);
135}
136
61a6976b
PM		 137struct plat_sci_reg {
138 u8 offset, size;
139};
140
141/* Helper for invalidating specific entries of an inherited map. */
142#define sci_reg_invalid { .offset = 0, .size = 0 }
143
d3184e68 144static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 145 [SCIx_PROBE_REGTYPE] = {
146 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
147 },
148
149 /*
150 * Common SCI definitions, dependent on the port's regshift
151 * value.
152 */
153 [SCIx_SCI_REGTYPE] = {
154 [SCSMR] = { 0x00, 8 },
155 [SCBRR] = { 0x01, 8 },
156 [SCSCR] = { 0x02, 8 },
157 [SCxTDR] = { 0x03, 8 },
158 [SCxSR] = { 0x04, 8 },
159 [SCxRDR] = { 0x05, 8 },
160 [SCFCR] = sci_reg_invalid,
161 [SCFDR] = sci_reg_invalid,
162 [SCTFDR] = sci_reg_invalid,
163 [SCRFDR] = sci_reg_invalid,
164 [SCSPTR] = sci_reg_invalid,
165 [SCLSR] = sci_reg_invalid,
f303b364 166 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 167 [SCPCR] = sci_reg_invalid,
168 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 169 },
170
171 /*
172 * Common definitions for legacy IrDA ports, dependent on
173 * regshift value.
174 */
175 [SCIx_IRDA_REGTYPE] = {
176 [SCSMR] = { 0x00, 8 },
177 [SCBRR] = { 0x01, 8 },
178 [SCSCR] = { 0x02, 8 },
179 [SCxTDR] = { 0x03, 8 },
180 [SCxSR] = { 0x04, 8 },
181 [SCxRDR] = { 0x05, 8 },
182 [SCFCR] = { 0x06, 8 },
183 [SCFDR] = { 0x07, 16 },
184 [SCTFDR] = sci_reg_invalid,
185 [SCRFDR] = sci_reg_invalid,
186 [SCSPTR] = sci_reg_invalid,
187 [SCLSR] = sci_reg_invalid,
f303b364 188 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 189 [SCPCR] = sci_reg_invalid,
190 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 191 },
192
193 /*
194 * Common SCIFA definitions.
195 */
196 [SCIx_SCIFA_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x20, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x24, 8 },
203 [SCFCR] = { 0x18, 16 },
204 [SCFDR] = { 0x1c, 16 },
205 [SCTFDR] = sci_reg_invalid,
206 [SCRFDR] = sci_reg_invalid,
207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
f303b364 209 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 210 [SCPCR] = { 0x30, 16 },
211 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 212 },
213
214 /*
215 * Common SCIFB definitions.
216 */
217 [SCIx_SCIFB_REGTYPE] = {
218 [SCSMR] = { 0x00, 16 },
219 [SCBRR] = { 0x04, 8 },
220 [SCSCR] = { 0x08, 16 },
221 [SCxTDR] = { 0x40, 8 },
222 [SCxSR] = { 0x14, 16 },
223 [SCxRDR] = { 0x60, 8 },
224 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 225 [SCFDR] = sci_reg_invalid,
226 [SCTFDR] = { 0x38, 16 },
227 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 228 [SCSPTR] = sci_reg_invalid,
229 [SCLSR] = sci_reg_invalid,
f303b364 230 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 231 [SCPCR] = { 0x30, 16 },
232 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 233 },
234
3af1f8a4
PE		 235 /*
236 * Common SH-2(A) SCIF definitions for ports with FIFO data
237 * count registers.
238 */
239 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
240 [SCSMR] = { 0x00, 16 },
241 [SCBRR] = { 0x04, 8 },
242 [SCSCR] = { 0x08, 16 },
243 [SCxTDR] = { 0x0c, 8 },
244 [SCxSR] = { 0x10, 16 },
245 [SCxRDR] = { 0x14, 8 },
246 [SCFCR] = { 0x18, 16 },
247 [SCFDR] = { 0x1c, 16 },
248 [SCTFDR] = sci_reg_invalid,
249 [SCRFDR] = sci_reg_invalid,
250 [SCSPTR] = { 0x20, 16 },
251 [SCLSR] = { 0x24, 16 },
f303b364 252 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 253 [SCPCR] = sci_reg_invalid,
254 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 255 },
256
61a6976b
PM		 257 /*
258 * Common SH-3 SCIF definitions.
259 */
260 [SCIx_SH3_SCIF_REGTYPE] = {
261 [SCSMR] = { 0x00, 8 },
262 [SCBRR] = { 0x02, 8 },
263 [SCSCR] = { 0x04, 8 },
264 [SCxTDR] = { 0x06, 8 },
265 [SCxSR] = { 0x08, 16 },
266 [SCxRDR] = { 0x0a, 8 },
267 [SCFCR] = { 0x0c, 8 },
268 [SCFDR] = { 0x0e, 16 },
269 [SCTFDR] = sci_reg_invalid,
270 [SCRFDR] = sci_reg_invalid,
271 [SCSPTR] = sci_reg_invalid,
272 [SCLSR] = sci_reg_invalid,
f303b364 273 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 274 [SCPCR] = sci_reg_invalid,
275 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 276 },
277
278 /*
279 * Common SH-4(A) SCIF(B) definitions.
280 */
281 [SCIx_SH4_SCIF_REGTYPE] = {
282 [SCSMR] = { 0x00, 16 },
283 [SCBRR] = { 0x04, 8 },
284 [SCSCR] = { 0x08, 16 },
285 [SCxTDR] = { 0x0c, 8 },
286 [SCxSR] = { 0x10, 16 },
287 [SCxRDR] = { 0x14, 8 },
288 [SCFCR] = { 0x18, 16 },
289 [SCFDR] = { 0x1c, 16 },
290 [SCTFDR] = sci_reg_invalid,
291 [SCRFDR] = sci_reg_invalid,
292 [SCSPTR] = { 0x20, 16 },
293 [SCLSR] = { 0x24, 16 },
f303b364 294 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 295 [SCPCR] = sci_reg_invalid,
296 [SCPDR] = sci_reg_invalid,
f303b364
UH		 297 },
298
299 /*
300 * Common HSCIF definitions.
301 */
302 [SCIx_HSCIF_REGTYPE] = {
303 [SCSMR] = { 0x00, 16 },
304 [SCBRR] = { 0x04, 8 },
305 [SCSCR] = { 0x08, 16 },
306 [SCxTDR] = { 0x0c, 8 },
307 [SCxSR] = { 0x10, 16 },
308 [SCxRDR] = { 0x14, 8 },
309 [SCFCR] = { 0x18, 16 },
310 [SCFDR] = { 0x1c, 16 },
311 [SCTFDR] = sci_reg_invalid,
312 [SCRFDR] = sci_reg_invalid,
313 [SCSPTR] = { 0x20, 16 },
314 [SCLSR] = { 0x24, 16 },
315 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 316 [SCPCR] = sci_reg_invalid,
317 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 318 },
319
320 /*
321 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
322 * register.
323 */
324 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
325 [SCSMR] = { 0x00, 16 },
326 [SCBRR] = { 0x04, 8 },
327 [SCSCR] = { 0x08, 16 },
328 [SCxTDR] = { 0x0c, 8 },
329 [SCxSR] = { 0x10, 16 },
330 [SCxRDR] = { 0x14, 8 },
331 [SCFCR] = { 0x18, 16 },
332 [SCFDR] = { 0x1c, 16 },
333 [SCTFDR] = sci_reg_invalid,
334 [SCRFDR] = sci_reg_invalid,
335 [SCSPTR] = sci_reg_invalid,
336 [SCLSR] = { 0x24, 16 },
f303b364 337 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 338 [SCPCR] = sci_reg_invalid,
339 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 340 },
341
342 /*
343 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
344 * count registers.
345 */
346 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
347 [SCSMR] = { 0x00, 16 },
348 [SCBRR] = { 0x04, 8 },
349 [SCSCR] = { 0x08, 16 },
350 [SCxTDR] = { 0x0c, 8 },
351 [SCxSR] = { 0x10, 16 },
352 [SCxRDR] = { 0x14, 8 },
353 [SCFCR] = { 0x18, 16 },
354 [SCFDR] = { 0x1c, 16 },
355 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
356 [SCRFDR] = { 0x20, 16 },
357 [SCSPTR] = { 0x24, 16 },
358 [SCLSR] = { 0x28, 16 },
f303b364 359 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 360 [SCPCR] = sci_reg_invalid,
361 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 362 },
363
364 /*
365 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
366 * registers.
367 */
368 [SCIx_SH7705_SCIF_REGTYPE] = {
369 [SCSMR] = { 0x00, 16 },
370 [SCBRR] = { 0x04, 8 },
371 [SCSCR] = { 0x08, 16 },
372 [SCxTDR] = { 0x20, 8 },
373 [SCxSR] = { 0x14, 16 },
374 [SCxRDR] = { 0x24, 8 },
375 [SCFCR] = { 0x18, 16 },
376 [SCFDR] = { 0x1c, 16 },
377 [SCTFDR] = sci_reg_invalid,
378 [SCRFDR] = sci_reg_invalid,
379 [SCSPTR] = sci_reg_invalid,
380 [SCLSR] = sci_reg_invalid,
f303b364 381 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 382 [SCPCR] = sci_reg_invalid,
383 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 384 },
385};
386
72b294cf
PM		 387#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
388
61a6976b
PM		 389/*
390 * The "offset" here is rather misleading, in that it refers to an enum
391 * value relative to the port mapping rather than the fixed offset
392 * itself, which needs to be manually retrieved from the platform's
393 * register map for the given port.
394 */
395static unsigned int sci_serial_in(struct uart_port *p, int offset)
396{
d3184e68 397 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 398
399 if (reg->size == 8)
400 return ioread8(p->membase + (reg->offset << p->regshift));
401 else if (reg->size == 16)
402 return ioread16(p->membase + (reg->offset << p->regshift));
403 else
404 WARN(1, "Invalid register access\n");
405
406 return 0;
407}
408
409static void sci_serial_out(struct uart_port *p, int offset, int value)
410{
d3184e68 411 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 412
413 if (reg->size == 8)
414 iowrite8(value, p->membase + (reg->offset << p->regshift));
415 else if (reg->size == 16)
416 iowrite16(value, p->membase + (reg->offset << p->regshift));
417 else
418 WARN(1, "Invalid register access\n");
419}
420
61a6976b
PM		 421static int sci_probe_regmap(struct plat_sci_port *cfg)
422{
423 switch (cfg->type) {
424 case PORT_SCI:
425 cfg->regtype = SCIx_SCI_REGTYPE;
426 break;
427 case PORT_IRDA:
428 cfg->regtype = SCIx_IRDA_REGTYPE;
429 break;
430 case PORT_SCIFA:
431 cfg->regtype = SCIx_SCIFA_REGTYPE;
432 break;
433 case PORT_SCIFB:
434 cfg->regtype = SCIx_SCIFB_REGTYPE;
435 break;
436 case PORT_SCIF:
437 /*
438 * The SH-4 is a bit of a misnomer here, although that's
439 * where this particular port layout originated. This
440 * configuration (or some slight variation thereof)
441 * remains the dominant model for all SCIFs.
442 */
443 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
444 break;
f303b364
UH		 445 case PORT_HSCIF:
446 cfg->regtype = SCIx_HSCIF_REGTYPE;
447 break;
61a6976b 448 default:
6c13d5d2 449 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 450 return -EINVAL;
451 }
452
453 return 0;
454}
455
23241d43
PM		 456static void sci_port_enable(struct sci_port *sci_port)
457{
458 if (!sci_port->port.dev)
459 return;
460
461 pm_runtime_get_sync(sci_port->port.dev);
462
b016b646 463 clk_prepare_enable(sci_port->iclk);
23241d43 464 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 465 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 466}
467
468static void sci_port_disable(struct sci_port *sci_port)
469{
470 if (!sci_port->port.dev)
471 return;
472
caec7038
LP		 473 /* Cancel the break timer to ensure that the timer handler will not try
474 * to access the hardware with clocks and power disabled. Reset the
475 * break flag to make the break debouncing state machine ready for the
476 * next break.
477 */
478 del_timer_sync(&sci_port->break_timer);
479 sci_port->break_flag = 0;
480
b016b646
LP		 481 clk_disable_unprepare(sci_port->fclk);
482 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 483
484 pm_runtime_put_sync(sci_port->port.dev);
485}
486
e1910fcd
GU		 487static inline unsigned long port_rx_irq_mask(struct uart_port *port)
488{
489 /*
490 * Not all ports (such as SCIFA) will support REIE. Rather than
491 * special-casing the port type, we check the port initialization
492 * IRQ enable mask to see whether the IRQ is desired at all. If
493 * it's unset, it's logically inferred that there's no point in
494 * testing for it.
495 */
496 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
497}
498
499static void sci_start_tx(struct uart_port *port)
500{
501 struct sci_port *s = to_sci_port(port);
502 unsigned short ctrl;
503
504#ifdef CONFIG_SERIAL_SH_SCI_DMA
505 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
506 u16 new, scr = serial_port_in(port, SCSCR);
507 if (s->chan_tx)
508 new = scr | SCSCR_TDRQE;
509 else
510 new = scr & ~SCSCR_TDRQE;
511 if (new != scr)
512 serial_port_out(port, SCSCR, new);
513 }
514
515 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
516 dma_submit_error(s->cookie_tx)) {
517 s->cookie_tx = 0;
518 schedule_work(&s->work_tx);
519 }
520#endif
521
522 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
523 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
524 ctrl = serial_port_in(port, SCSCR);
525 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
526 }
527}
528
529static void sci_stop_tx(struct uart_port *port)
530{
531 unsigned short ctrl;
532
533 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
534 ctrl = serial_port_in(port, SCSCR);
535
536 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
537 ctrl &= ~SCSCR_TDRQE;
538
539 ctrl &= ~SCSCR_TIE;
540
541 serial_port_out(port, SCSCR, ctrl);
542}
543
544static void sci_start_rx(struct uart_port *port)
545{
546 unsigned short ctrl;
547
548 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
549
550 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
551 ctrl &= ~SCSCR_RDRQE;
552
553 serial_port_out(port, SCSCR, ctrl);
554}
555
556static void sci_stop_rx(struct uart_port *port)
557{
558 unsigned short ctrl;
559
560 ctrl = serial_port_in(port, SCSCR);
561
562 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
563 ctrl &= ~SCSCR_RDRQE;
564
565 ctrl &= ~port_rx_irq_mask(port);
566
567 serial_port_out(port, SCSCR, ctrl);
568}
569
a1b5b43f
GU		 570static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
571{
572 if (port->type == PORT_SCI) {
573 /* Just store the mask */
574 serial_port_out(port, SCxSR, mask);
575 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
576 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
577 /* Only clear the status bits we want to clear */
578 serial_port_out(port, SCxSR,
579 serial_port_in(port, SCxSR) & mask);
580 } else {
581 /* Store the mask, clear parity/framing errors */
582 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
583 }
584}
585
07d2a1a1 586#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 587
588#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 589static int sci_poll_get_char(struct uart_port *port)
1da177e4 590{
1da177e4
LT		 591 unsigned short status;
592 int c;
593
e108b2ca 594 do {
b12bb29f 595 status = serial_port_in(port, SCxSR);
1da177e4 596 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 597 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 598 continue;
599 }
3f255eb3
JW		 600 break;
601 } while (1);
602
603 if (!(status & SCxSR_RDxF(port)))
604 return NO_POLL_CHAR;
07d2a1a1 605
b12bb29f 606 c = serial_port_in(port, SCxRDR);
07d2a1a1 607
e7c98dc7 608 /* Dummy read */
b12bb29f 609 serial_port_in(port, SCxSR);
a1b5b43f 610 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 611
612 return c;
613}
1f6fd5c9 614#endif
1da177e4 615
07d2a1a1 616static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 617{
1da177e4
LT		 618 unsigned short status;
619
1da177e4 620 do {
b12bb29f 621 status = serial_port_in(port, SCxSR);
1da177e4
LT		 622 } while (!(status & SCxSR_TDxE(port)));
623
b12bb29f 624 serial_port_out(port, SCxTDR, c);
a1b5b43f 625 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 626}
07d2a1a1 627#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 628
61a6976b 629static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 630{
61a6976b 631 struct sci_port *s = to_sci_port(port);
d3184e68 632 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 633
61a6976b
PM		 634 /*
635 * Use port-specific handler if provided.
636 */
637 if (s->cfg->ops && s->cfg->ops->init_pins) {
638 s->cfg->ops->init_pins(port, cflag);
639 return;
1da177e4 640 }
41504c39 641
61a6976b
PM		 642 /*
643 * For the generic path SCSPTR is necessary. Bail out if that's
644 * unavailable, too.
645 */
646 if (!reg->size)
647 return;
41504c39 648
faf02f8f
PM		 649 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
650 ((!(cflag & CRTSCTS)))) {
651 unsigned short status;
652
b12bb29f 653 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 654 status &= ~SCSPTR_CTSIO;
655 status |= SCSPTR_RTSIO;
b12bb29f 656 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 657 }
d5701647 658}
e108b2ca 659
72b294cf 660static int sci_txfill(struct uart_port *port)
e108b2ca 661{
d3184e68 662 const struct plat_sci_reg *reg;
e108b2ca 663
72b294cf
PM		 664 reg = sci_getreg(port, SCTFDR);
665 if (reg->size)
63f7ad11 666 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 667
72b294cf
PM		 668 reg = sci_getreg(port, SCFDR);
669 if (reg->size)
b12bb29f 670 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 671
b12bb29f 672 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 673}
674
73a19e4c
GL		 675static int sci_txroom(struct uart_port *port)
676{
72b294cf 677 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 678}
679
680static int sci_rxfill(struct uart_port *port)
e108b2ca 681{
d3184e68 682 const struct plat_sci_reg *reg;
72b294cf
PM		 683
684 reg = sci_getreg(port, SCRFDR);
685 if (reg->size)
63f7ad11 686 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 687
688 reg = sci_getreg(port, SCFDR);
689 if (reg->size)
b12bb29f 690 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 691
b12bb29f 692 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 693}
694
514820eb
PM		 695/*
696 * SCI helper for checking the state of the muxed port/RXD pins.
697 */
698static inline int sci_rxd_in(struct uart_port *port)
699{
700 struct sci_port *s = to_sci_port(port);
701
702 if (s->cfg->port_reg <= 0)
703 return 1;
704
0dd4d5cb 705 /* Cast for ARM damage */
e2afca69 706 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 707}
708
1da177e4
LT		 709/* ********************************************************************** *
710 * the interrupt related routines *
711 * ********************************************************************** */
712
713static void sci_transmit_chars(struct uart_port *port)
714{
ebd2c8f6 715 struct circ_buf *xmit = &port->state->xmit;
1da177e4 716 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 717 unsigned short status;
718 unsigned short ctrl;
e108b2ca 719 int count;
1da177e4 720
b12bb29f 721 status = serial_port_in(port, SCxSR);
1da177e4 722 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 723 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 724 if (uart_circ_empty(xmit))
8e698614 725 ctrl &= ~SCSCR_TIE;
e7c98dc7 726 else
8e698614 727 ctrl |= SCSCR_TIE;
b12bb29f 728 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 729 return;
730 }
731
72b294cf 732 count = sci_txroom(port);
1da177e4
LT		 733
734 do {
735 unsigned char c;
736
737 if (port->x_char) {
738 c = port->x_char;
739 port->x_char = 0;
740 } else if (!uart_circ_empty(xmit) && !stopped) {
741 c = xmit->buf[xmit->tail];
742 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
743 } else {
744 break;
745 }
746
b12bb29f 747 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 748
749 port->icount.tx++;
750 } while (--count > 0);
751
a1b5b43f 752 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 753
754 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
755 uart_write_wakeup(port);
756 if (uart_circ_empty(xmit)) {
b129a8cc 757 sci_stop_tx(port);
1da177e4 758 } else {
b12bb29f 759 ctrl = serial_port_in(port, SCSCR);
1da177e4 760
1a22f08d 761 if (port->type != PORT_SCI) {
b12bb29f 762 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 763 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 764 }
1da177e4 765
8e698614 766 ctrl |= SCSCR_TIE;
b12bb29f 767 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 768 }
769}
770
771/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 772#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 773
94c8b6db 774static void sci_receive_chars(struct uart_port *port)
1da177e4 775{
e7c98dc7 776 struct sci_port *sci_port = to_sci_port(port);
227434f8 777 struct tty_port *tport = &port->state->port;
1da177e4
LT		 778 int i, count, copied = 0;
779 unsigned short status;
33f0f88f 780 unsigned char flag;
1da177e4 781
b12bb29f 782 status = serial_port_in(port, SCxSR);
1da177e4
LT		 783 if (!(status & SCxSR_RDxF(port)))
784 return;
785
786 while (1) {
1da177e4 787 /* Don't copy more bytes than there is room for in the buffer */
227434f8 788 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 789
790 /* If for any reason we can't copy more data, we're done! */
791 if (count == 0)
792 break;
793
794 if (port->type == PORT_SCI) {
b12bb29f 795 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 796 if (uart_handle_sysrq_char(port, c) ||
797 sci_port->break_flag)
1da177e4 798 count = 0;
e7c98dc7 799 else
92a19f9c 800 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 801 } else {
e7c98dc7 802 for (i = 0; i < count; i++) {
b12bb29f 803 char c = serial_port_in(port, SCxRDR);
d97fbbed 804
b12bb29f 805 status = serial_port_in(port, SCxSR);
1da177e4
LT		 806#if defined(CONFIG_CPU_SH3)
807 /* Skip "chars" during break */
e108b2ca 808 if (sci_port->break_flag) {
1da177e4
LT		 809 if ((c == 0) &&
810 (status & SCxSR_FER(port))) {
811 count--; i--;
812 continue;
813 }
e108b2ca 814
1da177e4 815 /* Nonzero => end-of-break */
762c69e3 816 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 817 sci_port->break_flag = 0;
818
1da177e4
LT		 819 if (STEPFN(c)) {
820 count--; i--;
821 continue;
822 }
823 }
824#endif /* CONFIG_CPU_SH3 */
7d12e780 825 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 826 count--; i--;
827 continue;
828 }
829
830 /* Store data and status */
73a19e4c 831 if (status & SCxSR_FER(port)) {
33f0f88f 832 flag = TTY_FRAME;
d97fbbed 833 port->icount.frame++;
762c69e3 834 dev_notice(port->dev, "frame error\n");
73a19e4c 835 } else if (status & SCxSR_PER(port)) {
33f0f88f 836 flag = TTY_PARITY;
d97fbbed 837 port->icount.parity++;
762c69e3 838 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 839 } else
840 flag = TTY_NORMAL;
762c69e3 841
92a19f9c 842 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 843 }
844 }
845
b12bb29f 846 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 847 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 848
1da177e4
LT		 849 copied += count;
850 port->icount.rx += count;
851 }
852
853 if (copied) {
854 /* Tell the rest of the system the news. New characters! */
2e124b4a 855 tty_flip_buffer_push(tport);
1da177e4 856 } else {
b12bb29f 857 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 858 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 859 }
860}
861
862#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 863
864/*
865 * The sci generates interrupts during the break,
1da177e4
LT		 866 * 1 per millisecond or so during the break period, for 9600 baud.
867 * So dont bother disabling interrupts.
868 * But dont want more than 1 break event.
869 * Use a kernel timer to periodically poll the rx line until
870 * the break is finished.
871 */
94c8b6db 872static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 873{
bc9b3f5c 874 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 875}
94c8b6db 876
1da177e4
LT		 877/* Ensure that two consecutive samples find the break over. */
878static void sci_break_timer(unsigned long data)
879{
e108b2ca
PM		 880 struct sci_port *port = (struct sci_port *)data;
881
882 if (sci_rxd_in(&port->port) == 0) {
1da177e4 883 port->break_flag = 1;
e108b2ca
PM		 884 sci_schedule_break_timer(port);
885 } else if (port->break_flag == 1) {
1da177e4
LT		 886 /* break is over. */
887 port->break_flag = 2;
e108b2ca
PM		 888 sci_schedule_break_timer(port);
889 } else
890 port->break_flag = 0;
1da177e4
LT		 891}
892
94c8b6db 893static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 894{
895 int copied = 0;
b12bb29f 896 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 897 struct tty_port *tport = &port->state->port;
debf9507 898 struct sci_port *s = to_sci_port(port);
1da177e4 899
3ae988d9 900 /* Handle overruns */
75c249fd 901 if (status & s->overrun_mask) {
3ae988d9 902 port->icount.overrun++;
d97fbbed 903
3ae988d9
LP		 904 /* overrun error */
905 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
906 copied++;
762c69e3 907
9b971cd2 908 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 909 }
910
e108b2ca 911 if (status & SCxSR_FER(port)) {
1da177e4
LT		 912 if (sci_rxd_in(port) == 0) {
913 /* Notify of BREAK */
e7c98dc7 914 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 915
916 if (!sci_port->break_flag) {
d97fbbed
PM		 917 port->icount.brk++;
918
e108b2ca
PM		 919 sci_port->break_flag = 1;
920 sci_schedule_break_timer(sci_port);
921
1da177e4 922 /* Do sysrq handling. */
e108b2ca 923 if (uart_handle_break(port))
1da177e4 924 return 0;
762c69e3
PM		 925
926 dev_dbg(port->dev, "BREAK detected\n");
927
92a19f9c 928 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 929 copied++;
930 }
931
e108b2ca 932 } else {
1da177e4 933 /* frame error */
d97fbbed
PM		 934 port->icount.frame++;
935
92a19f9c 936 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 937 copied++;
762c69e3
PM		 938
939 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 940 }
941 }
942
e108b2ca 943 if (status & SCxSR_PER(port)) {
1da177e4 944 /* parity error */
d97fbbed
PM		 945 port->icount.parity++;
946
92a19f9c 947 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 948 copied++;
762c69e3 949
9b971cd2 950 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 951 }
952
33f0f88f 953 if (copied)
2e124b4a 954 tty_flip_buffer_push(tport);
1da177e4
LT		 955
956 return copied;
957}
958
94c8b6db 959static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 960{
92a19f9c 961 struct tty_port *tport = &port->state->port;
debf9507 962 struct sci_port *s = to_sci_port(port);
d3184e68 963 const struct plat_sci_reg *reg;
2e0842a1 964 int copied = 0;
75c249fd 965 u16 status;
d830fa45 966
2e0842a1 967 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 968 if (!reg->size)
d830fa45
PM		 969 return 0;
970
2e0842a1 971 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 972 if (status & s->overrun_mask) {
973 status &= ~s->overrun_mask;
2e0842a1 974 serial_port_out(port, s->overrun_reg, status);
d830fa45 975
d97fbbed
PM		 976 port->icount.overrun++;
977
92a19f9c 978 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 979 tty_flip_buffer_push(tport);
d830fa45 980
51b31f1c 981 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 982 copied++;
983 }
984
985 return copied;
986}
987
94c8b6db 988static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 989{
990 int copied = 0;
b12bb29f 991 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 992 struct tty_port *tport = &port->state->port;
a5660ada 993 struct sci_port *s = to_sci_port(port);
1da177e4 994
0b3d4ef6
PM		 995 if (uart_handle_break(port))
996 return 0;
997
b7a76e4b 998 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 999#if defined(CONFIG_CPU_SH3)
1000 /* Debounce break */
1001 s->break_flag = 1;
1002#endif
d97fbbed
PM		 1003
1004 port->icount.brk++;
1005
1da177e4 1006 /* Notify of BREAK */
92a19f9c 1007 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1008 copied++;
762c69e3
PM		 1009
1010 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1011 }
1012
33f0f88f 1013 if (copied)
2e124b4a 1014 tty_flip_buffer_push(tport);
e108b2ca 1015
d830fa45
PM		 1016 copied += sci_handle_fifo_overrun(port);
1017
1da177e4
LT		 1018 return copied;
1019}
1020
73a19e4c 1021#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1022static void sci_dma_tx_complete(void *arg)
1023{
1024 struct sci_port *s = arg;
1025 struct uart_port *port = &s->port;
1026 struct circ_buf *xmit = &port->state->xmit;
1027 unsigned long flags;
73a19e4c 1028
e1910fcd 1029 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1030
e1910fcd 1031 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1032
e1910fcd
GU		 1033 xmit->tail += s->tx_dma_len;
1034 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1035
e1910fcd 1036 port->icount.tx += s->tx_dma_len;
1da177e4 1037
e1910fcd
GU		 1038 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1039 uart_write_wakeup(port);
1da177e4 1040
e1910fcd
GU		 1041 if (!uart_circ_empty(xmit)) {
1042 s->cookie_tx = 0;
1043 schedule_work(&s->work_tx);
1044 } else {
1045 s->cookie_tx = -EINVAL;
1046 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1047 u16 ctrl = serial_port_in(port, SCSCR);
1048 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1049 }
1050 }
1da177e4 1051
fd78a76a 1052 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1053}
1054
e1910fcd
GU		 1055/* Locking: called with port lock held */
1056static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1057{
e1910fcd
GU		 1058 struct uart_port *port = &s->port;
1059 struct tty_port *tport = &port->state->port;
1060 int copied;
1da177e4 1061
e1910fcd
GU		 1062 copied = tty_insert_flip_string(tport, buf, count);
1063 if (copied < count) {
1064 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1065 count - copied);
1066 port->icount.buf_overrun++;
1da177e4
LT		 1067 }
1068
e1910fcd 1069 port->icount.rx += copied;
1da177e4 1070
e1910fcd 1071 return copied;
1da177e4
LT		 1072}
1073
e1910fcd 1074static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1075{
e1910fcd 1076 unsigned int i;
1da177e4 1077
e1910fcd
GU		 1078 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1079 if (s->active_rx == s->cookie_rx[i])
1080 return i;
1da177e4 1081
e1910fcd
GU		 1082 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1083 s->active_rx);
1084 return -1;
1da177e4
LT		 1085}
1086
e1910fcd 1087static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1088{
e1910fcd
GU		 1089 struct dma_chan *chan = s->chan_rx;
1090 struct uart_port *port = &s->port;
1091 unsigned long flags;
1092
1093 spin_lock_irqsave(&port->lock, flags);
1094 s->chan_rx = NULL;
1095 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1096 spin_unlock_irqrestore(&port->lock, flags);
1097 dmaengine_terminate_all(chan);
1098 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1099 sg_dma_address(&s->sg_rx[0]));
1100 dma_release_channel(chan);
1101 if (enable_pio)
1102 sci_start_rx(port);
f43dc23d
PM		 1103}
1104
e1910fcd 1105static void sci_dma_rx_complete(void *arg)
1da177e4 1106{
e1910fcd
GU		 1107 struct sci_port *s = arg;
1108 struct uart_port *port = &s->port;
1109 unsigned long flags;
1110 int active, count = 0;
1da177e4 1111
e1910fcd
GU		 1112 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1113 s->active_rx);
cb772fe7 1114
e1910fcd 1115 spin_lock_irqsave(&port->lock, flags);
1da177e4 1116
e1910fcd
GU		 1117 active = sci_dma_rx_find_active(s);
1118 if (active >= 0)
1119 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1120
e1910fcd 1121 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1122
e1910fcd 1123 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1124
e1910fcd
GU		 1125 if (count)
1126 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1127
e1910fcd 1128 schedule_work(&s->work_rx);
1da177e4
LT		 1129}
1130
e1910fcd 1131static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1132{
e1910fcd
GU		 1133 struct dma_chan *chan = s->chan_tx;
1134 struct uart_port *port = &s->port;
e552de24 1135 unsigned long flags;
1da177e4 1136
e1910fcd
GU		 1137 spin_lock_irqsave(&port->lock, flags);
1138 s->chan_tx = NULL;
1139 s->cookie_tx = -EINVAL;
1140 spin_unlock_irqrestore(&port->lock, flags);
1141 dmaengine_terminate_all(chan);
1142 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1143 DMA_TO_DEVICE);
1144 dma_release_channel(chan);
1145 if (enable_pio)
1146 sci_start_tx(port);
1147}
d535a230 1148
e1910fcd
GU		 1149static void sci_submit_rx(struct sci_port *s)
1150{
1151 struct dma_chan *chan = s->chan_rx;
1152 int i;
073e84c9 1153
e1910fcd
GU		 1154 for (i = 0; i < 2; i++) {
1155 struct scatterlist *sg = &s->sg_rx[i];
1156 struct dma_async_tx_descriptor *desc;
1da177e4 1157
e1910fcd
GU		 1158 desc = dmaengine_prep_slave_sg(chan,
1159 sg, 1, DMA_DEV_TO_MEM,
1160 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1161 if (!desc)
1162 goto fail;
501b825d 1163
e1910fcd
GU		 1164 desc->callback = sci_dma_rx_complete;
1165 desc->callback_param = s;
1166 s->cookie_rx[i] = dmaengine_submit(desc);
1167 if (dma_submit_error(s->cookie_rx[i]))
1168 goto fail;
9174fc8f 1169
e1910fcd
GU		 1170 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1171 s->cookie_rx[i], i);
1172 }
9174fc8f 1173
e1910fcd 1174 s->active_rx = s->cookie_rx[0];
9174fc8f 1175
e1910fcd
GU		 1176 dma_async_issue_pending(chan);
1177 return;
9174fc8f 1178
e1910fcd
GU		 1179fail:
1180 if (i)
1181 dmaengine_terminate_all(chan);
1182 for (i = 0; i < 2; i++)
1183 s->cookie_rx[i] = -EINVAL;
1184 s->active_rx = -EINVAL;
1185 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1186 sci_rx_dma_release(s, true);
1187}
9174fc8f 1188
e1910fcd 1189static void work_fn_rx(struct work_struct *work)
1da177e4 1190{
e1910fcd
GU		 1191 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1192 struct uart_port *port = &s->port;
1193 struct dma_async_tx_descriptor *desc;
1194 struct dma_tx_state state;
1195 enum dma_status status;
1196 unsigned long flags;
1197 int new;
9174fc8f 1198
e1910fcd
GU		 1199 spin_lock_irqsave(&port->lock, flags);
1200 new = sci_dma_rx_find_active(s);
1201 if (new < 0) {
1202 spin_unlock_irqrestore(&port->lock, flags);
1203 return;
1204 }
9174fc8f 1205
e1910fcd
GU		 1206 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1207 if (status != DMA_COMPLETE) {
1208 /* Handle incomplete DMA receive */
1209 struct dma_chan *chan = s->chan_rx;
1210 unsigned int read;
1211 int count;
9174fc8f 1212
e1910fcd
GU		 1213 dmaengine_terminate_all(chan);
1214 read = sg_dma_len(&s->sg_rx[new]) - state.residue;
1215 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1216 s->active_rx);
1217
1218 if (read) {
1219 count = sci_dma_rx_push(s, s->rx_buf[new], read);
1220 if (count)
1221 tty_flip_buffer_push(&port->state->port);
0e8963de
PM		 1222 }
1223
e1910fcd 1224 spin_unlock_irqrestore(&port->lock, flags);
9174fc8f 1225
e1910fcd
GU		 1226 sci_submit_rx(s);
1227 return;
1da177e4
LT		 1228 }
1229
e1910fcd
GU		 1230 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[new], 1,
1231 DMA_DEV_TO_MEM,
1232 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1233 if (!desc)
1234 goto fail;
9174fc8f 1235
e1910fcd
GU		 1236 desc->callback = sci_dma_rx_complete;
1237 desc->callback_param = s;
1238 s->cookie_rx[new] = dmaengine_submit(desc);
1239 if (dma_submit_error(s->cookie_rx[new]))
1240 goto fail;
9174fc8f 1241
e1910fcd 1242 s->active_rx = s->cookie_rx[!new];
9174fc8f 1243
e1910fcd
GU		 1244 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1245 __func__, s->cookie_rx[new], new, s->active_rx);
1246 spin_unlock_irqrestore(&port->lock, flags);
1247 return;
1248
1249fail:
1250 spin_unlock_irqrestore(&port->lock, flags);
1251 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1252 sci_rx_dma_release(s, true);
1da177e4
LT		 1253}
1254
e1910fcd 1255static void work_fn_tx(struct work_struct *work)
1da177e4 1256{
e1910fcd
GU		 1257 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1258 struct dma_async_tx_descriptor *desc;
1259 struct dma_chan *chan = s->chan_tx;
1260 struct uart_port *port = &s->port;
1261 struct circ_buf *xmit = &port->state->xmit;
1262 dma_addr_t buf;
1da177e4 1263
9174fc8f 1264 /*
e1910fcd
GU		 1265 * DMA is idle now.
1266 * Port xmit buffer is already mapped, and it is one page... Just adjust
1267 * offsets and lengths. Since it is a circular buffer, we have to
1268 * transmit till the end, and then the rest. Take the port lock to get a
1269 * consistent xmit buffer state.
9174fc8f 1270 */
e1910fcd
GU		 1271 spin_lock_irq(&port->lock);
1272 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1273 s->tx_dma_len = min_t(unsigned int,
1274 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1275 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1276 spin_unlock_irq(&port->lock);
0e8963de 1277
e1910fcd
GU		 1278 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1279 DMA_MEM_TO_DEV,
1280 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1281 if (!desc) {
1282 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1283 /* switch to PIO */
1284 sci_tx_dma_release(s, true);
1285 return;
1286 }
0e8963de 1287
e1910fcd
GU		 1288 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1289 DMA_TO_DEVICE);
1da177e4 1290
e1910fcd
GU		 1291 spin_lock_irq(&port->lock);
1292 desc->callback = sci_dma_tx_complete;
1293 desc->callback_param = s;
1294 spin_unlock_irq(&port->lock);
1295 s->cookie_tx = dmaengine_submit(desc);
1296 if (dma_submit_error(s->cookie_tx)) {
1297 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1298 /* switch to PIO */
1299 sci_tx_dma_release(s, true);
1300 return;
1da177e4 1301 }
1da177e4 1302
e1910fcd
GU		 1303 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1304 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1305
e1910fcd 1306 dma_async_issue_pending(chan);
1da177e4
LT		 1307}
1308
e1910fcd 1309static bool filter(struct dma_chan *chan, void *slave)
1da177e4 1310{
e1910fcd 1311 struct sh_dmae_slave *param = slave;
dc7e3ef7 1312
e1910fcd
GU		 1313 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1314 __func__, param->shdma_slave.slave_id);
1315
1316 chan->private = &param->shdma_slave;
1317 return true;
1da177e4
LT		 1318}
1319
e1910fcd 1320static void rx_timer_fn(unsigned long arg)
1da177e4 1321{
e1910fcd
GU		 1322 struct sci_port *s = (struct sci_port *)arg;
1323 struct uart_port *port = &s->port;
1324 u16 scr = serial_port_in(port, SCSCR);
1325
1326 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1327 scr &= ~SCSCR_RDRQE;
1328 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1329 }
1330 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1331 dev_dbg(port->dev, "DMA Rx timed out\n");
1332 schedule_work(&s->work_rx);
1da177e4
LT		 1333}
1334
e1910fcd 1335static void sci_request_dma(struct uart_port *port)
73a19e4c 1336{
e1910fcd
GU		 1337 struct sci_port *s = to_sci_port(port);
1338 struct sh_dmae_slave *param;
1339 struct dma_chan *chan;
1340 dma_cap_mask_t mask;
73a19e4c 1341
e1910fcd 1342 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1343
e1910fcd
GU		 1344 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1345 return;
73a19e4c 1346
e1910fcd
GU		 1347 dma_cap_zero(mask);
1348 dma_cap_set(DMA_SLAVE, mask);
73a19e4c 1349
e1910fcd 1350 param = &s->param_tx;
73a19e4c 1351
e1910fcd
GU		 1352 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1353 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c 1354
e1910fcd
GU		 1355 s->cookie_tx = -EINVAL;
1356 chan = dma_request_channel(mask, filter, param);
1357 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1358 if (chan) {
1359 s->chan_tx = chan;
1360 /* UART circular tx buffer is an aligned page. */
1361 s->tx_dma_addr = dma_map_single(chan->device->dev,
1362 port->state->xmit.buf,
1363 UART_XMIT_SIZE,
1364 DMA_TO_DEVICE);
1365 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1366 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1367 dma_release_channel(chan);
1368 s->chan_tx = NULL;
1369 } else {
1370 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1371 __func__, UART_XMIT_SIZE,
1372 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1373 }
e1910fcd
GU		 1374
1375 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1376 }
1377
e1910fcd 1378 param = &s->param_rx;
73a19e4c 1379
e1910fcd
GU		 1380 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1381 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c 1382
e1910fcd
GU		 1383 chan = dma_request_channel(mask, filter, param);
1384 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1385 if (chan) {
1386 unsigned int i;
1387 dma_addr_t dma;
1388 void *buf;
73a19e4c 1389
e1910fcd 1390 s->chan_rx = chan;
73a19e4c 1391
e1910fcd
GU		 1392 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1393 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1394 &dma, GFP_KERNEL);
1395 if (!buf) {
1396 dev_warn(port->dev,
1397 "Failed to allocate Rx dma buffer, using PIO\n");
1398 dma_release_channel(chan);
1399 s->chan_rx = NULL;
1400 sci_start_rx(port);
1401 return;
1402 }
73a19e4c 1403
e1910fcd
GU		 1404 for (i = 0; i < 2; i++) {
1405 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1406
e1910fcd
GU		 1407 sg_init_table(sg, 1);
1408 s->rx_buf[i] = buf;
1409 sg_dma_address(sg) = dma;
1410 sg->length = s->buf_len_rx;
0533502d 1411
e1910fcd
GU		 1412 buf += s->buf_len_rx;
1413 dma += s->buf_len_rx;
1414 }
1415
1416 INIT_WORK(&s->work_rx, work_fn_rx);
1417 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1418
1419 sci_submit_rx(s);
1420 }
0533502d
GU		 1421}
1422
e1910fcd 1423static void sci_free_dma(struct uart_port *port)
73a19e4c 1424{
e1910fcd 1425 struct sci_port *s = to_sci_port(port);
73a19e4c 1426
e1910fcd
GU		 1427 if (s->chan_tx)
1428 sci_tx_dma_release(s, false);
1429 if (s->chan_rx)
1430 sci_rx_dma_release(s, false);
1431}
1432#else
1433static inline void sci_request_dma(struct uart_port *port)
1434{
1435}
73a19e4c 1436
e1910fcd
GU		 1437static inline void sci_free_dma(struct uart_port *port)
1438{
1439}
1440#endif
73a19e4c 1441
e1910fcd
GU		 1442static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1443{
1444#ifdef CONFIG_SERIAL_SH_SCI_DMA
1445 struct uart_port *port = ptr;
1446 struct sci_port *s = to_sci_port(port);
73a19e4c 1447
e1910fcd
GU		 1448 if (s->chan_rx) {
1449 u16 scr = serial_port_in(port, SCSCR);
1450 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1451
e1910fcd
GU		 1452 /* Disable future Rx interrupts */
1453 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1454 disable_irq_nosync(irq);
1455 scr |= SCSCR_RDRQE;
1456 } else {
1457 scr &= ~SCSCR_RIE;
1458 }
1459 serial_port_out(port, SCSCR, scr);
1460 /* Clear current interrupt */
1461 serial_port_out(port, SCxSR,
1462 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1463 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1464 jiffies, s->rx_timeout);
1465 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1466
e1910fcd
GU		 1467 return IRQ_HANDLED;
1468 }
1469#endif
73a19e4c 1470
e1910fcd
GU		 1471 /* I think sci_receive_chars has to be called irrespective
1472 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1473 * to be disabled?
1474 */
1475 sci_receive_chars(ptr);
1476
1477 return IRQ_HANDLED;
73a19e4c
GL		 1478}
1479
e1910fcd 1480static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1481{
e1910fcd 1482 struct uart_port *port = ptr;
04928b79 1483 unsigned long flags;
73a19e4c 1484
04928b79 1485 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1486 sci_transmit_chars(port);
04928b79 1487 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1488
1489 return IRQ_HANDLED;
73a19e4c
GL		 1490}
1491
e1910fcd 1492static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1493{
e1910fcd
GU		 1494 struct uart_port *port = ptr;
1495 struct sci_port *s = to_sci_port(port);
73a19e4c 1496
e1910fcd
GU		 1497 /* Handle errors */
1498 if (port->type == PORT_SCI) {
1499 if (sci_handle_errors(port)) {
1500 /* discard character in rx buffer */
1501 serial_port_in(port, SCxSR);
1502 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1503 }
1504 } else {
1505 sci_handle_fifo_overrun(port);
1506 if (!s->chan_rx)
1507 sci_receive_chars(ptr);
1508 }
1509
1510 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1511
1512 /* Kick the transmission */
1513 if (!s->chan_tx)
1514 sci_tx_interrupt(irq, ptr);
1515
1516 return IRQ_HANDLED;
73a19e4c
GL		 1517}
1518
e1910fcd 1519static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1520{
e1910fcd 1521 struct uart_port *port = ptr;
73a19e4c 1522
e1910fcd
GU		 1523 /* Handle BREAKs */
1524 sci_handle_breaks(port);
1525 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1526
e1910fcd
GU		 1527 return IRQ_HANDLED;
1528}
73a19e4c 1529
e1910fcd
GU		 1530static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1531{
1532 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1533 struct uart_port *port = ptr;
1534 struct sci_port *s = to_sci_port(port);
1535 irqreturn_t ret = IRQ_NONE;
73a19e4c 1536
e1910fcd
GU		 1537 ssr_status = serial_port_in(port, SCxSR);
1538 scr_status = serial_port_in(port, SCSCR);
1539 if (s->overrun_reg == SCxSR)
1540 orer_status = ssr_status;
1541 else {
1542 if (sci_getreg(port, s->overrun_reg)->size)
1543 orer_status = serial_port_in(port, s->overrun_reg);
73a19e4c
GL		 1544 }
1545
e1910fcd 1546 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1547
e1910fcd
GU		 1548 /* Tx Interrupt */
1549 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1550 !s->chan_tx)
1551 ret = sci_tx_interrupt(irq, ptr);
658daa95 1552
e1910fcd
GU		 1553 /*
1554 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1555 * DR flags
1556 */
1557 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1558 (scr_status & SCSCR_RIE))
1559 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1560
e1910fcd
GU		 1561 /* Error Interrupt */
1562 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1563 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1564
e1910fcd
GU		 1565 /* Break Interrupt */
1566 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1567 ret = sci_br_interrupt(irq, ptr);
1568
1569 /* Overrun Interrupt */
1570 if (orer_status & s->overrun_mask) {
1571 sci_handle_fifo_overrun(port);
1572 ret = IRQ_HANDLED;
73a19e4c 1573 }
73a19e4c 1574
e1910fcd
GU		 1575 return ret;
1576}
73a19e4c 1577
e1910fcd
GU		 1578/*
1579 * Here we define a transition notifier so that we can update all of our
1580 * ports' baud rate when the peripheral clock changes.
1581 */
1582static int sci_notifier(struct notifier_block *self,
1583 unsigned long phase, void *p)
1584{
1585 struct sci_port *sci_port;
1586 unsigned long flags;
73a19e4c 1587
e1910fcd 1588 sci_port = container_of(self, struct sci_port, freq_transition);
73a19e4c 1589
e1910fcd
GU		 1590 if (phase == CPUFREQ_POSTCHANGE) {
1591 struct uart_port *port = &sci_port->port;
73a19e4c 1592
e1910fcd
GU		 1593 spin_lock_irqsave(&port->lock, flags);
1594 port->uartclk = clk_get_rate(sci_port->iclk);
1595 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1596 }
1597
e1910fcd
GU		 1598 return NOTIFY_OK;
1599}
73a19e4c 1600
e1910fcd
GU		 1601static const struct sci_irq_desc {
1602 const char *desc;
1603 irq_handler_t handler;
1604} sci_irq_desc[] = {
1605 /*
1606 * Split out handlers, the default case.
1607 */
1608 [SCIx_ERI_IRQ] = {
1609 .desc = "rx err",
1610 .handler = sci_er_interrupt,
1611 },
3089f381 1612
e1910fcd
GU		 1613 [SCIx_RXI_IRQ] = {
1614 .desc = "rx full",
1615 .handler = sci_rx_interrupt,
1616 },
47aceb92 1617
e1910fcd
GU		 1618 [SCIx_TXI_IRQ] = {
1619 .desc = "tx empty",
1620 .handler = sci_tx_interrupt,
1621 },
73a19e4c 1622
e1910fcd
GU		 1623 [SCIx_BRI_IRQ] = {
1624 .desc = "break",
1625 .handler = sci_br_interrupt,
1626 },
73a19e4c
GL		 1627
1628 /*
e1910fcd 1629 * Special muxed handler.
73a19e4c 1630 */
e1910fcd
GU		 1631 [SCIx_MUX_IRQ] = {
1632 .desc = "mux",
1633 .handler = sci_mpxed_interrupt,
1634 },
1635};
73a19e4c 1636
e1910fcd
GU		 1637static int sci_request_irq(struct sci_port *port)
1638{
1639 struct uart_port *up = &port->port;
1640 int i, j, ret = 0;
73a19e4c 1641
e1910fcd
GU		 1642 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1643 const struct sci_irq_desc *desc;
1644 int irq;
73a19e4c 1645
e1910fcd
GU		 1646 if (SCIx_IRQ_IS_MUXED(port)) {
1647 i = SCIx_MUX_IRQ;
1648 irq = up->irq;
1649 } else {
1650 irq = port->irqs[i];
1651
1652 /*
1653 * Certain port types won't support all of the
1654 * available interrupt sources.
1655 */
1656 if (unlikely(irq < 0))
1657 continue;
1658 }
1659
1660 desc = sci_irq_desc + i;
1661 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1662 dev_name(up->dev), desc->desc);
1663 if (!port->irqstr[j])
1664 goto out_nomem;
1665
1666 ret = request_irq(irq, desc->handler, up->irqflags,
1667 port->irqstr[j], port);
1668 if (unlikely(ret)) {
1669 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1670 goto out_noirq;
1671 }
73a19e4c
GL		 1672 }
1673
e1910fcd 1674 return 0;
1da177e4 1675
e1910fcd
GU		 1676out_noirq:
1677 while (--i >= 0)
1678 free_irq(port->irqs[i], port);
f43dc23d 1679
e1910fcd
GU		 1680out_nomem:
1681 while (--j >= 0)
1682 kfree(port->irqstr[j]);
f43dc23d 1683
e1910fcd 1684 return ret;
1da177e4
LT		 1685}
1686
e1910fcd 1687static void sci_free_irq(struct sci_port *port)
1da177e4 1688{
e1910fcd 1689 int i;
1da177e4 1690
e1910fcd
GU		 1691 /*
1692 * Intentionally in reverse order so we iterate over the muxed
1693 * IRQ first.
1694 */
1695 for (i = 0; i < SCIx_NR_IRQS; i++) {
1696 int irq = port->irqs[i];
f43dc23d 1697
e1910fcd
GU		 1698 /*
1699 * Certain port types won't support all of the available
1700 * interrupt sources.
1701 */
1702 if (unlikely(irq < 0))
1703 continue;
f43dc23d 1704
e1910fcd
GU		 1705 free_irq(port->irqs[i], port);
1706 kfree(port->irqstr[i]);
f43dc23d 1707
e1910fcd
GU		 1708 if (SCIx_IRQ_IS_MUXED(port)) {
1709 /* If there's only one IRQ, we're done. */
1710 return;
1711 }
1712 }
1da177e4
LT		 1713}
1714
e1910fcd 1715static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1716{
e1910fcd
GU		 1717 unsigned short status = serial_port_in(port, SCxSR);
1718 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1719
e1910fcd 1720 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1721}
1722
e1910fcd
GU		 1723/*
1724 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1725 * CTS/RTS is supported in hardware by at least one port and controlled
1726 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1727 * handled via the ->init_pins() op, which is a bit of a one-way street,
1728 * lacking any ability to defer pin control -- this will later be
1729 * converted over to the GPIO framework).
1730 *
1731 * Other modes (such as loopback) are supported generically on certain
1732 * port types, but not others. For these it's sufficient to test for the
1733 * existence of the support register and simply ignore the port type.
1734 */
1735static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1736{
e1910fcd
GU		 1737 if (mctrl & TIOCM_LOOP) {
1738 const struct plat_sci_reg *reg;
f43dc23d 1739
e1910fcd
GU		 1740 /*
1741 * Standard loopback mode for SCFCR ports.
1742 */
1743 reg = sci_getreg(port, SCFCR);
1744 if (reg->size)
1745 serial_port_out(port, SCFCR,
1746 serial_port_in(port, SCFCR) |
1747 SCFCR_LOOP);
1748 }
1749}
f43dc23d 1750
e1910fcd
GU		 1751static unsigned int sci_get_mctrl(struct uart_port *port)
1752{
1753 /*
1754 * CTS/RTS is handled in hardware when supported, while nothing
1755 * else is wired up. Keep it simple and simply assert DSR/CAR.
1756 */
1757 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1758}
1759
1da177e4
LT		 1760static void sci_break_ctl(struct uart_port *port, int break_state)
1761{
bbb4ce50 1762 struct sci_port *s = to_sci_port(port);
d3184e68 1763 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1764 unsigned short scscr, scsptr;
1765
a4e02f6d
SY		 1766 /* check wheter the port has SCSPTR */
1767 if (!reg->size) {
bbb4ce50
SY		 1768 /*
1769 * Not supported by hardware. Most parts couple break and rx
1770 * interrupts together, with break detection always enabled.
1771 */
a4e02f6d 1772 return;
bbb4ce50 1773 }
a4e02f6d
SY		 1774
1775 scsptr = serial_port_in(port, SCSPTR);
1776 scscr = serial_port_in(port, SCSCR);
1777
1778 if (break_state == -1) {
1779 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1780 scscr &= ~SCSCR_TE;
1781 } else {
1782 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1783 scscr |= SCSCR_TE;
1784 }
1785
1786 serial_port_out(port, SCSPTR, scsptr);
1787 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1788}
1789
1790static int sci_startup(struct uart_port *port)
1791{
a5660ada 1792 struct sci_port *s = to_sci_port(port);
33b48e16 1793 unsigned long flags;
073e84c9 1794 int ret;
1da177e4 1795
73a19e4c
GL		 1796 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1797
073e84c9
PM		 1798 ret = sci_request_irq(s);
1799 if (unlikely(ret < 0))
1800 return ret;
1801
73a19e4c 1802 sci_request_dma(port);
073e84c9 1803
33b48e16 1804 spin_lock_irqsave(&port->lock, flags);
d656901b 1805 sci_start_tx(port);
73a19e4c 1806 sci_start_rx(port);
33b48e16 1807 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1808
1809 return 0;
1810}
1811
1812static void sci_shutdown(struct uart_port *port)
1813{
a5660ada 1814 struct sci_port *s = to_sci_port(port);
33b48e16 1815 unsigned long flags;
1da177e4 1816
73a19e4c
GL		 1817 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1818
33b48e16 1819 spin_lock_irqsave(&port->lock, flags);
1da177e4 1820 sci_stop_rx(port);
b129a8cc 1821 sci_stop_tx(port);
33b48e16 1822 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1823
73a19e4c 1824 sci_free_dma(port);
1da177e4 1825 sci_free_irq(s);
1da177e4
LT		 1826}
1827
ec09c5eb 1828static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1829 unsigned long freq)
1830{
ec09c5eb
LP		 1831 if (s->sampling_rate)
1832 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1833
26c92f37
PM		 1834 /* Warn, but use a safe default */
1835 WARN_ON(1);
e8183a6c 1836
26c92f37
PM		 1837 return ((freq + 16 * bps) / (32 * bps) - 1);
1838}
1839
730c4e78
NI		 1840/* calculate frame length from SMR */
1841static int sci_baud_calc_frame_len(unsigned int smr_val)
1842{
1843 int len = 10;
1844
1845 if (smr_val & SCSMR_CHR)
1846 len--;
1847 if (smr_val & SCSMR_PE)
1848 len++;
1849 if (smr_val & SCSMR_STOP)
1850 len++;
1851
1852 return len;
1853}
1854
1855
f303b364
UH		 1856/* calculate sample rate, BRR, and clock select for HSCIF */
1857static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1858 int *brr, unsigned int *srr,
730c4e78 1859 unsigned int *cks, int frame_len)
f303b364 1860{
730c4e78 1861 int sr, c, br, err, recv_margin;
f303b364 1862 int min_err = 1000; /* 100% */
730c4e78 1863 int recv_max_margin = 0;
f303b364
UH		 1864
1865 /* Find the combination of sample rate and clock select with the
1866 smallest deviation from the desired baud rate. */
1867 for (sr = 8; sr <= 32; sr++) {
1868 for (c = 0; c <= 3; c++) {
1869 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1870 br = DIV_ROUND_CLOSEST(freq, (sr *
1871 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1872 br = clamp(br, 0, 255);
b7d66397
NI		 1873 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1874 (1 << (2 * c + 1)) / 1000)) -
1875 1000;
730c4e78
NI		 1876 /* Calc recv margin
1877 * M: Receive margin (%)
1878 * N: Ratio of bit rate to clock (N = sampling rate)
1879 * D: Clock duty (D = 0 to 1.0)
1880 * L: Frame length (L = 9 to 12)
1881 * F: Absolute value of clock frequency deviation
1882 *
1883 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1884 * (|D - 0.5| / N * (1 + F))|
1885 * NOTE: Usually, treat D for 0.5, F is 0 by this
1886 * calculation.
1887 */
1888 recv_margin = abs((500 -
1889 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1890 if (abs(min_err) > abs(err)) {
f303b364 1891 min_err = err;
730c4e78
NI		 1892 recv_max_margin = recv_margin;
1893 } else if ((min_err == err) &&
1894 (recv_margin > recv_max_margin))
1895 recv_max_margin = recv_margin;
1896 else
1897 continue;
1898
1899 *brr = br;
1900 *srr = sr - 1;
1901 *cks = c;
f303b364
UH		 1902 }
1903 }
1904
1905 if (min_err == 1000) {
1906 WARN_ON(1);
1907 /* use defaults */
1908 *brr = 255;
1909 *srr = 15;
1910 *cks = 0;
1911 }
1912}
1913
1ba76220
MD		 1914static void sci_reset(struct uart_port *port)
1915{
d3184e68 1916 const struct plat_sci_reg *reg;
1ba76220
MD		 1917 unsigned int status;
1918
1919 do {
b12bb29f 1920 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1921 } while (!(status & SCxSR_TEND(port)));
1922
b12bb29f 1923 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1924
0979e0e6
PM		 1925 reg = sci_getreg(port, SCFCR);
1926 if (reg->size)
b12bb29f 1927 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1928}
1929
606d099c
AC		 1930static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1931 struct ktermios *old)
1da177e4 1932{
00b9de9c 1933 struct sci_port *s = to_sci_port(port);
d3184e68 1934 const struct plat_sci_reg *reg;
730c4e78 1935 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1936 int t = -1;
d4759ded 1937 unsigned int srr = 15;
1da177e4 1938
730c4e78
NI		 1939 if ((termios->c_cflag & CSIZE) == CS7)
1940 smr_val |= SCSMR_CHR;
1941 if (termios->c_cflag & PARENB)
1942 smr_val |= SCSMR_PE;
1943 if (termios->c_cflag & PARODD)
1944 smr_val |= SCSMR_PE | SCSMR_ODD;
1945 if (termios->c_cflag & CSTOPB)
1946 smr_val |= SCSMR_STOP;
1947
154280fd
MD		 1948 /*
1949 * earlyprintk comes here early on with port->uartclk set to zero.
1950 * the clock framework is not up and running at this point so here
1951 * we assume that 115200 is the maximum baud rate. please note that
1952 * the baud rate is not programmed during earlyprintk - it is assumed
1953 * that the previous boot loader has enabled required clocks and
1954 * setup the baud rate generator hardware for us already.
1955 */
1956 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1957
154280fd 1958 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1959 if (likely(baud && port->uartclk)) {
ec09c5eb 1960 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1961 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1962 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1963 &cks, frame_len);
f303b364 1964 } else {
ec09c5eb 1965 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1966 for (cks = 0; t >= 256 && cks <= 3; cks++)
1967 t >>= 2;
1968 }
1969 }
e108b2ca 1970
23241d43 1971 sci_port_enable(s);
36003386 1972
1ba76220 1973 sci_reset(port);
1da177e4 1974
2944a331 1975 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 1976
1977 uart_update_timeout(port, termios->c_cflag, baud);
1978
9d482cc3
TY		 1979 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1980 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1981
4ffc3cdb 1982 if (t >= 0) {
26de4f1b 1983 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 1984 serial_port_out(port, SCBRR, t);
f303b364
UH		 1985 reg = sci_getreg(port, HSSRR);
1986 if (reg->size)
1987 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1988 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1989 } else
1990 serial_port_out(port, SCSMR, smr_val);
1da177e4 1991
d5701647 1992 sci_init_pins(port, termios->c_cflag);
0979e0e6 1993
73c3d53f
PM		 1994 reg = sci_getreg(port, SCFCR);
1995 if (reg->size) {
b12bb29f 1996 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1997
73c3d53f 1998 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1999 if (termios->c_cflag & CRTSCTS)
2000 ctrl |= SCFCR_MCE;
2001 else
2002 ctrl &= ~SCFCR_MCE;
faf02f8f 2003 }
73c3d53f
PM		 2004
2005 /*
2006 * As we've done a sci_reset() above, ensure we don't
2007 * interfere with the FIFOs while toggling MCE. As the
2008 * reset values could still be set, simply mask them out.
2009 */
2010 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2011
b12bb29f 2012 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2013 }
b7a76e4b 2014
b12bb29f 2015 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2016
3089f381
GL		 2017#ifdef CONFIG_SERIAL_SH_SCI_DMA
2018 /*
5f6d8515 2019 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2020 * See serial_core.c::uart_update_timeout().
2021 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2022 * function calculates 1 jiffie for the data plus 5 jiffies for the
2023 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2024 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2025 * value obtained by this formula is too small. Therefore, if the value
2026 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2027 */
2028 if (s->chan_rx) {
5f6d8515
NI		 2029 unsigned int bits;
2030
2031 /* byte size and parity */
2032 switch (termios->c_cflag & CSIZE) {
2033 case CS5:
2034 bits = 7;
2035 break;
2036 case CS6:
2037 bits = 8;
2038 break;
2039 case CS7:
2040 bits = 9;
2041 break;
2042 default:
2043 bits = 10;
2044 break;
2045 }
2046
2047 if (termios->c_cflag & CSTOPB)
2048 bits++;
2049 if (termios->c_cflag & PARENB)
2050 bits++;
2051 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2052 (baud / 10), 10);
9b971cd2 2053 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2054 s->rx_timeout * 1000 / HZ, port->timeout);
2055 if (s->rx_timeout < msecs_to_jiffies(20))
2056 s->rx_timeout = msecs_to_jiffies(20);
2057 }
2058#endif
2059
1da177e4 2060 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2061 sci_start_rx(port);
36003386 2062
23241d43 2063 sci_port_disable(s);
1da177e4
LT		 2064}
2065
0174e5ca
TK		 2066static void sci_pm(struct uart_port *port, unsigned int state,
2067 unsigned int oldstate)
2068{
2069 struct sci_port *sci_port = to_sci_port(port);
2070
2071 switch (state) {
d3dfe5d9 2072 case UART_PM_STATE_OFF:
0174e5ca
TK		 2073 sci_port_disable(sci_port);
2074 break;
2075 default:
2076 sci_port_enable(sci_port);
2077 break;
2078 }
2079}
2080
1da177e4
LT		 2081static const char *sci_type(struct uart_port *port)
2082{
2083 switch (port->type) {
e7c98dc7
MT		 2084 case PORT_IRDA:
2085 return "irda";
2086 case PORT_SCI:
2087 return "sci";
2088 case PORT_SCIF:
2089 return "scif";
2090 case PORT_SCIFA:
2091 return "scifa";
d1d4b10c
GL		 2092 case PORT_SCIFB:
2093 return "scifb";
f303b364
UH		 2094 case PORT_HSCIF:
2095 return "hscif";
1da177e4
LT		 2096 }
2097
fa43972f 2098 return NULL;
1da177e4
LT		 2099}
2100
f6e9495d
PM		 2101static int sci_remap_port(struct uart_port *port)
2102{
e4d6f911 2103 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2104
2105 /*
2106 * Nothing to do if there's already an established membase.
2107 */
2108 if (port->membase)
2109 return 0;
2110
2111 if (port->flags & UPF_IOREMAP) {
e4d6f911 2112 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2113 if (unlikely(!port->membase)) {
2114 dev_err(port->dev, "can't remap port#%d\n", port->line);
2115 return -ENXIO;
2116 }
2117 } else {
2118 /*
2119 * For the simple (and majority of) cases where we don't
2120 * need to do any remapping, just cast the cookie
2121 * directly.
2122 */
3af4e960 2123 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2124 }
2125
2126 return 0;
2127}
2128
e2651647 2129static void sci_release_port(struct uart_port *port)
1da177e4 2130{
e4d6f911
YS		 2131 struct sci_port *sport = to_sci_port(port);
2132
e2651647
PM		 2133 if (port->flags & UPF_IOREMAP) {
2134 iounmap(port->membase);
2135 port->membase = NULL;
2136 }
2137
e4d6f911 2138 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2139}
2140
e2651647 2141static int sci_request_port(struct uart_port *port)
1da177e4 2142{
e2651647 2143 struct resource *res;
e4d6f911 2144 struct sci_port *sport = to_sci_port(port);
f6e9495d 2145 int ret;
1da177e4 2146
e4d6f911
YS		 2147 res = request_mem_region(port->mapbase, sport->reg_size,
2148 dev_name(port->dev));
2149 if (unlikely(res == NULL)) {
2150 dev_err(port->dev, "request_mem_region failed.");
e2651647 2151 return -EBUSY;
e4d6f911 2152 }
1da177e4 2153
f6e9495d
PM		 2154 ret = sci_remap_port(port);
2155 if (unlikely(ret != 0)) {
2156 release_resource(res);
2157 return ret;
7ff731ae 2158 }
e2651647
PM		 2159
2160 return 0;
2161}
2162
2163static void sci_config_port(struct uart_port *port, int flags)
2164{
2165 if (flags & UART_CONFIG_TYPE) {
2166 struct sci_port *sport = to_sci_port(port);
2167
2168 port->type = sport->cfg->type;
2169 sci_request_port(port);
2170 }
1da177e4
LT		 2171}
2172
2173static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2174{
1da177e4
LT		 2175 if (ser->baud_base < 2400)
2176 /* No paper tape reader for Mitch.. */
2177 return -EINVAL;
2178
2179 return 0;
2180}
2181
2182static struct uart_ops sci_uart_ops = {
2183 .tx_empty = sci_tx_empty,
2184 .set_mctrl = sci_set_mctrl,
2185 .get_mctrl = sci_get_mctrl,
2186 .start_tx = sci_start_tx,
2187 .stop_tx = sci_stop_tx,
2188 .stop_rx = sci_stop_rx,
1da177e4
LT		 2189 .break_ctl = sci_break_ctl,
2190 .startup = sci_startup,
2191 .shutdown = sci_shutdown,
2192 .set_termios = sci_set_termios,
0174e5ca 2193 .pm = sci_pm,
1da177e4
LT		 2194 .type = sci_type,
2195 .release_port = sci_release_port,
2196 .request_port = sci_request_port,
2197 .config_port = sci_config_port,
2198 .verify_port = sci_verify_port,
07d2a1a1
PM		 2199#ifdef CONFIG_CONSOLE_POLL
2200 .poll_get_char = sci_poll_get_char,
2201 .poll_put_char = sci_poll_put_char,
2202#endif
1da177e4
LT		 2203};
2204
9671f099 2205static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2206 struct sci_port *sci_port, unsigned int index,
2207 struct plat_sci_port *p, bool early)
e108b2ca 2208{
73a19e4c 2209 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2210 const struct resource *res;
2211 unsigned int i;
3127c6b2 2212 int ret;
e108b2ca 2213
50f0959a
PM		 2214 sci_port->cfg = p;
2215
73a19e4c
GL		 2216 port->ops = &sci_uart_ops;
2217 port->iotype = UPIO_MEM;
2218 port->line = index;
75136d48 2219
89b5c1ab
LP		 2220 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2221 if (res == NULL)
2222 return -ENOMEM;
1fcc91a6 2223
89b5c1ab 2224 port->mapbase = res->start;
e4d6f911 2225 sci_port->reg_size = resource_size(res);
1fcc91a6 2226
89b5c1ab
LP		 2227 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2228 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2229
89b5c1ab
LP		 2230 /* The SCI generates several interrupts. They can be muxed together or
2231 * connected to different interrupt lines. In the muxed case only one
2232 * interrupt resource is specified. In the non-muxed case three or four
2233 * interrupt resources are specified, as the BRI interrupt is optional.
2234 */
2235 if (sci_port->irqs[0] < 0)
2236 return -ENXIO;
1fcc91a6 2237
89b5c1ab
LP		 2238 if (sci_port->irqs[1] < 0) {
2239 sci_port->irqs[1] = sci_port->irqs[0];
2240 sci_port->irqs[2] = sci_port->irqs[0];
2241 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2242 }
2243
b545e4f4
LP		 2244 if (p->regtype == SCIx_PROBE_REGTYPE) {
2245 ret = sci_probe_regmap(p);
2246 if (unlikely(ret))
2247 return ret;
2248 }
2249
75136d48 2250 switch (p->type) {
d1d4b10c
GL		 2251 case PORT_SCIFB:
2252 port->fifosize = 256;
2e0842a1 2253 sci_port->overrun_reg = SCxSR;
75c249fd 2254 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2255 sci_port->sampling_rate = 16;
d1d4b10c 2256 break;
f303b364
UH		 2257 case PORT_HSCIF:
2258 port->fifosize = 128;
2e0842a1 2259 sci_port->overrun_reg = SCLSR;
75c249fd 2260 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2261 sci_port->sampling_rate = 0;
f303b364 2262 break;
75136d48 2263 case PORT_SCIFA:
73a19e4c 2264 port->fifosize = 64;
2e0842a1 2265 sci_port->overrun_reg = SCxSR;
75c249fd 2266 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2267 sci_port->sampling_rate = 16;
75136d48
MP		 2268 break;
2269 case PORT_SCIF:
73a19e4c 2270 port->fifosize = 16;
ec09c5eb 2271 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2272 sci_port->overrun_reg = SCxSR;
75c249fd 2273 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2274 sci_port->sampling_rate = 16;
ec09c5eb 2275 } else {
2e0842a1 2276 sci_port->overrun_reg = SCLSR;
75c249fd 2277 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2278 sci_port->sampling_rate = 32;
ec09c5eb 2279 }
75136d48
MP		 2280 break;
2281 default:
73a19e4c 2282 port->fifosize = 1;
2e0842a1 2283 sci_port->overrun_reg = SCxSR;
75c249fd 2284 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2285 sci_port->sampling_rate = 32;
75136d48
MP		 2286 break;
2287 }
7b6fd3bf 2288
878fbb91
LP		 2289 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2290 * match the SoC datasheet, this should be investigated. Let platform
2291 * data override the sampling rate for now.
ec09c5eb 2292 */
f84b6bdc
GU		 2293 if (p->sampling_rate)
2294 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2295
1fcc91a6 2296 if (!early) {
c7ed1ab3
PM		 2297 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2298 if (IS_ERR(sci_port->iclk)) {
2299 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2300 if (IS_ERR(sci_port->iclk)) {
2301 dev_err(&dev->dev, "can't get iclk\n");
2302 return PTR_ERR(sci_port->iclk);
2303 }
2304 }
2305
2306 /*
2307 * The function clock is optional, ignore it if we can't
2308 * find it.
2309 */
2310 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2311 if (IS_ERR(sci_port->fclk))
2312 sci_port->fclk = NULL;
2313
73a19e4c 2314 port->dev = &dev->dev;
5e50d2d6
MD		 2315
2316 pm_runtime_enable(&dev->dev);
7b6fd3bf 2317 }
e108b2ca 2318
7ed7e071
MD		 2319 sci_port->break_timer.data = (unsigned long)sci_port;
2320 sci_port->break_timer.function = sci_break_timer;
2321 init_timer(&sci_port->break_timer);
2322
debf9507
PM		 2323 /*
2324 * Establish some sensible defaults for the error detection.
2325 */
5da0f468
GU		 2326 if (p->type == PORT_SCI) {
2327 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2328 sci_port->error_clear = SCI_ERROR_CLEAR;
2329 } else {
2330 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2331 sci_port->error_clear = SCIF_ERROR_CLEAR;
2332 }
debf9507 2333
3ae988d9
LP		 2334 /*
2335 * Make the error mask inclusive of overrun detection, if
2336 * supported.
2337 */
5da0f468 2338 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2339 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2340 sci_port->error_clear &= ~sci_port->overrun_mask;
2341 }
debf9507 2342
ce6738b6 2343 port->type = p->type;
b6e4a3f1 2344 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2345 port->regshift = p->regshift;
73a19e4c 2346
ce6738b6 2347 /*
61a6976b 2348 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2349 * for the multi-IRQ ports, which is where we are primarily
2350 * concerned with the shutdown path synchronization.
2351 *
2352 * For the muxed case there's nothing more to do.
2353 */
1fcc91a6 2354 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2355 port->irqflags = 0;
73a19e4c 2356
61a6976b
PM		 2357 port->serial_in = sci_serial_in;
2358 port->serial_out = sci_serial_out;
2359
937bb6e4
GL		 2360 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2361 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2362 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2363
c7ed1ab3 2364 return 0;
e108b2ca
PM		 2365}
2366
6dae1421
LP		 2367static void sci_cleanup_single(struct sci_port *port)
2368{
6dae1421
LP		 2369 clk_put(port->iclk);
2370 clk_put(port->fclk);
2371
2372 pm_runtime_disable(port->port.dev);
2373}
2374
1da177e4 2375#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2376static void serial_console_putchar(struct uart_port *port, int ch)
2377{
2378 sci_poll_put_char(port, ch);
2379}
2380
1da177e4
LT		 2381/*
2382 * Print a string to the serial port trying not to disturb
2383 * any possible real use of the port...
2384 */
2385static void serial_console_write(struct console *co, const char *s,
2386 unsigned count)
2387{
906b17dc
PM		 2388 struct sci_port *sci_port = &sci_ports[co->index];
2389 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2390 unsigned short bits, ctrl;
2391 unsigned long flags;
2392 int locked = 1;
2393
2394 local_irq_save(flags);
2395 if (port->sysrq)
2396 locked = 0;
2397 else if (oops_in_progress)
2398 locked = spin_trylock(&port->lock);
2399 else
2400 spin_lock(&port->lock);
2401
2402 /* first save the SCSCR then disable the interrupts */
2403 ctrl = serial_port_in(port, SCSCR);
2404 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2405
501b825d 2406 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2407
2408 /* wait until fifo is empty and last bit has been transmitted */
2409 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2410 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2411 cpu_relax();
40f70c03
SK		 2412
2413 /* restore the SCSCR */
2414 serial_port_out(port, SCSCR, ctrl);
2415
2416 if (locked)
2417 spin_unlock(&port->lock);
2418 local_irq_restore(flags);
1da177e4
LT		 2419}
2420
9671f099 2421static int serial_console_setup(struct console *co, char *options)
1da177e4 2422{
dc8e6f5b 2423 struct sci_port *sci_port;
1da177e4
LT		 2424 struct uart_port *port;
2425 int baud = 115200;
2426 int bits = 8;
2427 int parity = 'n';
2428 int flow = 'n';
2429 int ret;
2430
e108b2ca 2431 /*
906b17dc 2432 * Refuse to handle any bogus ports.
1da177e4 2433 */
906b17dc 2434 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2435 return -ENODEV;
e108b2ca 2436
906b17dc
PM		 2437 sci_port = &sci_ports[co->index];
2438 port = &sci_port->port;
2439
b2267a6b
AC		 2440 /*
2441 * Refuse to handle uninitialized ports.
2442 */
2443 if (!port->ops)
2444 return -ENODEV;
2445
f6e9495d
PM		 2446 ret = sci_remap_port(port);
2447 if (unlikely(ret != 0))
2448 return ret;
e108b2ca 2449
1da177e4
LT		 2450 if (options)
2451 uart_parse_options(options, &baud, &parity, &bits, &flow);
2452
ab7cfb55 2453 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2454}
2455
2456static struct console serial_console = {
2457 .name = "ttySC",
906b17dc 2458 .device = uart_console_device,
1da177e4
LT		 2459 .write = serial_console_write,
2460 .setup = serial_console_setup,
fa5da2f7 2461 .flags = CON_PRINTBUFFER,
1da177e4 2462 .index = -1,
906b17dc 2463 .data = &sci_uart_driver,
1da177e4
LT		 2464};
2465
7b6fd3bf
MD		 2466static struct console early_serial_console = {
2467 .name = "early_ttySC",
2468 .write = serial_console_write,
2469 .flags = CON_PRINTBUFFER,
906b17dc 2470 .index = -1,
7b6fd3bf 2471};
ecdf8a46 2472
7b6fd3bf
MD		 2473static char early_serial_buf[32];
2474
9671f099 2475static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2476{
574de559 2477 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2478
2479 if (early_serial_console.data)
2480 return -EEXIST;
2481
2482 early_serial_console.index = pdev->id;
ecdf8a46 2483
1fcc91a6 2484 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2485
2486 serial_console_setup(&early_serial_console, early_serial_buf);
2487
2488 if (!strstr(early_serial_buf, "keep"))
2489 early_serial_console.flags |= CON_BOOT;
2490
2491 register_console(&early_serial_console);
2492 return 0;
2493}
6a8c9799
NI		 2494
2495#define SCI_CONSOLE (&serial_console)
2496
ecdf8a46 2497#else
9671f099 2498static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2499{
2500 return -EINVAL;
2501}
1da177e4 2502
6a8c9799
NI		 2503#define SCI_CONSOLE NULL
2504
2505#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2506
6c13d5d2 2507static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2508
2509static struct uart_driver sci_uart_driver = {
2510 .owner = THIS_MODULE,
2511 .driver_name = "sci",
1da177e4
LT		 2512 .dev_name = "ttySC",
2513 .major = SCI_MAJOR,
2514 .minor = SCI_MINOR_START,
e108b2ca 2515 .nr = SCI_NPORTS,
1da177e4
LT		 2516 .cons = SCI_CONSOLE,
2517};
2518
54507f6e 2519static int sci_remove(struct platform_device *dev)
e552de24 2520{
d535a230 2521 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2522
d535a230
PM		 2523 cpufreq_unregister_notifier(&port->freq_transition,
2524 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2525
d535a230
PM		 2526 uart_remove_one_port(&sci_uart_driver, &port->port);
2527
6dae1421 2528 sci_cleanup_single(port);
e552de24 2529
e552de24
MD		 2530 return 0;
2531}
2532
20bdcab8
BH		 2533struct sci_port_info {
2534 unsigned int type;
2535 unsigned int regtype;
2536};
2537
2538static const struct of_device_id of_sci_match[] = {
2539 {
2540 .compatible = "renesas,scif",
ff43da00 2541 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2542 .type = PORT_SCIF,
2543 .regtype = SCIx_SH4_SCIF_REGTYPE,
2544 },
2545 }, {
2546 .compatible = "renesas,scifa",
ff43da00 2547 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2548 .type = PORT_SCIFA,
2549 .regtype = SCIx_SCIFA_REGTYPE,
2550 },
2551 }, {
2552 .compatible = "renesas,scifb",
ff43da00 2553 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2554 .type = PORT_SCIFB,
2555 .regtype = SCIx_SCIFB_REGTYPE,
2556 },
2557 }, {
2558 .compatible = "renesas,hscif",
ff43da00 2559 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2560 .type = PORT_HSCIF,
2561 .regtype = SCIx_HSCIF_REGTYPE,
2562 },
e1d0be61
YS		 2563 }, {
2564 .compatible = "renesas,sci",
2565 .data = &(const struct sci_port_info) {
2566 .type = PORT_SCI,
2567 .regtype = SCIx_SCI_REGTYPE,
2568 },
20bdcab8
BH		 2569 }, {
2570 /* Terminator */
2571 },
2572};
2573MODULE_DEVICE_TABLE(of, of_sci_match);
2574
2575static struct plat_sci_port *
2576sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2577{
2578 struct device_node *np = pdev->dev.of_node;
2579 const struct of_device_id *match;
2580 const struct sci_port_info *info;
2581 struct plat_sci_port *p;
2582 int id;
2583
2584 if (!IS_ENABLED(CONFIG_OF) || !np)
2585 return NULL;
2586
2587 match = of_match_node(of_sci_match, pdev->dev.of_node);
2588 if (!match)
2589 return NULL;
2590
2591 info = match->data;
2592
2593 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2594 if (!p)
20bdcab8 2595 return NULL;
20bdcab8
BH		 2596
2597 /* Get the line number for the aliases node. */
2598 id = of_alias_get_id(np, "serial");
2599 if (id < 0) {
2600 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2601 return NULL;
2602 }
2603
2604 *dev_id = id;
2605
2606 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2607 p->type = info->type;
2608 p->regtype = info->regtype;
2609 p->scscr = SCSCR_RE | SCSCR_TE;
2610
2611 return p;
2612}
2613
9671f099 2614static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2615 unsigned int index,
2616 struct plat_sci_port *p,
2617 struct sci_port *sciport)
2618{
0ee70712
MD		 2619 int ret;
2620
2621 /* Sanity check */
2622 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2623 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2624 index+1, SCI_NPORTS);
9b971cd2 2625 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2626 return -EINVAL;
0ee70712
MD		 2627 }
2628
1fcc91a6 2629 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2630 if (ret)
2631 return ret;
0ee70712 2632
6dae1421
LP		 2633 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2634 if (ret) {
2635 sci_cleanup_single(sciport);
2636 return ret;
2637 }
2638
2639 return 0;
0ee70712
MD		 2640}
2641
9671f099 2642static int sci_probe(struct platform_device *dev)
1da177e4 2643{
20bdcab8
BH		 2644 struct plat_sci_port *p;
2645 struct sci_port *sp;
2646 unsigned int dev_id;
ecdf8a46 2647 int ret;
d535a230 2648
ecdf8a46
PM		 2649 /*
2650 * If we've come here via earlyprintk initialization, head off to
2651 * the special early probe. We don't have sufficient device state
2652 * to make it beyond this yet.
2653 */
2654 if (is_early_platform_device(dev))
2655 return sci_probe_earlyprintk(dev);
7b6fd3bf 2656
20bdcab8
BH		 2657 if (dev->dev.of_node) {
2658 p = sci_parse_dt(dev, &dev_id);
2659 if (p == NULL)
2660 return -EINVAL;
2661 } else {
2662 p = dev->dev.platform_data;
2663 if (p == NULL) {
2664 dev_err(&dev->dev, "no platform data supplied\n");
2665 return -EINVAL;
2666 }
2667
2668 dev_id = dev->id;
2669 }
2670
2671 sp = &sci_ports[dev_id];
d535a230 2672 platform_set_drvdata(dev, sp);
e552de24 2673
20bdcab8 2674 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2675 if (ret)
6dae1421 2676 return ret;
e552de24 2677
d535a230 2678 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2679
d535a230
PM		 2680 ret = cpufreq_register_notifier(&sp->freq_transition,
2681 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2682 if (unlikely(ret < 0)) {
bf13c9a8 2683 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2684 sci_cleanup_single(sp);
2685 return ret;
2686 }
1da177e4
LT		 2687
2688#ifdef CONFIG_SH_STANDARD_BIOS
2689 sh_bios_gdb_detach();
2690#endif
2691
e108b2ca 2692 return 0;
1da177e4
LT		 2693}
2694
cb876341 2695static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2696{
d535a230 2697 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2698
d535a230
PM		 2699 if (sport)
2700 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2701
e108b2ca
PM		 2702 return 0;
2703}
1da177e4 2704
cb876341 2705static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2706{
d535a230 2707 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2708
d535a230
PM		 2709 if (sport)
2710 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2711
2712 return 0;
2713}
2714
cb876341 2715static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2716
e108b2ca
PM		 2717static struct platform_driver sci_driver = {
2718 .probe = sci_probe,
b9e39c89 2719 .remove = sci_remove,
e108b2ca
PM		 2720 .driver = {
2721 .name = "sh-sci",
6daa79b3 2722 .pm = &sci_dev_pm_ops,
20bdcab8 2723 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2724 },
2725};
2726
2727static int __init sci_init(void)
2728{
2729 int ret;
2730
6c13d5d2 2731 pr_info("%s\n", banner);
e108b2ca 2732
e108b2ca
PM		 2733 ret = uart_register_driver(&sci_uart_driver);
2734 if (likely(ret == 0)) {
2735 ret = platform_driver_register(&sci_driver);
2736 if (unlikely(ret))
2737 uart_unregister_driver(&sci_uart_driver);
2738 }
2739
2740 return ret;
2741}
2742
2743static void __exit sci_exit(void)
2744{
2745 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2746 uart_unregister_driver(&sci_uart_driver);
2747}
2748
7b6fd3bf
MD		 2749#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2750early_platform_init_buffer("earlyprintk", &sci_driver,
2751 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2752#endif
1da177e4
LT		 2753module_init(sci_init);
2754module_exit(sci_exit);
2755
e108b2ca 2756MODULE_LICENSE("GPL");
e169c139 2757MODULE_ALIAS("platform:sh-sci");
7f405f9c 2758MODULE_AUTHOR("Paul Mundt");
f303b364 2759MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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