[deliverable/linux.git] / drivers / tty / serial / uartlite.c

/*
 * uartlite.c: Serial driver for Xilinx uartlite serial controller
 *
 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
 * Copyright (C) 2007 Secret Lab Technologies Ltd.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/console.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <asm/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>

#define ULITE_NAME		"ttyUL"
#define ULITE_MAJOR		204
#define ULITE_MINOR		187
#define ULITE_NR_UARTS		4

/* ---------------------------------------------------------------------
 * Register definitions
 *
 * For register details see datasheet:
 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 
 */

#define ULITE_RX		0x00
#define ULITE_TX		0x04
#define ULITE_STATUS		0x08
#define ULITE_CONTROL		0x0c

#define ULITE_REGION		16

#define ULITE_STATUS_RXVALID	0x01
#define ULITE_STATUS_RXFULL	0x02
#define ULITE_STATUS_TXEMPTY	0x04
#define ULITE_STATUS_TXFULL	0x08
#define ULITE_STATUS_IE		0x10
#define ULITE_STATUS_OVERRUN	0x20
#define ULITE_STATUS_FRAME	0x40
#define ULITE_STATUS_PARITY	0x80

#define ULITE_CONTROL_RST_TX	0x01
#define ULITE_CONTROL_RST_RX	0x02
#define ULITE_CONTROL_IE	0x10


static struct uart_port ulite_ports[ULITE_NR_UARTS];

/* ---------------------------------------------------------------------
 * Core UART driver operations
 */

static int ulite_receive(struct uart_port *port, int stat)
{
	struct tty_struct *tty = port->state->port.tty;
	unsigned char ch = 0;
	char flag = TTY_NORMAL;

	if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		     | ULITE_STATUS_FRAME)) == 0)
		return 0;

	/* stats */
	if (stat & ULITE_STATUS_RXVALID) {
		port->icount.rx++;
		ch = ioread32be(port->membase + ULITE_RX);

		if (stat & ULITE_STATUS_PARITY)
			port->icount.parity++;
	}

	if (stat & ULITE_STATUS_OVERRUN)
		port->icount.overrun++;

	if (stat & ULITE_STATUS_FRAME)
		port->icount.frame++;


	/* drop byte with parity error if IGNPAR specificed */
	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
		stat &= ~ULITE_STATUS_RXVALID;

	stat &= port->read_status_mask;

	if (stat & ULITE_STATUS_PARITY)
		flag = TTY_PARITY;


	stat &= ~port->ignore_status_mask;

	if (stat & ULITE_STATUS_RXVALID)
		tty_insert_flip_char(tty, ch, flag);

	if (stat & ULITE_STATUS_FRAME)
		tty_insert_flip_char(tty, 0, TTY_FRAME);

	if (stat & ULITE_STATUS_OVERRUN)
		tty_insert_flip_char(tty, 0, TTY_OVERRUN);

	return 1;
}

static int ulite_transmit(struct uart_port *port, int stat)
{
	struct circ_buf *xmit  = &port->state->xmit;

	if (stat & ULITE_STATUS_TXFULL)
		return 0;

	if (port->x_char) {
		iowrite32be(port->x_char, port->membase + ULITE_TX);
		port->x_char = 0;
		port->icount.tx++;
		return 1;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
		return 0;

	iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	port->icount.tx++;

	/* wake up */
	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	return 1;
}

static irqreturn_t ulite_isr(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	int busy, n = 0;

	do {
		int stat = ioread32be(port->membase + ULITE_STATUS);
		busy  = ulite_receive(port, stat);
		busy |= ulite_transmit(port, stat);
		n++;
	} while (busy);

	/* work done? */
	if (n > 1) {
		tty_flip_buffer_push(port->state->port.tty);
		return IRQ_HANDLED;
	} else {
		return IRQ_NONE;
	}
}

static unsigned int ulite_tx_empty(struct uart_port *port)
{
	unsigned long flags;
	unsigned int ret;

	spin_lock_irqsave(&port->lock, flags);
	ret = ioread32be(port->membase + ULITE_STATUS);
	spin_unlock_irqrestore(&port->lock, flags);

	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
}

static unsigned int ulite_get_mctrl(struct uart_port *port)
{
	return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
}

static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	/* N/A */
}

static void ulite_stop_tx(struct uart_port *port)
{
	/* N/A */
}

static void ulite_start_tx(struct uart_port *port)
{
	ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
}

static void ulite_stop_rx(struct uart_port *port)
{
	/* don't forward any more data (like !CREAD) */
	port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
		| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
}

static void ulite_enable_ms(struct uart_port *port)
{
	/* N/A */
}

static void ulite_break_ctl(struct uart_port *port, int ctl)
{
	/* N/A */
}

static int ulite_startup(struct uart_port *port)
{
	int ret;

	ret = request_irq(port->irq, ulite_isr,
			  IRQF_SHARED | IRQF_SAMPLE_RANDOM, "uartlite", port);
	if (ret)
		return ret;

	iowrite32be(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
	       port->membase + ULITE_CONTROL);
	iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);

	return 0;
}

static void ulite_shutdown(struct uart_port *port)
{
	iowrite32be(0, port->membase + ULITE_CONTROL);
	ioread32be(port->membase + ULITE_CONTROL); /* dummy */
	free_irq(port->irq, port);
}

static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
			      struct ktermios *old)
{
	unsigned long flags;
	unsigned int baud;

	spin_lock_irqsave(&port->lock, flags);

	port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		| ULITE_STATUS_TXFULL;

	if (termios->c_iflag & INPCK)
		port->read_status_mask |=
			ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;

	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* ignore all characters if CREAD is not set */
	if ((termios->c_cflag & CREAD) == 0)
		port->ignore_status_mask |=
			ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* update timeout */
	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	uart_update_timeout(port, termios->c_cflag, baud);

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *ulite_type(struct uart_port *port)
{
	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
}

static void ulite_release_port(struct uart_port *port)
{
	release_mem_region(port->mapbase, ULITE_REGION);
	iounmap(port->membase);
	port->membase = NULL;
}

static int ulite_request_port(struct uart_port *port)
{
	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
		 port, (unsigned long long) port->mapbase);

	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
		dev_err(port->dev, "Memory region busy\n");
		return -EBUSY;
	}

	port->membase = ioremap(port->mapbase, ULITE_REGION);
	if (!port->membase) {
		dev_err(port->dev, "Unable to map registers\n");
		release_mem_region(port->mapbase, ULITE_REGION);
		return -EBUSY;
	}

	return 0;
}

static void ulite_config_port(struct uart_port *port, int flags)
{
	if (!ulite_request_port(port))
		port->type = PORT_UARTLITE;
}

static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	/* we don't want the core code to modify any port params */
	return -EINVAL;
}

#ifdef CONFIG_CONSOLE_POLL
static int ulite_get_poll_char(struct uart_port *port)
{
	if (!(ioread32be(port->membase + ULITE_STATUS)
						& ULITE_STATUS_RXVALID))
		return NO_POLL_CHAR;

	return ioread32be(port->membase + ULITE_RX);
}

static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
{
	while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)
		cpu_relax();

	/* write char to device */
	iowrite32be(ch, port->membase + ULITE_TX);
}
#endif

static struct uart_ops ulite_ops = {
	.tx_empty	= ulite_tx_empty,
	.set_mctrl	= ulite_set_mctrl,
	.get_mctrl	= ulite_get_mctrl,
	.stop_tx	= ulite_stop_tx,
	.start_tx	= ulite_start_tx,
	.stop_rx	= ulite_stop_rx,
	.enable_ms	= ulite_enable_ms,
	.break_ctl	= ulite_break_ctl,
	.startup	= ulite_startup,
	.shutdown	= ulite_shutdown,
	.set_termios	= ulite_set_termios,
	.type		= ulite_type,
	.release_port	= ulite_release_port,
	.request_port	= ulite_request_port,
	.config_port	= ulite_config_port,
	.verify_port	= ulite_verify_port,
#ifdef CONFIG_CONSOLE_POLL
	.poll_get_char	= ulite_get_poll_char,
	.poll_put_char	= ulite_put_poll_char,
#endif
};

/* ---------------------------------------------------------------------
 * Console driver operations
 */

#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
static void ulite_console_wait_tx(struct uart_port *port)
{
	int i;
	u8 val;

	/* Spin waiting for TX fifo to have space available */
	for (i = 0; i < 100000; i++) {
		val = ioread32be(port->membase + ULITE_STATUS);
		if ((val & ULITE_STATUS_TXFULL) == 0)
			break;
		cpu_relax();
	}
}

static void ulite_console_putchar(struct uart_port *port, int ch)
{
	ulite_console_wait_tx(port);
	iowrite32be(ch, port->membase + ULITE_TX);
}

static void ulite_console_write(struct console *co, const char *s,
				unsigned int count)
{
	struct uart_port *port = &ulite_ports[co->index];
	unsigned long flags;
	unsigned int ier;
	int locked = 1;

	if (oops_in_progress) {
		locked = spin_trylock_irqsave(&port->lock, flags);
	} else
		spin_lock_irqsave(&port->lock, flags);

	/* save and disable interrupt */
	ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
	iowrite32be(0, port->membase + ULITE_CONTROL);

	uart_console_write(port, s, count, ulite_console_putchar);

	ulite_console_wait_tx(port);

	/* restore interrupt state */
	if (ier)
		iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);

	if (locked)
		spin_unlock_irqrestore(&port->lock, flags);
}

static int __devinit ulite_console_setup(struct console *co, char *options)
{
	struct uart_port *port;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	if (co->index < 0 || co->index >= ULITE_NR_UARTS)
		return -EINVAL;

	port = &ulite_ports[co->index];

	/* Has the device been initialized yet? */
	if (!port->mapbase) {
		pr_debug("console on ttyUL%i not present\n", co->index);
		return -ENODEV;
	}

	/* not initialized yet? */
	if (!port->membase) {
		if (ulite_request_port(port))
			return -ENODEV;
	}

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver ulite_uart_driver;

static struct console ulite_console = {
	.name	= ULITE_NAME,
	.write	= ulite_console_write,
	.device	= uart_console_device,
	.setup	= ulite_console_setup,
	.flags	= CON_PRINTBUFFER,
	.index	= -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	.data	= &ulite_uart_driver,
};

static int __init ulite_console_init(void)
{
	register_console(&ulite_console);
	return 0;
}

console_initcall(ulite_console_init);

#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */

static struct uart_driver ulite_uart_driver = {
	.owner		= THIS_MODULE,
	.driver_name	= "uartlite",
	.dev_name	= ULITE_NAME,
	.major		= ULITE_MAJOR,
	.minor		= ULITE_MINOR,
	.nr		= ULITE_NR_UARTS,
#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	.cons		= &ulite_console,
#endif
};

/* ---------------------------------------------------------------------
 * Port assignment functions (mapping devices to uart_port structures)
 */

/** ulite_assign: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 * @id: requested id number.  Pass -1 for automatic port assignment
 * @base: base address of uartlite registers
 * @irq: irq number for uartlite
 *
 * Returns: 0 on success, <0 otherwise
 */
static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
{
	struct uart_port *port;
	int rc;

	/* if id = -1; then scan for a free id and use that */
	if (id < 0) {
		for (id = 0; id < ULITE_NR_UARTS; id++)
			if (ulite_ports[id].mapbase == 0)
				break;
	}
	if (id < 0 || id >= ULITE_NR_UARTS) {
		dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
		return -EINVAL;
	}

	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
		dev_err(dev, "cannot assign to %s%i; it is already in use\n",
			ULITE_NAME, id);
		return -EBUSY;
	}

	port = &ulite_ports[id];

	spin_lock_init(&port->lock);
	port->fifosize = 16;
	port->regshift = 2;
	port->iotype = UPIO_MEM;
	port->iobase = 1; /* mark port in use */
	port->mapbase = base;
	port->membase = NULL;
	port->ops = &ulite_ops;
	port->irq = irq;
	port->flags = UPF_BOOT_AUTOCONF;
	port->dev = dev;
	port->type = PORT_UNKNOWN;
	port->line = id;

	dev_set_drvdata(dev, port);

	/* Register the port */
	rc = uart_add_one_port(&ulite_uart_driver, port);
	if (rc) {
		dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
		port->mapbase = 0;
		dev_set_drvdata(dev, NULL);
		return rc;
	}

	return 0;
}

/** ulite_release: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 */
static int __devexit ulite_release(struct device *dev)
{
	struct uart_port *port = dev_get_drvdata(dev);
	int rc = 0;

	if (port) {
		rc = uart_remove_one_port(&ulite_uart_driver, port);
		dev_set_drvdata(dev, NULL);
		port->mapbase = 0;
	}

	return rc;
}

/* ---------------------------------------------------------------------
 * Platform bus binding
 */

#if defined(CONFIG_OF)
/* Match table for of_platform binding */
static struct of_device_id ulite_of_match[] __devinitdata = {
	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	{}
};
MODULE_DEVICE_TABLE(of, ulite_of_match);
#else /* CONFIG_OF */
#define ulite_of_match NULL
#endif /* CONFIG_OF */

static int __devinit ulite_probe(struct platform_device *pdev)
{
	struct resource *res, *res2;
	int id = pdev->id;
#ifdef CONFIG_OF
	const __be32 *prop;

	prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
	if (prop)
		id = be32_to_cpup(prop);
#endif

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res2)
		return -ENODEV;

	return ulite_assign(&pdev->dev, id, res->start, res2->start);
}

static int __devexit ulite_remove(struct platform_device *pdev)
{
	return ulite_release(&pdev->dev);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:uartlite");

static struct platform_driver ulite_platform_driver = {
	.probe = ulite_probe,
	.remove = __devexit_p(ulite_remove),
	.driver = {
		.owner = THIS_MODULE,
		.name  = "uartlite",
		.of_match_table = ulite_of_match,
	},
};

/* ---------------------------------------------------------------------
 * Module setup/teardown
 */

int __init ulite_init(void)
{
	int ret;

	pr_debug("uartlite: calling uart_register_driver()\n");
	ret = uart_register_driver(&ulite_uart_driver);
	if (ret)
		goto err_uart;

	pr_debug("uartlite: calling platform_driver_register()\n");
	ret = platform_driver_register(&ulite_platform_driver);
	if (ret)
		goto err_plat;

	return 0;

err_plat:
	uart_unregister_driver(&ulite_uart_driver);
err_uart:
	printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
	return ret;
}

void __exit ulite_exit(void)
{
	platform_driver_unregister(&ulite_platform_driver);
	uart_unregister_driver(&ulite_uart_driver);
}

module_init(ulite_init);
module_exit(ulite_exit);

MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
MODULE_DESCRIPTION("Xilinx uartlite serial driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
238b8721 PK	1	/*
	2	* uartlite.c: Serial driver for Xilinx uartlite serial controller
	3	*
852e1ea7 GL	4	* Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
852e1ea7 GL	5	* Copyright (C) 2007 Secret Lab Technologies Ltd.
238b8721 PK	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
	12	#include <linux/platform_device.h>
	13	#include <linux/module.h>
	14	#include <linux/console.h>
	15	#include <linux/serial.h>
	16	#include <linux/serial_core.h>
	17	#include <linux/tty.h>
	18	#include <linux/delay.h>
	19	#include <linux/interrupt.h>
0e349b0e	20	#include <linux/init.h>
238b8721	21	#include <asm/io.h>
0e349b0e	22	#include <linux/of.h>
22ae782f	23	#include <linux/of_address.h>
852e1ea7 GL	24	#include <linux/of_device.h>
852e1ea7 GL	25	#include <linux/of_platform.h>
0e349b0e	26
00775828	27	#define ULITE_NAME "ttyUL"
238b8721 PK	28	#define ULITE_MAJOR 204
	29	#define ULITE_MINOR 187
	30	#define ULITE_NR_UARTS 4
	31
435706b3 GL	32	/* ---------------------------------------------------------------------
	33	* Register definitions
	34	*
	35	* For register details see datasheet:
631dd1a8	36	* http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
435706b3 GL	37	*/
435706b3 GL	38
238b8721 PK	39	#define ULITE_RX 0x00
	40	#define ULITE_TX 0x04
	41	#define ULITE_STATUS 0x08
	42	#define ULITE_CONTROL 0x0c
	43
	44	#define ULITE_REGION 16
	45
	46	#define ULITE_STATUS_RXVALID 0x01
	47	#define ULITE_STATUS_RXFULL 0x02
	48	#define ULITE_STATUS_TXEMPTY 0x04
	49	#define ULITE_STATUS_TXFULL 0x08
	50	#define ULITE_STATUS_IE 0x10
	51	#define ULITE_STATUS_OVERRUN 0x20
	52	#define ULITE_STATUS_FRAME 0x40
	53	#define ULITE_STATUS_PARITY 0x80
	54
	55	#define ULITE_CONTROL_RST_TX 0x01
	56	#define ULITE_CONTROL_RST_RX 0x02
	57	#define ULITE_CONTROL_IE 0x10
	58
	59
483c79db	60	static struct uart_port ulite_ports[ULITE_NR_UARTS];
238b8721	61
435706b3 GL	62	/* ---------------------------------------------------------------------
	63	* Core UART driver operations
	64	*/
	65
238b8721 PK	66	static int ulite_receive(struct uart_port *port, int stat)
238b8721 PK	67	{
ebd2c8f6	68	struct tty_struct *tty = port->state->port.tty;
238b8721 PK	69	unsigned char ch = 0;
	70	char flag = TTY_NORMAL;
	71
	72	if ((stat & (ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	73	\| ULITE_STATUS_FRAME)) == 0)
	74	return 0;
	75
	76	/* stats */
	77	if (stat & ULITE_STATUS_RXVALID) {
	78	port->icount.rx++;
e5bbbb18	79	ch = ioread32be(port->membase + ULITE_RX);
238b8721 PK	80
	81	if (stat & ULITE_STATUS_PARITY)
	82	port->icount.parity++;
	83	}
	84
	85	if (stat & ULITE_STATUS_OVERRUN)
	86	port->icount.overrun++;
	87
	88	if (stat & ULITE_STATUS_FRAME)
	89	port->icount.frame++;
	90
	91
	92	/* drop byte with parity error if IGNPAR specificed */
	93	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
	94	stat &= ~ULITE_STATUS_RXVALID;
	95
	96	stat &= port->read_status_mask;
	97
	98	if (stat & ULITE_STATUS_PARITY)
	99	flag = TTY_PARITY;
	100
	101
	102	stat &= ~port->ignore_status_mask;
	103
	104	if (stat & ULITE_STATUS_RXVALID)
	105	tty_insert_flip_char(tty, ch, flag);
	106
	107	if (stat & ULITE_STATUS_FRAME)
	108	tty_insert_flip_char(tty, 0, TTY_FRAME);
	109
	110	if (stat & ULITE_STATUS_OVERRUN)
	111	tty_insert_flip_char(tty, 0, TTY_OVERRUN);
	112
	113	return 1;
	114	}
	115
	116	static int ulite_transmit(struct uart_port *port, int stat)
	117	{
ebd2c8f6	118	struct circ_buf *xmit = &port->state->xmit;
238b8721 PK	119
	120	if (stat & ULITE_STATUS_TXFULL)
	121	return 0;
	122
	123	if (port->x_char) {
e5bbbb18	124	iowrite32be(port->x_char, port->membase + ULITE_TX);
238b8721 PK	125	port->x_char = 0;
	126	port->icount.tx++;
	127	return 1;
	128	}
	129
	130	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port))
	131	return 0;
	132
e5bbbb18	133	iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
238b8721 PK	134	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	135	port->icount.tx++;
	136
	137	/* wake up */
	138	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	139	uart_write_wakeup(port);
	140
	141	return 1;
	142	}
	143
	144	static irqreturn_t ulite_isr(int irq, void *dev_id)
	145	{
15aafa2f	146	struct uart_port *port = dev_id;
d2cfe962	147	int busy, n = 0;
238b8721 PK	148
238b8721 PK	149	do {
e5bbbb18	150	int stat = ioread32be(port->membase + ULITE_STATUS);
238b8721 PK	151	busy = ulite_receive(port, stat);
238b8721 PK	152	busy \|= ulite_transmit(port, stat);
d2cfe962	153	n++;
238b8721 PK	154	} while (busy);
238b8721 PK	155
d2cfe962 PK	156	/* work done? */
	157	if (n > 1) {
	158	tty_flip_buffer_push(port->state->port.tty);
	159	return IRQ_HANDLED;
	160	} else {
	161	return IRQ_NONE;
	162	}
238b8721 PK	163	}
	164
	165	static unsigned int ulite_tx_empty(struct uart_port *port)
	166	{
	167	unsigned long flags;
	168	unsigned int ret;
	169
	170	spin_lock_irqsave(&port->lock, flags);
e5bbbb18	171	ret = ioread32be(port->membase + ULITE_STATUS);
238b8721 PK	172	spin_unlock_irqrestore(&port->lock, flags);
	173
	174	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
	175	}
	176
	177	static unsigned int ulite_get_mctrl(struct uart_port *port)
	178	{
	179	return TIOCM_CTS \| TIOCM_DSR \| TIOCM_CAR;
	180	}
	181
	182	static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
	183	{
	184	/* N/A */
	185	}
	186
	187	static void ulite_stop_tx(struct uart_port *port)
	188	{
	189	/* N/A */
	190	}
	191
	192	static void ulite_start_tx(struct uart_port *port)
	193	{
e5bbbb18	194	ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
238b8721 PK	195	}
	196
	197	static void ulite_stop_rx(struct uart_port *port)
	198	{
	199	/* don't forward any more data (like !CREAD) */
	200	port->ignore_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	201	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	202	}
	203
	204	static void ulite_enable_ms(struct uart_port *port)
	205	{
	206	/* N/A */
	207	}
	208
	209	static void ulite_break_ctl(struct uart_port *port, int ctl)
	210	{
	211	/* N/A */
	212	}
	213
	214	static int ulite_startup(struct uart_port *port)
	215	{
	216	int ret;
	217
	218	ret = request_irq(port->irq, ulite_isr,
d2cfe962	219	IRQF_SHARED \| IRQF_SAMPLE_RANDOM, "uartlite", port);
238b8721 PK	220	if (ret)
	221	return ret;
	222
e5bbbb18	223	iowrite32be(ULITE_CONTROL_RST_RX \| ULITE_CONTROL_RST_TX,
e077b50c	224	port->membase + ULITE_CONTROL);
e5bbbb18	225	iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
238b8721 PK	226
	227	return 0;
	228	}
	229
	230	static void ulite_shutdown(struct uart_port *port)
	231	{
e5bbbb18 JL	232	iowrite32be(0, port->membase + ULITE_CONTROL);
e5bbbb18 JL	233	ioread32be(port->membase + ULITE_CONTROL); /* dummy */
238b8721 PK	234	free_irq(port->irq, port);
	235	}
	236
606d099c AC	237	static void ulite_set_termios(struct uart_port port, struct ktermios termios,
606d099c AC	238	struct ktermios *old)
238b8721 PK	239	{
	240	unsigned long flags;
	241	unsigned int baud;
	242
	243	spin_lock_irqsave(&port->lock, flags);
	244
	245	port->read_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	246	\| ULITE_STATUS_TXFULL;
	247
	248	if (termios->c_iflag & INPCK)
	249	port->read_status_mask \|=
	250	ULITE_STATUS_PARITY \| ULITE_STATUS_FRAME;
	251
	252	port->ignore_status_mask = 0;
	253	if (termios->c_iflag & IGNPAR)
	254	port->ignore_status_mask \|= ULITE_STATUS_PARITY
	255	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	256
	257	/* ignore all characters if CREAD is not set */
	258	if ((termios->c_cflag & CREAD) == 0)
	259	port->ignore_status_mask \|=
	260	ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	261	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	262
	263	/* update timeout */
	264	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	265	uart_update_timeout(port, termios->c_cflag, baud);
	266
	267	spin_unlock_irqrestore(&port->lock, flags);
	268	}
	269
	270	static const char ulite_type(struct uart_port port)
	271	{
	272	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
	273	}
	274
	275	static void ulite_release_port(struct uart_port *port)
	276	{
	277	release_mem_region(port->mapbase, ULITE_REGION);
	278	iounmap(port->membase);
b81831c6	279	port->membase = NULL;
238b8721 PK	280	}
	281
	282	static int ulite_request_port(struct uart_port *port)
	283	{
a1080968 GL	284	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
a1080968 GL	285	port, (unsigned long long) port->mapbase);
0e349b0e	286
238b8721 PK	287	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
	288	dev_err(port->dev, "Memory region busy\n");
	289	return -EBUSY;
	290	}
	291
	292	port->membase = ioremap(port->mapbase, ULITE_REGION);
	293	if (!port->membase) {
	294	dev_err(port->dev, "Unable to map registers\n");
	295	release_mem_region(port->mapbase, ULITE_REGION);
	296	return -EBUSY;
	297	}
	298
	299	return 0;
	300	}
	301
	302	static void ulite_config_port(struct uart_port *port, int flags)
	303	{
e21654a7 PK	304	if (!ulite_request_port(port))
e21654a7 PK	305	port->type = PORT_UARTLITE;
238b8721 PK	306	}
	307
	308	static int ulite_verify_port(struct uart_port port, struct serial_struct ser)
	309	{
	310	/* we don't want the core code to modify any port params */
	311	return -EINVAL;
	312	}
	313
8a28af7f MS	314	#ifdef CONFIG_CONSOLE_POLL
	315	static int ulite_get_poll_char(struct uart_port *port)
	316	{
	317	if (!(ioread32be(port->membase + ULITE_STATUS)
	318	& ULITE_STATUS_RXVALID))
	319	return NO_POLL_CHAR;
	320
	321	return ioread32be(port->membase + ULITE_RX);
	322	}
	323
	324	static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
	325	{
	326	while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)
	327	cpu_relax();
	328
	329	/* write char to device */
	330	iowrite32be(ch, port->membase + ULITE_TX);
	331	}
	332	#endif
	333
238b8721 PK	334	static struct uart_ops ulite_ops = {
	335	.tx_empty = ulite_tx_empty,
	336	.set_mctrl = ulite_set_mctrl,
	337	.get_mctrl = ulite_get_mctrl,
	338	.stop_tx = ulite_stop_tx,
	339	.start_tx = ulite_start_tx,
	340	.stop_rx = ulite_stop_rx,
	341	.enable_ms = ulite_enable_ms,
	342	.break_ctl = ulite_break_ctl,
	343	.startup = ulite_startup,
	344	.shutdown = ulite_shutdown,
	345	.set_termios = ulite_set_termios,
	346	.type = ulite_type,
	347	.release_port = ulite_release_port,
	348	.request_port = ulite_request_port,
	349	.config_port = ulite_config_port,
8a28af7f MS	350	.verify_port = ulite_verify_port,
	351	#ifdef CONFIG_CONSOLE_POLL
	352	.poll_get_char = ulite_get_poll_char,
	353	.poll_put_char = ulite_put_poll_char,
	354	#endif
238b8721 PK	355	};
238b8721 PK	356
435706b3 GL	357	/* ---------------------------------------------------------------------
	358	* Console driver operations
	359	*/
	360
238b8721 PK	361	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	362	static void ulite_console_wait_tx(struct uart_port *port)
	363	{
	364	int i;
1d6b6987	365	u8 val;
238b8721	366
1d6b6987 GL	367	/* Spin waiting for TX fifo to have space available */
1d6b6987 GL	368	for (i = 0; i < 100000; i++) {
e5bbbb18	369	val = ioread32be(port->membase + ULITE_STATUS);
1d6b6987	370	if ((val & ULITE_STATUS_TXFULL) == 0)
238b8721	371	break;
1d6b6987	372	cpu_relax();
238b8721 PK	373	}
	374	}
	375
	376	static void ulite_console_putchar(struct uart_port *port, int ch)
	377	{
	378	ulite_console_wait_tx(port);
e5bbbb18	379	iowrite32be(ch, port->membase + ULITE_TX);
238b8721 PK	380	}
	381
	382	static void ulite_console_write(struct console co, const char s,
	383	unsigned int count)
	384	{
483c79db	385	struct uart_port *port = &ulite_ports[co->index];
238b8721 PK	386	unsigned long flags;
	387	unsigned int ier;
	388	int locked = 1;
	389
	390	if (oops_in_progress) {
	391	locked = spin_trylock_irqsave(&port->lock, flags);
	392	} else
	393	spin_lock_irqsave(&port->lock, flags);
	394
	395	/* save and disable interrupt */
e5bbbb18 JL	396	ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
e5bbbb18 JL	397	iowrite32be(0, port->membase + ULITE_CONTROL);
238b8721 PK	398
	399	uart_console_write(port, s, count, ulite_console_putchar);
	400
	401	ulite_console_wait_tx(port);
	402
	403	/* restore interrupt state */
	404	if (ier)
e5bbbb18	405	iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
238b8721 PK	406
	407	if (locked)
	408	spin_unlock_irqrestore(&port->lock, flags);
	409	}
	410
03eac7bb	411	static int __devinit ulite_console_setup(struct console co, char options)
238b8721 PK	412	{
	413	struct uart_port *port;
	414	int baud = 9600;
	415	int bits = 8;
	416	int parity = 'n';
	417	int flow = 'n';
	418
	419	if (co->index < 0 \|\| co->index >= ULITE_NR_UARTS)
	420	return -EINVAL;
	421
483c79db	422	port = &ulite_ports[co->index];
238b8721	423
3de66a17	424	/* Has the device been initialized yet? */
fb4e6e66 GL	425	if (!port->mapbase) {
	426	pr_debug("console on ttyUL%i not present\n", co->index);
	427	return -ENODEV;
	428	}
	429
238b8721	430	/* not initialized yet? */
852e1ea7	431	if (!port->membase) {
fb4e6e66 GL	432	if (ulite_request_port(port))
fb4e6e66 GL	433	return -ENODEV;
852e1ea7	434	}
238b8721 PK	435
	436	if (options)
	437	uart_parse_options(options, &baud, &parity, &bits, &flow);
	438
	439	return uart_set_options(port, co, baud, parity, bits, flow);
	440	}
	441
	442	static struct uart_driver ulite_uart_driver;
	443
	444	static struct console ulite_console = {
00775828	445	.name = ULITE_NAME,
238b8721 PK	446	.write = ulite_console_write,
	447	.device = uart_console_device,
	448	.setup = ulite_console_setup,
	449	.flags = CON_PRINTBUFFER,
	450	.index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	451	.data = &ulite_uart_driver,
	452	};
	453
	454	static int __init ulite_console_init(void)
	455	{
	456	register_console(&ulite_console);
	457	return 0;
	458	}
	459
	460	console_initcall(ulite_console_init);
	461
	462	#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
	463
	464	static struct uart_driver ulite_uart_driver = {
	465	.owner = THIS_MODULE,
	466	.driver_name = "uartlite",
00775828	467	.dev_name = ULITE_NAME,
238b8721 PK	468	.major = ULITE_MAJOR,
	469	.minor = ULITE_MINOR,
	470	.nr = ULITE_NR_UARTS,
	471	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	472	.cons = &ulite_console,
	473	#endif
	474	};
	475
435706b3 GL	476	/* ---------------------------------------------------------------------
	477	* Port assignment functions (mapping devices to uart_port structures)
	478	*/
	479
	480	/** ulite_assign: register a uartlite device with the driver
	481	*
	482	* @dev: pointer to device structure
	483	* @id: requested id number. Pass -1 for automatic port assignment
	484	* @base: base address of uartlite registers
	485	* @irq: irq number for uartlite
	486	*
	487	* Returns: 0 on success, <0 otherwise
	488	*/
8fa7b610	489	static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
238b8721	490	{
238b8721	491	struct uart_port *port;
8fa7b610	492	int rc;
238b8721	493
8fa7b610 GL	494	/* if id = -1; then scan for a free id and use that */
	495	if (id < 0) {
	496	for (id = 0; id < ULITE_NR_UARTS; id++)
	497	if (ulite_ports[id].mapbase == 0)
	498	break;
	499	}
	500	if (id < 0 \|\| id >= ULITE_NR_UARTS) {
	501	dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
238b8721	502	return -EINVAL;
8fa7b610	503	}
238b8721	504
fb4e6e66	505	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
8fa7b610 GL	506	dev_err(dev, "cannot assign to %s%i; it is already in use\n",
8fa7b610 GL	507	ULITE_NAME, id);
238b8721	508	return -EBUSY;
8fa7b610	509	}
238b8721	510
8fa7b610	511	port = &ulite_ports[id];
238b8721	512
8fa7b610 GL	513	spin_lock_init(&port->lock);
	514	port->fifosize = 16;
	515	port->regshift = 2;
	516	port->iotype = UPIO_MEM;
	517	port->iobase = 1; /* mark port in use */
	518	port->mapbase = base;
	519	port->membase = NULL;
	520	port->ops = &ulite_ops;
	521	port->irq = irq;
	522	port->flags = UPF_BOOT_AUTOCONF;
	523	port->dev = dev;
	524	port->type = PORT_UNKNOWN;
	525	port->line = id;
	526
	527	dev_set_drvdata(dev, port);
	528
	529	/* Register the port */
	530	rc = uart_add_one_port(&ulite_uart_driver, port);
	531	if (rc) {
	532	dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
	533	port->mapbase = 0;
	534	dev_set_drvdata(dev, NULL);
	535	return rc;
	536	}
238b8721	537
8fa7b610 GL	538	return 0;
8fa7b610 GL	539	}
238b8721	540
435706b3 GL	541	/** ulite_release: register a uartlite device with the driver
	542	*
	543	* @dev: pointer to device structure
	544	*/
f67702a3	545	static int __devexit ulite_release(struct device *dev)
8fa7b610 GL	546	{
	547	struct uart_port *port = dev_get_drvdata(dev);
	548	int rc = 0;
238b8721	549
8fa7b610 GL	550	if (port) {
	551	rc = uart_remove_one_port(&ulite_uart_driver, port);
	552	dev_set_drvdata(dev, NULL);
	553	port->mapbase = 0;
	554	}
238b8721	555
8fa7b610	556	return rc;
238b8721 PK	557	}
238b8721 PK	558
435706b3 GL	559	/* ---------------------------------------------------------------------
	560	* Platform bus binding
	561	*/
	562
e5263a51 GL	563	#if defined(CONFIG_OF)
	564	/* Match table for of_platform binding */
	565	static struct of_device_id ulite_of_match[] __devinitdata = {
	566	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	567	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	568	{}
	569	};
	570	MODULE_DEVICE_TABLE(of, ulite_of_match);
	571	#else /* CONFIG_OF */
	572	#define ulite_of_match NULL
	573	#endif /* CONFIG_OF */
	574
8fa7b610	575	static int __devinit ulite_probe(struct platform_device *pdev)
238b8721	576	{
8fa7b610	577	struct resource res, res2;
e5263a51 GL	578	int id = pdev->id;
	579	#ifdef CONFIG_OF
	580	const __be32 *prop;
	581
	582	prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
	583	if (prop)
	584	id = be32_to_cpup(prop);
	585	#endif
238b8721	586
8fa7b610 GL	587	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	588	if (!res)
	589	return -ENODEV;
238b8721	590
8fa7b610 GL	591	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	592	if (!res2)
	593	return -ENODEV;
238b8721	594
e5263a51	595	return ulite_assign(&pdev->dev, id, res->start, res2->start);
8fa7b610	596	}
238b8721	597
f67702a3	598	static int __devexit ulite_remove(struct platform_device *pdev)
8fa7b610 GL	599	{
8fa7b610 GL	600	return ulite_release(&pdev->dev);
238b8721 PK	601	}
238b8721 PK	602
e169c139 KS	603	/* work with hotplug and coldplug */
	604	MODULE_ALIAS("platform:uartlite");
	605
238b8721	606	static struct platform_driver ulite_platform_driver = {
e5263a51 GL	607	.probe = ulite_probe,
e5263a51 GL	608	.remove = __devexit_p(ulite_remove),
852e1ea7	609	.driver = {
4018294b	610	.owner = THIS_MODULE,
e5263a51	611	.name = "uartlite",
4018294b	612	.of_match_table = ulite_of_match,
852e1ea7 GL	613	},
	614	};
	615
435706b3 GL	616	/* ---------------------------------------------------------------------
	617	* Module setup/teardown
	618	*/
	619
238b8721 PK	620	int __init ulite_init(void)
	621	{
	622	int ret;
	623
852e1ea7	624	pr_debug("uartlite: calling uart_register_driver()\n");
238b8721 PK	625	ret = uart_register_driver(&ulite_uart_driver);
238b8721 PK	626	if (ret)
852e1ea7 GL	627	goto err_uart;
852e1ea7 GL	628
852e1ea7	629	pr_debug("uartlite: calling platform_driver_register()\n");
238b8721 PK	630	ret = platform_driver_register(&ulite_platform_driver);
238b8721 PK	631	if (ret)
852e1ea7 GL	632	goto err_plat;
	633
	634	return 0;
238b8721	635
852e1ea7	636	err_plat:
852e1ea7 GL	637	uart_unregister_driver(&ulite_uart_driver);
	638	err_uart:
	639	printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
238b8721 PK	640	return ret;
	641	}
	642
	643	void __exit ulite_exit(void)
	644	{
	645	platform_driver_unregister(&ulite_platform_driver);
	646	uart_unregister_driver(&ulite_uart_driver);
	647	}
	648
	649	module_init(ulite_init);
	650	module_exit(ulite_exit);
	651
	652	MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
	653	MODULE_DESCRIPTION("Xilinx uartlite serial driver");
	654	MODULE_LICENSE("GPL");