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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux
[deliverable/linux.git] / drivers / tty / synclink.c
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1da177e4 1/*
0ff1b2c8 2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
1da177e4
LT		 3 *
4 * Device driver for Microgate SyncLink ISA and PCI
5 * high speed multiprotocol serial adapters.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 *
14 * Original release 01/11/99
15 *
16 * This code is released under the GNU General Public License (GPL)
17 *
18 * This driver is primarily intended for use in synchronous
19 * HDLC mode. Asynchronous mode is also provided.
20 *
21 * When operating in synchronous mode, each call to mgsl_write()
22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
23 * will start assembling an HDLC frame that will not be sent until
24 * mgsl_flush_chars or mgsl_write is called.
25 *
26 * Synchronous receive data is reported as complete frames. To accomplish
27 * this, the TTY flip buffer is bypassed (too small to hold largest
28 * frame and may fragment frames) and the line discipline
29 * receive entry point is called directly.
30 *
31 * This driver has been tested with a slightly modified ppp.c driver
32 * for synchronous PPP.
33 *
34 * 2000/02/16
35 * Added interface for syncppp.c driver (an alternate synchronous PPP
36 * implementation that also supports Cisco HDLC). Each device instance
37 * registers as a tty device AND a network device (if dosyncppp option
38 * is set for the device). The functionality is determined by which
39 * device interface is opened.
40 *
41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
51 * OF THE POSSIBILITY OF SUCH DAMAGE.
52 */
53
54#if defined(__i386__)
55# define BREAKPOINT() asm(" int $3");
56#else
57# define BREAKPOINT() { }
58#endif
59
60#define MAX_ISA_DEVICES 10
61#define MAX_PCI_DEVICES 10
62#define MAX_TOTAL_DEVICES 20
63
1da177e4
LT		 64#include <linux/module.h>
65#include <linux/errno.h>
66#include <linux/signal.h>
67#include <linux/sched.h>
68#include <linux/timer.h>
69#include <linux/interrupt.h>
70#include <linux/pci.h>
71#include <linux/tty.h>
72#include <linux/tty_flip.h>
73#include <linux/serial.h>
74#include <linux/major.h>
75#include <linux/string.h>
76#include <linux/fcntl.h>
77#include <linux/ptrace.h>
78#include <linux/ioport.h>
79#include <linux/mm.h>
d337829b 80#include <linux/seq_file.h>
1da177e4
LT		 81#include <linux/slab.h>
82#include <linux/delay.h>
1da177e4 83#include <linux/netdevice.h>
1da177e4
LT		 84#include <linux/vmalloc.h>
85#include <linux/init.h>
1da177e4 86#include <linux/ioctl.h>
3dd1247f 87#include <linux/synclink.h>
1da177e4 88
1da177e4
LT		 89#include <asm/io.h>
90#include <asm/irq.h>
91#include <asm/dma.h>
92#include <linux/bitops.h>
93#include <asm/types.h>
94#include <linux/termios.h>
95#include <linux/workqueue.h>
96#include <linux/hdlc.h>
0ff1b2c8 97#include <linux/dma-mapping.h>
1da177e4 98
af69c7f9
PF		 99#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100#define SYNCLINK_GENERIC_HDLC 1
101#else
102#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 103#endif
104
105#define GET_USER(error,value,addr) error = get_user(value,addr)
106#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107#define PUT_USER(error,value,addr) error = put_user(value,addr)
108#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
109
110#include <asm/uaccess.h>
111
1da177e4
LT		 112#define RCLRVALUE 0xffff
113
114static MGSL_PARAMS default_params = {
115 MGSL_MODE_HDLC, /* unsigned long mode */
116 0, /* unsigned char loopback; */
117 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
118 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
119 0, /* unsigned long clock_speed; */
120 0xff, /* unsigned char addr_filter; */
121 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
122 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
123 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
124 9600, /* unsigned long data_rate; */
125 8, /* unsigned char data_bits; */
126 1, /* unsigned char stop_bits; */
127 ASYNC_PARITY_NONE /* unsigned char parity; */
128};
129
130#define SHARED_MEM_ADDRESS_SIZE 0x40000
623a4395
PF		 131#define BUFFERLISTSIZE 4096
132#define DMABUFFERSIZE 4096
1da177e4
LT		 133#define MAXRXFRAMES 7
134
135typedef struct _DMABUFFERENTRY
136{
137 u32 phys_addr; /* 32-bit flat physical address of data buffer */
4a918bc2
PF		 138 volatile u16 count; /* buffer size/data count */
139 volatile u16 status; /* Control/status field */
140 volatile u16 rcc; /* character count field */
1da177e4
LT		 141 u16 reserved; /* padding required by 16C32 */
142 u32 link; /* 32-bit flat link to next buffer entry */
143 char *virt_addr; /* virtual address of data buffer */
144 u32 phys_entry; /* physical address of this buffer entry */
0ff1b2c8 145 dma_addr_t dma_addr;
1da177e4
LT		 146} DMABUFFERENTRY, *DMAPBUFFERENTRY;
147
148/* The queue of BH actions to be performed */
149
150#define BH_RECEIVE 1
151#define BH_TRANSMIT 2
152#define BH_STATUS 4
153
154#define IO_PIN_SHUTDOWN_LIMIT 100
155
1da177e4
LT		 156struct _input_signal_events {
157 int ri_up;
158 int ri_down;
159 int dsr_up;
160 int dsr_down;
161 int dcd_up;
162 int dcd_down;
163 int cts_up;
164 int cts_down;
165};
166
167/* transmit holding buffer definitions*/
168#define MAX_TX_HOLDING_BUFFERS 5
169struct tx_holding_buffer {
170 int buffer_size;
171 unsigned char * buffer;
172};
173
174
175/*
176 * Device instance data structure
177 */
178
179struct mgsl_struct {
180 int magic;
8fb06c77 181 struct tty_port port;
1da177e4
LT		 182 int line;
183 int hw_version;
1da177e4
LT		 184
185 struct mgsl_icount icount;
186
1da177e4
LT		 187 int timeout;
188 int x_char; /* xon/xoff character */
1da177e4
LT		 189 u16 read_status_mask;
190 u16 ignore_status_mask;
191 unsigned char *xmit_buf;
192 int xmit_head;
193 int xmit_tail;
194 int xmit_cnt;
195
1da177e4
LT		 196 wait_queue_head_t status_event_wait_q;
197 wait_queue_head_t event_wait_q;
198 struct timer_list tx_timer; /* HDLC transmit timeout timer */
199 struct mgsl_struct *next_device; /* device list link */
200
201 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
202 struct work_struct task; /* task structure for scheduling bh */
203
204 u32 EventMask; /* event trigger mask */
205 u32 RecordedEvents; /* pending events */
206
207 u32 max_frame_size; /* as set by device config */
208
209 u32 pending_bh;
210
0fab6de0 211 bool bh_running; /* Protection from multiple */
1da177e4 212 int isr_overflow;
0fab6de0 213 bool bh_requested;
1da177e4
LT		 214
215 int dcd_chkcount; /* check counts to prevent */
216 int cts_chkcount; /* too many IRQs if a signal */
217 int dsr_chkcount; /* is floating */
218 int ri_chkcount;
219
220 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
0ff1b2c8
PF		 221 u32 buffer_list_phys;
222 dma_addr_t buffer_list_dma_addr;
1da177e4
LT		 223
224 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
225 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
226 unsigned int current_rx_buffer;
227
228 int num_tx_dma_buffers; /* number of tx dma frames required */
229 int tx_dma_buffers_used;
230 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
231 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
232 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
233 int current_tx_buffer; /* next tx dma buffer to be loaded */
234
235 unsigned char *intermediate_rxbuffer;
236
237 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
238 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
239 int put_tx_holding_index; /* next tx holding buffer to store user request */
240 int tx_holding_count; /* number of tx holding buffers waiting */
241 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
242
0fab6de0
JP		 243 bool rx_enabled;
244 bool rx_overflow;
245 bool rx_rcc_underrun;
1da177e4 246
0fab6de0
JP		 247 bool tx_enabled;
248 bool tx_active;
1da177e4
LT		 249 u32 idle_mode;
250
251 u16 cmr_value;
252 u16 tcsr_value;
253
254 char device_name[25]; /* device instance name */
255
256 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
257 unsigned char bus; /* expansion bus number (zero based) */
258 unsigned char function; /* PCI device number */
259
260 unsigned int io_base; /* base I/O address of adapter */
261 unsigned int io_addr_size; /* size of the I/O address range */
0fab6de0 262 bool io_addr_requested; /* true if I/O address requested */
1da177e4
LT		 263
264 unsigned int irq_level; /* interrupt level */
265 unsigned long irq_flags;
0fab6de0 266 bool irq_requested; /* true if IRQ requested */
1da177e4
LT		 267
268 unsigned int dma_level; /* DMA channel */
0fab6de0 269 bool dma_requested; /* true if dma channel requested */
1da177e4
LT		 270
271 u16 mbre_bit;
272 u16 loopback_bits;
273 u16 usc_idle_mode;
274
275 MGSL_PARAMS params; /* communications parameters */
276
277 unsigned char serial_signals; /* current serial signal states */
278
0fab6de0 279 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 280 unsigned int init_error; /* Initialization startup error (DIAGS) */
281 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
282
283 u32 last_mem_alloc;
284 unsigned char* memory_base; /* shared memory address (PCI only) */
285 u32 phys_memory_base;
0fab6de0 286 bool shared_mem_requested;
1da177e4
LT		 287
288 unsigned char* lcr_base; /* local config registers (PCI only) */
289 u32 phys_lcr_base;
290 u32 lcr_offset;
0fab6de0 291 bool lcr_mem_requested;
1da177e4
LT		 292
293 u32 misc_ctrl_value;
a6b68a69 294 char *flag_buf;
0fab6de0 295 bool drop_rts_on_tx_done;
1da177e4 296
0fab6de0
JP		 297 bool loopmode_insert_requested;
298 bool loopmode_send_done_requested;
1da177e4
LT		 299
300 struct _input_signal_events input_signal_events;
301
302 /* generic HDLC device parts */
303 int netcount;
1da177e4
LT		 304 spinlock_t netlock;
305
af69c7f9 306#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 307 struct net_device *netdev;
308#endif
309};
310
311#define MGSL_MAGIC 0x5401
312
313/*
314 * The size of the serial xmit buffer is 1 page, or 4096 bytes
315 */
316#ifndef SERIAL_XMIT_SIZE
317#define SERIAL_XMIT_SIZE 4096
318#endif
319
320/*
321 * These macros define the offsets used in calculating the
322 * I/O address of the specified USC registers.
323 */
324
325
326#define DCPIN 2 /* Bit 1 of I/O address */
327#define SDPIN 4 /* Bit 2 of I/O address */
328
329#define DCAR 0 /* DMA command/address register */
330#define CCAR SDPIN /* channel command/address register */
331#define DATAREG DCPIN + SDPIN /* serial data register */
332#define MSBONLY 0x41
333#define LSBONLY 0x40
334
335/*
336 * These macros define the register address (ordinal number)
337 * used for writing address/value pairs to the USC.
338 */
339
340#define CMR 0x02 /* Channel mode Register */
341#define CCSR 0x04 /* Channel Command/status Register */
342#define CCR 0x06 /* Channel Control Register */
343#define PSR 0x08 /* Port status Register */
344#define PCR 0x0a /* Port Control Register */
345#define TMDR 0x0c /* Test mode Data Register */
346#define TMCR 0x0e /* Test mode Control Register */
347#define CMCR 0x10 /* Clock mode Control Register */
348#define HCR 0x12 /* Hardware Configuration Register */
349#define IVR 0x14 /* Interrupt Vector Register */
350#define IOCR 0x16 /* Input/Output Control Register */
351#define ICR 0x18 /* Interrupt Control Register */
352#define DCCR 0x1a /* Daisy Chain Control Register */
353#define MISR 0x1c /* Misc Interrupt status Register */
354#define SICR 0x1e /* status Interrupt Control Register */
355#define RDR 0x20 /* Receive Data Register */
356#define RMR 0x22 /* Receive mode Register */
357#define RCSR 0x24 /* Receive Command/status Register */
358#define RICR 0x26 /* Receive Interrupt Control Register */
359#define RSR 0x28 /* Receive Sync Register */
360#define RCLR 0x2a /* Receive count Limit Register */
361#define RCCR 0x2c /* Receive Character count Register */
362#define TC0R 0x2e /* Time Constant 0 Register */
363#define TDR 0x30 /* Transmit Data Register */
364#define TMR 0x32 /* Transmit mode Register */
365#define TCSR 0x34 /* Transmit Command/status Register */
366#define TICR 0x36 /* Transmit Interrupt Control Register */
367#define TSR 0x38 /* Transmit Sync Register */
368#define TCLR 0x3a /* Transmit count Limit Register */
369#define TCCR 0x3c /* Transmit Character count Register */
370#define TC1R 0x3e /* Time Constant 1 Register */
371
372
373/*
374 * MACRO DEFINITIONS FOR DMA REGISTERS
375 */
376
377#define DCR 0x06 /* DMA Control Register (shared) */
378#define DACR 0x08 /* DMA Array count Register (shared) */
379#define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
380#define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
381#define DICR 0x18 /* DMA Interrupt Control Register (shared) */
382#define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
383#define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
384
385#define TDMR 0x02 /* Transmit DMA mode Register */
386#define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
387#define TBCR 0x2a /* Transmit Byte count Register */
388#define TARL 0x2c /* Transmit Address Register (low) */
389#define TARU 0x2e /* Transmit Address Register (high) */
390#define NTBCR 0x3a /* Next Transmit Byte count Register */
391#define NTARL 0x3c /* Next Transmit Address Register (low) */
392#define NTARU 0x3e /* Next Transmit Address Register (high) */
393
394#define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
395#define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
396#define RBCR 0xaa /* Receive Byte count Register */
397#define RARL 0xac /* Receive Address Register (low) */
398#define RARU 0xae /* Receive Address Register (high) */
399#define NRBCR 0xba /* Next Receive Byte count Register */
400#define NRARL 0xbc /* Next Receive Address Register (low) */
401#define NRARU 0xbe /* Next Receive Address Register (high) */
402
403
404/*
405 * MACRO DEFINITIONS FOR MODEM STATUS BITS
406 */
407
408#define MODEMSTATUS_DTR 0x80
409#define MODEMSTATUS_DSR 0x40
410#define MODEMSTATUS_RTS 0x20
411#define MODEMSTATUS_CTS 0x10
412#define MODEMSTATUS_RI 0x04
413#define MODEMSTATUS_DCD 0x01
414
415
416/*
417 * Channel Command/Address Register (CCAR) Command Codes
418 */
419
420#define RTCmd_Null 0x0000
421#define RTCmd_ResetHighestIus 0x1000
422#define RTCmd_TriggerChannelLoadDma 0x2000
423#define RTCmd_TriggerRxDma 0x2800
424#define RTCmd_TriggerTxDma 0x3000
425#define RTCmd_TriggerRxAndTxDma 0x3800
426#define RTCmd_PurgeRxFifo 0x4800
427#define RTCmd_PurgeTxFifo 0x5000
428#define RTCmd_PurgeRxAndTxFifo 0x5800
429#define RTCmd_LoadRcc 0x6800
430#define RTCmd_LoadTcc 0x7000
431#define RTCmd_LoadRccAndTcc 0x7800
432#define RTCmd_LoadTC0 0x8800
433#define RTCmd_LoadTC1 0x9000
434#define RTCmd_LoadTC0AndTC1 0x9800
435#define RTCmd_SerialDataLSBFirst 0xa000
436#define RTCmd_SerialDataMSBFirst 0xa800
437#define RTCmd_SelectBigEndian 0xb000
438#define RTCmd_SelectLittleEndian 0xb800
439
440
441/*
442 * DMA Command/Address Register (DCAR) Command Codes
443 */
444
445#define DmaCmd_Null 0x0000
446#define DmaCmd_ResetTxChannel 0x1000
447#define DmaCmd_ResetRxChannel 0x1200
448#define DmaCmd_StartTxChannel 0x2000
449#define DmaCmd_StartRxChannel 0x2200
450#define DmaCmd_ContinueTxChannel 0x3000
451#define DmaCmd_ContinueRxChannel 0x3200
452#define DmaCmd_PauseTxChannel 0x4000
453#define DmaCmd_PauseRxChannel 0x4200
454#define DmaCmd_AbortTxChannel 0x5000
455#define DmaCmd_AbortRxChannel 0x5200
456#define DmaCmd_InitTxChannel 0x7000
457#define DmaCmd_InitRxChannel 0x7200
458#define DmaCmd_ResetHighestDmaIus 0x8000
459#define DmaCmd_ResetAllChannels 0x9000
460#define DmaCmd_StartAllChannels 0xa000
461#define DmaCmd_ContinueAllChannels 0xb000
462#define DmaCmd_PauseAllChannels 0xc000
463#define DmaCmd_AbortAllChannels 0xd000
464#define DmaCmd_InitAllChannels 0xf000
465
466#define TCmd_Null 0x0000
467#define TCmd_ClearTxCRC 0x2000
468#define TCmd_SelectTicrTtsaData 0x4000
469#define TCmd_SelectTicrTxFifostatus 0x5000
470#define TCmd_SelectTicrIntLevel 0x6000
471#define TCmd_SelectTicrdma_level 0x7000
472#define TCmd_SendFrame 0x8000
473#define TCmd_SendAbort 0x9000
474#define TCmd_EnableDleInsertion 0xc000
475#define TCmd_DisableDleInsertion 0xd000
476#define TCmd_ClearEofEom 0xe000
477#define TCmd_SetEofEom 0xf000
478
479#define RCmd_Null 0x0000
480#define RCmd_ClearRxCRC 0x2000
481#define RCmd_EnterHuntmode 0x3000
482#define RCmd_SelectRicrRtsaData 0x4000
483#define RCmd_SelectRicrRxFifostatus 0x5000
484#define RCmd_SelectRicrIntLevel 0x6000
485#define RCmd_SelectRicrdma_level 0x7000
486
487/*
488 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
489 */
490
491#define RECEIVE_STATUS BIT5
492#define RECEIVE_DATA BIT4
493#define TRANSMIT_STATUS BIT3
494#define TRANSMIT_DATA BIT2
495#define IO_PIN BIT1
496#define MISC BIT0
497
498
499/*
500 * Receive status Bits in Receive Command/status Register RCSR
501 */
502
503#define RXSTATUS_SHORT_FRAME BIT8
504#define RXSTATUS_CODE_VIOLATION BIT8
505#define RXSTATUS_EXITED_HUNT BIT7
506#define RXSTATUS_IDLE_RECEIVED BIT6
507#define RXSTATUS_BREAK_RECEIVED BIT5
508#define RXSTATUS_ABORT_RECEIVED BIT5
509#define RXSTATUS_RXBOUND BIT4
510#define RXSTATUS_CRC_ERROR BIT3
511#define RXSTATUS_FRAMING_ERROR BIT3
512#define RXSTATUS_ABORT BIT2
513#define RXSTATUS_PARITY_ERROR BIT2
514#define RXSTATUS_OVERRUN BIT1
515#define RXSTATUS_DATA_AVAILABLE BIT0
516#define RXSTATUS_ALL 0x01f6
517#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
518
519/*
520 * Values for setting transmit idle mode in
521 * Transmit Control/status Register (TCSR)
522 */
523#define IDLEMODE_FLAGS 0x0000
524#define IDLEMODE_ALT_ONE_ZERO 0x0100
525#define IDLEMODE_ZERO 0x0200
526#define IDLEMODE_ONE 0x0300
527#define IDLEMODE_ALT_MARK_SPACE 0x0500
528#define IDLEMODE_SPACE 0x0600
529#define IDLEMODE_MARK 0x0700
530#define IDLEMODE_MASK 0x0700
531
532/*
533 * IUSC revision identifiers
534 */
535#define IUSC_SL1660 0x4d44
536#define IUSC_PRE_SL1660 0x4553
537
538/*
539 * Transmit status Bits in Transmit Command/status Register (TCSR)
540 */
541
542#define TCSR_PRESERVE 0x0F00
543
544#define TCSR_UNDERWAIT BIT11
545#define TXSTATUS_PREAMBLE_SENT BIT7
546#define TXSTATUS_IDLE_SENT BIT6
547#define TXSTATUS_ABORT_SENT BIT5
548#define TXSTATUS_EOF_SENT BIT4
549#define TXSTATUS_EOM_SENT BIT4
550#define TXSTATUS_CRC_SENT BIT3
551#define TXSTATUS_ALL_SENT BIT2
552#define TXSTATUS_UNDERRUN BIT1
553#define TXSTATUS_FIFO_EMPTY BIT0
554#define TXSTATUS_ALL 0x00fa
555#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
556
557
558#define MISCSTATUS_RXC_LATCHED BIT15
559#define MISCSTATUS_RXC BIT14
560#define MISCSTATUS_TXC_LATCHED BIT13
561#define MISCSTATUS_TXC BIT12
562#define MISCSTATUS_RI_LATCHED BIT11
563#define MISCSTATUS_RI BIT10
564#define MISCSTATUS_DSR_LATCHED BIT9
565#define MISCSTATUS_DSR BIT8
566#define MISCSTATUS_DCD_LATCHED BIT7
567#define MISCSTATUS_DCD BIT6
568#define MISCSTATUS_CTS_LATCHED BIT5
569#define MISCSTATUS_CTS BIT4
570#define MISCSTATUS_RCC_UNDERRUN BIT3
571#define MISCSTATUS_DPLL_NO_SYNC BIT2
572#define MISCSTATUS_BRG1_ZERO BIT1
573#define MISCSTATUS_BRG0_ZERO BIT0
574
575#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
576#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
577
578#define SICR_RXC_ACTIVE BIT15
579#define SICR_RXC_INACTIVE BIT14
e06922aa 580#define SICR_RXC (BIT15|BIT14)
1da177e4
LT		 581#define SICR_TXC_ACTIVE BIT13
582#define SICR_TXC_INACTIVE BIT12
e06922aa 583#define SICR_TXC (BIT13|BIT12)
1da177e4
LT		 584#define SICR_RI_ACTIVE BIT11
585#define SICR_RI_INACTIVE BIT10
e06922aa 586#define SICR_RI (BIT11|BIT10)
1da177e4
LT		 587#define SICR_DSR_ACTIVE BIT9
588#define SICR_DSR_INACTIVE BIT8
e06922aa 589#define SICR_DSR (BIT9|BIT8)
1da177e4
LT		 590#define SICR_DCD_ACTIVE BIT7
591#define SICR_DCD_INACTIVE BIT6
e06922aa 592#define SICR_DCD (BIT7|BIT6)
1da177e4
LT		 593#define SICR_CTS_ACTIVE BIT5
594#define SICR_CTS_INACTIVE BIT4
e06922aa 595#define SICR_CTS (BIT5|BIT4)
1da177e4
LT		 596#define SICR_RCC_UNDERFLOW BIT3
597#define SICR_DPLL_NO_SYNC BIT2
598#define SICR_BRG1_ZERO BIT1
599#define SICR_BRG0_ZERO BIT0
600
601void usc_DisableMasterIrqBit( struct mgsl_struct *info );
602void usc_EnableMasterIrqBit( struct mgsl_struct *info );
603void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
604void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
605void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
606
607#define usc_EnableInterrupts( a, b ) \
608 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
609
610#define usc_DisableInterrupts( a, b ) \
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
612
613#define usc_EnableMasterIrqBit(a) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
615
616#define usc_DisableMasterIrqBit(a) \
617 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
618
619#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
620
621/*
622 * Transmit status Bits in Transmit Control status Register (TCSR)
623 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
624 */
625
626#define TXSTATUS_PREAMBLE_SENT BIT7
627#define TXSTATUS_IDLE_SENT BIT6
628#define TXSTATUS_ABORT_SENT BIT5
629#define TXSTATUS_EOF BIT4
630#define TXSTATUS_CRC_SENT BIT3
631#define TXSTATUS_ALL_SENT BIT2
632#define TXSTATUS_UNDERRUN BIT1
633#define TXSTATUS_FIFO_EMPTY BIT0
634
635#define DICR_MASTER BIT15
636#define DICR_TRANSMIT BIT0
637#define DICR_RECEIVE BIT1
638
639#define usc_EnableDmaInterrupts(a,b) \
640 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
641
642#define usc_DisableDmaInterrupts(a,b) \
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
644
645#define usc_EnableStatusIrqs(a,b) \
646 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
647
648#define usc_DisablestatusIrqs(a,b) \
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
650
651/* Transmit status Bits in Transmit Control status Register (TCSR) */
652/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
653
654
655#define DISABLE_UNCONDITIONAL 0
656#define DISABLE_END_OF_FRAME 1
657#define ENABLE_UNCONDITIONAL 2
658#define ENABLE_AUTO_CTS 3
659#define ENABLE_AUTO_DCD 3
660#define usc_EnableTransmitter(a,b) \
661 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
662#define usc_EnableReceiver(a,b) \
663 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
664
665static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
666static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
667static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
668
669static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
670static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
671static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
672void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
673void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
674
675#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
676#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
677
678#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
679
680static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
681static void usc_start_receiver( struct mgsl_struct *info );
682static void usc_stop_receiver( struct mgsl_struct *info );
683
684static void usc_start_transmitter( struct mgsl_struct *info );
685static void usc_stop_transmitter( struct mgsl_struct *info );
686static void usc_set_txidle( struct mgsl_struct *info );
687static void usc_load_txfifo( struct mgsl_struct *info );
688
689static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
690static void usc_enable_loopback( struct mgsl_struct *info, int enable );
691
692static void usc_get_serial_signals( struct mgsl_struct *info );
693static void usc_set_serial_signals( struct mgsl_struct *info );
694
695static void usc_reset( struct mgsl_struct *info );
696
697static void usc_set_sync_mode( struct mgsl_struct *info );
698static void usc_set_sdlc_mode( struct mgsl_struct *info );
699static void usc_set_async_mode( struct mgsl_struct *info );
700static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
701
702static void usc_loopback_frame( struct mgsl_struct *info );
703
704static void mgsl_tx_timeout(unsigned long context);
705
706
707static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
708static void usc_loopmode_insert_request( struct mgsl_struct * info );
709static int usc_loopmode_active( struct mgsl_struct * info);
710static void usc_loopmode_send_done( struct mgsl_struct * info );
711
712static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
713
af69c7f9 714#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 715#define dev_to_port(D) (dev_to_hdlc(D)->priv)
716static void hdlcdev_tx_done(struct mgsl_struct *info);
717static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
718static int hdlcdev_init(struct mgsl_struct *info);
719static void hdlcdev_exit(struct mgsl_struct *info);
720#endif
721
722/*
723 * Defines a BUS descriptor value for the PCI adapter
724 * local bus address ranges.
725 */
726
727#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
728(0x00400020 + \
729((WrHold) << 30) + \
730((WrDly) << 28) + \
731((RdDly) << 26) + \
732((Nwdd) << 20) + \
733((Nwad) << 15) + \
734((Nxda) << 13) + \
735((Nrdd) << 11) + \
736((Nrad) << 6) )
737
738static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
739
740/*
741 * Adapter diagnostic routines
742 */
0fab6de0
JP		 743static bool mgsl_register_test( struct mgsl_struct *info );
744static bool mgsl_irq_test( struct mgsl_struct *info );
745static bool mgsl_dma_test( struct mgsl_struct *info );
746static bool mgsl_memory_test( struct mgsl_struct *info );
1da177e4
LT		 747static int mgsl_adapter_test( struct mgsl_struct *info );
748
749/*
750 * device and resource management routines
751 */
752static int mgsl_claim_resources(struct mgsl_struct *info);
753static void mgsl_release_resources(struct mgsl_struct *info);
754static void mgsl_add_device(struct mgsl_struct *info);
755static struct mgsl_struct* mgsl_allocate_device(void);
756
757/*
758 * DMA buffer manupulation functions.
759 */
760static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
0fab6de0
JP		 761static bool mgsl_get_rx_frame( struct mgsl_struct *info );
762static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
1da177e4
LT		 763static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
764static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
765static int num_free_tx_dma_buffers(struct mgsl_struct *info);
766static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
767static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
768
769/*
770 * DMA and Shared Memory buffer allocation and formatting
771 */
772static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
773static void mgsl_free_dma_buffers(struct mgsl_struct *info);
774static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
775static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
776static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
777static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
778static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
779static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
780static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
781static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
0fab6de0 782static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
1da177e4
LT		 783static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
784
785/*
786 * Bottom half interrupt handlers
787 */
c4028958 788static void mgsl_bh_handler(struct work_struct *work);
1da177e4
LT		 789static void mgsl_bh_receive(struct mgsl_struct *info);
790static void mgsl_bh_transmit(struct mgsl_struct *info);
791static void mgsl_bh_status(struct mgsl_struct *info);
792
793/*
794 * Interrupt handler routines and dispatch table.
795 */
796static void mgsl_isr_null( struct mgsl_struct *info );
797static void mgsl_isr_transmit_data( struct mgsl_struct *info );
798static void mgsl_isr_receive_data( struct mgsl_struct *info );
799static void mgsl_isr_receive_status( struct mgsl_struct *info );
800static void mgsl_isr_transmit_status( struct mgsl_struct *info );
801static void mgsl_isr_io_pin( struct mgsl_struct *info );
802static void mgsl_isr_misc( struct mgsl_struct *info );
803static void mgsl_isr_receive_dma( struct mgsl_struct *info );
804static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
805
806typedef void (*isr_dispatch_func)(struct mgsl_struct *);
807
808static isr_dispatch_func UscIsrTable[7] =
809{
810 mgsl_isr_null,
811 mgsl_isr_misc,
812 mgsl_isr_io_pin,
813 mgsl_isr_transmit_data,
814 mgsl_isr_transmit_status,
815 mgsl_isr_receive_data,
816 mgsl_isr_receive_status
817};
818
819/*
820 * ioctl call handlers
821 */
60b33c13 822static int tiocmget(struct tty_struct *tty);
20b9d177 823static int tiocmset(struct tty_struct *tty,
1da177e4
LT		 824 unsigned int set, unsigned int clear);
825static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
826 __user *user_icount);
827static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
828static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
829static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
830static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
831static int mgsl_txenable(struct mgsl_struct * info, int enable);
832static int mgsl_txabort(struct mgsl_struct * info);
833static int mgsl_rxenable(struct mgsl_struct * info, int enable);
834static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
835static int mgsl_loopmode_send_done( struct mgsl_struct * info );
836
837/* set non-zero on successful registration with PCI subsystem */
0fab6de0 838static bool pci_registered;
1da177e4
LT		 839
840/*
841 * Global linked list of SyncLink devices
842 */
843static struct mgsl_struct *mgsl_device_list;
844static int mgsl_device_count;
845
846/*
847 * Set this param to non-zero to load eax with the
848 * .text section address and breakpoint on module load.
849 * This is useful for use with gdb and add-symbol-file command.
850 */
90ab5ee9 851static bool break_on_load;
1da177e4
LT		 852
853/*
854 * Driver major number, defaults to zero to get auto
855 * assigned major number. May be forced as module parameter.
856 */
857static int ttymajor;
858
859/*
860 * Array of user specified options for ISA adapters.
861 */
862static int io[MAX_ISA_DEVICES];
863static int irq[MAX_ISA_DEVICES];
864static int dma[MAX_ISA_DEVICES];
865static int debug_level;
866static int maxframe[MAX_TOTAL_DEVICES];
1da177e4
LT		 867static int txdmabufs[MAX_TOTAL_DEVICES];
868static int txholdbufs[MAX_TOTAL_DEVICES];
869
870module_param(break_on_load, bool, 0);
871module_param(ttymajor, int, 0);
872module_param_array(io, int, NULL, 0);
873module_param_array(irq, int, NULL, 0);
874module_param_array(dma, int, NULL, 0);
875module_param(debug_level, int, 0);
876module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 877module_param_array(txdmabufs, int, NULL, 0);
878module_param_array(txholdbufs, int, NULL, 0);
879
880static char *driver_name = "SyncLink serial driver";
0ff1b2c8 881static char *driver_version = "$Revision: 4.38 $";
1da177e4
LT		 882
883static int synclink_init_one (struct pci_dev *dev,
884 const struct pci_device_id *ent);
885static void synclink_remove_one (struct pci_dev *dev);
886
887static struct pci_device_id synclink_pci_tbl[] = {
888 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
889 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
890 { 0, }, /* terminate list */
891};
892MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
893
894MODULE_LICENSE("GPL");
895
896static struct pci_driver synclink_pci_driver = {
897 .name = "synclink",
898 .id_table = synclink_pci_tbl,
899 .probe = synclink_init_one,
91116cba 900 .remove = synclink_remove_one,
1da177e4
LT		 901};
902
903static struct tty_driver *serial_driver;
904
905/* number of characters left in xmit buffer before we ask for more */
906#define WAKEUP_CHARS 256
907
908
909static void mgsl_change_params(struct mgsl_struct *info);
910static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
911
912/*
913 * 1st function defined in .text section. Calling this function in
914 * init_module() followed by a breakpoint allows a remote debugger
915 * (gdb) to get the .text address for the add-symbol-file command.
916 * This allows remote debugging of dynamically loadable modules.
917 */
918static void* mgsl_get_text_ptr(void)
919{
920 return mgsl_get_text_ptr;
921}
922
1da177e4
LT		 923static inline int mgsl_paranoia_check(struct mgsl_struct *info,
924 char *name, const char *routine)
925{
926#ifdef MGSL_PARANOIA_CHECK
927 static const char *badmagic =
928 "Warning: bad magic number for mgsl struct (%s) in %s\n";
929 static const char *badinfo =
930 "Warning: null mgsl_struct for (%s) in %s\n";
931
932 if (!info) {
933 printk(badinfo, name, routine);
934 return 1;
935 }
936 if (info->magic != MGSL_MAGIC) {
937 printk(badmagic, name, routine);
938 return 1;
939 }
940#else
941 if (!info)
942 return 1;
943#endif
944 return 0;
945}
946
947/**
948 * line discipline callback wrappers
949 *
950 * The wrappers maintain line discipline references
951 * while calling into the line discipline.
952 *
953 * ldisc_receive_buf - pass receive data to line discipline
954 */
955
956static void ldisc_receive_buf(struct tty_struct *tty,
957 const __u8 *data, char *flags, int count)
958{
959 struct tty_ldisc *ld;
960 if (!tty)
961 return;
962 ld = tty_ldisc_ref(tty);
963 if (ld) {
a352def2
AC		 964 if (ld->ops->receive_buf)
965 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 966 tty_ldisc_deref(ld);
967 }
968}
969
970/* mgsl_stop() throttle (stop) transmitter
971 *
972 * Arguments: tty pointer to tty info structure
973 * Return Value: None
974 */
975static void mgsl_stop(struct tty_struct *tty)
976{
c9f19e96 977 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 978 unsigned long flags;
979
980 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
981 return;
982
983 if ( debug_level >= DEBUG_LEVEL_INFO )
984 printk("mgsl_stop(%s)\n",info->device_name);
985
986 spin_lock_irqsave(&info->irq_spinlock,flags);
987 if (info->tx_enabled)
988 usc_stop_transmitter(info);
989 spin_unlock_irqrestore(&info->irq_spinlock,flags);
990
991} /* end of mgsl_stop() */
992
993/* mgsl_start() release (start) transmitter
994 *
995 * Arguments: tty pointer to tty info structure
996 * Return Value: None
997 */
998static void mgsl_start(struct tty_struct *tty)
999{
c9f19e96 1000 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 1001 unsigned long flags;
1002
1003 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1004 return;
1005
1006 if ( debug_level >= DEBUG_LEVEL_INFO )
1007 printk("mgsl_start(%s)\n",info->device_name);
1008
1009 spin_lock_irqsave(&info->irq_spinlock,flags);
1010 if (!info->tx_enabled)
1011 usc_start_transmitter(info);
1012 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1013
1014} /* end of mgsl_start() */
1015
1016/*
1017 * Bottom half work queue access functions
1018 */
1019
1020/* mgsl_bh_action() Return next bottom half action to perform.
1021 * Return Value: BH action code or 0 if nothing to do.
1022 */
1023static int mgsl_bh_action(struct mgsl_struct *info)
1024{
1025 unsigned long flags;
1026 int rc = 0;
1027
1028 spin_lock_irqsave(&info->irq_spinlock,flags);
1029
1030 if (info->pending_bh & BH_RECEIVE) {
1031 info->pending_bh &= ~BH_RECEIVE;
1032 rc = BH_RECEIVE;
1033 } else if (info->pending_bh & BH_TRANSMIT) {
1034 info->pending_bh &= ~BH_TRANSMIT;
1035 rc = BH_TRANSMIT;
1036 } else if (info->pending_bh & BH_STATUS) {
1037 info->pending_bh &= ~BH_STATUS;
1038 rc = BH_STATUS;
1039 }
1040
1041 if (!rc) {
1042 /* Mark BH routine as complete */
0fab6de0
JP		 1043 info->bh_running = false;
1044 info->bh_requested = false;
1da177e4
LT		 1045 }
1046
1047 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1048
1049 return rc;
1050}
1051
1052/*
1053 * Perform bottom half processing of work items queued by ISR.
1054 */
c4028958 1055static void mgsl_bh_handler(struct work_struct *work)
1da177e4 1056{
c4028958
DH		 1057 struct mgsl_struct *info =
1058 container_of(work, struct mgsl_struct, task);
1da177e4
LT		 1059 int action;
1060
1da177e4
LT		 1061 if ( debug_level >= DEBUG_LEVEL_BH )
1062 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1063 __FILE__,__LINE__,info->device_name);
1064
0fab6de0 1065 info->bh_running = true;
1da177e4
LT		 1066
1067 while((action = mgsl_bh_action(info)) != 0) {
1068
1069 /* Process work item */
1070 if ( debug_level >= DEBUG_LEVEL_BH )
1071 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1072 __FILE__,__LINE__,action);
1073
1074 switch (action) {
1075
1076 case BH_RECEIVE:
1077 mgsl_bh_receive(info);
1078 break;
1079 case BH_TRANSMIT:
1080 mgsl_bh_transmit(info);
1081 break;
1082 case BH_STATUS:
1083 mgsl_bh_status(info);
1084 break;
1085 default:
1086 /* unknown work item ID */
1087 printk("Unknown work item ID=%08X!\n", action);
1088 break;
1089 }
1090 }
1091
1092 if ( debug_level >= DEBUG_LEVEL_BH )
1093 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1094 __FILE__,__LINE__,info->device_name);
1095}
1096
1097static void mgsl_bh_receive(struct mgsl_struct *info)
1098{
0fab6de0 1099 bool (*get_rx_frame)(struct mgsl_struct *info) =
1da177e4
LT		 1100 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1101
1102 if ( debug_level >= DEBUG_LEVEL_BH )
1103 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1104 __FILE__,__LINE__,info->device_name);
1105
1106 do
1107 {
1108 if (info->rx_rcc_underrun) {
1109 unsigned long flags;
1110 spin_lock_irqsave(&info->irq_spinlock,flags);
1111 usc_start_receiver(info);
1112 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1113 return;
1114 }
1115 } while(get_rx_frame(info));
1116}
1117
1118static void mgsl_bh_transmit(struct mgsl_struct *info)
1119{
8fb06c77 1120 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 1121 unsigned long flags;
1122
1123 if ( debug_level >= DEBUG_LEVEL_BH )
1124 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1125 __FILE__,__LINE__,info->device_name);
1126
b963a844 1127 if (tty)
1da177e4 1128 tty_wakeup(tty);
1da177e4
LT		 1129
1130 /* if transmitter idle and loopmode_send_done_requested
1131 * then start echoing RxD to TxD
1132 */
1133 spin_lock_irqsave(&info->irq_spinlock,flags);
1134 if ( !info->tx_active && info->loopmode_send_done_requested )
1135 usc_loopmode_send_done( info );
1136 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1137}
1138
1139static void mgsl_bh_status(struct mgsl_struct *info)
1140{
1141 if ( debug_level >= DEBUG_LEVEL_BH )
1142 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1143 __FILE__,__LINE__,info->device_name);
1144
1145 info->ri_chkcount = 0;
1146 info->dsr_chkcount = 0;
1147 info->dcd_chkcount = 0;
1148 info->cts_chkcount = 0;
1149}
1150
1151/* mgsl_isr_receive_status()
1152 *
1153 * Service a receive status interrupt. The type of status
1154 * interrupt is indicated by the state of the RCSR.
1155 * This is only used for HDLC mode.
1156 *
1157 * Arguments: info pointer to device instance data
1158 * Return Value: None
1159 */
1160static void mgsl_isr_receive_status( struct mgsl_struct *info )
1161{
1162 u16 status = usc_InReg( info, RCSR );
1163
e06922aa 1164 if ( debug_level >= DEBUG_LEVEL_ISR )
1da177e4
LT		 1165 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1166 __FILE__,__LINE__,status);
1167
1168 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1169 info->loopmode_insert_requested &&
1170 usc_loopmode_active(info) )
1171 {
1172 ++info->icount.rxabort;
0fab6de0 1173 info->loopmode_insert_requested = false;
1da177e4
LT		 1174
1175 /* clear CMR:13 to start echoing RxD to TxD */
1176 info->cmr_value &= ~BIT13;
1177 usc_OutReg(info, CMR, info->cmr_value);
1178
1179 /* disable received abort irq (no longer required) */
1180 usc_OutReg(info, RICR,
1181 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1182 }
1183
e06922aa 1184 if (status & (RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED)) {
1da177e4
LT		 1185 if (status & RXSTATUS_EXITED_HUNT)
1186 info->icount.exithunt++;
1187 if (status & RXSTATUS_IDLE_RECEIVED)
1188 info->icount.rxidle++;
1189 wake_up_interruptible(&info->event_wait_q);
1190 }
1191
1192 if (status & RXSTATUS_OVERRUN){
1193 info->icount.rxover++;
1194 usc_process_rxoverrun_sync( info );
1195 }
1196
1197 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1198 usc_UnlatchRxstatusBits( info, status );
1199
1200} /* end of mgsl_isr_receive_status() */
1201
1202/* mgsl_isr_transmit_status()
1203 *
1204 * Service a transmit status interrupt
1205 * HDLC mode :end of transmit frame
1206 * Async mode:all data is sent
1207 * transmit status is indicated by bits in the TCSR.
1208 *
1209 * Arguments: info pointer to device instance data
1210 * Return Value: None
1211 */
1212static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1213{
1214 u16 status = usc_InReg( info, TCSR );
1215
1216 if ( debug_level >= DEBUG_LEVEL_ISR )
1217 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1218 __FILE__,__LINE__,status);
1219
1220 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1221 usc_UnlatchTxstatusBits( info, status );
1222
1223 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1224 {
1225 /* finished sending HDLC abort. This may leave */
1226 /* the TxFifo with data from the aborted frame */
1227 /* so purge the TxFifo. Also shutdown the DMA */
1228 /* channel in case there is data remaining in */
1229 /* the DMA buffer */
1230 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1231 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1232 }
1233
1234 if ( status & TXSTATUS_EOF_SENT )
1235 info->icount.txok++;
1236 else if ( status & TXSTATUS_UNDERRUN )
1237 info->icount.txunder++;
1238 else if ( status & TXSTATUS_ABORT_SENT )
1239 info->icount.txabort++;
1240 else
1241 info->icount.txunder++;
1242
0fab6de0 1243 info->tx_active = false;
1da177e4
LT		 1244 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1245 del_timer(&info->tx_timer);
1246
1247 if ( info->drop_rts_on_tx_done ) {
1248 usc_get_serial_signals( info );
1249 if ( info->serial_signals & SerialSignal_RTS ) {
1250 info->serial_signals &= ~SerialSignal_RTS;
1251 usc_set_serial_signals( info );
1252 }
0fab6de0 1253 info->drop_rts_on_tx_done = false;
1da177e4
LT		 1254 }
1255
af69c7f9 1256#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 1257 if (info->netcount)
1258 hdlcdev_tx_done(info);
1259 else
1260#endif
1261 {
8fb06c77 1262 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1da177e4
LT		 1263 usc_stop_transmitter(info);
1264 return;
1265 }
1266 info->pending_bh |= BH_TRANSMIT;
1267 }
1268
1269} /* end of mgsl_isr_transmit_status() */
1270
1271/* mgsl_isr_io_pin()
1272 *
1273 * Service an Input/Output pin interrupt. The type of
1274 * interrupt is indicated by bits in the MISR
1275 *
1276 * Arguments: info pointer to device instance data
1277 * Return Value: None
1278 */
1279static void mgsl_isr_io_pin( struct mgsl_struct *info )
1280{
1281 struct mgsl_icount *icount;
1282 u16 status = usc_InReg( info, MISR );
1283
1284 if ( debug_level >= DEBUG_LEVEL_ISR )
1285 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1286 __FILE__,__LINE__,status);
1287
1288 usc_ClearIrqPendingBits( info, IO_PIN );
1289 usc_UnlatchIostatusBits( info, status );
1290
1291 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1292 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1293 icount = &info->icount;
1294 /* update input line counters */
1295 if (status & MISCSTATUS_RI_LATCHED) {
1296 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1297 usc_DisablestatusIrqs(info,SICR_RI);
1298 icount->rng++;
1299 if ( status & MISCSTATUS_RI )
1300 info->input_signal_events.ri_up++;
1301 else
1302 info->input_signal_events.ri_down++;
1303 }
1304 if (status & MISCSTATUS_DSR_LATCHED) {
1305 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1306 usc_DisablestatusIrqs(info,SICR_DSR);
1307 icount->dsr++;
1308 if ( status & MISCSTATUS_DSR )
1309 info->input_signal_events.dsr_up++;
1310 else
1311 info->input_signal_events.dsr_down++;
1312 }
1313 if (status & MISCSTATUS_DCD_LATCHED) {
1314 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1315 usc_DisablestatusIrqs(info,SICR_DCD);
1316 icount->dcd++;
1317 if (status & MISCSTATUS_DCD) {
1318 info->input_signal_events.dcd_up++;
1319 } else
1320 info->input_signal_events.dcd_down++;
af69c7f9 1321#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 1322 if (info->netcount) {
1323 if (status & MISCSTATUS_DCD)
1324 netif_carrier_on(info->netdev);
1325 else
1326 netif_carrier_off(info->netdev);
1327 }
1da177e4
LT		 1328#endif
1329 }
1330 if (status & MISCSTATUS_CTS_LATCHED)
1331 {
1332 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1333 usc_DisablestatusIrqs(info,SICR_CTS);
1334 icount->cts++;
1335 if ( status & MISCSTATUS_CTS )
1336 info->input_signal_events.cts_up++;
1337 else
1338 info->input_signal_events.cts_down++;
1339 }
1340 wake_up_interruptible(&info->status_event_wait_q);
1341 wake_up_interruptible(&info->event_wait_q);
1342
8fb06c77 1343 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1da177e4
LT		 1344 (status & MISCSTATUS_DCD_LATCHED) ) {
1345 if ( debug_level >= DEBUG_LEVEL_ISR )
1346 printk("%s CD now %s...", info->device_name,
1347 (status & MISCSTATUS_DCD) ? "on" : "off");
1348 if (status & MISCSTATUS_DCD)
8fb06c77 1349 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1350 else {
1351 if ( debug_level >= DEBUG_LEVEL_ISR )
1352 printk("doing serial hangup...");
8fb06c77
AC		 1353 if (info->port.tty)
1354 tty_hangup(info->port.tty);
1da177e4
LT		 1355 }
1356 }
1357
f21ec3d2 1358 if (tty_port_cts_enabled(&info->port) &&
1da177e4 1359 (status & MISCSTATUS_CTS_LATCHED) ) {
8fb06c77 1360 if (info->port.tty->hw_stopped) {
1da177e4
LT		 1361 if (status & MISCSTATUS_CTS) {
1362 if ( debug_level >= DEBUG_LEVEL_ISR )
1363 printk("CTS tx start...");
8fb06c77
AC		 1364 if (info->port.tty)
1365 info->port.tty->hw_stopped = 0;
1da177e4
LT		 1366 usc_start_transmitter(info);
1367 info->pending_bh |= BH_TRANSMIT;
1368 return;
1369 }
1370 } else {
1371 if (!(status & MISCSTATUS_CTS)) {
1372 if ( debug_level >= DEBUG_LEVEL_ISR )
1373 printk("CTS tx stop...");
8fb06c77
AC		 1374 if (info->port.tty)
1375 info->port.tty->hw_stopped = 1;
1da177e4
LT		 1376 usc_stop_transmitter(info);
1377 }
1378 }
1379 }
1380 }
1381
1382 info->pending_bh |= BH_STATUS;
1383
1384 /* for diagnostics set IRQ flag */
1385 if ( status & MISCSTATUS_TXC_LATCHED ){
1386 usc_OutReg( info, SICR,
1387 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1388 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
0fab6de0 1389 info->irq_occurred = true;
1da177e4
LT		 1390 }
1391
1392} /* end of mgsl_isr_io_pin() */
1393
1394/* mgsl_isr_transmit_data()
1395 *
1396 * Service a transmit data interrupt (async mode only).
1397 *
1398 * Arguments: info pointer to device instance data
1399 * Return Value: None
1400 */
1401static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1402{
1403 if ( debug_level >= DEBUG_LEVEL_ISR )
1404 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1405 __FILE__,__LINE__,info->xmit_cnt);
1406
1407 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1408
8fb06c77 1409 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1da177e4
LT		 1410 usc_stop_transmitter(info);
1411 return;
1412 }
1413
1414 if ( info->xmit_cnt )
1415 usc_load_txfifo( info );
1416 else
0fab6de0 1417 info->tx_active = false;
1da177e4
LT		 1418
1419 if (info->xmit_cnt < WAKEUP_CHARS)
1420 info->pending_bh |= BH_TRANSMIT;
1421
1422} /* end of mgsl_isr_transmit_data() */
1423
1424/* mgsl_isr_receive_data()
1425 *
1426 * Service a receive data interrupt. This occurs
1427 * when operating in asynchronous interrupt transfer mode.
1428 * The receive data FIFO is flushed to the receive data buffers.
1429 *
1430 * Arguments: info pointer to device instance data
1431 * Return Value: None
1432 */
1433static void mgsl_isr_receive_data( struct mgsl_struct *info )
1434{
1435 int Fifocount;
1436 u16 status;
33f0f88f 1437 int work = 0;
1da177e4 1438 unsigned char DataByte;
1da177e4
LT		 1439 struct mgsl_icount *icount = &info->icount;
1440
1441 if ( debug_level >= DEBUG_LEVEL_ISR )
1442 printk("%s(%d):mgsl_isr_receive_data\n",
1443 __FILE__,__LINE__);
1444
1445 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1446
1447 /* select FIFO status for RICR readback */
1448 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1449
1450 /* clear the Wordstatus bit so that status readback */
1451 /* only reflects the status of this byte */
1452 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1453
1454 /* flush the receive FIFO */
1455
1456 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
33f0f88f
AC		 1457 int flag;
1458
1da177e4
LT		 1459 /* read one byte from RxFIFO */
1460 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1461 info->io_base + CCAR );
1462 DataByte = inb( info->io_base + CCAR );
1463
1464 /* get the status of the received byte */
1465 status = usc_InReg(info, RCSR);
e06922aa
AJ		 1466 if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1467 RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) )
1da177e4
LT		 1468 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1469
1da177e4
LT		 1470 icount->rx++;
1471
33f0f88f 1472 flag = 0;
e06922aa
AJ		 1473 if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1474 RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) ) {
1475 printk("rxerr=%04X\n",status);
1da177e4
LT		 1476 /* update error statistics */
1477 if ( status & RXSTATUS_BREAK_RECEIVED ) {
e06922aa 1478 status &= ~(RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR);
1da177e4 1479 icount->brk++;
e06922aa 1480 } else if (status & RXSTATUS_PARITY_ERROR)
1da177e4
LT		 1481 icount->parity++;
1482 else if (status & RXSTATUS_FRAMING_ERROR)
1483 icount->frame++;
1484 else if (status & RXSTATUS_OVERRUN) {
1485 /* must issue purge fifo cmd before */
1486 /* 16C32 accepts more receive chars */
1487 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1488 icount->overrun++;
1489 }
1490
e06922aa 1491 /* discard char if tty control flags say so */
1da177e4
LT		 1492 if (status & info->ignore_status_mask)
1493 continue;
1494
1495 status &= info->read_status_mask;
1496
1497 if (status & RXSTATUS_BREAK_RECEIVED) {
33f0f88f 1498 flag = TTY_BREAK;
8fb06c77 1499 if (info->port.flags & ASYNC_SAK)
2e124b4a 1500 do_SAK(info->port.tty);
1da177e4 1501 } else if (status & RXSTATUS_PARITY_ERROR)
33f0f88f 1502 flag = TTY_PARITY;
1da177e4 1503 else if (status & RXSTATUS_FRAMING_ERROR)
33f0f88f 1504 flag = TTY_FRAME;
1da177e4 1505 } /* end of if (error) */
92a19f9c 1506 tty_insert_flip_char(&info->port, DataByte, flag);
33f0f88f
AC		 1507 if (status & RXSTATUS_OVERRUN) {
1508 /* Overrun is special, since it's
1509 * reported immediately, and doesn't
1510 * affect the current character
1511 */
92a19f9c 1512 work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
33f0f88f 1513 }
1da177e4
LT		 1514 }
1515
1516 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1da177e4
LT		 1517 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1518 __FILE__,__LINE__,icount->rx,icount->brk,
1519 icount->parity,icount->frame,icount->overrun);
1520 }
1521
33f0f88f 1522 if(work)
2e124b4a 1523 tty_flip_buffer_push(&info->port);
1da177e4
LT		 1524}
1525
1526/* mgsl_isr_misc()
1527 *
8dfba4d7 1528 * Service a miscellaneous interrupt source.
1da177e4
LT		 1529 *
1530 * Arguments: info pointer to device extension (instance data)
1531 * Return Value: None
1532 */
1533static void mgsl_isr_misc( struct mgsl_struct *info )
1534{
1535 u16 status = usc_InReg( info, MISR );
1536
1537 if ( debug_level >= DEBUG_LEVEL_ISR )
1538 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1539 __FILE__,__LINE__,status);
1540
1541 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1542 (info->params.mode == MGSL_MODE_HDLC)) {
1543
1544 /* turn off receiver and rx DMA */
1545 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1546 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1547 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
e06922aa
AJ		 1548 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
1549 usc_DisableInterrupts(info, RECEIVE_DATA | RECEIVE_STATUS);
1da177e4
LT		 1550
1551 /* schedule BH handler to restart receiver */
1552 info->pending_bh |= BH_RECEIVE;
0fab6de0 1553 info->rx_rcc_underrun = true;
1da177e4
LT		 1554 }
1555
1556 usc_ClearIrqPendingBits( info, MISC );
1557 usc_UnlatchMiscstatusBits( info, status );
1558
1559} /* end of mgsl_isr_misc() */
1560
1561/* mgsl_isr_null()
1562 *
1563 * Services undefined interrupt vectors from the
1564 * USC. (hence this function SHOULD never be called)
1565 *
1566 * Arguments: info pointer to device extension (instance data)
1567 * Return Value: None
1568 */
1569static void mgsl_isr_null( struct mgsl_struct *info )
1570{
1571
1572} /* end of mgsl_isr_null() */
1573
1574/* mgsl_isr_receive_dma()
1575 *
1576 * Service a receive DMA channel interrupt.
1577 * For this driver there are two sources of receive DMA interrupts
1578 * as identified in the Receive DMA mode Register (RDMR):
1579 *
1580 * BIT3 EOA/EOL End of List, all receive buffers in receive
1581 * buffer list have been filled (no more free buffers
1582 * available). The DMA controller has shut down.
1583 *
1584 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1585 * DMA buffer is terminated in response to completion
1586 * of a good frame or a frame with errors. The status
1587 * of the frame is stored in the buffer entry in the
1588 * list of receive buffer entries.
1589 *
1590 * Arguments: info pointer to device instance data
1591 * Return Value: None
1592 */
1593static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1594{
1595 u16 status;
1596
1597 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
e06922aa 1598 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 );
1da177e4
LT		 1599
1600 /* Read the receive DMA status to identify interrupt type. */
1601 /* This also clears the status bits. */
1602 status = usc_InDmaReg( info, RDMR );
1603
1604 if ( debug_level >= DEBUG_LEVEL_ISR )
1605 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1606 __FILE__,__LINE__,info->device_name,status);
1607
1608 info->pending_bh |= BH_RECEIVE;
1609
1610 if ( status & BIT3 ) {
0fab6de0 1611 info->rx_overflow = true;
1da177e4
LT		 1612 info->icount.buf_overrun++;
1613 }
1614
1615} /* end of mgsl_isr_receive_dma() */
1616
1617/* mgsl_isr_transmit_dma()
1618 *
1619 * This function services a transmit DMA channel interrupt.
1620 *
1621 * For this driver there is one source of transmit DMA interrupts
1622 * as identified in the Transmit DMA Mode Register (TDMR):
1623 *
1624 * BIT2 EOB End of Buffer. This interrupt occurs when a
1625 * transmit DMA buffer has been emptied.
1626 *
1627 * The driver maintains enough transmit DMA buffers to hold at least
1628 * one max frame size transmit frame. When operating in a buffered
1629 * transmit mode, there may be enough transmit DMA buffers to hold at
1630 * least two or more max frame size frames. On an EOB condition,
1631 * determine if there are any queued transmit buffers and copy into
1632 * transmit DMA buffers if we have room.
1633 *
1634 * Arguments: info pointer to device instance data
1635 * Return Value: None
1636 */
1637static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1638{
1639 u16 status;
1640
1641 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
e06922aa 1642 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
1da177e4
LT		 1643
1644 /* Read the transmit DMA status to identify interrupt type. */
1645 /* This also clears the status bits. */
1646
1647 status = usc_InDmaReg( info, TDMR );
1648
1649 if ( debug_level >= DEBUG_LEVEL_ISR )
1650 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1651 __FILE__,__LINE__,info->device_name,status);
1652
1653 if ( status & BIT2 ) {
1654 --info->tx_dma_buffers_used;
1655
1656 /* if there are transmit frames queued,
1657 * try to load the next one
1658 */
1659 if ( load_next_tx_holding_buffer(info) ) {
1660 /* if call returns non-zero value, we have
1661 * at least one free tx holding buffer
1662 */
1663 info->pending_bh |= BH_TRANSMIT;
1664 }
1665 }
1666
1667} /* end of mgsl_isr_transmit_dma() */
1668
1669/* mgsl_interrupt()
1670 *
1671 * Interrupt service routine entry point.
1672 *
1673 * Arguments:
1674 *
1675 * irq interrupt number that caused interrupt
1676 * dev_id device ID supplied during interrupt registration
1da177e4
LT		 1677 *
1678 * Return Value: None
1679 */
a6f97b29 1680static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1da177e4 1681{
a6f97b29 1682 struct mgsl_struct *info = dev_id;
1da177e4
LT		 1683 u16 UscVector;
1684 u16 DmaVector;
1685
1686 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 1687 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1688 __FILE__, __LINE__, info->irq_level);
1da177e4 1689
1da177e4
LT		 1690 spin_lock(&info->irq_spinlock);
1691
1692 for(;;) {
1693 /* Read the interrupt vectors from hardware. */
1694 UscVector = usc_InReg(info, IVR) >> 9;
1695 DmaVector = usc_InDmaReg(info, DIVR);
1696
1697 if ( debug_level >= DEBUG_LEVEL_ISR )
1698 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1699 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1700
1701 if ( !UscVector && !DmaVector )
1702 break;
1703
1704 /* Dispatch interrupt vector */
1705 if ( UscVector )
1706 (*UscIsrTable[UscVector])(info);
1707 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1708 mgsl_isr_transmit_dma(info);
1709 else
1710 mgsl_isr_receive_dma(info);
1711
1712 if ( info->isr_overflow ) {
a6f97b29
JG		 1713 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1714 __FILE__, __LINE__, info->device_name, info->irq_level);
1da177e4
LT		 1715 usc_DisableMasterIrqBit(info);
1716 usc_DisableDmaInterrupts(info,DICR_MASTER);
1717 break;
1718 }
1719 }
1720
1721 /* Request bottom half processing if there's something
1722 * for it to do and the bh is not already running
1723 */
1724
1725 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1726 if ( debug_level >= DEBUG_LEVEL_ISR )
1727 printk("%s(%d):%s queueing bh task.\n",
1728 __FILE__,__LINE__,info->device_name);
1729 schedule_work(&info->task);
0fab6de0 1730 info->bh_requested = true;
1da177e4
LT		 1731 }
1732
1733 spin_unlock(&info->irq_spinlock);
1734
1735 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 1736 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1737 __FILE__, __LINE__, info->irq_level);
1738
1da177e4
LT		 1739 return IRQ_HANDLED;
1740} /* end of mgsl_interrupt() */
1741
1742/* startup()
1743 *
1744 * Initialize and start device.
1745 *
1746 * Arguments: info pointer to device instance data
1747 * Return Value: 0 if success, otherwise error code
1748 */
1749static int startup(struct mgsl_struct * info)
1750{
1751 int retval = 0;
1752
1753 if ( debug_level >= DEBUG_LEVEL_INFO )
1754 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1755
8fb06c77 1756 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4
LT		 1757 return 0;
1758
1759 if (!info->xmit_buf) {
1760 /* allocate a page of memory for a transmit buffer */
1761 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1762 if (!info->xmit_buf) {
1763 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1764 __FILE__,__LINE__,info->device_name);
1765 return -ENOMEM;
1766 }
1767 }
1768
1769 info->pending_bh = 0;
1770
9661239f
PF		 1771 memset(&info->icount, 0, sizeof(info->icount));
1772
40565f19 1773 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1da177e4
LT		 1774
1775 /* Allocate and claim adapter resources */
1776 retval = mgsl_claim_resources(info);
1777
1778 /* perform existence check and diagnostics */
1779 if ( !retval )
1780 retval = mgsl_adapter_test(info);
1781
1782 if ( retval ) {
8fb06c77
AC		 1783 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1784 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 1785 mgsl_release_resources(info);
1786 return retval;
1787 }
1788
1789 /* program hardware for current parameters */
1790 mgsl_change_params(info);
1791
8fb06c77
AC		 1792 if (info->port.tty)
1793 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 1794
8fb06c77 1795 info->port.flags |= ASYNC_INITIALIZED;
1da177e4
LT		 1796
1797 return 0;
1798
1799} /* end of startup() */
1800
1801/* shutdown()
1802 *
1803 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1804 *
1805 * Arguments: info pointer to device instance data
1806 * Return Value: None
1807 */
1808static void shutdown(struct mgsl_struct * info)
1809{
1810 unsigned long flags;
1811
8fb06c77 1812 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 1813 return;
1814
1815 if (debug_level >= DEBUG_LEVEL_INFO)
1816 printk("%s(%d):mgsl_shutdown(%s)\n",
1817 __FILE__,__LINE__, info->device_name );
1818
1819 /* clear status wait queue because status changes */
1820 /* can't happen after shutting down the hardware */
1821 wake_up_interruptible(&info->status_event_wait_q);
1822 wake_up_interruptible(&info->event_wait_q);
1823
40565f19 1824 del_timer_sync(&info->tx_timer);
1da177e4
LT		 1825
1826 if (info->xmit_buf) {
1827 free_page((unsigned long) info->xmit_buf);
1828 info->xmit_buf = NULL;
1829 }
1830
1831 spin_lock_irqsave(&info->irq_spinlock,flags);
1832 usc_DisableMasterIrqBit(info);
1833 usc_stop_receiver(info);
1834 usc_stop_transmitter(info);
e06922aa
AJ		 1835 usc_DisableInterrupts(info,RECEIVE_DATA | RECEIVE_STATUS |
1836 TRANSMIT_DATA | TRANSMIT_STATUS | IO_PIN | MISC );
1da177e4 1837 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
adc8d746 1838
1da177e4
LT		 1839 /* Disable DMAEN (Port 7, Bit 14) */
1840 /* This disconnects the DMA request signal from the ISA bus */
1841 /* on the ISA adapter. This has no effect for the PCI adapter */
1842 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
adc8d746 1843
1da177e4
LT		 1844 /* Disable INTEN (Port 6, Bit12) */
1845 /* This disconnects the IRQ request signal to the ISA bus */
1846 /* on the ISA adapter. This has no effect for the PCI adapter */
1847 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
adc8d746
AC		 1848
1849 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
9fe8074b 1850 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 1851 usc_set_serial_signals(info);
1852 }
adc8d746 1853
1da177e4
LT		 1854 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1855
1856 mgsl_release_resources(info);
1857
8fb06c77
AC		 1858 if (info->port.tty)
1859 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 1860
8fb06c77 1861 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4
LT		 1862
1863} /* end of shutdown() */
1864
1865static void mgsl_program_hw(struct mgsl_struct *info)
1866{
1867 unsigned long flags;
1868
1869 spin_lock_irqsave(&info->irq_spinlock,flags);
1870
1871 usc_stop_receiver(info);
1872 usc_stop_transmitter(info);
1873 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1874
1875 if (info->params.mode == MGSL_MODE_HDLC ||
1876 info->params.mode == MGSL_MODE_RAW ||
1877 info->netcount)
1878 usc_set_sync_mode(info);
1879 else
1880 usc_set_async_mode(info);
1881
1882 usc_set_serial_signals(info);
1883
1884 info->dcd_chkcount = 0;
1885 info->cts_chkcount = 0;
1886 info->ri_chkcount = 0;
1887 info->dsr_chkcount = 0;
1888
e06922aa 1889 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1da177e4
LT		 1890 usc_EnableInterrupts(info, IO_PIN);
1891 usc_get_serial_signals(info);
1892
adc8d746 1893 if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
1da177e4
LT		 1894 usc_start_receiver(info);
1895
1896 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1897}
1898
1899/* Reconfigure adapter based on new parameters
1900 */
1901static void mgsl_change_params(struct mgsl_struct *info)
1902{
1903 unsigned cflag;
1904 int bits_per_char;
1905
adc8d746 1906 if (!info->port.tty)
1da177e4
LT		 1907 return;
1908
1909 if (debug_level >= DEBUG_LEVEL_INFO)
1910 printk("%s(%d):mgsl_change_params(%s)\n",
1911 __FILE__,__LINE__, info->device_name );
1912
adc8d746 1913 cflag = info->port.tty->termios.c_cflag;
1da177e4 1914
9fe8074b
JP		 1915 /* if B0 rate (hangup) specified then negate RTS and DTR */
1916 /* otherwise assert RTS and DTR */
1da177e4 1917 if (cflag & CBAUD)
9fe8074b 1918 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1da177e4 1919 else
9fe8074b 1920 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 1921
1922 /* byte size and parity */
1923
1924 switch (cflag & CSIZE) {
1925 case CS5: info->params.data_bits = 5; break;
1926 case CS6: info->params.data_bits = 6; break;
1927 case CS7: info->params.data_bits = 7; break;
1928 case CS8: info->params.data_bits = 8; break;
1929 /* Never happens, but GCC is too dumb to figure it out */
1930 default: info->params.data_bits = 7; break;
1931 }
1932
1933 if (cflag & CSTOPB)
1934 info->params.stop_bits = 2;
1935 else
1936 info->params.stop_bits = 1;
1937
1938 info->params.parity = ASYNC_PARITY_NONE;
1939 if (cflag & PARENB) {
1940 if (cflag & PARODD)
1941 info->params.parity = ASYNC_PARITY_ODD;
1942 else
1943 info->params.parity = ASYNC_PARITY_EVEN;
1944#ifdef CMSPAR
1945 if (cflag & CMSPAR)
1946 info->params.parity = ASYNC_PARITY_SPACE;
1947#endif
1948 }
1949
1950 /* calculate number of jiffies to transmit a full
1951 * FIFO (32 bytes) at specified data rate
1952 */
1953 bits_per_char = info->params.data_bits +
1954 info->params.stop_bits + 1;
1955
1956 /* if port data rate is set to 460800 or less then
1957 * allow tty settings to override, otherwise keep the
1958 * current data rate.
1959 */
1960 if (info->params.data_rate <= 460800)
8fb06c77 1961 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1da177e4
LT		 1962
1963 if ( info->params.data_rate ) {
1964 info->timeout = (32*HZ*bits_per_char) /
1965 info->params.data_rate;
1966 }
1967 info->timeout += HZ/50; /* Add .02 seconds of slop */
1968
1969 if (cflag & CRTSCTS)
8fb06c77 1970 info->port.flags |= ASYNC_CTS_FLOW;
1da177e4 1971 else
8fb06c77 1972 info->port.flags &= ~ASYNC_CTS_FLOW;
1da177e4
LT		 1973
1974 if (cflag & CLOCAL)
8fb06c77 1975 info->port.flags &= ~ASYNC_CHECK_CD;
1da177e4 1976 else
8fb06c77 1977 info->port.flags |= ASYNC_CHECK_CD;
1da177e4
LT		 1978
1979 /* process tty input control flags */
1980
1981 info->read_status_mask = RXSTATUS_OVERRUN;
8fb06c77 1982 if (I_INPCK(info->port.tty))
1da177e4 1983 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
8fb06c77 1984 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1da177e4
LT		 1985 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1986
8fb06c77 1987 if (I_IGNPAR(info->port.tty))
1da177e4 1988 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
8fb06c77 1989 if (I_IGNBRK(info->port.tty)) {
1da177e4
LT		 1990 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1991 /* If ignoring parity and break indicators, ignore
1992 * overruns too. (For real raw support).
1993 */
8fb06c77 1994 if (I_IGNPAR(info->port.tty))
1da177e4
LT		 1995 info->ignore_status_mask |= RXSTATUS_OVERRUN;
1996 }
1997
1998 mgsl_program_hw(info);
1999
2000} /* end of mgsl_change_params() */
2001
2002/* mgsl_put_char()
2003 *
2004 * Add a character to the transmit buffer.
2005 *
2006 * Arguments: tty pointer to tty information structure
2007 * ch character to add to transmit buffer
2008 *
2009 * Return Value: None
2010 */
55da7789 2011static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 2012{
07648230 2013 struct mgsl_struct *info = tty->driver_data;
1da177e4 2014 unsigned long flags;
07648230 2015 int ret = 0;
1da177e4 2016
07648230 2017 if (debug_level >= DEBUG_LEVEL_INFO) {
5098021e 2018 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
07648230 2019 __FILE__, __LINE__, ch, info->device_name);
1da177e4
LT		 2020 }
2021
2022 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
55da7789 2023 return 0;
1da177e4 2024
ca1cce49 2025 if (!info->xmit_buf)
55da7789 2026 return 0;
1da177e4 2027
07648230 2028 spin_lock_irqsave(&info->irq_spinlock, flags);
1da177e4 2029
07648230 2030 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
1da177e4
LT		 2031 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2032 info->xmit_buf[info->xmit_head++] = ch;
2033 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2034 info->xmit_cnt++;
55da7789 2035 ret = 1;
1da177e4
LT		 2036 }
2037 }
07648230 2038 spin_unlock_irqrestore(&info->irq_spinlock, flags);
55da7789 2039 return ret;
1da177e4
LT		 2040
2041} /* end of mgsl_put_char() */
2042
2043/* mgsl_flush_chars()
2044 *
2045 * Enable transmitter so remaining characters in the
2046 * transmit buffer are sent.
2047 *
2048 * Arguments: tty pointer to tty information structure
2049 * Return Value: None
2050 */
2051static void mgsl_flush_chars(struct tty_struct *tty)
2052{
c9f19e96 2053 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2054 unsigned long flags;
2055
2056 if ( debug_level >= DEBUG_LEVEL_INFO )
2057 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2058 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2059
2060 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2061 return;
2062
2063 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2064 !info->xmit_buf)
2065 return;
2066
2067 if ( debug_level >= DEBUG_LEVEL_INFO )
2068 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2069 __FILE__,__LINE__,info->device_name );
2070
2071 spin_lock_irqsave(&info->irq_spinlock,flags);
2072
2073 if (!info->tx_active) {
2074 if ( (info->params.mode == MGSL_MODE_HDLC ||
2075 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2076 /* operating in synchronous (frame oriented) mode */
2077 /* copy data from circular xmit_buf to */
2078 /* transmit DMA buffer. */
2079 mgsl_load_tx_dma_buffer(info,
2080 info->xmit_buf,info->xmit_cnt);
2081 }
2082 usc_start_transmitter(info);
2083 }
2084
2085 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2086
2087} /* end of mgsl_flush_chars() */
2088
2089/* mgsl_write()
2090 *
2091 * Send a block of data
2092 *
2093 * Arguments:
2094 *
2095 * tty pointer to tty information structure
2096 * buf pointer to buffer containing send data
2097 * count size of send data in bytes
2098 *
2099 * Return Value: number of characters written
2100 */
2101static int mgsl_write(struct tty_struct * tty,
2102 const unsigned char *buf, int count)
2103{
2104 int c, ret = 0;
c9f19e96 2105 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2106 unsigned long flags;
2107
2108 if ( debug_level >= DEBUG_LEVEL_INFO )
2109 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2110 __FILE__,__LINE__,info->device_name,count);
2111
2112 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2113 goto cleanup;
2114
ca1cce49 2115 if (!info->xmit_buf)
1da177e4
LT		 2116 goto cleanup;
2117
2118 if ( info->params.mode == MGSL_MODE_HDLC ||
2119 info->params.mode == MGSL_MODE_RAW ) {
2120 /* operating in synchronous (frame oriented) mode */
1da177e4
LT		 2121 if (info->tx_active) {
2122
2123 if ( info->params.mode == MGSL_MODE_HDLC ) {
2124 ret = 0;
2125 goto cleanup;
2126 }
2127 /* transmitter is actively sending data -
2128 * if we have multiple transmit dma and
2129 * holding buffers, attempt to queue this
2130 * frame for transmission at a later time.
2131 */
2132 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2133 /* no tx holding buffers available */
2134 ret = 0;
2135 goto cleanup;
2136 }
2137
2138 /* queue transmit frame request */
2139 ret = count;
2140 save_tx_buffer_request(info,buf,count);
2141
2142 /* if we have sufficient tx dma buffers,
2143 * load the next buffered tx request
2144 */
2145 spin_lock_irqsave(&info->irq_spinlock,flags);
2146 load_next_tx_holding_buffer(info);
2147 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2148 goto cleanup;
2149 }
2150
2151 /* if operating in HDLC LoopMode and the adapter */
2152 /* has yet to be inserted into the loop, we can't */
2153 /* transmit */
2154
2155 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2156 !usc_loopmode_active(info) )
2157 {
2158 ret = 0;
2159 goto cleanup;
2160 }
2161
2162 if ( info->xmit_cnt ) {
2163 /* Send accumulated from send_char() calls */
2164 /* as frame and wait before accepting more data. */
2165 ret = 0;
2166
2167 /* copy data from circular xmit_buf to */
2168 /* transmit DMA buffer. */
2169 mgsl_load_tx_dma_buffer(info,
2170 info->xmit_buf,info->xmit_cnt);
2171 if ( debug_level >= DEBUG_LEVEL_INFO )
2172 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2173 __FILE__,__LINE__,info->device_name);
2174 } else {
2175 if ( debug_level >= DEBUG_LEVEL_INFO )
2176 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2177 __FILE__,__LINE__,info->device_name);
2178 ret = count;
2179 info->xmit_cnt = count;
2180 mgsl_load_tx_dma_buffer(info,buf,count);
2181 }
2182 } else {
2183 while (1) {
2184 spin_lock_irqsave(&info->irq_spinlock,flags);
2185 c = min_t(int, count,
2186 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2187 SERIAL_XMIT_SIZE - info->xmit_head));
2188 if (c <= 0) {
2189 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2190 break;
2191 }
2192 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2193 info->xmit_head = ((info->xmit_head + c) &
2194 (SERIAL_XMIT_SIZE-1));
2195 info->xmit_cnt += c;
2196 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2197 buf += c;
2198 count -= c;
2199 ret += c;
2200 }
2201 }
2202
2203 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2204 spin_lock_irqsave(&info->irq_spinlock,flags);
2205 if (!info->tx_active)
2206 usc_start_transmitter(info);
2207 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2208 }
2209cleanup:
2210 if ( debug_level >= DEBUG_LEVEL_INFO )
2211 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2212 __FILE__,__LINE__,info->device_name,ret);
2213
2214 return ret;
2215
2216} /* end of mgsl_write() */
2217
2218/* mgsl_write_room()
2219 *
2220 * Return the count of free bytes in transmit buffer
2221 *
2222 * Arguments: tty pointer to tty info structure
2223 * Return Value: None
2224 */
2225static int mgsl_write_room(struct tty_struct *tty)
2226{
c9f19e96 2227 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2228 int ret;
2229
2230 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2231 return 0;
2232 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2233 if (ret < 0)
2234 ret = 0;
2235
2236 if (debug_level >= DEBUG_LEVEL_INFO)
2237 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2238 __FILE__,__LINE__, info->device_name,ret );
2239
2240 if ( info->params.mode == MGSL_MODE_HDLC ||
2241 info->params.mode == MGSL_MODE_RAW ) {
2242 /* operating in synchronous (frame oriented) mode */
2243 if ( info->tx_active )
2244 return 0;
2245 else
2246 return HDLC_MAX_FRAME_SIZE;
2247 }
2248
2249 return ret;
2250
2251} /* end of mgsl_write_room() */
2252
2253/* mgsl_chars_in_buffer()
2254 *
2255 * Return the count of bytes in transmit buffer
2256 *
2257 * Arguments: tty pointer to tty info structure
2258 * Return Value: None
2259 */
2260static int mgsl_chars_in_buffer(struct tty_struct *tty)
2261{
c9f19e96 2262 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2263
2264 if (debug_level >= DEBUG_LEVEL_INFO)
2265 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2266 __FILE__,__LINE__, info->device_name );
2267
2268 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2269 return 0;
2270
2271 if (debug_level >= DEBUG_LEVEL_INFO)
2272 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2273 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2274
2275 if ( info->params.mode == MGSL_MODE_HDLC ||
2276 info->params.mode == MGSL_MODE_RAW ) {
2277 /* operating in synchronous (frame oriented) mode */
2278 if ( info->tx_active )
2279 return info->max_frame_size;
2280 else
2281 return 0;
2282 }
2283
2284 return info->xmit_cnt;
2285} /* end of mgsl_chars_in_buffer() */
2286
2287/* mgsl_flush_buffer()
2288 *
2289 * Discard all data in the send buffer
2290 *
2291 * Arguments: tty pointer to tty info structure
2292 * Return Value: None
2293 */
2294static void mgsl_flush_buffer(struct tty_struct *tty)
2295{
c9f19e96 2296 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2297 unsigned long flags;
2298
2299 if (debug_level >= DEBUG_LEVEL_INFO)
2300 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2301 __FILE__,__LINE__, info->device_name );
2302
2303 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2304 return;
2305
2306 spin_lock_irqsave(&info->irq_spinlock,flags);
2307 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2308 del_timer(&info->tx_timer);
2309 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2310
1da177e4
LT		 2311 tty_wakeup(tty);
2312}
2313
2314/* mgsl_send_xchar()
2315 *
2316 * Send a high-priority XON/XOFF character
2317 *
2318 * Arguments: tty pointer to tty info structure
2319 * ch character to send
2320 * Return Value: None
2321 */
2322static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2323{
c9f19e96 2324 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2325 unsigned long flags;
2326
2327 if (debug_level >= DEBUG_LEVEL_INFO)
2328 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2329 __FILE__,__LINE__, info->device_name, ch );
2330
2331 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2332 return;
2333
2334 info->x_char = ch;
2335 if (ch) {
2336 /* Make sure transmit interrupts are on */
2337 spin_lock_irqsave(&info->irq_spinlock,flags);
2338 if (!info->tx_enabled)
2339 usc_start_transmitter(info);
2340 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2341 }
2342} /* end of mgsl_send_xchar() */
2343
2344/* mgsl_throttle()
2345 *
2346 * Signal remote device to throttle send data (our receive data)
2347 *
2348 * Arguments: tty pointer to tty info structure
2349 * Return Value: None
2350 */
2351static void mgsl_throttle(struct tty_struct * tty)
2352{
c9f19e96 2353 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2354 unsigned long flags;
2355
2356 if (debug_level >= DEBUG_LEVEL_INFO)
2357 printk("%s(%d):mgsl_throttle(%s) entry\n",
2358 __FILE__,__LINE__, info->device_name );
2359
2360 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2361 return;
2362
2363 if (I_IXOFF(tty))
2364 mgsl_send_xchar(tty, STOP_CHAR(tty));
adc8d746
AC		 2365
2366 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 2367 spin_lock_irqsave(&info->irq_spinlock,flags);
2368 info->serial_signals &= ~SerialSignal_RTS;
2369 usc_set_serial_signals(info);
2370 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2371 }
2372} /* end of mgsl_throttle() */
2373
2374/* mgsl_unthrottle()
2375 *
2376 * Signal remote device to stop throttling send data (our receive data)
2377 *
2378 * Arguments: tty pointer to tty info structure
2379 * Return Value: None
2380 */
2381static void mgsl_unthrottle(struct tty_struct * tty)
2382{
c9f19e96 2383 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2384 unsigned long flags;
2385
2386 if (debug_level >= DEBUG_LEVEL_INFO)
2387 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2388 __FILE__,__LINE__, info->device_name );
2389
2390 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2391 return;
2392
2393 if (I_IXOFF(tty)) {
2394 if (info->x_char)
2395 info->x_char = 0;
2396 else
2397 mgsl_send_xchar(tty, START_CHAR(tty));
2398 }
adc8d746
AC		 2399
2400 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 2401 spin_lock_irqsave(&info->irq_spinlock,flags);
2402 info->serial_signals |= SerialSignal_RTS;
2403 usc_set_serial_signals(info);
2404 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2405 }
2406
2407} /* end of mgsl_unthrottle() */
2408
2409/* mgsl_get_stats()
2410 *
2411 * get the current serial parameters information
2412 *
2413 * Arguments: info pointer to device instance data
2414 * user_icount pointer to buffer to hold returned stats
2415 *
2416 * Return Value: 0 if success, otherwise error code
2417 */
2418static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2419{
2420 int err;
2421
2422 if (debug_level >= DEBUG_LEVEL_INFO)
2423 printk("%s(%d):mgsl_get_params(%s)\n",
2424 __FILE__,__LINE__, info->device_name);
2425
9661239f
PF		 2426 if (!user_icount) {
2427 memset(&info->icount, 0, sizeof(info->icount));
2428 } else {
f602501d 2429 mutex_lock(&info->port.mutex);
9661239f 2430 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
f602501d 2431 mutex_unlock(&info->port.mutex);
9661239f
PF		 2432 if (err)
2433 return -EFAULT;
1da177e4
LT		 2434 }
2435
2436 return 0;
2437
2438} /* end of mgsl_get_stats() */
2439
2440/* mgsl_get_params()
2441 *
2442 * get the current serial parameters information
2443 *
2444 * Arguments: info pointer to device instance data
2445 * user_params pointer to buffer to hold returned params
2446 *
2447 * Return Value: 0 if success, otherwise error code
2448 */
2449static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2450{
2451 int err;
2452 if (debug_level >= DEBUG_LEVEL_INFO)
2453 printk("%s(%d):mgsl_get_params(%s)\n",
2454 __FILE__,__LINE__, info->device_name);
2455
f602501d 2456 mutex_lock(&info->port.mutex);
1da177e4 2457 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
f602501d 2458 mutex_unlock(&info->port.mutex);
1da177e4
LT		 2459 if (err) {
2460 if ( debug_level >= DEBUG_LEVEL_INFO )
2461 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2462 __FILE__,__LINE__,info->device_name);
2463 return -EFAULT;
2464 }
2465
2466 return 0;
2467
2468} /* end of mgsl_get_params() */
2469
2470/* mgsl_set_params()
2471 *
2472 * set the serial parameters
2473 *
2474 * Arguments:
2475 *
2476 * info pointer to device instance data
2477 * new_params user buffer containing new serial params
2478 *
2479 * Return Value: 0 if success, otherwise error code
2480 */
2481static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2482{
2483 unsigned long flags;
2484 MGSL_PARAMS tmp_params;
2485 int err;
2486
2487 if (debug_level >= DEBUG_LEVEL_INFO)
2488 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2489 info->device_name );
2490 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2491 if (err) {
2492 if ( debug_level >= DEBUG_LEVEL_INFO )
2493 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2494 __FILE__,__LINE__,info->device_name);
2495 return -EFAULT;
2496 }
2497
f602501d 2498 mutex_lock(&info->port.mutex);
1da177e4
LT		 2499 spin_lock_irqsave(&info->irq_spinlock,flags);
2500 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2501 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2502
2503 mgsl_change_params(info);
f602501d 2504 mutex_unlock(&info->port.mutex);
1da177e4
LT		 2505
2506 return 0;
2507
2508} /* end of mgsl_set_params() */
2509
2510/* mgsl_get_txidle()
2511 *
2512 * get the current transmit idle mode
2513 *
2514 * Arguments: info pointer to device instance data
2515 * idle_mode pointer to buffer to hold returned idle mode
2516 *
2517 * Return Value: 0 if success, otherwise error code
2518 */
2519static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2520{
2521 int err;
2522
2523 if (debug_level >= DEBUG_LEVEL_INFO)
2524 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2525 __FILE__,__LINE__, info->device_name, info->idle_mode);
2526
2527 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2528 if (err) {
2529 if ( debug_level >= DEBUG_LEVEL_INFO )
2530 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2531 __FILE__,__LINE__,info->device_name);
2532 return -EFAULT;
2533 }
2534
2535 return 0;
2536
2537} /* end of mgsl_get_txidle() */
2538
2539/* mgsl_set_txidle() service ioctl to set transmit idle mode
2540 *
2541 * Arguments: info pointer to device instance data
2542 * idle_mode new idle mode
2543 *
2544 * Return Value: 0 if success, otherwise error code
2545 */
2546static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2547{
2548 unsigned long flags;
2549
2550 if (debug_level >= DEBUG_LEVEL_INFO)
2551 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2552 info->device_name, idle_mode );
2553
2554 spin_lock_irqsave(&info->irq_spinlock,flags);
2555 info->idle_mode = idle_mode;
2556 usc_set_txidle( info );
2557 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2558 return 0;
2559
2560} /* end of mgsl_set_txidle() */
2561
2562/* mgsl_txenable()
2563 *
2564 * enable or disable the transmitter
2565 *
2566 * Arguments:
2567 *
2568 * info pointer to device instance data
2569 * enable 1 = enable, 0 = disable
2570 *
2571 * Return Value: 0 if success, otherwise error code
2572 */
2573static int mgsl_txenable(struct mgsl_struct * info, int enable)
2574{
2575 unsigned long flags;
2576
2577 if (debug_level >= DEBUG_LEVEL_INFO)
2578 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2579 info->device_name, enable);
2580
2581 spin_lock_irqsave(&info->irq_spinlock,flags);
2582 if ( enable ) {
2583 if ( !info->tx_enabled ) {
2584
2585 usc_start_transmitter(info);
2586 /*--------------------------------------------------
2587 * if HDLC/SDLC Loop mode, attempt to insert the
2588 * station in the 'loop' by setting CMR:13. Upon
2589 * receipt of the next GoAhead (RxAbort) sequence,
2590 * the OnLoop indicator (CCSR:7) should go active
2591 * to indicate that we are on the loop
2592 *--------------------------------------------------*/
2593 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2594 usc_loopmode_insert_request( info );
2595 }
2596 } else {
2597 if ( info->tx_enabled )
2598 usc_stop_transmitter(info);
2599 }
2600 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2601 return 0;
2602
2603} /* end of mgsl_txenable() */
2604
2605/* mgsl_txabort() abort send HDLC frame
2606 *
2607 * Arguments: info pointer to device instance data
2608 * Return Value: 0 if success, otherwise error code
2609 */
2610static int mgsl_txabort(struct mgsl_struct * info)
2611{
2612 unsigned long flags;
2613
2614 if (debug_level >= DEBUG_LEVEL_INFO)
2615 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2616 info->device_name);
2617
2618 spin_lock_irqsave(&info->irq_spinlock,flags);
2619 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2620 {
2621 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2622 usc_loopmode_cancel_transmit( info );
2623 else
2624 usc_TCmd(info,TCmd_SendAbort);
2625 }
2626 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2627 return 0;
2628
2629} /* end of mgsl_txabort() */
2630
2631/* mgsl_rxenable() enable or disable the receiver
2632 *
2633 * Arguments: info pointer to device instance data
2634 * enable 1 = enable, 0 = disable
2635 * Return Value: 0 if success, otherwise error code
2636 */
2637static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2638{
2639 unsigned long flags;
2640
2641 if (debug_level >= DEBUG_LEVEL_INFO)
2642 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2643 info->device_name, enable);
2644
2645 spin_lock_irqsave(&info->irq_spinlock,flags);
2646 if ( enable ) {
2647 if ( !info->rx_enabled )
2648 usc_start_receiver(info);
2649 } else {
2650 if ( info->rx_enabled )
2651 usc_stop_receiver(info);
2652 }
2653 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2654 return 0;
2655
2656} /* end of mgsl_rxenable() */
2657
2658/* mgsl_wait_event() wait for specified event to occur
2659 *
2660 * Arguments: info pointer to device instance data
2661 * mask pointer to bitmask of events to wait for
2662 * Return Value: 0 if successful and bit mask updated with
2663 * of events triggerred,
2664 * otherwise error code
2665 */
2666static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2667{
2668 unsigned long flags;
2669 int s;
2670 int rc=0;
2671 struct mgsl_icount cprev, cnow;
2672 int events;
2673 int mask;
2674 struct _input_signal_events oldsigs, newsigs;
2675 DECLARE_WAITQUEUE(wait, current);
2676
2677 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2678 if (rc) {
2679 return -EFAULT;
2680 }
2681
2682 if (debug_level >= DEBUG_LEVEL_INFO)
2683 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2684 info->device_name, mask);
2685
2686 spin_lock_irqsave(&info->irq_spinlock,flags);
2687
2688 /* return immediately if state matches requested events */
2689 usc_get_serial_signals(info);
2690 s = info->serial_signals;
2691 events = mask &
2692 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2693 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2694 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2695 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2696 if (events) {
2697 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2698 goto exit;
2699 }
2700
2701 /* save current irq counts */
2702 cprev = info->icount;
2703 oldsigs = info->input_signal_events;
2704
2705 /* enable hunt and idle irqs if needed */
2706 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2707 u16 oldreg = usc_InReg(info,RICR);
2708 u16 newreg = oldreg +
2709 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2710 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2711 if (oldreg != newreg)
2712 usc_OutReg(info, RICR, newreg);
2713 }
2714
2715 set_current_state(TASK_INTERRUPTIBLE);
2716 add_wait_queue(&info->event_wait_q, &wait);
2717
2718 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2719
2720
2721 for(;;) {
2722 schedule();
2723 if (signal_pending(current)) {
2724 rc = -ERESTARTSYS;
2725 break;
2726 }
2727
2728 /* get current irq counts */
2729 spin_lock_irqsave(&info->irq_spinlock,flags);
2730 cnow = info->icount;
2731 newsigs = info->input_signal_events;
2732 set_current_state(TASK_INTERRUPTIBLE);
2733 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2734
2735 /* if no change, wait aborted for some reason */
2736 if (newsigs.dsr_up == oldsigs.dsr_up &&
2737 newsigs.dsr_down == oldsigs.dsr_down &&
2738 newsigs.dcd_up == oldsigs.dcd_up &&
2739 newsigs.dcd_down == oldsigs.dcd_down &&
2740 newsigs.cts_up == oldsigs.cts_up &&
2741 newsigs.cts_down == oldsigs.cts_down &&
2742 newsigs.ri_up == oldsigs.ri_up &&
2743 newsigs.ri_down == oldsigs.ri_down &&
2744 cnow.exithunt == cprev.exithunt &&
2745 cnow.rxidle == cprev.rxidle) {
2746 rc = -EIO;
2747 break;
2748 }
2749
2750 events = mask &
2751 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2752 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2753 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2754 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2755 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2756 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2757 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2758 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2759 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2760 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2761 if (events)
2762 break;
2763
2764 cprev = cnow;
2765 oldsigs = newsigs;
2766 }
2767
2768 remove_wait_queue(&info->event_wait_q, &wait);
2769 set_current_state(TASK_RUNNING);
2770
2771 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2772 spin_lock_irqsave(&info->irq_spinlock,flags);
2773 if (!waitqueue_active(&info->event_wait_q)) {
2774 /* disable enable exit hunt mode/idle rcvd IRQs */
2775 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
e06922aa 2776 ~(RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED));
1da177e4
LT		 2777 }
2778 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2779 }
2780exit:
2781 if ( rc == 0 )
2782 PUT_USER(rc, events, mask_ptr);
2783
2784 return rc;
2785
2786} /* end of mgsl_wait_event() */
2787
2788static int modem_input_wait(struct mgsl_struct *info,int arg)
2789{
2790 unsigned long flags;
2791 int rc;
2792 struct mgsl_icount cprev, cnow;
2793 DECLARE_WAITQUEUE(wait, current);
2794
2795 /* save current irq counts */
2796 spin_lock_irqsave(&info->irq_spinlock,flags);
2797 cprev = info->icount;
2798 add_wait_queue(&info->status_event_wait_q, &wait);
2799 set_current_state(TASK_INTERRUPTIBLE);
2800 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2801
2802 for(;;) {
2803 schedule();
2804 if (signal_pending(current)) {
2805 rc = -ERESTARTSYS;
2806 break;
2807 }
2808
2809 /* get new irq counts */
2810 spin_lock_irqsave(&info->irq_spinlock,flags);
2811 cnow = info->icount;
2812 set_current_state(TASK_INTERRUPTIBLE);
2813 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2814
2815 /* if no change, wait aborted for some reason */
2816 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2817 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2818 rc = -EIO;
2819 break;
2820 }
2821
2822 /* check for change in caller specified modem input */
2823 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2824 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2825 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2826 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2827 rc = 0;
2828 break;
2829 }
2830
2831 cprev = cnow;
2832 }
2833 remove_wait_queue(&info->status_event_wait_q, &wait);
2834 set_current_state(TASK_RUNNING);
2835 return rc;
2836}
2837
2838/* return the state of the serial control and status signals
2839 */
60b33c13 2840static int tiocmget(struct tty_struct *tty)
1da177e4 2841{
c9f19e96 2842 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2843 unsigned int result;
2844 unsigned long flags;
2845
2846 spin_lock_irqsave(&info->irq_spinlock,flags);
2847 usc_get_serial_signals(info);
2848 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2849
2850 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2851 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2852 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2853 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2854 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2855 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2856
2857 if (debug_level >= DEBUG_LEVEL_INFO)
2858 printk("%s(%d):%s tiocmget() value=%08X\n",
2859 __FILE__,__LINE__, info->device_name, result );
2860 return result;
2861}
2862
2863/* set modem control signals (DTR/RTS)
2864 */
20b9d177
AC		 2865static int tiocmset(struct tty_struct *tty,
2866 unsigned int set, unsigned int clear)
1da177e4 2867{
c9f19e96 2868 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2869 unsigned long flags;
2870
2871 if (debug_level >= DEBUG_LEVEL_INFO)
2872 printk("%s(%d):%s tiocmset(%x,%x)\n",
2873 __FILE__,__LINE__,info->device_name, set, clear);
2874
2875 if (set & TIOCM_RTS)
2876 info->serial_signals |= SerialSignal_RTS;
2877 if (set & TIOCM_DTR)
2878 info->serial_signals |= SerialSignal_DTR;
2879 if (clear & TIOCM_RTS)
2880 info->serial_signals &= ~SerialSignal_RTS;
2881 if (clear & TIOCM_DTR)
2882 info->serial_signals &= ~SerialSignal_DTR;
2883
2884 spin_lock_irqsave(&info->irq_spinlock,flags);
2885 usc_set_serial_signals(info);
2886 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2887
2888 return 0;
2889}
2890
2891/* mgsl_break() Set or clear transmit break condition
2892 *
2893 * Arguments: tty pointer to tty instance data
2894 * break_state -1=set break condition, 0=clear
9e98966c 2895 * Return Value: error code
1da177e4 2896 */
9e98966c 2897static int mgsl_break(struct tty_struct *tty, int break_state)
1da177e4 2898{
c9f19e96 2899 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 2900 unsigned long flags;
2901
2902 if (debug_level >= DEBUG_LEVEL_INFO)
2903 printk("%s(%d):mgsl_break(%s,%d)\n",
2904 __FILE__,__LINE__, info->device_name, break_state);
2905
2906 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
9e98966c 2907 return -EINVAL;
1da177e4
LT		 2908
2909 spin_lock_irqsave(&info->irq_spinlock,flags);
2910 if (break_state == -1)
2911 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2912 else
2913 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2914 spin_unlock_irqrestore(&info->irq_spinlock,flags);
9e98966c 2915 return 0;
1da177e4
LT		 2916
2917} /* end of mgsl_break() */
2918
0587102c
AC		 2919/*
2920 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2921 * Return: write counters to the user passed counter struct
2922 * NB: both 1->0 and 0->1 transitions are counted except for
2923 * RI where only 0->1 is counted.
2924 */
2925static int msgl_get_icount(struct tty_struct *tty,
2926 struct serial_icounter_struct *icount)
2927
2928{
2929 struct mgsl_struct * info = tty->driver_data;
2930 struct mgsl_icount cnow; /* kernel counter temps */
2931 unsigned long flags;
2932
2933 spin_lock_irqsave(&info->irq_spinlock,flags);
2934 cnow = info->icount;
2935 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2936
2937 icount->cts = cnow.cts;
2938 icount->dsr = cnow.dsr;
2939 icount->rng = cnow.rng;
2940 icount->dcd = cnow.dcd;
2941 icount->rx = cnow.rx;
2942 icount->tx = cnow.tx;
2943 icount->frame = cnow.frame;
2944 icount->overrun = cnow.overrun;
2945 icount->parity = cnow.parity;
2946 icount->brk = cnow.brk;
2947 icount->buf_overrun = cnow.buf_overrun;
2948 return 0;
2949}
2950
1da177e4
LT		 2951/* mgsl_ioctl() Service an IOCTL request
2952 *
2953 * Arguments:
2954 *
2955 * tty pointer to tty instance data
1da177e4
LT		 2956 * cmd IOCTL command code
2957 * arg command argument/context
2958 *
2959 * Return Value: 0 if success, otherwise error code
2960 */
6caa76b7 2961static int mgsl_ioctl(struct tty_struct *tty,
1da177e4
LT		 2962 unsigned int cmd, unsigned long arg)
2963{
c9f19e96 2964 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 2965
2966 if (debug_level >= DEBUG_LEVEL_INFO)
2967 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2968 info->device_name, cmd );
2969
2970 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2971 return -ENODEV;
2972
2973 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
0587102c 2974 (cmd != TIOCMIWAIT)) {
1da177e4
LT		 2975 if (tty->flags & (1 << TTY_IO_ERROR))
2976 return -EIO;
2977 }
2978
f602501d 2979 return mgsl_ioctl_common(info, cmd, arg);
1da177e4
LT		 2980}
2981
2982static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2983{
1da177e4 2984 void __user *argp = (void __user *)arg;
1da177e4
LT		 2985
2986 switch (cmd) {
2987 case MGSL_IOCGPARAMS:
2988 return mgsl_get_params(info, argp);
2989 case MGSL_IOCSPARAMS:
2990 return mgsl_set_params(info, argp);
2991 case MGSL_IOCGTXIDLE:
2992 return mgsl_get_txidle(info, argp);
2993 case MGSL_IOCSTXIDLE:
2994 return mgsl_set_txidle(info,(int)arg);
2995 case MGSL_IOCTXENABLE:
2996 return mgsl_txenable(info,(int)arg);
2997 case MGSL_IOCRXENABLE:
2998 return mgsl_rxenable(info,(int)arg);
2999 case MGSL_IOCTXABORT:
3000 return mgsl_txabort(info);
3001 case MGSL_IOCGSTATS:
3002 return mgsl_get_stats(info, argp);
3003 case MGSL_IOCWAITEVENT:
3004 return mgsl_wait_event(info, argp);
3005 case MGSL_IOCLOOPTXDONE:
3006 return mgsl_loopmode_send_done(info);
3007 /* Wait for modem input (DCD,RI,DSR,CTS) change
3008 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3009 */
3010 case TIOCMIWAIT:
3011 return modem_input_wait(info,(int)arg);
3012
1da177e4
LT		 3013 default:
3014 return -ENOIOCTLCMD;
3015 }
3016 return 0;
3017}
3018
3019/* mgsl_set_termios()
3020 *
3021 * Set new termios settings
3022 *
3023 * Arguments:
3024 *
3025 * tty pointer to tty structure
3026 * termios pointer to buffer to hold returned old termios
3027 *
3028 * Return Value: None
3029 */
606d099c 3030static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4 3031{
c9f19e96 3032 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 3033 unsigned long flags;
3034
3035 if (debug_level >= DEBUG_LEVEL_INFO)
3036 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3037 tty->driver->name );
3038
1da177e4
LT		 3039 mgsl_change_params(info);
3040
3041 /* Handle transition to B0 status */
3042 if (old_termios->c_cflag & CBAUD &&
adc8d746 3043 !(tty->termios.c_cflag & CBAUD)) {
9fe8074b 3044 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 3045 spin_lock_irqsave(&info->irq_spinlock,flags);
3046 usc_set_serial_signals(info);
3047 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3048 }
3049
3050 /* Handle transition away from B0 status */
3051 if (!(old_termios->c_cflag & CBAUD) &&
adc8d746 3052 tty->termios.c_cflag & CBAUD) {
1da177e4 3053 info->serial_signals |= SerialSignal_DTR;
adc8d746 3054 if (!(tty->termios.c_cflag & CRTSCTS) ||
1da177e4
LT		 3055 !test_bit(TTY_THROTTLED, &tty->flags)) {
3056 info->serial_signals |= SerialSignal_RTS;
3057 }
3058 spin_lock_irqsave(&info->irq_spinlock,flags);
3059 usc_set_serial_signals(info);
3060 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3061 }
3062
3063 /* Handle turning off CRTSCTS */
3064 if (old_termios->c_cflag & CRTSCTS &&
adc8d746 3065 !(tty->termios.c_cflag & CRTSCTS)) {
1da177e4
LT		 3066 tty->hw_stopped = 0;
3067 mgsl_start(tty);
3068 }
3069
3070} /* end of mgsl_set_termios() */
3071
3072/* mgsl_close()
3073 *
3074 * Called when port is closed. Wait for remaining data to be
3075 * sent. Disable port and free resources.
3076 *
3077 * Arguments:
3078 *
3079 * tty pointer to open tty structure
3080 * filp pointer to open file object
3081 *
3082 * Return Value: None
3083 */
3084static void mgsl_close(struct tty_struct *tty, struct file * filp)
3085{
c9f19e96 3086 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 3087
3088 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3089 return;
3090
3091 if (debug_level >= DEBUG_LEVEL_INFO)
3092 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
8fb06c77 3093 __FILE__,__LINE__, info->device_name, info->port.count);
1da177e4 3094
e06922aa 3095 if (tty_port_close_start(&info->port, tty, filp) == 0)
1da177e4 3096 goto cleanup;
f602501d
AC		 3097
3098 mutex_lock(&info->port.mutex);
8fb06c77 3099 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4 3100 mgsl_wait_until_sent(tty, info->timeout);
978e595f 3101 mgsl_flush_buffer(tty);
1da177e4 3102 tty_ldisc_flush(tty);
1da177e4 3103 shutdown(info);
f602501d 3104 mutex_unlock(&info->port.mutex);
a6614999
AC		 3105
3106 tty_port_close_end(&info->port, tty);
8fb06c77 3107 info->port.tty = NULL;
1da177e4
LT		 3108cleanup:
3109 if (debug_level >= DEBUG_LEVEL_INFO)
3110 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
8fb06c77 3111 tty->driver->name, info->port.count);
1da177e4
LT		 3112
3113} /* end of mgsl_close() */
3114
3115/* mgsl_wait_until_sent()
3116 *
3117 * Wait until the transmitter is empty.
3118 *
3119 * Arguments:
3120 *
3121 * tty pointer to tty info structure
3122 * timeout time to wait for send completion
3123 *
3124 * Return Value: None
3125 */
3126static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3127{
c9f19e96 3128 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 3129 unsigned long orig_jiffies, char_time;
3130
3131 if (!info )
3132 return;
3133
3134 if (debug_level >= DEBUG_LEVEL_INFO)
3135 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3136 __FILE__,__LINE__, info->device_name );
3137
3138 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3139 return;
3140
8fb06c77 3141 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 3142 goto exit;
3143
3144 orig_jiffies = jiffies;
3145
3146 /* Set check interval to 1/5 of estimated time to
3147 * send a character, and make it at least 1. The check
3148 * interval should also be less than the timeout.
3149 * Note: use tight timings here to satisfy the NIST-PCTS.
3150 */
978e595f 3151
1da177e4
LT		 3152 if ( info->params.data_rate ) {
3153 char_time = info->timeout/(32 * 5);
3154 if (!char_time)
3155 char_time++;
3156 } else
3157 char_time = 1;
3158
3159 if (timeout)
3160 char_time = min_t(unsigned long, char_time, timeout);
3161
3162 if ( info->params.mode == MGSL_MODE_HDLC ||
3163 info->params.mode == MGSL_MODE_RAW ) {
3164 while (info->tx_active) {
3165 msleep_interruptible(jiffies_to_msecs(char_time));
3166 if (signal_pending(current))
3167 break;
3168 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3169 break;
3170 }
3171 } else {
3172 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3173 info->tx_enabled) {
3174 msleep_interruptible(jiffies_to_msecs(char_time));
3175 if (signal_pending(current))
3176 break;
3177 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3178 break;
3179 }
3180 }
3181
3182exit:
3183 if (debug_level >= DEBUG_LEVEL_INFO)
3184 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3185 __FILE__,__LINE__, info->device_name );
3186
3187} /* end of mgsl_wait_until_sent() */
3188
3189/* mgsl_hangup()
3190 *
3191 * Called by tty_hangup() when a hangup is signaled.
3192 * This is the same as to closing all open files for the port.
3193 *
3194 * Arguments: tty pointer to associated tty object
3195 * Return Value: None
3196 */
3197static void mgsl_hangup(struct tty_struct *tty)
3198{
c9f19e96 3199 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 3200
3201 if (debug_level >= DEBUG_LEVEL_INFO)
3202 printk("%s(%d):mgsl_hangup(%s)\n",
3203 __FILE__,__LINE__, info->device_name );
3204
3205 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3206 return;
3207
3208 mgsl_flush_buffer(tty);
3209 shutdown(info);
3210
8fb06c77
AC		 3211 info->port.count = 0;
3212 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3213 info->port.tty = NULL;
1da177e4 3214
8fb06c77 3215 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 3216
3217} /* end of mgsl_hangup() */
3218
31f35939
AC		 3219/*
3220 * carrier_raised()
3221 *
3222 * Return true if carrier is raised
3223 */
3224
3225static int carrier_raised(struct tty_port *port)
3226{
3227 unsigned long flags;
3228 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3229
3230 spin_lock_irqsave(&info->irq_spinlock, flags);
3231 usc_get_serial_signals(info);
3232 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3233 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3234}
3235
fcc8ac18 3236static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 3237{
3238 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3239 unsigned long flags;
3240
3241 spin_lock_irqsave(&info->irq_spinlock,flags);
fcc8ac18 3242 if (on)
9fe8074b 3243 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
fcc8ac18 3244 else
9fe8074b 3245 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
5d951fb4
AC		 3246 usc_set_serial_signals(info);
3247 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3248}
3249
3250
1da177e4
LT		 3251/* block_til_ready()
3252 *
3253 * Block the current process until the specified port
3254 * is ready to be opened.
3255 *
3256 * Arguments:
3257 *
3258 * tty pointer to tty info structure
3259 * filp pointer to open file object
3260 * info pointer to device instance data
3261 *
3262 * Return Value: 0 if success, otherwise error code
3263 */
3264static int block_til_ready(struct tty_struct *tty, struct file * filp,
3265 struct mgsl_struct *info)
3266{
3267 DECLARE_WAITQUEUE(wait, current);
3268 int retval;
0fab6de0 3269 bool do_clocal = false;
1da177e4 3270 unsigned long flags;
31f35939
AC		 3271 int dcd;
3272 struct tty_port *port = &info->port;
1da177e4
LT		 3273
3274 if (debug_level >= DEBUG_LEVEL_INFO)
3275 printk("%s(%d):block_til_ready on %s\n",
3276 __FILE__,__LINE__, tty->driver->name );
3277
3278 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3279 /* nonblock mode is set or port is not enabled */
31f35939 3280 port->flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3281 return 0;
3282 }
3283
adc8d746 3284 if (tty->termios.c_cflag & CLOCAL)
0fab6de0 3285 do_clocal = true;
1da177e4
LT		 3286
3287 /* Wait for carrier detect and the line to become
3288 * free (i.e., not in use by the callout). While we are in
31f35939 3289 * this loop, port->count is dropped by one, so that
1da177e4
LT		 3290 * mgsl_close() knows when to free things. We restore it upon
3291 * exit, either normal or abnormal.
3292 */
3293
3294 retval = 0;
31f35939 3295 add_wait_queue(&port->open_wait, &wait);
1da177e4
LT		 3296
3297 if (debug_level >= DEBUG_LEVEL_INFO)
3298 printk("%s(%d):block_til_ready before block on %s count=%d\n",
31f35939 3299 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4
LT		 3300
3301 spin_lock_irqsave(&info->irq_spinlock, flags);
e359a4e3 3302 port->count--;
1da177e4 3303 spin_unlock_irqrestore(&info->irq_spinlock, flags);
31f35939 3304 port->blocked_open++;
1da177e4
LT		 3305
3306 while (1) {
78c6ccca 3307 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
5d951fb4 3308 tty_port_raise_dtr_rts(port);
1da177e4
LT		 3309
3310 set_current_state(TASK_INTERRUPTIBLE);
3311
31f35939
AC		 3312 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3313 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 3314 -EAGAIN : -ERESTARTSYS;
3315 break;
3316 }
3317
31f35939 3318 dcd = tty_port_carrier_raised(&info->port);
1da177e4 3319
31f35939 3320 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
1da177e4 3321 break;
1da177e4
LT		 3322
3323 if (signal_pending(current)) {
3324 retval = -ERESTARTSYS;
3325 break;
3326 }
3327
3328 if (debug_level >= DEBUG_LEVEL_INFO)
3329 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
31f35939 3330 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4 3331
89c8d91e 3332 tty_unlock(tty);
1da177e4 3333 schedule();
89c8d91e 3334 tty_lock(tty);
1da177e4
LT		 3335 }
3336
3337 set_current_state(TASK_RUNNING);
31f35939 3338 remove_wait_queue(&port->open_wait, &wait);
1da177e4 3339
36c621d8 3340 /* FIXME: Racy on hangup during close wait */
e359a4e3 3341 if (!tty_hung_up_p(filp))
31f35939
AC		 3342 port->count++;
3343 port->blocked_open--;
1da177e4
LT		 3344
3345 if (debug_level >= DEBUG_LEVEL_INFO)
3346 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
31f35939 3347 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4
LT		 3348
3349 if (!retval)
31f35939 3350 port->flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3351
3352 return retval;
3353
3354} /* end of block_til_ready() */
3355
8a3ad104
JS		 3356static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
3357{
3358 struct mgsl_struct *info;
3359 int line = tty->index;
3360
3361 /* verify range of specified line number */
3362 if (line >= mgsl_device_count) {
3363 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3364 __FILE__, __LINE__, line);
3365 return -ENODEV;
3366 }
3367
3368 /* find the info structure for the specified line */
3369 info = mgsl_device_list;
3370 while (info && info->line != line)
3371 info = info->next_device;
3372 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3373 return -ENODEV;
3374 tty->driver_data = info;
3375
3376 return tty_port_install(&info->port, driver, tty);
3377}
3378
1da177e4
LT		 3379/* mgsl_open()
3380 *
3381 * Called when a port is opened. Init and enable port.
3382 * Perform serial-specific initialization for the tty structure.
3383 *
3384 * Arguments: tty pointer to tty info structure
3385 * filp associated file pointer
3386 *
3387 * Return Value: 0 if success, otherwise error code
3388 */
3389static int mgsl_open(struct tty_struct *tty, struct file * filp)
3390{
8a3ad104 3391 struct mgsl_struct *info = tty->driver_data;
1da177e4 3392 unsigned long flags;
8a3ad104 3393 int retval;
1da177e4 3394
8fb06c77 3395 info->port.tty = tty;
1da177e4
LT		 3396
3397 if (debug_level >= DEBUG_LEVEL_INFO)
3398 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
8fb06c77 3399 __FILE__,__LINE__,tty->driver->name, info->port.count);
1da177e4
LT		 3400
3401 /* If port is closing, signal caller to try again */
e359a4e3 3402 if (info->port.flags & ASYNC_CLOSING){
b8c98ae4
AB		 3403 wait_event_interruptible_tty(tty, info->port.close_wait,
3404 !(info->port.flags & ASYNC_CLOSING));
8fb06c77 3405 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 3406 -EAGAIN : -ERESTARTSYS);
3407 goto cleanup;
3408 }
3409
d6c53c0e 3410 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 3411
3412 spin_lock_irqsave(&info->netlock, flags);
3413 if (info->netcount) {
3414 retval = -EBUSY;
3415 spin_unlock_irqrestore(&info->netlock, flags);
3416 goto cleanup;
3417 }
8fb06c77 3418 info->port.count++;
1da177e4
LT		 3419 spin_unlock_irqrestore(&info->netlock, flags);
3420
8fb06c77 3421 if (info->port.count == 1) {
1da177e4
LT		 3422 /* 1st open on this device, init hardware */
3423 retval = startup(info);
3424 if (retval < 0)
3425 goto cleanup;
3426 }
3427
3428 retval = block_til_ready(tty, filp, info);
3429 if (retval) {
3430 if (debug_level >= DEBUG_LEVEL_INFO)
3431 printk("%s(%d):block_til_ready(%s) returned %d\n",
3432 __FILE__,__LINE__, info->device_name, retval);
3433 goto cleanup;
3434 }
3435
3436 if (debug_level >= DEBUG_LEVEL_INFO)
3437 printk("%s(%d):mgsl_open(%s) success\n",
3438 __FILE__,__LINE__, info->device_name);
3439 retval = 0;
3440
3441cleanup:
3442 if (retval) {
3443 if (tty->count == 1)
8fb06c77
AC		 3444 info->port.tty = NULL; /* tty layer will release tty struct */
3445 if(info->port.count)
3446 info->port.count--;
1da177e4
LT		 3447 }
3448
3449 return retval;
3450
3451} /* end of mgsl_open() */
3452
3453/*
3454 * /proc fs routines....
3455 */
3456
d337829b 3457static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
1da177e4
LT		 3458{
3459 char stat_buf[30];
1da177e4
LT		 3460 unsigned long flags;
3461
3462 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
d337829b 3463 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
1da177e4
LT		 3464 info->device_name, info->io_base, info->irq_level,
3465 info->phys_memory_base, info->phys_lcr_base);
3466 } else {
d337829b 3467 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
1da177e4
LT		 3468 info->device_name, info->io_base,
3469 info->irq_level, info->dma_level);
3470 }
3471
3472 /* output current serial signal states */
3473 spin_lock_irqsave(&info->irq_spinlock,flags);
3474 usc_get_serial_signals(info);
3475 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3476
3477 stat_buf[0] = 0;
3478 stat_buf[1] = 0;
3479 if (info->serial_signals & SerialSignal_RTS)
3480 strcat(stat_buf, "|RTS");
3481 if (info->serial_signals & SerialSignal_CTS)
3482 strcat(stat_buf, "|CTS");
3483 if (info->serial_signals & SerialSignal_DTR)
3484 strcat(stat_buf, "|DTR");
3485 if (info->serial_signals & SerialSignal_DSR)
3486 strcat(stat_buf, "|DSR");
3487 if (info->serial_signals & SerialSignal_DCD)
3488 strcat(stat_buf, "|CD");
3489 if (info->serial_signals & SerialSignal_RI)
3490 strcat(stat_buf, "|RI");
3491
3492 if (info->params.mode == MGSL_MODE_HDLC ||
3493 info->params.mode == MGSL_MODE_RAW ) {
d337829b 3494 seq_printf(m, " HDLC txok:%d rxok:%d",
1da177e4
LT		 3495 info->icount.txok, info->icount.rxok);
3496 if (info->icount.txunder)
d337829b 3497 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 3498 if (info->icount.txabort)
d337829b 3499 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 3500 if (info->icount.rxshort)
d337829b 3501 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 3502 if (info->icount.rxlong)
d337829b 3503 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 3504 if (info->icount.rxover)
d337829b 3505 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 3506 if (info->icount.rxcrc)
d337829b 3507 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1da177e4 3508 } else {
d337829b 3509 seq_printf(m, " ASYNC tx:%d rx:%d",
1da177e4
LT		 3510 info->icount.tx, info->icount.rx);
3511 if (info->icount.frame)
d337829b 3512 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 3513 if (info->icount.parity)
d337829b 3514 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 3515 if (info->icount.brk)
d337829b 3516 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 3517 if (info->icount.overrun)
d337829b 3518 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4
LT		 3519 }
3520
3521 /* Append serial signal status to end */
d337829b 3522 seq_printf(m, " %s\n", stat_buf+1);
1da177e4 3523
d337829b 3524 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 3525 info->tx_active,info->bh_requested,info->bh_running,
3526 info->pending_bh);
3527
3528 spin_lock_irqsave(&info->irq_spinlock,flags);
3529 {
3530 u16 Tcsr = usc_InReg( info, TCSR );
3531 u16 Tdmr = usc_InDmaReg( info, TDMR );
3532 u16 Ticr = usc_InReg( info, TICR );
3533 u16 Rscr = usc_InReg( info, RCSR );
3534 u16 Rdmr = usc_InDmaReg( info, RDMR );
3535 u16 Ricr = usc_InReg( info, RICR );
3536 u16 Icr = usc_InReg( info, ICR );
3537 u16 Dccr = usc_InReg( info, DCCR );
3538 u16 Tmr = usc_InReg( info, TMR );
3539 u16 Tccr = usc_InReg( info, TCCR );
3540 u16 Ccar = inw( info->io_base + CCAR );
d337829b 3541 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
1da177e4
LT		 3542 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3543 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3544 }
3545 spin_unlock_irqrestore(&info->irq_spinlock,flags);
d337829b 3546}
1da177e4 3547
d337829b
AD		 3548/* Called to print information about devices */
3549static int mgsl_proc_show(struct seq_file *m, void *v)
1da177e4 3550{
1da177e4
LT		 3551 struct mgsl_struct *info;
3552
d337829b 3553 seq_printf(m, "synclink driver:%s\n", driver_version);
1da177e4
LT		 3554
3555 info = mgsl_device_list;
3556 while( info ) {
d337829b 3557 line_info(m, info);
1da177e4
LT		 3558 info = info->next_device;
3559 }
d337829b
AD		 3560 return 0;
3561}
1da177e4 3562
d337829b
AD		 3563static int mgsl_proc_open(struct inode *inode, struct file *file)
3564{
3565 return single_open(file, mgsl_proc_show, NULL);
3566}
3567
3568static const struct file_operations mgsl_proc_fops = {
3569 .owner = THIS_MODULE,
3570 .open = mgsl_proc_open,
3571 .read = seq_read,
3572 .llseek = seq_lseek,
3573 .release = single_release,
3574};
1da177e4
LT		 3575
3576/* mgsl_allocate_dma_buffers()
3577 *
3578 * Allocate and format DMA buffers (ISA adapter)
3579 * or format shared memory buffers (PCI adapter).
3580 *
3581 * Arguments: info pointer to device instance data
3582 * Return Value: 0 if success, otherwise error
3583 */
3584static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3585{
3586 unsigned short BuffersPerFrame;
3587
3588 info->last_mem_alloc = 0;
3589
3590 /* Calculate the number of DMA buffers necessary to hold the */
3591 /* largest allowable frame size. Note: If the max frame size is */
3592 /* not an even multiple of the DMA buffer size then we need to */
3593 /* round the buffer count per frame up one. */
3594
3595 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3596 if ( info->max_frame_size % DMABUFFERSIZE )
3597 BuffersPerFrame++;
3598
3599 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3600 /*
3601 * The PCI adapter has 256KBytes of shared memory to use.
3602 * This is 64 PAGE_SIZE buffers.
3603 *
3604 * The first page is used for padding at this time so the
3605 * buffer list does not begin at offset 0 of the PCI
3606 * adapter's shared memory.
3607 *
3608 * The 2nd page is used for the buffer list. A 4K buffer
3609 * list can hold 128 DMA_BUFFER structures at 32 bytes
3610 * each.
3611 *
3612 * This leaves 62 4K pages.
3613 *
3614 * The next N pages are used for transmit frame(s). We
3615 * reserve enough 4K page blocks to hold the required
3616 * number of transmit dma buffers (num_tx_dma_buffers),
3617 * each of MaxFrameSize size.
3618 *
3619 * Of the remaining pages (62-N), determine how many can
3620 * be used to receive full MaxFrameSize inbound frames
3621 */
3622 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3623 info->rx_buffer_count = 62 - info->tx_buffer_count;
3624 } else {
3625 /* Calculate the number of PAGE_SIZE buffers needed for */
3626 /* receive and transmit DMA buffers. */
3627
3628
3629 /* Calculate the number of DMA buffers necessary to */
3630 /* hold 7 max size receive frames and one max size transmit frame. */
3631 /* The receive buffer count is bumped by one so we avoid an */
3632 /* End of List condition if all receive buffers are used when */
3633 /* using linked list DMA buffers. */
3634
3635 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3636 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3637
3638 /*
3639 * limit total TxBuffers & RxBuffers to 62 4K total
3640 * (ala PCI Allocation)
3641 */
3642
3643 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3644 info->rx_buffer_count = 62 - info->tx_buffer_count;
3645
3646 }
3647
3648 if ( debug_level >= DEBUG_LEVEL_INFO )
3649 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3650 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3651
3652 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3653 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3654 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3655 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3656 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3657 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3658 return -ENOMEM;
3659 }
3660
3661 mgsl_reset_rx_dma_buffers( info );
3662 mgsl_reset_tx_dma_buffers( info );
3663
3664 return 0;
3665
3666} /* end of mgsl_allocate_dma_buffers() */
3667
3668/*
3669 * mgsl_alloc_buffer_list_memory()
3670 *
3671 * Allocate a common DMA buffer for use as the
3672 * receive and transmit buffer lists.
3673 *
3674 * A buffer list is a set of buffer entries where each entry contains
3675 * a pointer to an actual buffer and a pointer to the next buffer entry
3676 * (plus some other info about the buffer).
3677 *
3678 * The buffer entries for a list are built to form a circular list so
3679 * that when the entire list has been traversed you start back at the
3680 * beginning.
3681 *
3682 * This function allocates memory for just the buffer entries.
3683 * The links (pointer to next entry) are filled in with the physical
3684 * address of the next entry so the adapter can navigate the list
3685 * using bus master DMA. The pointers to the actual buffers are filled
3686 * out later when the actual buffers are allocated.
3687 *
3688 * Arguments: info pointer to device instance data
3689 * Return Value: 0 if success, otherwise error
3690 */
3691static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3692{
3693 unsigned int i;
3694
3695 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3696 /* PCI adapter uses shared memory. */
3697 info->buffer_list = info->memory_base + info->last_mem_alloc;
3698 info->buffer_list_phys = info->last_mem_alloc;
3699 info->last_mem_alloc += BUFFERLISTSIZE;
3700 } else {
3701 /* ISA adapter uses system memory. */
3702 /* The buffer lists are allocated as a common buffer that both */
3703 /* the processor and adapter can access. This allows the driver to */
3704 /* inspect portions of the buffer while other portions are being */
3705 /* updated by the adapter using Bus Master DMA. */
3706
0ff1b2c8
PF		 3707 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3708 if (info->buffer_list == NULL)
1da177e4 3709 return -ENOMEM;
0ff1b2c8 3710 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
1da177e4
LT		 3711 }
3712
3713 /* We got the memory for the buffer entry lists. */
3714 /* Initialize the memory block to all zeros. */
3715 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3716
3717 /* Save virtual address pointers to the receive and */
3718 /* transmit buffer lists. (Receive 1st). These pointers will */
3719 /* be used by the processor to access the lists. */
3720 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3721 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3722 info->tx_buffer_list += info->rx_buffer_count;
3723
3724 /*
3725 * Build the links for the buffer entry lists such that
3726 * two circular lists are built. (Transmit and Receive).
3727 *
3728 * Note: the links are physical addresses
3729 * which are read by the adapter to determine the next
3730 * buffer entry to use.
3731 */
3732
3733 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3734 /* calculate and store physical address of this buffer entry */
3735 info->rx_buffer_list[i].phys_entry =
3736 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3737
3738 /* calculate and store physical address of */
3739 /* next entry in cirular list of entries */
3740
3741 info->rx_buffer_list[i].link = info->buffer_list_phys;
3742
3743 if ( i < info->rx_buffer_count - 1 )
3744 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3745 }
3746
3747 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3748 /* calculate and store physical address of this buffer entry */
3749 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3750 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3751
3752 /* calculate and store physical address of */
3753 /* next entry in cirular list of entries */
3754
3755 info->tx_buffer_list[i].link = info->buffer_list_phys +
3756 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3757
3758 if ( i < info->tx_buffer_count - 1 )
3759 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3760 }
3761
3762 return 0;
3763
3764} /* end of mgsl_alloc_buffer_list_memory() */
3765
3766/* Free DMA buffers allocated for use as the
3767 * receive and transmit buffer lists.
3768 * Warning:
3769 *
3770 * The data transfer buffers associated with the buffer list
3771 * MUST be freed before freeing the buffer list itself because
3772 * the buffer list contains the information necessary to free
3773 * the individual buffers!
3774 */
3775static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3776{
0ff1b2c8
PF		 3777 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3778 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
1da177e4
LT		 3779
3780 info->buffer_list = NULL;
3781 info->rx_buffer_list = NULL;
3782 info->tx_buffer_list = NULL;
3783
3784} /* end of mgsl_free_buffer_list_memory() */
3785
3786/*
3787 * mgsl_alloc_frame_memory()
3788 *
3789 * Allocate the frame DMA buffers used by the specified buffer list.
3790 * Each DMA buffer will be one memory page in size. This is necessary
3791 * because memory can fragment enough that it may be impossible
3792 * contiguous pages.
3793 *
3794 * Arguments:
3795 *
3796 * info pointer to device instance data
3797 * BufferList pointer to list of buffer entries
3798 * Buffercount count of buffer entries in buffer list
3799 *
3800 * Return Value: 0 if success, otherwise -ENOMEM
3801 */
3802static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3803{
3804 int i;
0ff1b2c8 3805 u32 phys_addr;
1da177e4
LT		 3806
3807 /* Allocate page sized buffers for the receive buffer list */
3808
3809 for ( i = 0; i < Buffercount; i++ ) {
3810 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3811 /* PCI adapter uses shared memory buffers. */
3812 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3813 phys_addr = info->last_mem_alloc;
3814 info->last_mem_alloc += DMABUFFERSIZE;
3815 } else {
3816 /* ISA adapter uses system memory. */
0ff1b2c8
PF		 3817 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3818 if (BufferList[i].virt_addr == NULL)
1da177e4 3819 return -ENOMEM;
0ff1b2c8 3820 phys_addr = (u32)(BufferList[i].dma_addr);
1da177e4
LT		 3821 }
3822 BufferList[i].phys_addr = phys_addr;
3823 }
3824
3825 return 0;
3826
3827} /* end of mgsl_alloc_frame_memory() */
3828
3829/*
3830 * mgsl_free_frame_memory()
3831 *
3832 * Free the buffers associated with
3833 * each buffer entry of a buffer list.
3834 *
3835 * Arguments:
3836 *
3837 * info pointer to device instance data
3838 * BufferList pointer to list of buffer entries
3839 * Buffercount count of buffer entries in buffer list
3840 *
3841 * Return Value: None
3842 */
3843static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3844{
3845 int i;
3846
3847 if ( BufferList ) {
3848 for ( i = 0 ; i < Buffercount ; i++ ) {
3849 if ( BufferList[i].virt_addr ) {
3850 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
0ff1b2c8 3851 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
1da177e4
LT		 3852 BufferList[i].virt_addr = NULL;
3853 }
3854 }
3855 }
3856
3857} /* end of mgsl_free_frame_memory() */
3858
3859/* mgsl_free_dma_buffers()
3860 *
3861 * Free DMA buffers
3862 *
3863 * Arguments: info pointer to device instance data
3864 * Return Value: None
3865 */
3866static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3867{
3868 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3869 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3870 mgsl_free_buffer_list_memory( info );
3871
3872} /* end of mgsl_free_dma_buffers() */
3873
3874
3875/*
3876 * mgsl_alloc_intermediate_rxbuffer_memory()
3877 *
3878 * Allocate a buffer large enough to hold max_frame_size. This buffer
3879 * is used to pass an assembled frame to the line discipline.
3880 *
3881 * Arguments:
3882 *
3883 * info pointer to device instance data
3884 *
3885 * Return Value: 0 if success, otherwise -ENOMEM
3886 */
3887static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3888{
3889 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3890 if ( info->intermediate_rxbuffer == NULL )
3891 return -ENOMEM;
a6b68a69
PF		 3892 /* unused flag buffer to satisfy receive_buf calling interface */
3893 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3894 if (!info->flag_buf) {
3895 kfree(info->intermediate_rxbuffer);
3896 info->intermediate_rxbuffer = NULL;
3897 return -ENOMEM;
3898 }
1da177e4
LT		 3899 return 0;
3900
3901} /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3902
3903/*
3904 * mgsl_free_intermediate_rxbuffer_memory()
3905 *
3906 *
3907 * Arguments:
3908 *
3909 * info pointer to device instance data
3910 *
3911 * Return Value: None
3912 */
3913static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3914{
735d5661 3915 kfree(info->intermediate_rxbuffer);
1da177e4 3916 info->intermediate_rxbuffer = NULL;
a6b68a69
PF		 3917 kfree(info->flag_buf);
3918 info->flag_buf = NULL;
1da177e4
LT		 3919
3920} /* end of mgsl_free_intermediate_rxbuffer_memory() */
3921
3922/*
3923 * mgsl_alloc_intermediate_txbuffer_memory()
3924 *
3925 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3926 * This buffer is used to load transmit frames into the adapter's dma transfer
3927 * buffers when there is sufficient space.
3928 *
3929 * Arguments:
3930 *
3931 * info pointer to device instance data
3932 *
3933 * Return Value: 0 if success, otherwise -ENOMEM
3934 */
3935static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3936{
3937 int i;
3938
3939 if ( debug_level >= DEBUG_LEVEL_INFO )
3940 printk("%s %s(%d) allocating %d tx holding buffers\n",
3941 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3942
3943 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3944
3945 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3946 info->tx_holding_buffers[i].buffer =
3947 kmalloc(info->max_frame_size, GFP_KERNEL);
d9a2f4a4
AC		 3948 if (info->tx_holding_buffers[i].buffer == NULL) {
3949 for (--i; i >= 0; i--) {
3950 kfree(info->tx_holding_buffers[i].buffer);
3951 info->tx_holding_buffers[i].buffer = NULL;
3952 }
1da177e4 3953 return -ENOMEM;
d9a2f4a4 3954 }
1da177e4
LT		 3955 }
3956
3957 return 0;
3958
3959} /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3960
3961/*
3962 * mgsl_free_intermediate_txbuffer_memory()
3963 *
3964 *
3965 * Arguments:
3966 *
3967 * info pointer to device instance data
3968 *
3969 * Return Value: None
3970 */
3971static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3972{
3973 int i;
3974
3975 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
735d5661
JJ		 3976 kfree(info->tx_holding_buffers[i].buffer);
3977 info->tx_holding_buffers[i].buffer = NULL;
1da177e4
LT		 3978 }
3979
3980 info->get_tx_holding_index = 0;
3981 info->put_tx_holding_index = 0;
3982 info->tx_holding_count = 0;
3983
3984} /* end of mgsl_free_intermediate_txbuffer_memory() */
3985
3986
3987/*
3988 * load_next_tx_holding_buffer()
3989 *
3990 * attempts to load the next buffered tx request into the
3991 * tx dma buffers
3992 *
3993 * Arguments:
3994 *
3995 * info pointer to device instance data
3996 *
0fab6de0 3997 * Return Value: true if next buffered tx request loaded
1da177e4 3998 * into adapter's tx dma buffer,
0fab6de0 3999 * false otherwise
1da177e4 4000 */
0fab6de0 4001static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
1da177e4 4002{
0fab6de0 4003 bool ret = false;
1da177e4
LT		 4004
4005 if ( info->tx_holding_count ) {
4006 /* determine if we have enough tx dma buffers
4007 * to accommodate the next tx frame
4008 */
4009 struct tx_holding_buffer *ptx =
4010 &info->tx_holding_buffers[info->get_tx_holding_index];
4011 int num_free = num_free_tx_dma_buffers(info);
4012 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4013 if ( ptx->buffer_size % DMABUFFERSIZE )
4014 ++num_needed;
4015
4016 if (num_needed <= num_free) {
4017 info->xmit_cnt = ptx->buffer_size;
4018 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4019
4020 --info->tx_holding_count;
4021 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4022 info->get_tx_holding_index=0;
4023
4024 /* restart transmit timer */
4025 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4026
0fab6de0 4027 ret = true;
1da177e4
LT		 4028 }
4029 }
4030
4031 return ret;
4032}
4033
4034/*
4035 * save_tx_buffer_request()
4036 *
4037 * attempt to store transmit frame request for later transmission
4038 *
4039 * Arguments:
4040 *
4041 * info pointer to device instance data
4042 * Buffer pointer to buffer containing frame to load
4043 * BufferSize size in bytes of frame in Buffer
4044 *
4045 * Return Value: 1 if able to store, 0 otherwise
4046 */
4047static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4048{
4049 struct tx_holding_buffer *ptx;
4050
4051 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4052 return 0; /* all buffers in use */
4053 }
4054
4055 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4056 ptx->buffer_size = BufferSize;
4057 memcpy( ptx->buffer, Buffer, BufferSize);
4058
4059 ++info->tx_holding_count;
4060 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4061 info->put_tx_holding_index=0;
4062
4063 return 1;
4064}
4065
4066static int mgsl_claim_resources(struct mgsl_struct *info)
4067{
4068 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4069 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4070 __FILE__,__LINE__,info->device_name, info->io_base);
4071 return -ENODEV;
4072 }
0fab6de0 4073 info->io_addr_requested = true;
1da177e4
LT		 4074
4075 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4076 info->device_name, info ) < 0 ) {
25985edc 4077 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
1da177e4
LT		 4078 __FILE__,__LINE__,info->device_name, info->irq_level );
4079 goto errout;
4080 }
0fab6de0 4081 info->irq_requested = true;
1da177e4
LT		 4082
4083 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4084 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4085 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4086 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4087 goto errout;
4088 }
0fab6de0 4089 info->shared_mem_requested = true;
1da177e4
LT		 4090 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4091 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4092 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4093 goto errout;
4094 }
0fab6de0 4095 info->lcr_mem_requested = true;
1da177e4 4096
24cb2335
AC		 4097 info->memory_base = ioremap_nocache(info->phys_memory_base,
4098 0x40000);
1da177e4 4099 if (!info->memory_base) {
25985edc 4100 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
1da177e4
LT		 4101 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4102 goto errout;
4103 }
4104
4105 if ( !mgsl_memory_test(info) ) {
4106 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4107 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4108 goto errout;
4109 }
4110
24cb2335
AC		 4111 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4112 PAGE_SIZE);
1da177e4 4113 if (!info->lcr_base) {
25985edc 4114 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
1da177e4
LT		 4115 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4116 goto errout;
4117 }
24cb2335 4118 info->lcr_base += info->lcr_offset;
1da177e4
LT		 4119
4120 } else {
4121 /* claim DMA channel */
4122
4123 if (request_dma(info->dma_level,info->device_name) < 0){
25985edc 4124 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
1da177e4
LT		 4125 __FILE__,__LINE__,info->device_name, info->dma_level );
4126 mgsl_release_resources( info );
4127 return -ENODEV;
4128 }
0fab6de0 4129 info->dma_requested = true;
1da177e4
LT		 4130
4131 /* ISA adapter uses bus master DMA */
4132 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4133 enable_dma(info->dma_level);
4134 }
4135
4136 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
25985edc 4137 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
1da177e4
LT		 4138 __FILE__,__LINE__,info->device_name, info->dma_level );
4139 goto errout;
4140 }
4141
4142 return 0;
4143errout:
4144 mgsl_release_resources(info);
4145 return -ENODEV;
4146
4147} /* end of mgsl_claim_resources() */
4148
4149static void mgsl_release_resources(struct mgsl_struct *info)
4150{
4151 if ( debug_level >= DEBUG_LEVEL_INFO )
4152 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4153 __FILE__,__LINE__,info->device_name );
4154
4155 if ( info->irq_requested ) {
4156 free_irq(info->irq_level, info);
0fab6de0 4157 info->irq_requested = false;
1da177e4
LT		 4158 }
4159 if ( info->dma_requested ) {
4160 disable_dma(info->dma_level);
4161 free_dma(info->dma_level);
0fab6de0 4162 info->dma_requested = false;
1da177e4
LT		 4163 }
4164 mgsl_free_dma_buffers(info);
4165 mgsl_free_intermediate_rxbuffer_memory(info);
4166 mgsl_free_intermediate_txbuffer_memory(info);
4167
4168 if ( info->io_addr_requested ) {
4169 release_region(info->io_base,info->io_addr_size);
0fab6de0 4170 info->io_addr_requested = false;
1da177e4
LT		 4171 }
4172 if ( info->shared_mem_requested ) {
4173 release_mem_region(info->phys_memory_base,0x40000);
0fab6de0 4174 info->shared_mem_requested = false;
1da177e4
LT		 4175 }
4176 if ( info->lcr_mem_requested ) {
4177 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
0fab6de0 4178 info->lcr_mem_requested = false;
1da177e4
LT		 4179 }
4180 if (info->memory_base){
4181 iounmap(info->memory_base);
4182 info->memory_base = NULL;
4183 }
4184 if (info->lcr_base){
4185 iounmap(info->lcr_base - info->lcr_offset);
4186 info->lcr_base = NULL;
4187 }
4188
4189 if ( debug_level >= DEBUG_LEVEL_INFO )
4190 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4191 __FILE__,__LINE__,info->device_name );
4192
4193} /* end of mgsl_release_resources() */
4194
4195/* mgsl_add_device()
4196 *
4197 * Add the specified device instance data structure to the
4198 * global linked list of devices and increment the device count.
4199 *
4200 * Arguments: info pointer to device instance data
4201 * Return Value: None
4202 */
4203static void mgsl_add_device( struct mgsl_struct *info )
4204{
4205 info->next_device = NULL;
4206 info->line = mgsl_device_count;
4207 sprintf(info->device_name,"ttySL%d",info->line);
4208
4209 if (info->line < MAX_TOTAL_DEVICES) {
4210 if (maxframe[info->line])
4211 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 4212
4213 if (txdmabufs[info->line]) {
4214 info->num_tx_dma_buffers = txdmabufs[info->line];
4215 if (info->num_tx_dma_buffers < 1)
4216 info->num_tx_dma_buffers = 1;
4217 }
4218
4219 if (txholdbufs[info->line]) {
4220 info->num_tx_holding_buffers = txholdbufs[info->line];
4221 if (info->num_tx_holding_buffers < 1)
4222 info->num_tx_holding_buffers = 1;
4223 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4224 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4225 }
4226 }
4227
4228 mgsl_device_count++;
4229
4230 if ( !mgsl_device_list )
4231 mgsl_device_list = info;
4232 else {
4233 struct mgsl_struct *current_dev = mgsl_device_list;
4234 while( current_dev->next_device )
4235 current_dev = current_dev->next_device;
4236 current_dev->next_device = info;
4237 }
4238
4239 if ( info->max_frame_size < 4096 )
4240 info->max_frame_size = 4096;
4241 else if ( info->max_frame_size > 65535 )
4242 info->max_frame_size = 65535;
4243
4244 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4245 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4246 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4247 info->phys_memory_base, info->phys_lcr_base,
4248 info->max_frame_size );
4249 } else {
4250 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4251 info->device_name, info->io_base, info->irq_level, info->dma_level,
4252 info->max_frame_size );
4253 }
4254
af69c7f9 4255#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 4256 hdlcdev_init(info);
4257#endif
4258
4259} /* end of mgsl_add_device() */
4260
31f35939
AC		 4261static const struct tty_port_operations mgsl_port_ops = {
4262 .carrier_raised = carrier_raised,
fcc8ac18 4263 .dtr_rts = dtr_rts,
31f35939
AC		 4264};
4265
4266
1da177e4
LT		 4267/* mgsl_allocate_device()
4268 *
4269 * Allocate and initialize a device instance structure
4270 *
4271 * Arguments: none
4272 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4273 */
4274static struct mgsl_struct* mgsl_allocate_device(void)
4275{
4276 struct mgsl_struct *info;
4277
dd00cc48 4278 info = kzalloc(sizeof(struct mgsl_struct),
1da177e4
LT		 4279 GFP_KERNEL);
4280
4281 if (!info) {
4282 printk("Error can't allocate device instance data\n");
4283 } else {
44b7d1b3 4284 tty_port_init(&info->port);
31f35939 4285 info->port.ops = &mgsl_port_ops;
1da177e4 4286 info->magic = MGSL_MAGIC;
c4028958 4287 INIT_WORK(&info->task, mgsl_bh_handler);
1da177e4 4288 info->max_frame_size = 4096;
44b7d1b3
AC		 4289 info->port.close_delay = 5*HZ/10;
4290 info->port.closing_wait = 30*HZ;
1da177e4
LT		 4291 init_waitqueue_head(&info->status_event_wait_q);
4292 init_waitqueue_head(&info->event_wait_q);
4293 spin_lock_init(&info->irq_spinlock);
4294 spin_lock_init(&info->netlock);
4295 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
e06922aa 4296 info->idle_mode = HDLC_TXIDLE_FLAGS;
1da177e4
LT		 4297 info->num_tx_dma_buffers = 1;
4298 info->num_tx_holding_buffers = 0;
4299 }
4300
4301 return info;
4302
4303} /* end of mgsl_allocate_device()*/
4304
b68e31d0 4305static const struct tty_operations mgsl_ops = {
8a3ad104 4306 .install = mgsl_install,
1da177e4
LT		 4307 .open = mgsl_open,
4308 .close = mgsl_close,
4309 .write = mgsl_write,
4310 .put_char = mgsl_put_char,
4311 .flush_chars = mgsl_flush_chars,
4312 .write_room = mgsl_write_room,
4313 .chars_in_buffer = mgsl_chars_in_buffer,
4314 .flush_buffer = mgsl_flush_buffer,
4315 .ioctl = mgsl_ioctl,
4316 .throttle = mgsl_throttle,
4317 .unthrottle = mgsl_unthrottle,
4318 .send_xchar = mgsl_send_xchar,
4319 .break_ctl = mgsl_break,
4320 .wait_until_sent = mgsl_wait_until_sent,
1da177e4
LT		 4321 .set_termios = mgsl_set_termios,
4322 .stop = mgsl_stop,
4323 .start = mgsl_start,
4324 .hangup = mgsl_hangup,
4325 .tiocmget = tiocmget,
4326 .tiocmset = tiocmset,
0587102c 4327 .get_icount = msgl_get_icount,
d337829b 4328 .proc_fops = &mgsl_proc_fops,
1da177e4
LT		 4329};
4330
4331/*
4332 * perform tty device initialization
4333 */
4334static int mgsl_init_tty(void)
4335{
4336 int rc;
4337
4338 serial_driver = alloc_tty_driver(128);
4339 if (!serial_driver)
4340 return -ENOMEM;
4341
1da177e4
LT		 4342 serial_driver->driver_name = "synclink";
4343 serial_driver->name = "ttySL";
4344 serial_driver->major = ttymajor;
4345 serial_driver->minor_start = 64;
4346 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4347 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4348 serial_driver->init_termios = tty_std_termios;
4349 serial_driver->init_termios.c_cflag =
4350 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 4351 serial_driver->init_termios.c_ispeed = 9600;
4352 serial_driver->init_termios.c_ospeed = 9600;
1da177e4
LT		 4353 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4354 tty_set_operations(serial_driver, &mgsl_ops);
4355 if ((rc = tty_register_driver(serial_driver)) < 0) {
4356 printk("%s(%d):Couldn't register serial driver\n",
4357 __FILE__,__LINE__);
4358 put_tty_driver(serial_driver);
4359 serial_driver = NULL;
4360 return rc;
4361 }
4362
4363 printk("%s %s, tty major#%d\n",
4364 driver_name, driver_version,
4365 serial_driver->major);
4366 return 0;
4367}
4368
4369/* enumerate user specified ISA adapters
4370 */
4371static void mgsl_enum_isa_devices(void)
4372{
4373 struct mgsl_struct *info;
4374 int i;
4375
4376 /* Check for user specified ISA devices */
4377
4378 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4379 if ( debug_level >= DEBUG_LEVEL_INFO )
4380 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4381 io[i], irq[i], dma[i] );
4382
4383 info = mgsl_allocate_device();
4384 if ( !info ) {
4385 /* error allocating device instance data */
4386 if ( debug_level >= DEBUG_LEVEL_ERROR )
4387 printk( "can't allocate device instance data.\n");
4388 continue;
4389 }
4390
4391 /* Copy user configuration info to device instance data */
4392 info->io_base = (unsigned int)io[i];
4393 info->irq_level = (unsigned int)irq[i];
4394 info->irq_level = irq_canonicalize(info->irq_level);
4395 info->dma_level = (unsigned int)dma[i];
4396 info->bus_type = MGSL_BUS_TYPE_ISA;
4397 info->io_addr_size = 16;
4398 info->irq_flags = 0;
4399
4400 mgsl_add_device( info );
4401 }
4402}
4403
4404static void synclink_cleanup(void)
4405{
4406 int rc;
4407 struct mgsl_struct *info;
4408 struct mgsl_struct *tmp;
4409
4410 printk("Unloading %s: %s\n", driver_name, driver_version);
4411
4412 if (serial_driver) {
4413 if ((rc = tty_unregister_driver(serial_driver)))
4414 printk("%s(%d) failed to unregister tty driver err=%d\n",
4415 __FILE__,__LINE__,rc);
4416 put_tty_driver(serial_driver);
4417 }
4418
4419 info = mgsl_device_list;
4420 while(info) {
af69c7f9 4421#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 4422 hdlcdev_exit(info);
4423#endif
4424 mgsl_release_resources(info);
4425 tmp = info;
4426 info = info->next_device;
191c5f10 4427 tty_port_destroy(&tmp->port);
1da177e4
LT		 4428 kfree(tmp);
4429 }
4430
1da177e4
LT		 4431 if (pci_registered)
4432 pci_unregister_driver(&synclink_pci_driver);
4433}
4434
4435static int __init synclink_init(void)
4436{
4437 int rc;
4438
4439 if (break_on_load) {
4440 mgsl_get_text_ptr();
4441 BREAKPOINT();
4442 }
4443
4444 printk("%s %s\n", driver_name, driver_version);
4445
4446 mgsl_enum_isa_devices();
4447 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4448 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4449 else
0fab6de0 4450 pci_registered = true;
1da177e4
LT		 4451
4452 if ((rc = mgsl_init_tty()) < 0)
4453 goto error;
4454
4455 return 0;
4456
4457error:
4458 synclink_cleanup();
4459 return rc;
4460}
4461
4462static void __exit synclink_exit(void)
4463{
4464 synclink_cleanup();
4465}
4466
4467module_init(synclink_init);
4468module_exit(synclink_exit);
4469
4470/*
4471 * usc_RTCmd()
4472 *
4473 * Issue a USC Receive/Transmit command to the
4474 * Channel Command/Address Register (CCAR).
4475 *
4476 * Notes:
4477 *
4478 * The command is encoded in the most significant 5 bits <15..11>
4479 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4480 * and Bits <6..0> must be written as zeros.
4481 *
4482 * Arguments:
4483 *
4484 * info pointer to device information structure
4485 * Cmd command mask (use symbolic macros)
4486 *
4487 * Return Value:
4488 *
4489 * None
4490 */
4491static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4492{
4493 /* output command to CCAR in bits <15..11> */
4494 /* preserve bits <10..7>, bits <6..0> must be zero */
4495
4496 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4497
4498 /* Read to flush write to CCAR */
4499 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4500 inw( info->io_base + CCAR );
4501
4502} /* end of usc_RTCmd() */
4503
4504/*
4505 * usc_DmaCmd()
4506 *
4507 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4508 *
4509 * Arguments:
4510 *
4511 * info pointer to device information structure
4512 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4513 *
4514 * Return Value:
4515 *
4516 * None
4517 */
4518static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4519{
4520 /* write command mask to DCAR */
4521 outw( Cmd + info->mbre_bit, info->io_base );
4522
4523 /* Read to flush write to DCAR */
4524 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4525 inw( info->io_base );
4526
4527} /* end of usc_DmaCmd() */
4528
4529/*
4530 * usc_OutDmaReg()
4531 *
4532 * Write a 16-bit value to a USC DMA register
4533 *
4534 * Arguments:
4535 *
4536 * info pointer to device info structure
4537 * RegAddr register address (number) for write
4538 * RegValue 16-bit value to write to register
4539 *
4540 * Return Value:
4541 *
4542 * None
4543 *
4544 */
4545static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4546{
4547 /* Note: The DCAR is located at the adapter base address */
4548 /* Note: must preserve state of BIT8 in DCAR */
4549
4550 outw( RegAddr + info->mbre_bit, info->io_base );
4551 outw( RegValue, info->io_base );
4552
4553 /* Read to flush write to DCAR */
4554 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4555 inw( info->io_base );
4556
4557} /* end of usc_OutDmaReg() */
4558
4559/*
4560 * usc_InDmaReg()
4561 *
4562 * Read a 16-bit value from a DMA register
4563 *
4564 * Arguments:
4565 *
4566 * info pointer to device info structure
4567 * RegAddr register address (number) to read from
4568 *
4569 * Return Value:
4570 *
4571 * The 16-bit value read from register
4572 *
4573 */
4574static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4575{
4576 /* Note: The DCAR is located at the adapter base address */
4577 /* Note: must preserve state of BIT8 in DCAR */
4578
4579 outw( RegAddr + info->mbre_bit, info->io_base );
4580 return inw( info->io_base );
4581
4582} /* end of usc_InDmaReg() */
4583
4584/*
4585 *
4586 * usc_OutReg()
4587 *
4588 * Write a 16-bit value to a USC serial channel register
4589 *
4590 * Arguments:
4591 *
4592 * info pointer to device info structure
4593 * RegAddr register address (number) to write to
4594 * RegValue 16-bit value to write to register
4595 *
4596 * Return Value:
4597 *
4598 * None
4599 *
4600 */
4601static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4602{
4603 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4604 outw( RegValue, info->io_base + CCAR );
4605
4606 /* Read to flush write to CCAR */
4607 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4608 inw( info->io_base + CCAR );
4609
4610} /* end of usc_OutReg() */
4611
4612/*
4613 * usc_InReg()
4614 *
4615 * Reads a 16-bit value from a USC serial channel register
4616 *
4617 * Arguments:
4618 *
4619 * info pointer to device extension
4620 * RegAddr register address (number) to read from
4621 *
4622 * Return Value:
4623 *
4624 * 16-bit value read from register
4625 */
4626static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4627{
4628 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4629 return inw( info->io_base + CCAR );
4630
4631} /* end of usc_InReg() */
4632
4633/* usc_set_sdlc_mode()
4634 *
4635 * Set up the adapter for SDLC DMA communications.
4636 *
4637 * Arguments: info pointer to device instance data
4638 * Return Value: NONE
4639 */
4640static void usc_set_sdlc_mode( struct mgsl_struct *info )
4641{
4642 u16 RegValue;
0fab6de0 4643 bool PreSL1660;
1da177e4
LT		 4644
4645 /*
4646 * determine if the IUSC on the adapter is pre-SL1660. If
4647 * not, take advantage of the UnderWait feature of more
4648 * modern chips. If an underrun occurs and this bit is set,
4649 * the transmitter will idle the programmed idle pattern
4650 * until the driver has time to service the underrun. Otherwise,
4651 * the dma controller may get the cycles previously requested
4652 * and begin transmitting queued tx data.
4653 */
4654 usc_OutReg(info,TMCR,0x1f);
4655 RegValue=usc_InReg(info,TMDR);
0fab6de0 4656 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
1da177e4
LT		 4657
4658 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4659 {
4660 /*
4661 ** Channel Mode Register (CMR)
4662 **
4663 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4664 ** <13> 0 0 = Transmit Disabled (initially)
4665 ** <12> 0 1 = Consecutive Idles share common 0
4666 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4667 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4668 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4669 **
4670 ** 1000 1110 0000 0110 = 0x8e06
4671 */
4672 RegValue = 0x8e06;
4673
4674 /*--------------------------------------------------
4675 * ignore user options for UnderRun Actions and
4676 * preambles
4677 *--------------------------------------------------*/
4678 }
4679 else
4680 {
4681 /* Channel mode Register (CMR)
4682 *
4683 * <15..14> 00 Tx Sub modes, Underrun Action
4684 * <13> 0 1 = Send Preamble before opening flag
4685 * <12> 0 1 = Consecutive Idles share common 0
4686 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4687 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4688 * <3..0> 0110 Receiver mode = HDLC/SDLC
4689 *
4690 * 0000 0110 0000 0110 = 0x0606
4691 */
4692 if (info->params.mode == MGSL_MODE_RAW) {
4693 RegValue = 0x0001; /* Set Receive mode = external sync */
4694
4695 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4696 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4697
4698 /*
4699 * TxSubMode:
4700 * CMR <15> 0 Don't send CRC on Tx Underrun
4701 * CMR <14> x undefined
4702 * CMR <13> 0 Send preamble before openning sync
4703 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4704 *
4705 * TxMode:
4706 * CMR <11-8) 0100 MonoSync
4707 *
4708 * 0x00 0100 xxxx xxxx 04xx
4709 */
4710 RegValue |= 0x0400;
4711 }
4712 else {
4713
4714 RegValue = 0x0606;
4715
4716 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4717 RegValue |= BIT14;
4718 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4719 RegValue |= BIT15;
4720 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
e06922aa 4721 RegValue |= BIT15 | BIT14;
1da177e4
LT		 4722 }
4723
4724 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4725 RegValue |= BIT13;
4726 }
4727
4728 if ( info->params.mode == MGSL_MODE_HDLC &&
4729 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4730 RegValue |= BIT12;
4731
4732 if ( info->params.addr_filter != 0xff )
4733 {
4734 /* set up receive address filtering */
4735 usc_OutReg( info, RSR, info->params.addr_filter );
4736 RegValue |= BIT4;
4737 }
4738
4739 usc_OutReg( info, CMR, RegValue );
4740 info->cmr_value = RegValue;
4741
4742 /* Receiver mode Register (RMR)
4743 *
4744 * <15..13> 000 encoding
4745 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4746 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4747 * <9> 0 1 = Include Receive chars in CRC
4748 * <8> 1 1 = Use Abort/PE bit as abort indicator
4749 * <7..6> 00 Even parity
4750 * <5> 0 parity disabled
4751 * <4..2> 000 Receive Char Length = 8 bits
4752 * <1..0> 00 Disable Receiver
4753 *
4754 * 0000 0101 0000 0000 = 0x0500
4755 */
4756
4757 RegValue = 0x0500;
4758
4759 switch ( info->params.encoding ) {
4760 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4761 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
e06922aa 4762 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
1da177e4 4763 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
e06922aa
AJ		 4764 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
4765 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
4766 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
1da177e4
LT		 4767 }
4768
4769 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4770 RegValue |= BIT9;
4771 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4772 RegValue |= ( BIT12 | BIT10 | BIT9 );
4773
4774 usc_OutReg( info, RMR, RegValue );
4775
4776 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4777 /* When an opening flag of an SDLC frame is recognized the */
4778 /* Receive Character count (RCC) is loaded with the value in */
4779 /* RCLR. The RCC is decremented for each received byte. The */
4780 /* value of RCC is stored after the closing flag of the frame */
4781 /* allowing the frame size to be computed. */
4782
4783 usc_OutReg( info, RCLR, RCLRVALUE );
4784
4785 usc_RCmd( info, RCmd_SelectRicrdma_level );
4786
4787 /* Receive Interrupt Control Register (RICR)
4788 *
4789 * <15..8> ? RxFIFO DMA Request Level
4790 * <7> 0 Exited Hunt IA (Interrupt Arm)
4791 * <6> 0 Idle Received IA
4792 * <5> 0 Break/Abort IA
4793 * <4> 0 Rx Bound IA
4794 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4795 * <2> 0 Abort/PE IA
4796 * <1> 1 Rx Overrun IA
4797 * <0> 0 Select TC0 value for readback
4798 *
4799 * 0000 0000 0000 1000 = 0x000a
4800 */
4801
4802 /* Carry over the Exit Hunt and Idle Received bits */
4803 /* in case they have been armed by usc_ArmEvents. */
4804
4805 RegValue = usc_InReg( info, RICR ) & 0xc0;
4806
4807 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4808 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4809 else
4810 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4811
4812 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4813
4814 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4815 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4816
4817 /* Transmit mode Register (TMR)
4818 *
4819 * <15..13> 000 encoding
4820 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4821 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4822 * <9> 0 1 = Tx CRC Enabled
4823 * <8> 0 1 = Append CRC to end of transmit frame
4824 * <7..6> 00 Transmit parity Even
4825 * <5> 0 Transmit parity Disabled
4826 * <4..2> 000 Tx Char Length = 8 bits
4827 * <1..0> 00 Disable Transmitter
4828 *
4829 * 0000 0100 0000 0000 = 0x0400
4830 */
4831
4832 RegValue = 0x0400;
4833
4834 switch ( info->params.encoding ) {
4835 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4836 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
e06922aa 4837 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
1da177e4 4838 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
e06922aa
AJ		 4839 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
4840 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
4841 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
1da177e4
LT		 4842 }
4843
4844 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
e06922aa 4845 RegValue |= BIT9 | BIT8;
1da177e4
LT		 4846 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4847 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4848
4849 usc_OutReg( info, TMR, RegValue );
4850
4851 usc_set_txidle( info );
4852
4853
4854 usc_TCmd( info, TCmd_SelectTicrdma_level );
4855
4856 /* Transmit Interrupt Control Register (TICR)
4857 *
4858 * <15..8> ? Transmit FIFO DMA Level
4859 * <7> 0 Present IA (Interrupt Arm)
4860 * <6> 0 Idle Sent IA
4861 * <5> 1 Abort Sent IA
4862 * <4> 1 EOF/EOM Sent IA
4863 * <3> 0 CRC Sent IA
4864 * <2> 1 1 = Wait for SW Trigger to Start Frame
4865 * <1> 1 Tx Underrun IA
4866 * <0> 0 TC0 constant on read back
4867 *
4868 * 0000 0000 0011 0110 = 0x0036
4869 */
4870
4871 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4872 usc_OutReg( info, TICR, 0x0736 );
4873 else
4874 usc_OutReg( info, TICR, 0x1436 );
4875
4876 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4877 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4878
4879 /*
4880 ** Transmit Command/Status Register (TCSR)
4881 **
4882 ** <15..12> 0000 TCmd
4883 ** <11> 0/1 UnderWait
4884 ** <10..08> 000 TxIdle
4885 ** <7> x PreSent
4886 ** <6> x IdleSent
4887 ** <5> x AbortSent
4888 ** <4> x EOF/EOM Sent
4889 ** <3> x CRC Sent
4890 ** <2> x All Sent
4891 ** <1> x TxUnder
4892 ** <0> x TxEmpty
4893 **
4894 ** 0000 0000 0000 0000 = 0x0000
4895 */
4896 info->tcsr_value = 0;
4897
4898 if ( !PreSL1660 )
4899 info->tcsr_value |= TCSR_UNDERWAIT;
4900
4901 usc_OutReg( info, TCSR, info->tcsr_value );
4902
4903 /* Clock mode Control Register (CMCR)
4904 *
4905 * <15..14> 00 counter 1 Source = Disabled
4906 * <13..12> 00 counter 0 Source = Disabled
4907 * <11..10> 11 BRG1 Input is TxC Pin
4908 * <9..8> 11 BRG0 Input is TxC Pin
4909 * <7..6> 01 DPLL Input is BRG1 Output
4910 * <5..3> XXX TxCLK comes from Port 0
4911 * <2..0> XXX RxCLK comes from Port 1
4912 *
4913 * 0000 1111 0111 0111 = 0x0f77
4914 */
4915
4916 RegValue = 0x0f40;
4917
4918 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4919 RegValue |= 0x0003; /* RxCLK from DPLL */
4920 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4921 RegValue |= 0x0004; /* RxCLK from BRG0 */
4922 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4923 RegValue |= 0x0006; /* RxCLK from TXC Input */
4924 else
4925 RegValue |= 0x0007; /* RxCLK from Port1 */
4926
4927 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4928 RegValue |= 0x0018; /* TxCLK from DPLL */
4929 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4930 RegValue |= 0x0020; /* TxCLK from BRG0 */
4931 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4932 RegValue |= 0x0038; /* RxCLK from TXC Input */
4933 else
4934 RegValue |= 0x0030; /* TxCLK from Port0 */
4935
4936 usc_OutReg( info, CMCR, RegValue );
4937
4938
4939 /* Hardware Configuration Register (HCR)
4940 *
4941 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4942 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4943 * <12> 0 CVOK:0=report code violation in biphase
4944 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4945 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4946 * <7..6> 00 reserved
4947 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4948 * <4> X BRG1 Enable
4949 * <3..2> 00 reserved
4950 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4951 * <0> 0 BRG0 Enable
4952 */
4953
4954 RegValue = 0x0000;
4955
e06922aa 4956 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL | HDLC_FLAG_TXC_DPLL) ) {
1da177e4
LT		 4957 u32 XtalSpeed;
4958 u32 DpllDivisor;
4959 u16 Tc;
4960
4961 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4962 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4963
4964 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4965 XtalSpeed = 11059200;
4966 else
4967 XtalSpeed = 14745600;
4968
4969 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4970 DpllDivisor = 16;
4971 RegValue |= BIT10;
4972 }
4973 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4974 DpllDivisor = 8;
4975 RegValue |= BIT11;
4976 }
4977 else
4978 DpllDivisor = 32;
4979
4980 /* Tc = (Xtal/Speed) - 1 */
4981 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4982 /* then rounding up gives a more precise time constant. Instead */
4983 /* of rounding up and then subtracting 1 we just don't subtract */
4984 /* the one in this case. */
4985
4986 /*--------------------------------------------------
4987 * ejz: for DPLL mode, application should use the
4988 * same clock speed as the partner system, even
4989 * though clocking is derived from the input RxData.
4990 * In case the user uses a 0 for the clock speed,
4991 * default to 0xffffffff and don't try to divide by
4992 * zero
4993 *--------------------------------------------------*/
4994 if ( info->params.clock_speed )
4995 {
4996 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4997 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4998 / info->params.clock_speed) )
4999 Tc--;
5000 }
5001 else
5002 Tc = -1;
5003
5004
5005 /* Write 16-bit Time Constant for BRG1 */
5006 usc_OutReg( info, TC1R, Tc );
5007
5008 RegValue |= BIT4; /* enable BRG1 */
5009
5010 switch ( info->params.encoding ) {
5011 case HDLC_ENCODING_NRZ:
5012 case HDLC_ENCODING_NRZB:
5013 case HDLC_ENCODING_NRZI_MARK:
5014 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5015 case HDLC_ENCODING_BIPHASE_MARK:
5016 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5017 case HDLC_ENCODING_BIPHASE_LEVEL:
e06922aa 5018 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break;
1da177e4
LT		 5019 }
5020 }
5021
5022 usc_OutReg( info, HCR, RegValue );
5023
5024
5025 /* Channel Control/status Register (CCSR)
5026 *
5027 * <15> X RCC FIFO Overflow status (RO)
5028 * <14> X RCC FIFO Not Empty status (RO)
5029 * <13> 0 1 = Clear RCC FIFO (WO)
5030 * <12> X DPLL Sync (RW)
5031 * <11> X DPLL 2 Missed Clocks status (RO)
5032 * <10> X DPLL 1 Missed Clock status (RO)
5033 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5034 * <7> X SDLC Loop On status (RO)
5035 * <6> X SDLC Loop Send status (RO)
5036 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5037 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5038 * <1..0> 00 reserved
5039 *
5040 * 0000 0000 0010 0000 = 0x0020
5041 */
5042
5043 usc_OutReg( info, CCSR, 0x1020 );
5044
5045
5046 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5047 usc_OutReg( info, SICR,
5048 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5049 }
5050
5051
5052 /* enable Master Interrupt Enable bit (MIE) */
5053 usc_EnableMasterIrqBit( info );
5054
e06922aa
AJ		 5055 usc_ClearIrqPendingBits( info, RECEIVE_STATUS | RECEIVE_DATA |
5056 TRANSMIT_STATUS | TRANSMIT_DATA | MISC);
1da177e4
LT		 5057
5058 /* arm RCC underflow interrupt */
5059 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5060 usc_EnableInterrupts(info, MISC);
5061
5062 info->mbre_bit = 0;
5063 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5064 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5065 info->mbre_bit = BIT8;
5066 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5067
5068 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5069 /* Enable DMAEN (Port 7, Bit 14) */
5070 /* This connects the DMA request signal to the ISA bus */
5071 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5072 }
5073
5074 /* DMA Control Register (DCR)
5075 *
5076 * <15..14> 10 Priority mode = Alternating Tx/Rx
5077 * 01 Rx has priority
5078 * 00 Tx has priority
5079 *
5080 * <13> 1 Enable Priority Preempt per DCR<15..14>
5081 * (WARNING DCR<11..10> must be 00 when this is 1)
5082 * 0 Choose activate channel per DCR<11..10>
5083 *
5084 * <12> 0 Little Endian for Array/List
5085 * <11..10> 00 Both Channels can use each bus grant
5086 * <9..6> 0000 reserved
5087 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5088 * <4> 0 1 = drive D/C and S/D pins
5089 * <3> 1 1 = Add one wait state to all DMA cycles.
5090 * <2> 0 1 = Strobe /UAS on every transfer.
5091 * <1..0> 11 Addr incrementing only affects LS24 bits
5092 *
5093 * 0110 0000 0000 1011 = 0x600b
5094 */
5095
5096 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5097 /* PCI adapter does not need DMA wait state */
5098 usc_OutDmaReg( info, DCR, 0xa00b );
5099 }
5100 else
5101 usc_OutDmaReg( info, DCR, 0x800b );
5102
5103
5104 /* Receive DMA mode Register (RDMR)
5105 *
5106 * <15..14> 11 DMA mode = Linked List Buffer mode
5107 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5108 * <12> 1 Clear count of List Entry after fetching
5109 * <11..10> 00 Address mode = Increment
5110 * <9> 1 Terminate Buffer on RxBound
5111 * <8> 0 Bus Width = 16bits
5112 * <7..0> ? status Bits (write as 0s)
5113 *
5114 * 1111 0010 0000 0000 = 0xf200
5115 */
5116
5117 usc_OutDmaReg( info, RDMR, 0xf200 );
5118
5119
5120 /* Transmit DMA mode Register (TDMR)
5121 *
5122 * <15..14> 11 DMA mode = Linked List Buffer mode
5123 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5124 * <12> 1 Clear count of List Entry after fetching
5125 * <11..10> 00 Address mode = Increment
5126 * <9> 1 Terminate Buffer on end of frame
5127 * <8> 0 Bus Width = 16bits
5128 * <7..0> ? status Bits (Read Only so write as 0)
5129 *
5130 * 1111 0010 0000 0000 = 0xf200
5131 */
5132
5133 usc_OutDmaReg( info, TDMR, 0xf200 );
5134
5135
5136 /* DMA Interrupt Control Register (DICR)
5137 *
5138 * <15> 1 DMA Interrupt Enable
5139 * <14> 0 1 = Disable IEO from USC
5140 * <13> 0 1 = Don't provide vector during IntAck
5141 * <12> 1 1 = Include status in Vector
5142 * <10..2> 0 reserved, Must be 0s
5143 * <1> 0 1 = Rx DMA Interrupt Enabled
5144 * <0> 0 1 = Tx DMA Interrupt Enabled
5145 *
5146 * 1001 0000 0000 0000 = 0x9000
5147 */
5148
5149 usc_OutDmaReg( info, DICR, 0x9000 );
5150
5151 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5152 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5153 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5154
5155 /* Channel Control Register (CCR)
5156 *
5157 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5158 * <13> 0 Trigger Tx on SW Command Disabled
5159 * <12> 0 Flag Preamble Disabled
5160 * <11..10> 00 Preamble Length
5161 * <9..8> 00 Preamble Pattern
5162 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5163 * <5> 0 Trigger Rx on SW Command Disabled
5164 * <4..0> 0 reserved
5165 *
5166 * 1000 0000 1000 0000 = 0x8080
5167 */
5168
5169 RegValue = 0x8080;
5170
5171 switch ( info->params.preamble_length ) {
5172 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5173 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
e06922aa 5174 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break;
1da177e4
LT		 5175 }
5176
5177 switch ( info->params.preamble ) {
e06922aa 5178 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
1da177e4
LT		 5179 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5180 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
e06922aa 5181 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break;
1da177e4
LT		 5182 }
5183
5184 usc_OutReg( info, CCR, RegValue );
5185
5186
5187 /*
5188 * Burst/Dwell Control Register
5189 *
5190 * <15..8> 0x20 Maximum number of transfers per bus grant
5191 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5192 */
5193
5194 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5195 /* don't limit bus occupancy on PCI adapter */
5196 usc_OutDmaReg( info, BDCR, 0x0000 );
5197 }
5198 else
5199 usc_OutDmaReg( info, BDCR, 0x2000 );
5200
5201 usc_stop_transmitter(info);
5202 usc_stop_receiver(info);
5203
5204} /* end of usc_set_sdlc_mode() */
5205
5206/* usc_enable_loopback()
5207 *
5208 * Set the 16C32 for internal loopback mode.
5209 * The TxCLK and RxCLK signals are generated from the BRG0 and
5210 * the TxD is looped back to the RxD internally.
5211 *
5212 * Arguments: info pointer to device instance data
5213 * enable 1 = enable loopback, 0 = disable
5214 * Return Value: None
5215 */
5216static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5217{
5218 if (enable) {
5219 /* blank external TXD output */
e06922aa 5220 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6));
1da177e4
LT		 5221
5222 /* Clock mode Control Register (CMCR)
5223 *
5224 * <15..14> 00 counter 1 Disabled
5225 * <13..12> 00 counter 0 Disabled
5226 * <11..10> 11 BRG1 Input is TxC Pin
5227 * <9..8> 11 BRG0 Input is TxC Pin
5228 * <7..6> 01 DPLL Input is BRG1 Output
5229 * <5..3> 100 TxCLK comes from BRG0
5230 * <2..0> 100 RxCLK comes from BRG0
5231 *
5232 * 0000 1111 0110 0100 = 0x0f64
5233 */
5234
5235 usc_OutReg( info, CMCR, 0x0f64 );
5236
5237 /* Write 16-bit Time Constant for BRG0 */
5238 /* use clock speed if available, otherwise use 8 for diagnostics */
5239 if (info->params.clock_speed) {
5240 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5241 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5242 else
5243 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5244 } else
5245 usc_OutReg(info, TC0R, (u16)8);
5246
5247 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5248 mode = Continuous Set Bit 0 to enable BRG0. */
5249 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5250
5251 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5252 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5253
5254 /* set Internal Data loopback mode */
5255 info->loopback_bits = 0x300;
5256 outw( 0x0300, info->io_base + CCAR );
5257 } else {
5258 /* enable external TXD output */
e06922aa 5259 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6));
1da177e4
LT		 5260
5261 /* clear Internal Data loopback mode */
5262 info->loopback_bits = 0;
5263 outw( 0,info->io_base + CCAR );
5264 }
5265
5266} /* end of usc_enable_loopback() */
5267
5268/* usc_enable_aux_clock()
5269 *
5270 * Enabled the AUX clock output at the specified frequency.
5271 *
5272 * Arguments:
5273 *
5274 * info pointer to device extension
5275 * data_rate data rate of clock in bits per second
5276 * A data rate of 0 disables the AUX clock.
5277 *
5278 * Return Value: None
5279 */
5280static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5281{
5282 u32 XtalSpeed;
5283 u16 Tc;
5284
5285 if ( data_rate ) {
5286 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5287 XtalSpeed = 11059200;
5288 else
5289 XtalSpeed = 14745600;
5290
5291
5292 /* Tc = (Xtal/Speed) - 1 */
5293 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5294 /* then rounding up gives a more precise time constant. Instead */
5295 /* of rounding up and then subtracting 1 we just don't subtract */
5296 /* the one in this case. */
5297
5298
5299 Tc = (u16)(XtalSpeed/data_rate);
5300 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5301 Tc--;
5302
5303 /* Write 16-bit Time Constant for BRG0 */
5304 usc_OutReg( info, TC0R, Tc );
5305
5306 /*
5307 * Hardware Configuration Register (HCR)
5308 * Clear Bit 1, BRG0 mode = Continuous
5309 * Set Bit 0 to enable BRG0.
5310 */
5311
5312 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5313
5314 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5315 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5316 } else {
5317 /* data rate == 0 so turn off BRG0 */
5318 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5319 }
5320
5321} /* end of usc_enable_aux_clock() */
5322
5323/*
5324 *
5325 * usc_process_rxoverrun_sync()
5326 *
5327 * This function processes a receive overrun by resetting the
5328 * receive DMA buffers and issuing a Purge Rx FIFO command
5329 * to allow the receiver to continue receiving.
5330 *
5331 * Arguments:
5332 *
5333 * info pointer to device extension
5334 *
5335 * Return Value: None
5336 */
5337static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5338{
5339 int start_index;
5340 int end_index;
5341 int frame_start_index;
0fab6de0
JP		 5342 bool start_of_frame_found = false;
5343 bool end_of_frame_found = false;
5344 bool reprogram_dma = false;
1da177e4
LT		 5345
5346 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5347 u32 phys_addr;
5348
5349 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5350 usc_RCmd( info, RCmd_EnterHuntmode );
5351 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5352
5353 /* CurrentRxBuffer points to the 1st buffer of the next */
5354 /* possibly available receive frame. */
5355
5356 frame_start_index = start_index = end_index = info->current_rx_buffer;
5357
5358 /* Search for an unfinished string of buffers. This means */
5359 /* that a receive frame started (at least one buffer with */
5360 /* count set to zero) but there is no terminiting buffer */
5361 /* (status set to non-zero). */
5362
5363 while( !buffer_list[end_index].count )
5364 {
5365 /* Count field has been reset to zero by 16C32. */
5366 /* This buffer is currently in use. */
5367
5368 if ( !start_of_frame_found )
5369 {
0fab6de0 5370 start_of_frame_found = true;
1da177e4 5371 frame_start_index = end_index;
0fab6de0 5372 end_of_frame_found = false;
1da177e4
LT		 5373 }
5374
5375 if ( buffer_list[end_index].status )
5376 {
5377 /* Status field has been set by 16C32. */
5378 /* This is the last buffer of a received frame. */
5379
5380 /* We want to leave the buffers for this frame intact. */
5381 /* Move on to next possible frame. */
5382
0fab6de0
JP		 5383 start_of_frame_found = false;
5384 end_of_frame_found = true;
1da177e4
LT		 5385 }
5386
5387 /* advance to next buffer entry in linked list */
5388 end_index++;
5389 if ( end_index == info->rx_buffer_count )
5390 end_index = 0;
5391
5392 if ( start_index == end_index )
5393 {
5394 /* The entire list has been searched with all Counts == 0 and */
5395 /* all Status == 0. The receive buffers are */
5396 /* completely screwed, reset all receive buffers! */
5397 mgsl_reset_rx_dma_buffers( info );
5398 frame_start_index = 0;
0fab6de0
JP		 5399 start_of_frame_found = false;
5400 reprogram_dma = true;
1da177e4
LT		 5401 break;
5402 }
5403 }
5404
5405 if ( start_of_frame_found && !end_of_frame_found )
5406 {
5407 /* There is an unfinished string of receive DMA buffers */
5408 /* as a result of the receiver overrun. */
5409
5410 /* Reset the buffers for the unfinished frame */
5411 /* and reprogram the receive DMA controller to start */
5412 /* at the 1st buffer of unfinished frame. */
5413
5414 start_index = frame_start_index;
5415
5416 do
5417 {
5418 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5419
5420 /* Adjust index for wrap around. */
5421 if ( start_index == info->rx_buffer_count )
5422 start_index = 0;
5423
5424 } while( start_index != end_index );
5425
0fab6de0 5426 reprogram_dma = true;
1da177e4
LT		 5427 }
5428
5429 if ( reprogram_dma )
5430 {
5431 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5432 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5433 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5434
5435 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5436
5437 /* This empties the receive FIFO and loads the RCC with RCLR */
5438 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5439
5440 /* program 16C32 with physical address of 1st DMA buffer entry */
5441 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5442 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5443 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5444
5445 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
e06922aa 5446 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
1da177e4
LT		 5447 usc_EnableInterrupts( info, RECEIVE_STATUS );
5448
5449 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5450 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5451
e06922aa 5452 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
1da177e4
LT		 5453 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5454 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5455 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5456 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5457 else
5458 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5459 }
5460 else
5461 {
5462 /* This empties the receive FIFO and loads the RCC with RCLR */
5463 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5464 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5465 }
5466
5467} /* end of usc_process_rxoverrun_sync() */
5468
5469/* usc_stop_receiver()
5470 *
5471 * Disable USC receiver
5472 *
5473 * Arguments: info pointer to device instance data
5474 * Return Value: None
5475 */
5476static void usc_stop_receiver( struct mgsl_struct *info )
5477{
5478 if (debug_level >= DEBUG_LEVEL_ISR)
5479 printk("%s(%d):usc_stop_receiver(%s)\n",
5480 __FILE__,__LINE__, info->device_name );
5481
5482 /* Disable receive DMA channel. */
5483 /* This also disables receive DMA channel interrupts */
5484 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5485
5486 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
e06922aa
AJ		 5487 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5488 usc_DisableInterrupts( info, RECEIVE_DATA | RECEIVE_STATUS );
1da177e4
LT		 5489
5490 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5491
5492 /* This empties the receive FIFO and loads the RCC with RCLR */
5493 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5494 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5495
0fab6de0
JP		 5496 info->rx_enabled = false;
5497 info->rx_overflow = false;
5498 info->rx_rcc_underrun = false;
1da177e4
LT		 5499
5500} /* end of stop_receiver() */
5501
5502/* usc_start_receiver()
5503 *
5504 * Enable the USC receiver
5505 *
5506 * Arguments: info pointer to device instance data
5507 * Return Value: None
5508 */
5509static void usc_start_receiver( struct mgsl_struct *info )
5510{
5511 u32 phys_addr;
5512
5513 if (debug_level >= DEBUG_LEVEL_ISR)
5514 printk("%s(%d):usc_start_receiver(%s)\n",
5515 __FILE__,__LINE__, info->device_name );
5516
5517 mgsl_reset_rx_dma_buffers( info );
5518 usc_stop_receiver( info );
5519
5520 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5521 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5522
5523 if ( info->params.mode == MGSL_MODE_HDLC ||
5524 info->params.mode == MGSL_MODE_RAW ) {
5525 /* DMA mode Transfers */
5526 /* Program the DMA controller. */
5527 /* Enable the DMA controller end of buffer interrupt. */
5528
5529 /* program 16C32 with physical address of 1st DMA buffer entry */
5530 phys_addr = info->rx_buffer_list[0].phys_entry;
5531 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5532 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5533
5534 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
e06922aa 5535 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
1da177e4
LT		 5536 usc_EnableInterrupts( info, RECEIVE_STATUS );
5537
5538 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5539 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5540
e06922aa 5541 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
1da177e4
LT		 5542 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5543 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5544 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5545 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5546 else
5547 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5548 } else {
5549 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
e06922aa 5550 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
1da177e4
LT		 5551 usc_EnableInterrupts(info, RECEIVE_DATA);
5552
5553 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5554 usc_RCmd( info, RCmd_EnterHuntmode );
5555
5556 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5557 }
5558
5559 usc_OutReg( info, CCSR, 0x1020 );
5560
0fab6de0 5561 info->rx_enabled = true;
1da177e4
LT		 5562
5563} /* end of usc_start_receiver() */
5564
5565/* usc_start_transmitter()
5566 *
5567 * Enable the USC transmitter and send a transmit frame if
5568 * one is loaded in the DMA buffers.
5569 *
5570 * Arguments: info pointer to device instance data
5571 * Return Value: None
5572 */
5573static void usc_start_transmitter( struct mgsl_struct *info )
5574{
5575 u32 phys_addr;
5576 unsigned int FrameSize;
5577
5578 if (debug_level >= DEBUG_LEVEL_ISR)
5579 printk("%s(%d):usc_start_transmitter(%s)\n",
5580 __FILE__,__LINE__, info->device_name );
5581
5582 if ( info->xmit_cnt ) {
5583
5584 /* If auto RTS enabled and RTS is inactive, then assert */
5585 /* RTS and set a flag indicating that the driver should */
5586 /* negate RTS when the transmission completes. */
5587
0fab6de0 5588 info->drop_rts_on_tx_done = false;
1da177e4
LT		 5589
5590 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5591 usc_get_serial_signals( info );
5592 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5593 info->serial_signals |= SerialSignal_RTS;
5594 usc_set_serial_signals( info );
0fab6de0 5595 info->drop_rts_on_tx_done = true;
1da177e4
LT		 5596 }
5597 }
5598
5599
5600 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5601 if ( !info->tx_active ) {
5602 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5603 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5604 usc_EnableInterrupts(info, TRANSMIT_DATA);
5605 usc_load_txfifo(info);
5606 }
5607 } else {
5608 /* Disable transmit DMA controller while programming. */
5609 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5610
5611 /* Transmit DMA buffer is loaded, so program USC */
5612 /* to send the frame contained in the buffers. */
5613
5614 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5615
5616 /* if operating in Raw sync mode, reset the rcc component
5617 * of the tx dma buffer entry, otherwise, the serial controller
5618 * will send a closing sync char after this count.
5619 */
5620 if ( info->params.mode == MGSL_MODE_RAW )
5621 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5622
5623 /* Program the Transmit Character Length Register (TCLR) */
5624 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5625 usc_OutReg( info, TCLR, (u16)FrameSize );
5626
5627 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5628
5629 /* Program the address of the 1st DMA Buffer Entry in linked list */
5630 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5631 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5632 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5633
5634 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5635 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5636 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5637
5638 if ( info->params.mode == MGSL_MODE_RAW &&
5639 info->num_tx_dma_buffers > 1 ) {
5640 /* When running external sync mode, attempt to 'stream' transmit */
5641 /* by filling tx dma buffers as they become available. To do this */
5642 /* we need to enable Tx DMA EOB Status interrupts : */
5643 /* */
5644 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5645 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5646
5647 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5648 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5649 }
5650
5651 /* Initialize Transmit DMA Channel */
5652 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5653
5654 usc_TCmd( info, TCmd_SendFrame );
5655
40565f19
JS		 5656 mod_timer(&info->tx_timer, jiffies +
5657 msecs_to_jiffies(5000));
1da177e4 5658 }
0fab6de0 5659 info->tx_active = true;
1da177e4
LT		 5660 }
5661
5662 if ( !info->tx_enabled ) {
0fab6de0 5663 info->tx_enabled = true;
1da177e4
LT		 5664 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5665 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5666 else
5667 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5668 }
5669
5670} /* end of usc_start_transmitter() */
5671
5672/* usc_stop_transmitter()
5673 *
5674 * Stops the transmitter and DMA
5675 *
5676 * Arguments: info pointer to device isntance data
5677 * Return Value: None
5678 */
5679static void usc_stop_transmitter( struct mgsl_struct *info )
5680{
5681 if (debug_level >= DEBUG_LEVEL_ISR)
5682 printk("%s(%d):usc_stop_transmitter(%s)\n",
5683 __FILE__,__LINE__, info->device_name );
5684
5685 del_timer(&info->tx_timer);
5686
5687 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5688 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5689 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5690
5691 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5692 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5693 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5694
0fab6de0
JP		 5695 info->tx_enabled = false;
5696 info->tx_active = false;
1da177e4
LT		 5697
5698} /* end of usc_stop_transmitter() */
5699
5700/* usc_load_txfifo()
5701 *
5702 * Fill the transmit FIFO until the FIFO is full or
5703 * there is no more data to load.
5704 *
5705 * Arguments: info pointer to device extension (instance data)
5706 * Return Value: None
5707 */
5708static void usc_load_txfifo( struct mgsl_struct *info )
5709{
5710 int Fifocount;
5711 u8 TwoBytes[2];
5712
5713 if ( !info->xmit_cnt && !info->x_char )
5714 return;
5715
5716 /* Select transmit FIFO status readback in TICR */
5717 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5718
5719 /* load the Transmit FIFO until FIFOs full or all data sent */
5720
5721 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5722 /* there is more space in the transmit FIFO and */
5723 /* there is more data in transmit buffer */
5724
5725 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5726 /* write a 16-bit word from transmit buffer to 16C32 */
5727
5728 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5729 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5730 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5731 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5732
5733 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5734
5735 info->xmit_cnt -= 2;
5736 info->icount.tx += 2;
5737 } else {
5738 /* only 1 byte left to transmit or 1 FIFO slot left */
5739
5740 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5741 info->io_base + CCAR );
5742
5743 if (info->x_char) {
5744 /* transmit pending high priority char */
5745 outw( info->x_char,info->io_base + CCAR );
5746 info->x_char = 0;
5747 } else {
5748 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5749 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5750 info->xmit_cnt--;
5751 }
5752 info->icount.tx++;
5753 }
5754 }
5755
5756} /* end of usc_load_txfifo() */
5757
5758/* usc_reset()
5759 *
5760 * Reset the adapter to a known state and prepare it for further use.
5761 *
5762 * Arguments: info pointer to device instance data
5763 * Return Value: None
5764 */
5765static void usc_reset( struct mgsl_struct *info )
5766{
5767 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5768 int i;
5769 u32 readval;
5770
5771 /* Set BIT30 of Misc Control Register */
5772 /* (Local Control Register 0x50) to force reset of USC. */
5773
5774 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5775 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5776
5777 info->misc_ctrl_value |= BIT30;
5778 *MiscCtrl = info->misc_ctrl_value;
5779
5780 /*
5781 * Force at least 170ns delay before clearing
5782 * reset bit. Each read from LCR takes at least
5783 * 30ns so 10 times for 300ns to be safe.
5784 */
5785 for(i=0;i<10;i++)
5786 readval = *MiscCtrl;
5787
5788 info->misc_ctrl_value &= ~BIT30;
5789 *MiscCtrl = info->misc_ctrl_value;
5790
5791 *LCR0BRDR = BUS_DESCRIPTOR(
5792 1, // Write Strobe Hold (0-3)
5793 2, // Write Strobe Delay (0-3)
5794 2, // Read Strobe Delay (0-3)
5795 0, // NWDD (Write data-data) (0-3)
5796 4, // NWAD (Write Addr-data) (0-31)
5797 0, // NXDA (Read/Write Data-Addr) (0-3)
5798 0, // NRDD (Read Data-Data) (0-3)
5799 5 // NRAD (Read Addr-Data) (0-31)
5800 );
5801 } else {
5802 /* do HW reset */
5803 outb( 0,info->io_base + 8 );
5804 }
5805
5806 info->mbre_bit = 0;
5807 info->loopback_bits = 0;
5808 info->usc_idle_mode = 0;
5809
5810 /*
5811 * Program the Bus Configuration Register (BCR)
5812 *
5813 * <15> 0 Don't use separate address
5814 * <14..6> 0 reserved
5815 * <5..4> 00 IAckmode = Default, don't care
5816 * <3> 1 Bus Request Totem Pole output
5817 * <2> 1 Use 16 Bit data bus
5818 * <1> 0 IRQ Totem Pole output
5819 * <0> 0 Don't Shift Right Addr
5820 *
5821 * 0000 0000 0000 1100 = 0x000c
5822 *
5823 * By writing to io_base + SDPIN the Wait/Ack pin is
5824 * programmed to work as a Wait pin.
5825 */
5826
5827 outw( 0x000c,info->io_base + SDPIN );
5828
5829
5830 outw( 0,info->io_base );
5831 outw( 0,info->io_base + CCAR );
5832
5833 /* select little endian byte ordering */
5834 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5835
5836
5837 /* Port Control Register (PCR)
5838 *
5839 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5840 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5841 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5842 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5843 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5844 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5845 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5846 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5847 *
5848 * 1111 0000 1111 0101 = 0xf0f5
5849 */
5850
5851 usc_OutReg( info, PCR, 0xf0f5 );
5852
5853
5854 /*
5855 * Input/Output Control Register
5856 *
5857 * <15..14> 00 CTS is active low input
5858 * <13..12> 00 DCD is active low input
5859 * <11..10> 00 TxREQ pin is input (DSR)
5860 * <9..8> 00 RxREQ pin is input (RI)
5861 * <7..6> 00 TxD is output (Transmit Data)
5862 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5863 * <2..0> 100 RxC is Output (drive with BRG0)
5864 *
5865 * 0000 0000 0000 0100 = 0x0004
5866 */
5867
5868 usc_OutReg( info, IOCR, 0x0004 );
5869
5870} /* end of usc_reset() */
5871
5872/* usc_set_async_mode()
5873 *
5874 * Program adapter for asynchronous communications.
5875 *
5876 * Arguments: info pointer to device instance data
5877 * Return Value: None
5878 */
5879static void usc_set_async_mode( struct mgsl_struct *info )
5880{
5881 u16 RegValue;
5882
5883 /* disable interrupts while programming USC */
5884 usc_DisableMasterIrqBit( info );
5885
5886 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5887 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5888
5889 usc_loopback_frame( info );
5890
5891 /* Channel mode Register (CMR)
5892 *
5893 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5894 * <13..12> 00 00 = 16X Clock
5895 * <11..8> 0000 Transmitter mode = Asynchronous
5896 * <7..6> 00 reserved?
5897 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5898 * <3..0> 0000 Receiver mode = Asynchronous
5899 *
5900 * 0000 0000 0000 0000 = 0x0
5901 */
5902
5903 RegValue = 0;
5904 if ( info->params.stop_bits != 1 )
5905 RegValue |= BIT14;
5906 usc_OutReg( info, CMR, RegValue );
5907
5908
5909 /* Receiver mode Register (RMR)
5910 *
5911 * <15..13> 000 encoding = None
5912 * <12..08> 00000 reserved (Sync Only)
5913 * <7..6> 00 Even parity
5914 * <5> 0 parity disabled
5915 * <4..2> 000 Receive Char Length = 8 bits
5916 * <1..0> 00 Disable Receiver
5917 *
5918 * 0000 0000 0000 0000 = 0x0
5919 */
5920
5921 RegValue = 0;
5922
5923 if ( info->params.data_bits != 8 )
e06922aa 5924 RegValue |= BIT4 | BIT3 | BIT2;
1da177e4
LT		 5925
5926 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5927 RegValue |= BIT5;
5928 if ( info->params.parity != ASYNC_PARITY_ODD )
5929 RegValue |= BIT6;
5930 }
5931
5932 usc_OutReg( info, RMR, RegValue );
5933
5934
5935 /* Set IRQ trigger level */
5936
5937 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5938
5939
5940 /* Receive Interrupt Control Register (RICR)
5941 *
5942 * <15..8> ? RxFIFO IRQ Request Level
5943 *
5944 * Note: For async mode the receive FIFO level must be set
7f927fcc 5945 * to 0 to avoid the situation where the FIFO contains fewer bytes
1da177e4
LT		 5946 * than the trigger level and no more data is expected.
5947 *
5948 * <7> 0 Exited Hunt IA (Interrupt Arm)
5949 * <6> 0 Idle Received IA
5950 * <5> 0 Break/Abort IA
5951 * <4> 0 Rx Bound IA
5952 * <3> 0 Queued status reflects oldest byte in FIFO
5953 * <2> 0 Abort/PE IA
5954 * <1> 0 Rx Overrun IA
5955 * <0> 0 Select TC0 value for readback
5956 *
5957 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5958 */
5959
5960 usc_OutReg( info, RICR, 0x0000 );
5961
5962 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5963 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5964
5965
5966 /* Transmit mode Register (TMR)
5967 *
5968 * <15..13> 000 encoding = None
5969 * <12..08> 00000 reserved (Sync Only)
5970 * <7..6> 00 Transmit parity Even
5971 * <5> 0 Transmit parity Disabled
5972 * <4..2> 000 Tx Char Length = 8 bits
5973 * <1..0> 00 Disable Transmitter
5974 *
5975 * 0000 0000 0000 0000 = 0x0
5976 */
5977
5978 RegValue = 0;
5979
5980 if ( info->params.data_bits != 8 )
e06922aa 5981 RegValue |= BIT4 | BIT3 | BIT2;
1da177e4
LT		 5982
5983 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5984 RegValue |= BIT5;
5985 if ( info->params.parity != ASYNC_PARITY_ODD )
5986 RegValue |= BIT6;
5987 }
5988
5989 usc_OutReg( info, TMR, RegValue );
5990
5991 usc_set_txidle( info );
5992
5993
5994 /* Set IRQ trigger level */
5995
5996 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5997
5998
5999 /* Transmit Interrupt Control Register (TICR)
6000 *
6001 * <15..8> ? Transmit FIFO IRQ Level
6002 * <7> 0 Present IA (Interrupt Arm)
6003 * <6> 1 Idle Sent IA
6004 * <5> 0 Abort Sent IA
6005 * <4> 0 EOF/EOM Sent IA
6006 * <3> 0 CRC Sent IA
6007 * <2> 0 1 = Wait for SW Trigger to Start Frame
6008 * <1> 0 Tx Underrun IA
6009 * <0> 0 TC0 constant on read back
6010 *
6011 * 0000 0000 0100 0000 = 0x0040
6012 */
6013
6014 usc_OutReg( info, TICR, 0x1f40 );
6015
6016 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6017 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6018
6019 usc_enable_async_clock( info, info->params.data_rate );
6020
6021
6022 /* Channel Control/status Register (CCSR)
6023 *
6024 * <15> X RCC FIFO Overflow status (RO)
6025 * <14> X RCC FIFO Not Empty status (RO)
6026 * <13> 0 1 = Clear RCC FIFO (WO)
6027 * <12> X DPLL in Sync status (RO)
6028 * <11> X DPLL 2 Missed Clocks status (RO)
6029 * <10> X DPLL 1 Missed Clock status (RO)
6030 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6031 * <7> X SDLC Loop On status (RO)
6032 * <6> X SDLC Loop Send status (RO)
6033 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6034 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6035 * <1..0> 00 reserved
6036 *
6037 * 0000 0000 0010 0000 = 0x0020
6038 */
6039
6040 usc_OutReg( info, CCSR, 0x0020 );
6041
6042 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6043 RECEIVE_DATA + RECEIVE_STATUS );
6044
6045 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6046 RECEIVE_DATA + RECEIVE_STATUS );
6047
6048 usc_EnableMasterIrqBit( info );
6049
6050 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6051 /* Enable INTEN (Port 6, Bit12) */
6052 /* This connects the IRQ request signal to the ISA bus */
6053 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6054 }
6055
7c1fff58
PF		 6056 if (info->params.loopback) {
6057 info->loopback_bits = 0x300;
6058 outw(0x0300, info->io_base + CCAR);
6059 }
6060
1da177e4
LT		 6061} /* end of usc_set_async_mode() */
6062
6063/* usc_loopback_frame()
6064 *
6065 * Loop back a small (2 byte) dummy SDLC frame.
6066 * Interrupts and DMA are NOT used. The purpose of this is to
6067 * clear any 'stale' status info left over from running in async mode.
6068 *
6069 * The 16C32 shows the strange behaviour of marking the 1st
6070 * received SDLC frame with a CRC error even when there is no
6071 * CRC error. To get around this a small dummy from of 2 bytes
6072 * is looped back when switching from async to sync mode.
6073 *
6074 * Arguments: info pointer to device instance data
6075 * Return Value: None
6076 */
6077static void usc_loopback_frame( struct mgsl_struct *info )
6078{
6079 int i;
6080 unsigned long oldmode = info->params.mode;
6081
6082 info->params.mode = MGSL_MODE_HDLC;
6083
6084 usc_DisableMasterIrqBit( info );
6085
6086 usc_set_sdlc_mode( info );
6087 usc_enable_loopback( info, 1 );
6088
6089 /* Write 16-bit Time Constant for BRG0 */
6090 usc_OutReg( info, TC0R, 0 );
6091
6092 /* Channel Control Register (CCR)
6093 *
6094 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6095 * <13> 0 Trigger Tx on SW Command Disabled
6096 * <12> 0 Flag Preamble Disabled
6097 * <11..10> 00 Preamble Length = 8-Bits
6098 * <9..8> 01 Preamble Pattern = flags
6099 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6100 * <5> 0 Trigger Rx on SW Command Disabled
6101 * <4..0> 0 reserved
6102 *
6103 * 0000 0001 0000 0000 = 0x0100
6104 */
6105
6106 usc_OutReg( info, CCR, 0x0100 );
6107
6108 /* SETUP RECEIVER */
6109 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6110 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6111
6112 /* SETUP TRANSMITTER */
6113 /* Program the Transmit Character Length Register (TCLR) */
6114 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6115 usc_OutReg( info, TCLR, 2 );
6116 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6117
6118 /* unlatch Tx status bits, and start transmit channel. */
6119 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6120 outw(0,info->io_base + DATAREG);
6121
6122 /* ENABLE TRANSMITTER */
6123 usc_TCmd( info, TCmd_SendFrame );
6124 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6125
6126 /* WAIT FOR RECEIVE COMPLETE */
6127 for (i=0 ; i<1000 ; i++)
e06922aa 6128 if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1))
1da177e4
LT		 6129 break;
6130
6131 /* clear Internal Data loopback mode */
6132 usc_enable_loopback(info, 0);
6133
6134 usc_EnableMasterIrqBit(info);
6135
6136 info->params.mode = oldmode;
6137
6138} /* end of usc_loopback_frame() */
6139
6140/* usc_set_sync_mode() Programs the USC for SDLC communications.
6141 *
6142 * Arguments: info pointer to adapter info structure
6143 * Return Value: None
6144 */
6145static void usc_set_sync_mode( struct mgsl_struct *info )
6146{
6147 usc_loopback_frame( info );
6148 usc_set_sdlc_mode( info );
6149
6150 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6151 /* Enable INTEN (Port 6, Bit12) */
6152 /* This connects the IRQ request signal to the ISA bus */
6153 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6154 }
6155
6156 usc_enable_aux_clock(info, info->params.clock_speed);
6157
6158 if (info->params.loopback)
6159 usc_enable_loopback(info,1);
6160
6161} /* end of mgsl_set_sync_mode() */
6162
6163/* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6164 *
6165 * Arguments: info pointer to device instance data
6166 * Return Value: None
6167 */
6168static void usc_set_txidle( struct mgsl_struct *info )
6169{
6170 u16 usc_idle_mode = IDLEMODE_FLAGS;
6171
6172 /* Map API idle mode to USC register bits */
6173
6174 switch( info->idle_mode ){
6175 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6176 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6177 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6178 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6179 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6180 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6181 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6182 }
6183
6184 info->usc_idle_mode = usc_idle_mode;
6185 //usc_OutReg(info, TCSR, usc_idle_mode);
6186 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6187 info->tcsr_value += usc_idle_mode;
6188 usc_OutReg(info, TCSR, info->tcsr_value);
6189
6190 /*
6191 * if SyncLink WAN adapter is running in external sync mode, the
6192 * transmitter has been set to Monosync in order to try to mimic
6193 * a true raw outbound bit stream. Monosync still sends an open/close
6194 * sync char at the start/end of a frame. Try to match those sync
6195 * patterns to the idle mode set here
6196 */
6197 if ( info->params.mode == MGSL_MODE_RAW ) {
6198 unsigned char syncpat = 0;
6199 switch( info->idle_mode ) {
6200 case HDLC_TXIDLE_FLAGS:
6201 syncpat = 0x7e;
6202 break;
6203 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6204 syncpat = 0x55;
6205 break;
6206 case HDLC_TXIDLE_ZEROS:
6207 case HDLC_TXIDLE_SPACE:
6208 syncpat = 0x00;
6209 break;
6210 case HDLC_TXIDLE_ONES:
6211 case HDLC_TXIDLE_MARK:
6212 syncpat = 0xff;
6213 break;
6214 case HDLC_TXIDLE_ALT_MARK_SPACE:
6215 syncpat = 0xaa;
6216 break;
6217 }
6218
6219 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6220 }
6221
6222} /* end of usc_set_txidle() */
6223
6224/* usc_get_serial_signals()
6225 *
6226 * Query the adapter for the state of the V24 status (input) signals.
6227 *
6228 * Arguments: info pointer to device instance data
6229 * Return Value: None
6230 */
6231static void usc_get_serial_signals( struct mgsl_struct *info )
6232{
6233 u16 status;
6234
9fe8074b
JP		 6235 /* clear all serial signals except RTS and DTR */
6236 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
1da177e4
LT		 6237
6238 /* Read the Misc Interrupt status Register (MISR) to get */
6239 /* the V24 status signals. */
6240
6241 status = usc_InReg( info, MISR );
6242
6243 /* set serial signal bits to reflect MISR */
6244
6245 if ( status & MISCSTATUS_CTS )
6246 info->serial_signals |= SerialSignal_CTS;
6247
6248 if ( status & MISCSTATUS_DCD )
6249 info->serial_signals |= SerialSignal_DCD;
6250
6251 if ( status & MISCSTATUS_RI )
6252 info->serial_signals |= SerialSignal_RI;
6253
6254 if ( status & MISCSTATUS_DSR )
6255 info->serial_signals |= SerialSignal_DSR;
6256
6257} /* end of usc_get_serial_signals() */
6258
6259/* usc_set_serial_signals()
6260 *
9fe8074b 6261 * Set the state of RTS and DTR based on contents of
1da177e4
LT		 6262 * serial_signals member of device extension.
6263 *
6264 * Arguments: info pointer to device instance data
6265 * Return Value: None
6266 */
6267static void usc_set_serial_signals( struct mgsl_struct *info )
6268{
6269 u16 Control;
6270 unsigned char V24Out = info->serial_signals;
6271
6272 /* get the current value of the Port Control Register (PCR) */
6273
6274 Control = usc_InReg( info, PCR );
6275
6276 if ( V24Out & SerialSignal_RTS )
6277 Control &= ~(BIT6);
6278 else
6279 Control |= BIT6;
6280
6281 if ( V24Out & SerialSignal_DTR )
6282 Control &= ~(BIT4);
6283 else
6284 Control |= BIT4;
6285
6286 usc_OutReg( info, PCR, Control );
6287
6288} /* end of usc_set_serial_signals() */
6289
6290/* usc_enable_async_clock()
6291 *
6292 * Enable the async clock at the specified frequency.
6293 *
6294 * Arguments: info pointer to device instance data
6295 * data_rate data rate of clock in bps
6296 * 0 disables the AUX clock.
6297 * Return Value: None
6298 */
6299static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6300{
6301 if ( data_rate ) {
6302 /*
6303 * Clock mode Control Register (CMCR)
6304 *
6305 * <15..14> 00 counter 1 Disabled
6306 * <13..12> 00 counter 0 Disabled
6307 * <11..10> 11 BRG1 Input is TxC Pin
6308 * <9..8> 11 BRG0 Input is TxC Pin
6309 * <7..6> 01 DPLL Input is BRG1 Output
6310 * <5..3> 100 TxCLK comes from BRG0
6311 * <2..0> 100 RxCLK comes from BRG0
6312 *
6313 * 0000 1111 0110 0100 = 0x0f64
6314 */
6315
6316 usc_OutReg( info, CMCR, 0x0f64 );
6317
6318
6319 /*
6320 * Write 16-bit Time Constant for BRG0
6321 * Time Constant = (ClkSpeed / data_rate) - 1
6322 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6323 */
6324
6325 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6326 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6327 else
6328 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6329
6330
6331 /*
6332 * Hardware Configuration Register (HCR)
6333 * Clear Bit 1, BRG0 mode = Continuous
6334 * Set Bit 0 to enable BRG0.
6335 */
6336
6337 usc_OutReg( info, HCR,
6338 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6339
6340
6341 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6342
6343 usc_OutReg( info, IOCR,
6344 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6345 } else {
6346 /* data rate == 0 so turn off BRG0 */
6347 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6348 }
6349
6350} /* end of usc_enable_async_clock() */
6351
6352/*
6353 * Buffer Structures:
6354 *
6355 * Normal memory access uses virtual addresses that can make discontiguous
6356 * physical memory pages appear to be contiguous in the virtual address
6357 * space (the processors memory mapping handles the conversions).
6358 *
6359 * DMA transfers require physically contiguous memory. This is because
6360 * the DMA system controller and DMA bus masters deal with memory using
6361 * only physical addresses.
6362 *
6363 * This causes a problem under Windows NT when large DMA buffers are
6364 * needed. Fragmentation of the nonpaged pool prevents allocations of
6365 * physically contiguous buffers larger than the PAGE_SIZE.
6366 *
6367 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6368 * allows DMA transfers to physically discontiguous buffers. Information
6369 * about each data transfer buffer is contained in a memory structure
6370 * called a 'buffer entry'. A list of buffer entries is maintained
6371 * to track and control the use of the data transfer buffers.
6372 *
6373 * To support this strategy we will allocate sufficient PAGE_SIZE
6374 * contiguous memory buffers to allow for the total required buffer
6375 * space.
6376 *
6377 * The 16C32 accesses the list of buffer entries using Bus Master
6378 * DMA. Control information is read from the buffer entries by the
6379 * 16C32 to control data transfers. status information is written to
6380 * the buffer entries by the 16C32 to indicate the status of completed
6381 * transfers.
6382 *
6383 * The CPU writes control information to the buffer entries to control
6384 * the 16C32 and reads status information from the buffer entries to
6385 * determine information about received and transmitted frames.
6386 *
6387 * Because the CPU and 16C32 (adapter) both need simultaneous access
6388 * to the buffer entries, the buffer entry memory is allocated with
6389 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6390 * entry list to PAGE_SIZE.
6391 *
6392 * The actual data buffers on the other hand will only be accessed
6393 * by the CPU or the adapter but not by both simultaneously. This allows
6394 * Scatter/Gather packet based DMA procedures for using physically
6395 * discontiguous pages.
6396 */
6397
6398/*
6399 * mgsl_reset_tx_dma_buffers()
6400 *
6401 * Set the count for all transmit buffers to 0 to indicate the
6402 * buffer is available for use and set the current buffer to the
6403 * first buffer. This effectively makes all buffers free and
6404 * discards any data in buffers.
6405 *
6406 * Arguments: info pointer to device instance data
6407 * Return Value: None
6408 */
6409static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6410{
6411 unsigned int i;
6412
6413 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6414 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6415 }
6416
6417 info->current_tx_buffer = 0;
6418 info->start_tx_dma_buffer = 0;
6419 info->tx_dma_buffers_used = 0;
6420
6421 info->get_tx_holding_index = 0;
6422 info->put_tx_holding_index = 0;
6423 info->tx_holding_count = 0;
6424
6425} /* end of mgsl_reset_tx_dma_buffers() */
6426
6427/*
6428 * num_free_tx_dma_buffers()
6429 *
6430 * returns the number of free tx dma buffers available
6431 *
6432 * Arguments: info pointer to device instance data
6433 * Return Value: number of free tx dma buffers
6434 */
6435static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6436{
6437 return info->tx_buffer_count - info->tx_dma_buffers_used;
6438}
6439
6440/*
6441 * mgsl_reset_rx_dma_buffers()
6442 *
6443 * Set the count for all receive buffers to DMABUFFERSIZE
6444 * and set the current buffer to the first buffer. This effectively
6445 * makes all buffers free and discards any data in buffers.
6446 *
6447 * Arguments: info pointer to device instance data
6448 * Return Value: None
6449 */
6450static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6451{
6452 unsigned int i;
6453
6454 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6455 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6456// info->rx_buffer_list[i].count = DMABUFFERSIZE;
6457// info->rx_buffer_list[i].status = 0;
6458 }
6459
6460 info->current_rx_buffer = 0;
6461
6462} /* end of mgsl_reset_rx_dma_buffers() */
6463
6464/*
6465 * mgsl_free_rx_frame_buffers()
6466 *
6467 * Free the receive buffers used by a received SDLC
6468 * frame such that the buffers can be reused.
6469 *
6470 * Arguments:
6471 *
6472 * info pointer to device instance data
6473 * StartIndex index of 1st receive buffer of frame
6474 * EndIndex index of last receive buffer of frame
6475 *
6476 * Return Value: None
6477 */
6478static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6479{
0fab6de0 6480 bool Done = false;
1da177e4
LT		 6481 DMABUFFERENTRY *pBufEntry;
6482 unsigned int Index;
6483
6484 /* Starting with 1st buffer entry of the frame clear the status */
6485 /* field and set the count field to DMA Buffer Size. */
6486
6487 Index = StartIndex;
6488
6489 while( !Done ) {
6490 pBufEntry = &(info->rx_buffer_list[Index]);
6491
6492 if ( Index == EndIndex ) {
6493 /* This is the last buffer of the frame! */
0fab6de0 6494 Done = true;
1da177e4
LT		 6495 }
6496
6497 /* reset current buffer for reuse */
6498// pBufEntry->status = 0;
6499// pBufEntry->count = DMABUFFERSIZE;
6500 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6501
6502 /* advance to next buffer entry in linked list */
6503 Index++;
6504 if ( Index == info->rx_buffer_count )
6505 Index = 0;
6506 }
6507
6508 /* set current buffer to next buffer after last buffer of frame */
6509 info->current_rx_buffer = Index;
6510
6511} /* end of free_rx_frame_buffers() */
6512
6513/* mgsl_get_rx_frame()
6514 *
6515 * This function attempts to return a received SDLC frame from the
6516 * receive DMA buffers. Only frames received without errors are returned.
6517 *
6518 * Arguments: info pointer to device extension
0fab6de0 6519 * Return Value: true if frame returned, otherwise false
1da177e4 6520 */
0fab6de0 6521static bool mgsl_get_rx_frame(struct mgsl_struct *info)
1da177e4
LT		 6522{
6523 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6524 unsigned short status;
6525 DMABUFFERENTRY *pBufEntry;
6526 unsigned int framesize = 0;
0fab6de0 6527 bool ReturnCode = false;
1da177e4 6528 unsigned long flags;
8fb06c77 6529 struct tty_struct *tty = info->port.tty;
0fab6de0 6530 bool return_frame = false;
1da177e4
LT		 6531
6532 /*
6533 * current_rx_buffer points to the 1st buffer of the next available
6534 * receive frame. To find the last buffer of the frame look for
6535 * a non-zero status field in the buffer entries. (The status
6536 * field is set by the 16C32 after completing a receive frame.
6537 */
6538
6539 StartIndex = EndIndex = info->current_rx_buffer;
6540
6541 while( !info->rx_buffer_list[EndIndex].status ) {
6542 /*
6543 * If the count field of the buffer entry is non-zero then
6544 * this buffer has not been used. (The 16C32 clears the count
6545 * field when it starts using the buffer.) If an unused buffer
6546 * is encountered then there are no frames available.
6547 */
6548
6549 if ( info->rx_buffer_list[EndIndex].count )
6550 goto Cleanup;
6551
6552 /* advance to next buffer entry in linked list */
6553 EndIndex++;
6554 if ( EndIndex == info->rx_buffer_count )
6555 EndIndex = 0;
6556
6557 /* if entire list searched then no frame available */
6558 if ( EndIndex == StartIndex ) {
6559 /* If this occurs then something bad happened,
6560 * all buffers have been 'used' but none mark
6561 * the end of a frame. Reset buffers and receiver.
6562 */
6563
6564 if ( info->rx_enabled ){
6565 spin_lock_irqsave(&info->irq_spinlock,flags);
6566 usc_start_receiver(info);
6567 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6568 }
6569 goto Cleanup;
6570 }
6571 }
6572
6573
6574 /* check status of receive frame */
6575
6576 status = info->rx_buffer_list[EndIndex].status;
6577
e06922aa
AJ		 6578 if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6579 RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
1da177e4
LT		 6580 if ( status & RXSTATUS_SHORT_FRAME )
6581 info->icount.rxshort++;
6582 else if ( status & RXSTATUS_ABORT )
6583 info->icount.rxabort++;
6584 else if ( status & RXSTATUS_OVERRUN )
6585 info->icount.rxover++;
6586 else {
6587 info->icount.rxcrc++;
6588 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
0fab6de0 6589 return_frame = true;
1da177e4
LT		 6590 }
6591 framesize = 0;
af69c7f9 6592#if SYNCLINK_GENERIC_HDLC
1da177e4 6593 {
198191c4
KH		 6594 info->netdev->stats.rx_errors++;
6595 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 6596 }
6597#endif
6598 } else
0fab6de0 6599 return_frame = true;
1da177e4
LT		 6600
6601 if ( return_frame ) {
6602 /* receive frame has no errors, get frame size.
6603 * The frame size is the starting value of the RCC (which was
6604 * set to 0xffff) minus the ending value of the RCC (decremented
6605 * once for each receive character) minus 2 for the 16-bit CRC.
6606 */
6607
6608 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6609
6610 /* adjust frame size for CRC if any */
6611 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6612 framesize -= 2;
6613 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6614 framesize -= 4;
6615 }
6616
6617 if ( debug_level >= DEBUG_LEVEL_BH )
6618 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6619 __FILE__,__LINE__,info->device_name,status,framesize);
6620
6621 if ( debug_level >= DEBUG_LEVEL_DATA )
6622 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6623 min_t(int, framesize, DMABUFFERSIZE),0);
6624
6625 if (framesize) {
6626 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6627 ((framesize+1) > info->max_frame_size) ) ||
6628 (framesize > info->max_frame_size) )
6629 info->icount.rxlong++;
6630 else {
6631 /* copy dma buffer(s) to contiguous intermediate buffer */
6632 int copy_count = framesize;
6633 int index = StartIndex;
6634 unsigned char *ptmp = info->intermediate_rxbuffer;
6635
6636 if ( !(status & RXSTATUS_CRC_ERROR))
6637 info->icount.rxok++;
6638
6639 while(copy_count) {
6640 int partial_count;
6641 if ( copy_count > DMABUFFERSIZE )
6642 partial_count = DMABUFFERSIZE;
6643 else
6644 partial_count = copy_count;
6645
6646 pBufEntry = &(info->rx_buffer_list[index]);
6647 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6648 ptmp += partial_count;
6649 copy_count -= partial_count;
6650
6651 if ( ++index == info->rx_buffer_count )
6652 index = 0;
6653 }
6654
6655 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6656 ++framesize;
6657 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6658 RX_CRC_ERROR :
6659 RX_OK);
6660
6661 if ( debug_level >= DEBUG_LEVEL_DATA )
6662 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6663 __FILE__,__LINE__,info->device_name,
6664 *ptmp);
6665 }
6666
af69c7f9 6667#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 6668 if (info->netcount)
6669 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6670 else
6671#endif
6672 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6673 }
6674 }
6675 /* Free the buffers used by this frame. */
6676 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6677
0fab6de0 6678 ReturnCode = true;
1da177e4
LT		 6679
6680Cleanup:
6681
6682 if ( info->rx_enabled && info->rx_overflow ) {
6683 /* The receiver needs to restarted because of
6684 * a receive overflow (buffer or FIFO). If the
6685 * receive buffers are now empty, then restart receiver.
6686 */
6687
6688 if ( !info->rx_buffer_list[EndIndex].status &&
6689 info->rx_buffer_list[EndIndex].count ) {
6690 spin_lock_irqsave(&info->irq_spinlock,flags);
6691 usc_start_receiver(info);
6692 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6693 }
6694 }
6695
6696 return ReturnCode;
6697
6698} /* end of mgsl_get_rx_frame() */
6699
6700/* mgsl_get_raw_rx_frame()
6701 *
6702 * This function attempts to return a received frame from the
6703 * receive DMA buffers when running in external loop mode. In this mode,
6704 * we will return at most one DMABUFFERSIZE frame to the application.
6705 * The USC receiver is triggering off of DCD going active to start a new
6706 * frame, and DCD going inactive to terminate the frame (similar to
6707 * processing a closing flag character).
6708 *
6709 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6710 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6711 * status field and the RCC field will indicate the length of the
6712 * entire received frame. We take this RCC field and get the modulus
6713 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6714 * last Rx DMA buffer and return that last portion of the frame.
6715 *
6716 * Arguments: info pointer to device extension
0fab6de0 6717 * Return Value: true if frame returned, otherwise false
1da177e4 6718 */
0fab6de0 6719static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
1da177e4
LT		 6720{
6721 unsigned int CurrentIndex, NextIndex;
6722 unsigned short status;
6723 DMABUFFERENTRY *pBufEntry;
6724 unsigned int framesize = 0;
0fab6de0 6725 bool ReturnCode = false;
1da177e4 6726 unsigned long flags;
8fb06c77 6727 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 6728
6729 /*
6730 * current_rx_buffer points to the 1st buffer of the next available
6731 * receive frame. The status field is set by the 16C32 after
6732 * completing a receive frame. If the status field of this buffer
6733 * is zero, either the USC is still filling this buffer or this
6734 * is one of a series of buffers making up a received frame.
6735 *
6736 * If the count field of this buffer is zero, the USC is either
6737 * using this buffer or has used this buffer. Look at the count
6738 * field of the next buffer. If that next buffer's count is
6739 * non-zero, the USC is still actively using the current buffer.
6740 * Otherwise, if the next buffer's count field is zero, the
6741 * current buffer is complete and the USC is using the next
6742 * buffer.
6743 */
6744 CurrentIndex = NextIndex = info->current_rx_buffer;
6745 ++NextIndex;
6746 if ( NextIndex == info->rx_buffer_count )
6747 NextIndex = 0;
6748
6749 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6750 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6751 info->rx_buffer_list[NextIndex].count == 0)) {
6752 /*
6753 * Either the status field of this dma buffer is non-zero
6754 * (indicating the last buffer of a receive frame) or the next
6755 * buffer is marked as in use -- implying this buffer is complete
6756 * and an intermediate buffer for this received frame.
6757 */
6758
6759 status = info->rx_buffer_list[CurrentIndex].status;
6760
e06922aa
AJ		 6761 if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6762 RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
1da177e4
LT		 6763 if ( status & RXSTATUS_SHORT_FRAME )
6764 info->icount.rxshort++;
6765 else if ( status & RXSTATUS_ABORT )
6766 info->icount.rxabort++;
6767 else if ( status & RXSTATUS_OVERRUN )
6768 info->icount.rxover++;
6769 else
6770 info->icount.rxcrc++;
6771 framesize = 0;
6772 } else {
6773 /*
6774 * A receive frame is available, get frame size and status.
6775 *
6776 * The frame size is the starting value of the RCC (which was
6777 * set to 0xffff) minus the ending value of the RCC (decremented
6778 * once for each receive character) minus 2 or 4 for the 16-bit
6779 * or 32-bit CRC.
6780 *
6781 * If the status field is zero, this is an intermediate buffer.
6782 * It's size is 4K.
6783 *
6784 * If the DMA Buffer Entry's Status field is non-zero, the
6785 * receive operation completed normally (ie: DCD dropped). The
6786 * RCC field is valid and holds the received frame size.
6787 * It is possible that the RCC field will be zero on a DMA buffer
6788 * entry with a non-zero status. This can occur if the total
6789 * frame size (number of bytes between the time DCD goes active
6790 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6791 * case the 16C32 has underrun on the RCC count and appears to
6792 * stop updating this counter to let us know the actual received
6793 * frame size. If this happens (non-zero status and zero RCC),
6794 * simply return the entire RxDMA Buffer
6795 */
6796 if ( status ) {
6797 /*
6798 * In the event that the final RxDMA Buffer is
6799 * terminated with a non-zero status and the RCC
6800 * field is zero, we interpret this as the RCC
6801 * having underflowed (received frame > 65535 bytes).
6802 *
6803 * Signal the event to the user by passing back
6804 * a status of RxStatus_CrcError returning the full
6805 * buffer and let the app figure out what data is
6806 * actually valid
6807 */
6808 if ( info->rx_buffer_list[CurrentIndex].rcc )
6809 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6810 else
6811 framesize = DMABUFFERSIZE;
6812 }
6813 else
6814 framesize = DMABUFFERSIZE;
6815 }
6816
6817 if ( framesize > DMABUFFERSIZE ) {
6818 /*
6819 * if running in raw sync mode, ISR handler for
6820 * End Of Buffer events terminates all buffers at 4K.
6821 * If this frame size is said to be >4K, get the
6822 * actual number of bytes of the frame in this buffer.
6823 */
6824 framesize = framesize % DMABUFFERSIZE;
6825 }
6826
6827
6828 if ( debug_level >= DEBUG_LEVEL_BH )
6829 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6830 __FILE__,__LINE__,info->device_name,status,framesize);
6831
6832 if ( debug_level >= DEBUG_LEVEL_DATA )
6833 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6834 min_t(int, framesize, DMABUFFERSIZE),0);
6835
6836 if (framesize) {
6837 /* copy dma buffer(s) to contiguous intermediate buffer */
6838 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6839
6840 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6841 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6842 info->icount.rxok++;
6843
6844 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6845 }
6846
6847 /* Free the buffers used by this frame. */
6848 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6849
0fab6de0 6850 ReturnCode = true;
1da177e4
LT		 6851 }
6852
6853
6854 if ( info->rx_enabled && info->rx_overflow ) {
6855 /* The receiver needs to restarted because of
6856 * a receive overflow (buffer or FIFO). If the
6857 * receive buffers are now empty, then restart receiver.
6858 */
6859
6860 if ( !info->rx_buffer_list[CurrentIndex].status &&
6861 info->rx_buffer_list[CurrentIndex].count ) {
6862 spin_lock_irqsave(&info->irq_spinlock,flags);
6863 usc_start_receiver(info);
6864 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6865 }
6866 }
6867
6868 return ReturnCode;
6869
6870} /* end of mgsl_get_raw_rx_frame() */
6871
6872/* mgsl_load_tx_dma_buffer()
6873 *
6874 * Load the transmit DMA buffer with the specified data.
6875 *
6876 * Arguments:
6877 *
6878 * info pointer to device extension
6879 * Buffer pointer to buffer containing frame to load
6880 * BufferSize size in bytes of frame in Buffer
6881 *
6882 * Return Value: None
6883 */
6884static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6885 const char *Buffer, unsigned int BufferSize)
6886{
6887 unsigned short Copycount;
6888 unsigned int i = 0;
6889 DMABUFFERENTRY *pBufEntry;
6890
6891 if ( debug_level >= DEBUG_LEVEL_DATA )
6892 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6893
6894 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6895 /* set CMR:13 to start transmit when
6896 * next GoAhead (abort) is received
6897 */
e06922aa 6898 info->cmr_value |= BIT13;
1da177e4
LT		 6899 }
6900
6901 /* begin loading the frame in the next available tx dma
6902 * buffer, remember it's starting location for setting
6903 * up tx dma operation
6904 */
6905 i = info->current_tx_buffer;
6906 info->start_tx_dma_buffer = i;
6907
6908 /* Setup the status and RCC (Frame Size) fields of the 1st */
6909 /* buffer entry in the transmit DMA buffer list. */
6910
6911 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6912 info->tx_buffer_list[i].rcc = BufferSize;
6913 info->tx_buffer_list[i].count = BufferSize;
6914
6915 /* Copy frame data from 1st source buffer to the DMA buffers. */
6916 /* The frame data may span multiple DMA buffers. */
6917
6918 while( BufferSize ){
6919 /* Get a pointer to next DMA buffer entry. */
6920 pBufEntry = &info->tx_buffer_list[i++];
6921
6922 if ( i == info->tx_buffer_count )
6923 i=0;
6924
6925 /* Calculate the number of bytes that can be copied from */
6926 /* the source buffer to this DMA buffer. */
6927 if ( BufferSize > DMABUFFERSIZE )
6928 Copycount = DMABUFFERSIZE;
6929 else
6930 Copycount = BufferSize;
6931
6932 /* Actually copy data from source buffer to DMA buffer. */
6933 /* Also set the data count for this individual DMA buffer. */
6934 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6935 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6936 else
6937 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6938
6939 pBufEntry->count = Copycount;
6940
6941 /* Advance source pointer and reduce remaining data count. */
6942 Buffer += Copycount;
6943 BufferSize -= Copycount;
6944
6945 ++info->tx_dma_buffers_used;
6946 }
6947
6948 /* remember next available tx dma buffer */
6949 info->current_tx_buffer = i;
6950
6951} /* end of mgsl_load_tx_dma_buffer() */
6952
6953/*
6954 * mgsl_register_test()
6955 *
6956 * Performs a register test of the 16C32.
6957 *
6958 * Arguments: info pointer to device instance data
0fab6de0 6959 * Return Value: true if test passed, otherwise false
1da177e4 6960 */
0fab6de0 6961static bool mgsl_register_test( struct mgsl_struct *info )
1da177e4
LT		 6962{
6963 static unsigned short BitPatterns[] =
6964 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
fe971071 6965 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
1da177e4 6966 unsigned int i;
0fab6de0 6967 bool rc = true;
1da177e4
LT		 6968 unsigned long flags;
6969
6970 spin_lock_irqsave(&info->irq_spinlock,flags);
6971 usc_reset(info);
6972
6973 /* Verify the reset state of some registers. */
6974
6975 if ( (usc_InReg( info, SICR ) != 0) ||
6976 (usc_InReg( info, IVR ) != 0) ||
6977 (usc_InDmaReg( info, DIVR ) != 0) ){
0fab6de0 6978 rc = false;
1da177e4
LT		 6979 }
6980
0fab6de0 6981 if ( rc ){
1da177e4
LT		 6982 /* Write bit patterns to various registers but do it out of */
6983 /* sync, then read back and verify values. */
6984
6985 for ( i = 0 ; i < Patterncount ; i++ ) {
6986 usc_OutReg( info, TC0R, BitPatterns[i] );
6987 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6988 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6989 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6990 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6991 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6992
6993 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6994 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6995 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6996 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6997 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6998 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
0fab6de0 6999 rc = false;
1da177e4
LT		 7000 break;
7001 }
7002 }
7003 }
7004
7005 usc_reset(info);
7006 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7007
7008 return rc;
7009
7010} /* end of mgsl_register_test() */
7011
7012/* mgsl_irq_test() Perform interrupt test of the 16C32.
7013 *
7014 * Arguments: info pointer to device instance data
0fab6de0 7015 * Return Value: true if test passed, otherwise false
1da177e4 7016 */
0fab6de0 7017static bool mgsl_irq_test( struct mgsl_struct *info )
1da177e4
LT		 7018{
7019 unsigned long EndTime;
7020 unsigned long flags;
7021
7022 spin_lock_irqsave(&info->irq_spinlock,flags);
7023 usc_reset(info);
7024
7025 /*
7026 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
0fab6de0 7027 * The ISR sets irq_occurred to true.
1da177e4
LT		 7028 */
7029
0fab6de0 7030 info->irq_occurred = false;
1da177e4
LT		 7031
7032 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7033 /* Enable INTEN (Port 6, Bit12) */
7034 /* This connects the IRQ request signal to the ISA bus */
7035 /* on the ISA adapter. This has no effect for the PCI adapter */
7036 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7037
7038 usc_EnableMasterIrqBit(info);
7039 usc_EnableInterrupts(info, IO_PIN);
7040 usc_ClearIrqPendingBits(info, IO_PIN);
7041
7042 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7043 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7044
7045 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7046
7047 EndTime=100;
7048 while( EndTime-- && !info->irq_occurred ) {
7049 msleep_interruptible(10);
7050 }
7051
7052 spin_lock_irqsave(&info->irq_spinlock,flags);
7053 usc_reset(info);
7054 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7055
0fab6de0 7056 return info->irq_occurred;
1da177e4
LT		 7057
7058} /* end of mgsl_irq_test() */
7059
7060/* mgsl_dma_test()
7061 *
7062 * Perform a DMA test of the 16C32. A small frame is
7063 * transmitted via DMA from a transmit buffer to a receive buffer
7064 * using single buffer DMA mode.
7065 *
7066 * Arguments: info pointer to device instance data
0fab6de0 7067 * Return Value: true if test passed, otherwise false
1da177e4 7068 */
0fab6de0 7069static bool mgsl_dma_test( struct mgsl_struct *info )
1da177e4
LT		 7070{
7071 unsigned short FifoLevel;
7072 unsigned long phys_addr;
7073 unsigned int FrameSize;
7074 unsigned int i;
7075 char *TmpPtr;
0fab6de0 7076 bool rc = true;
1da177e4
LT		 7077 unsigned short status=0;
7078 unsigned long EndTime;
7079 unsigned long flags;
7080 MGSL_PARAMS tmp_params;
7081
7082 /* save current port options */
7083 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7084 /* load default port options */
7085 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7086
7087#define TESTFRAMESIZE 40
7088
7089 spin_lock_irqsave(&info->irq_spinlock,flags);
7090
7091 /* setup 16C32 for SDLC DMA transfer mode */
7092
7093 usc_reset(info);
7094 usc_set_sdlc_mode(info);
7095 usc_enable_loopback(info,1);
7096
7097 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7098 * field of the buffer entry after fetching buffer address. This
7099 * way we can detect a DMA failure for a DMA read (which should be
7100 * non-destructive to system memory) before we try and write to
7101 * memory (where a failure could corrupt system memory).
7102 */
7103
7104 /* Receive DMA mode Register (RDMR)
7105 *
7106 * <15..14> 11 DMA mode = Linked List Buffer mode
7107 * <13> 1 RSBinA/L = store Rx status Block in List entry
7108 * <12> 0 1 = Clear count of List Entry after fetching
7109 * <11..10> 00 Address mode = Increment
7110 * <9> 1 Terminate Buffer on RxBound
7111 * <8> 0 Bus Width = 16bits
7112 * <7..0> ? status Bits (write as 0s)
7113 *
7114 * 1110 0010 0000 0000 = 0xe200
7115 */
7116
7117 usc_OutDmaReg( info, RDMR, 0xe200 );
7118
7119 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7120
7121
7122 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7123
7124 FrameSize = TESTFRAMESIZE;
7125
7126 /* setup 1st transmit buffer entry: */
7127 /* with frame size and transmit control word */
7128
7129 info->tx_buffer_list[0].count = FrameSize;
7130 info->tx_buffer_list[0].rcc = FrameSize;
7131 info->tx_buffer_list[0].status = 0x4000;
7132
7133 /* build a transmit frame in 1st transmit DMA buffer */
7134
7135 TmpPtr = info->tx_buffer_list[0].virt_addr;
7136 for (i = 0; i < FrameSize; i++ )
7137 *TmpPtr++ = i;
7138
7139 /* setup 1st receive buffer entry: */
7140 /* clear status, set max receive buffer size */
7141
7142 info->rx_buffer_list[0].status = 0;
7143 info->rx_buffer_list[0].count = FrameSize + 4;
7144
7145 /* zero out the 1st receive buffer */
7146
7147 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7148
7149 /* Set count field of next buffer entries to prevent */
7150 /* 16C32 from using buffers after the 1st one. */
7151
7152 info->tx_buffer_list[1].count = 0;
7153 info->rx_buffer_list[1].count = 0;
7154
7155
7156 /***************************/
7157 /* Program 16C32 receiver. */
7158 /***************************/
7159
7160 spin_lock_irqsave(&info->irq_spinlock,flags);
7161
7162 /* setup DMA transfers */
7163 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7164
7165 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7166 phys_addr = info->rx_buffer_list[0].phys_entry;
7167 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7168 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7169
7170 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7171 usc_InDmaReg( info, RDMR );
7172 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7173
7174 /* Enable Receiver (RMR <1..0> = 10) */
7175 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7176
7177 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7178
7179
7180 /*************************************************************/
7181 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7182 /*************************************************************/
7183
7184 /* Wait 100ms for interrupt. */
7185 EndTime = jiffies + msecs_to_jiffies(100);
7186
7187 for(;;) {
7188 if (time_after(jiffies, EndTime)) {
0fab6de0 7189 rc = false;
1da177e4
LT		 7190 break;
7191 }
7192
7193 spin_lock_irqsave(&info->irq_spinlock,flags);
7194 status = usc_InDmaReg( info, RDMR );
7195 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7196
7197 if ( !(status & BIT4) && (status & BIT5) ) {
7198 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7199 /* BUSY (BIT 5) is active (channel still active). */
7200 /* This means the buffer entry read has completed. */
7201 break;
7202 }
7203 }
7204
7205
7206 /******************************/
7207 /* Program 16C32 transmitter. */
7208 /******************************/
7209
7210 spin_lock_irqsave(&info->irq_spinlock,flags);
7211
7212 /* Program the Transmit Character Length Register (TCLR) */
7213 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7214
7215 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7216 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7217
7218 /* Program the address of the 1st DMA Buffer Entry in linked list */
7219
7220 phys_addr = info->tx_buffer_list[0].phys_entry;
7221 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7222 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7223
7224 /* unlatch Tx status bits, and start transmit channel. */
7225
7226 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7227 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7228
7229 /* wait for DMA controller to fill transmit FIFO */
7230
7231 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7232
7233 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7234
7235
7236 /**********************************/
7237 /* WAIT FOR TRANSMIT FIFO TO FILL */
7238 /**********************************/
7239
7240 /* Wait 100ms */
7241 EndTime = jiffies + msecs_to_jiffies(100);
7242
7243 for(;;) {
7244 if (time_after(jiffies, EndTime)) {
0fab6de0 7245 rc = false;
1da177e4
LT		 7246 break;
7247 }
7248
7249 spin_lock_irqsave(&info->irq_spinlock,flags);
7250 FifoLevel = usc_InReg(info, TICR) >> 8;
7251 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7252
7253 if ( FifoLevel < 16 )
7254 break;
7255 else
7256 if ( FrameSize < 32 ) {
7257 /* This frame is smaller than the entire transmit FIFO */
7258 /* so wait for the entire frame to be loaded. */
7259 if ( FifoLevel <= (32 - FrameSize) )
7260 break;
7261 }
7262 }
7263
7264
0fab6de0 7265 if ( rc )
1da177e4
LT		 7266 {
7267 /* Enable 16C32 transmitter. */
7268
7269 spin_lock_irqsave(&info->irq_spinlock,flags);
7270
7271 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7272 usc_TCmd( info, TCmd_SendFrame );
7273 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7274
7275 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7276
e06922aa 7277
1da177e4
LT		 7278 /******************************/
7279 /* WAIT FOR TRANSMIT COMPLETE */
7280 /******************************/
7281
7282 /* Wait 100ms */
7283 EndTime = jiffies + msecs_to_jiffies(100);
7284
7285 /* While timer not expired wait for transmit complete */
7286
7287 spin_lock_irqsave(&info->irq_spinlock,flags);
7288 status = usc_InReg( info, TCSR );
7289 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7290
e06922aa 7291 while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) {
1da177e4 7292 if (time_after(jiffies, EndTime)) {
0fab6de0 7293 rc = false;
1da177e4
LT		 7294 break;
7295 }
7296
7297 spin_lock_irqsave(&info->irq_spinlock,flags);
7298 status = usc_InReg( info, TCSR );
7299 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7300 }
7301 }
7302
7303
0fab6de0 7304 if ( rc ){
1da177e4 7305 /* CHECK FOR TRANSMIT ERRORS */
e06922aa 7306 if ( status & (BIT5 | BIT1) )
0fab6de0 7307 rc = false;
1da177e4
LT		 7308 }
7309
0fab6de0 7310 if ( rc ) {
1da177e4
LT		 7311 /* WAIT FOR RECEIVE COMPLETE */
7312
7313 /* Wait 100ms */
7314 EndTime = jiffies + msecs_to_jiffies(100);
7315
7316 /* Wait for 16C32 to write receive status to buffer entry. */
7317 status=info->rx_buffer_list[0].status;
7318 while ( status == 0 ) {
7319 if (time_after(jiffies, EndTime)) {
0fab6de0 7320 rc = false;
1da177e4
LT		 7321 break;
7322 }
7323 status=info->rx_buffer_list[0].status;
7324 }
7325 }
7326
7327
0fab6de0 7328 if ( rc ) {
1da177e4
LT		 7329 /* CHECK FOR RECEIVE ERRORS */
7330 status = info->rx_buffer_list[0].status;
7331
e06922aa 7332 if ( status & (BIT8 | BIT3 | BIT1) ) {
1da177e4 7333 /* receive error has occurred */
0fab6de0 7334 rc = false;
1da177e4
LT		 7335 } else {
7336 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7337 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
0fab6de0 7338 rc = false;
1da177e4
LT		 7339 }
7340 }
7341 }
7342
7343 spin_lock_irqsave(&info->irq_spinlock,flags);
7344 usc_reset( info );
7345 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7346
7347 /* restore current port options */
7348 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7349
7350 return rc;
7351
7352} /* end of mgsl_dma_test() */
7353
7354/* mgsl_adapter_test()
7355 *
7356 * Perform the register, IRQ, and DMA tests for the 16C32.
7357 *
7358 * Arguments: info pointer to device instance data
7359 * Return Value: 0 if success, otherwise -ENODEV
7360 */
7361static int mgsl_adapter_test( struct mgsl_struct *info )
7362{
7363 if ( debug_level >= DEBUG_LEVEL_INFO )
7364 printk( "%s(%d):Testing device %s\n",
7365 __FILE__,__LINE__,info->device_name );
7366
7367 if ( !mgsl_register_test( info ) ) {
7368 info->init_error = DiagStatus_AddressFailure;
7369 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7370 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7371 return -ENODEV;
7372 }
7373
7374 if ( !mgsl_irq_test( info ) ) {
7375 info->init_error = DiagStatus_IrqFailure;
7376 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7377 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7378 return -ENODEV;
7379 }
7380
7381 if ( !mgsl_dma_test( info ) ) {
7382 info->init_error = DiagStatus_DmaFailure;
7383 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7384 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7385 return -ENODEV;
7386 }
7387
7388 if ( debug_level >= DEBUG_LEVEL_INFO )
7389 printk( "%s(%d):device %s passed diagnostics\n",
7390 __FILE__,__LINE__,info->device_name );
7391
7392 return 0;
7393
7394} /* end of mgsl_adapter_test() */
7395
7396/* mgsl_memory_test()
7397 *
7398 * Test the shared memory on a PCI adapter.
7399 *
7400 * Arguments: info pointer to device instance data
0fab6de0 7401 * Return Value: true if test passed, otherwise false
1da177e4 7402 */
0fab6de0 7403static bool mgsl_memory_test( struct mgsl_struct *info )
1da177e4 7404{
fe971071
TK		 7405 static unsigned long BitPatterns[] =
7406 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7407 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
1da177e4
LT		 7408 unsigned long i;
7409 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7410 unsigned long * TestAddr;
7411
7412 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
0fab6de0 7413 return true;
1da177e4
LT		 7414
7415 TestAddr = (unsigned long *)info->memory_base;
7416
7417 /* Test data lines with test pattern at one location. */
7418
7419 for ( i = 0 ; i < Patterncount ; i++ ) {
7420 *TestAddr = BitPatterns[i];
7421 if ( *TestAddr != BitPatterns[i] )
0fab6de0 7422 return false;
1da177e4
LT		 7423 }
7424
7425 /* Test address lines with incrementing pattern over */
7426 /* entire address range. */
7427
7428 for ( i = 0 ; i < TestLimit ; i++ ) {
7429 *TestAddr = i * 4;
7430 TestAddr++;
7431 }
7432
7433 TestAddr = (unsigned long *)info->memory_base;
7434
7435 for ( i = 0 ; i < TestLimit ; i++ ) {
7436 if ( *TestAddr != i * 4 )
0fab6de0 7437 return false;
1da177e4
LT		 7438 TestAddr++;
7439 }
7440
7441 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7442
0fab6de0 7443 return true;
1da177e4
LT		 7444
7445} /* End Of mgsl_memory_test() */
7446
7447
7448/* mgsl_load_pci_memory()
7449 *
7450 * Load a large block of data into the PCI shared memory.
7451 * Use this instead of memcpy() or memmove() to move data
7452 * into the PCI shared memory.
7453 *
7454 * Notes:
7455 *
7456 * This function prevents the PCI9050 interface chip from hogging
7457 * the adapter local bus, which can starve the 16C32 by preventing
7458 * 16C32 bus master cycles.
7459 *
7460 * The PCI9050 documentation says that the 9050 will always release
7461 * control of the local bus after completing the current read
7462 * or write operation.
7463 *
7464 * It appears that as long as the PCI9050 write FIFO is full, the
7465 * PCI9050 treats all of the writes as a single burst transaction
7466 * and will not release the bus. This causes DMA latency problems
7467 * at high speeds when copying large data blocks to the shared
7468 * memory.
7469 *
7470 * This function in effect, breaks the a large shared memory write
7471 * into multiple transations by interleaving a shared memory read
7472 * which will flush the write FIFO and 'complete' the write
7473 * transation. This allows any pending DMA request to gain control
7474 * of the local bus in a timely fasion.
7475 *
7476 * Arguments:
7477 *
7478 * TargetPtr pointer to target address in PCI shared memory
7479 * SourcePtr pointer to source buffer for data
7480 * count count in bytes of data to copy
7481 *
7482 * Return Value: None
7483 */
7484static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7485 unsigned short count )
7486{
7487 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7488#define PCI_LOAD_INTERVAL 64
7489
7490 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7491 unsigned short Index;
7492 unsigned long Dummy;
7493
7494 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7495 {
7496 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7497 Dummy = *((volatile unsigned long *)TargetPtr);
7498 TargetPtr += PCI_LOAD_INTERVAL;
7499 SourcePtr += PCI_LOAD_INTERVAL;
7500 }
7501
7502 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7503
7504} /* End Of mgsl_load_pci_memory() */
7505
7506static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7507{
7508 int i;
7509 int linecount;
7510 if (xmit)
7511 printk("%s tx data:\n",info->device_name);
7512 else
7513 printk("%s rx data:\n",info->device_name);
7514
7515 while(count) {
7516 if (count > 16)
7517 linecount = 16;
7518 else
7519 linecount = count;
7520
7521 for(i=0;i<linecount;i++)
7522 printk("%02X ",(unsigned char)data[i]);
7523 for(;i<17;i++)
7524 printk(" ");
7525 for(i=0;i<linecount;i++) {
7526 if (data[i]>=040 && data[i]<=0176)
7527 printk("%c",data[i]);
7528 else
7529 printk(".");
7530 }
7531 printk("\n");
7532
7533 data += linecount;
7534 count -= linecount;
7535 }
7536} /* end of mgsl_trace_block() */
7537
7538/* mgsl_tx_timeout()
7539 *
7540 * called when HDLC frame times out
7541 * update stats and do tx completion processing
7542 *
7543 * Arguments: context pointer to device instance data
7544 * Return Value: None
7545 */
7546static void mgsl_tx_timeout(unsigned long context)
7547{
7548 struct mgsl_struct *info = (struct mgsl_struct*)context;
7549 unsigned long flags;
7550
7551 if ( debug_level >= DEBUG_LEVEL_INFO )
7552 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7553 __FILE__,__LINE__,info->device_name);
7554 if(info->tx_active &&
7555 (info->params.mode == MGSL_MODE_HDLC ||
7556 info->params.mode == MGSL_MODE_RAW) ) {
7557 info->icount.txtimeout++;
7558 }
7559 spin_lock_irqsave(&info->irq_spinlock,flags);
0fab6de0 7560 info->tx_active = false;
1da177e4
LT		 7561 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7562
7563 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7564 usc_loopmode_cancel_transmit( info );
7565
7566 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7567
af69c7f9 7568#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 7569 if (info->netcount)
7570 hdlcdev_tx_done(info);
7571 else
7572#endif
7573 mgsl_bh_transmit(info);
7574
7575} /* end of mgsl_tx_timeout() */
7576
7577/* signal that there are no more frames to send, so that
7578 * line is 'released' by echoing RxD to TxD when current
7579 * transmission is complete (or immediately if no tx in progress).
7580 */
7581static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7582{
7583 unsigned long flags;
7584
7585 spin_lock_irqsave(&info->irq_spinlock,flags);
7586 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7587 if (info->tx_active)
0fab6de0 7588 info->loopmode_send_done_requested = true;
1da177e4
LT		 7589 else
7590 usc_loopmode_send_done(info);
7591 }
7592 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7593
7594 return 0;
7595}
7596
7597/* release the line by echoing RxD to TxD
7598 * upon completion of a transmit frame
7599 */
7600static void usc_loopmode_send_done( struct mgsl_struct * info )
7601{
0fab6de0 7602 info->loopmode_send_done_requested = false;
1da177e4 7603 /* clear CMR:13 to 0 to start echoing RxData to TxData */
e06922aa 7604 info->cmr_value &= ~BIT13;
1da177e4
LT		 7605 usc_OutReg(info, CMR, info->cmr_value);
7606}
7607
7608/* abort a transmit in progress while in HDLC LoopMode
7609 */
7610static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7611{
7612 /* reset tx dma channel and purge TxFifo */
7613 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7614 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7615 usc_loopmode_send_done( info );
7616}
7617
7618/* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7619 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7620 * we must clear CMR:13 to begin repeating TxData to RxData
7621 */
7622static void usc_loopmode_insert_request( struct mgsl_struct * info )
7623{
0fab6de0 7624 info->loopmode_insert_requested = true;
1da177e4
LT		 7625
7626 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7627 * begin repeating TxData on RxData (complete insertion)
7628 */
7629 usc_OutReg( info, RICR,
7630 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7631
7632 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7633 info->cmr_value |= BIT13;
7634 usc_OutReg(info, CMR, info->cmr_value);
7635}
7636
7637/* return 1 if station is inserted into the loop, otherwise 0
7638 */
7639static int usc_loopmode_active( struct mgsl_struct * info)
7640{
7641 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7642}
7643
af69c7f9 7644#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 7645
7646/**
7647 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7648 * set encoding and frame check sequence (FCS) options
7649 *
7650 * dev pointer to network device structure
7651 * encoding serial encoding setting
7652 * parity FCS setting
7653 *
7654 * returns 0 if success, otherwise error code
7655 */
7656static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7657 unsigned short parity)
7658{
7659 struct mgsl_struct *info = dev_to_port(dev);
7660 unsigned char new_encoding;
7661 unsigned short new_crctype;
7662
7663 /* return error if TTY interface open */
8fb06c77 7664 if (info->port.count)
1da177e4
LT		 7665 return -EBUSY;
7666
7667 switch (encoding)
7668 {
7669 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7670 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7671 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7672 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7673 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7674 default: return -EINVAL;
7675 }
7676
7677 switch (parity)
7678 {
7679 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7680 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7681 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7682 default: return -EINVAL;
7683 }
7684
7685 info->params.encoding = new_encoding;
53b3531b 7686 info->params.crc_type = new_crctype;
1da177e4
LT		 7687
7688 /* if network interface up, reprogram hardware */
7689 if (info->netcount)
7690 mgsl_program_hw(info);
7691
7692 return 0;
7693}
7694
7695/**
7696 * called by generic HDLC layer to send frame
7697 *
7698 * skb socket buffer containing HDLC frame
7699 * dev pointer to network device structure
1da177e4 7700 */
4c5d502d
SH		 7701static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7702 struct net_device *dev)
1da177e4
LT		 7703{
7704 struct mgsl_struct *info = dev_to_port(dev);
1da177e4
LT		 7705 unsigned long flags;
7706
7707 if (debug_level >= DEBUG_LEVEL_INFO)
7708 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7709
7710 /* stop sending until this frame completes */
7711 netif_stop_queue(dev);
7712
7713 /* copy data to device buffers */
7714 info->xmit_cnt = skb->len;
7715 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7716
7717 /* update network statistics */
198191c4
KH		 7718 dev->stats.tx_packets++;
7719 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 7720
7721 /* done with socket buffer, so free it */
7722 dev_kfree_skb(skb);
7723
7724 /* save start time for transmit timeout detection */
7725 dev->trans_start = jiffies;
7726
7727 /* start hardware transmitter if necessary */
7728 spin_lock_irqsave(&info->irq_spinlock,flags);
7729 if (!info->tx_active)
7730 usc_start_transmitter(info);
7731 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7732
4c5d502d 7733 return NETDEV_TX_OK;
1da177e4
LT		 7734}
7735
7736/**
7737 * called by network layer when interface enabled
7738 * claim resources and initialize hardware
7739 *
7740 * dev pointer to network device structure
7741 *
7742 * returns 0 if success, otherwise error code
7743 */
7744static int hdlcdev_open(struct net_device *dev)
7745{
7746 struct mgsl_struct *info = dev_to_port(dev);
7747 int rc;
7748 unsigned long flags;
7749
7750 if (debug_level >= DEBUG_LEVEL_INFO)
7751 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7752
7753 /* generic HDLC layer open processing */
7754 if ((rc = hdlc_open(dev)))
7755 return rc;
7756
7757 /* arbitrate between network and tty opens */
7758 spin_lock_irqsave(&info->netlock, flags);
8fb06c77 7759 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 7760 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7761 spin_unlock_irqrestore(&info->netlock, flags);
7762 return -EBUSY;
7763 }
7764 info->netcount=1;
7765 spin_unlock_irqrestore(&info->netlock, flags);
7766
7767 /* claim resources and init adapter */
7768 if ((rc = startup(info)) != 0) {
7769 spin_lock_irqsave(&info->netlock, flags);
7770 info->netcount=0;
7771 spin_unlock_irqrestore(&info->netlock, flags);
7772 return rc;
7773 }
7774
9fe8074b
JP		 7775 /* assert RTS and DTR, apply hardware settings */
7776 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1da177e4
LT		 7777 mgsl_program_hw(info);
7778
7779 /* enable network layer transmit */
7780 dev->trans_start = jiffies;
7781 netif_start_queue(dev);
7782
7783 /* inform generic HDLC layer of current DCD status */
7784 spin_lock_irqsave(&info->irq_spinlock, flags);
7785 usc_get_serial_signals(info);
7786 spin_unlock_irqrestore(&info->irq_spinlock, flags);
fbeff3c1
KH		 7787 if (info->serial_signals & SerialSignal_DCD)
7788 netif_carrier_on(dev);
7789 else
7790 netif_carrier_off(dev);
1da177e4
LT		 7791 return 0;
7792}
7793
7794/**
7795 * called by network layer when interface is disabled
7796 * shutdown hardware and release resources
7797 *
7798 * dev pointer to network device structure
7799 *
7800 * returns 0 if success, otherwise error code
7801 */
7802static int hdlcdev_close(struct net_device *dev)
7803{
7804 struct mgsl_struct *info = dev_to_port(dev);
7805 unsigned long flags;
7806
7807 if (debug_level >= DEBUG_LEVEL_INFO)
7808 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7809
7810 netif_stop_queue(dev);
7811
7812 /* shutdown adapter and release resources */
7813 shutdown(info);
7814
7815 hdlc_close(dev);
7816
7817 spin_lock_irqsave(&info->netlock, flags);
7818 info->netcount=0;
7819 spin_unlock_irqrestore(&info->netlock, flags);
7820
7821 return 0;
7822}
7823
7824/**
7825 * called by network layer to process IOCTL call to network device
7826 *
7827 * dev pointer to network device structure
7828 * ifr pointer to network interface request structure
7829 * cmd IOCTL command code
7830 *
7831 * returns 0 if success, otherwise error code
7832 */
7833static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7834{
7835 const size_t size = sizeof(sync_serial_settings);
7836 sync_serial_settings new_line;
7837 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7838 struct mgsl_struct *info = dev_to_port(dev);
7839 unsigned int flags;
7840
7841 if (debug_level >= DEBUG_LEVEL_INFO)
7842 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7843
7844 /* return error if TTY interface open */
8fb06c77 7845 if (info->port.count)
1da177e4
LT		 7846 return -EBUSY;
7847
7848 if (cmd != SIOCWANDEV)
7849 return hdlc_ioctl(dev, ifr, cmd);
7850
7851 switch(ifr->ifr_settings.type) {
7852 case IF_GET_IFACE: /* return current sync_serial_settings */
7853
7854 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7855 if (ifr->ifr_settings.size < size) {
7856 ifr->ifr_settings.size = size; /* data size wanted */
7857 return -ENOBUFS;
7858 }
7859
7860 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7861 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7862 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7863 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7864
b19a47e0 7865 memset(&new_line, 0, sizeof(new_line));
1da177e4
LT		 7866 switch (flags){
7867 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7868 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7869 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7870 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7871 default: new_line.clock_type = CLOCK_DEFAULT;
7872 }
7873
7874 new_line.clock_rate = info->params.clock_speed;
7875 new_line.loopback = info->params.loopback ? 1:0;
7876
7877 if (copy_to_user(line, &new_line, size))
7878 return -EFAULT;
7879 return 0;
7880
7881 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7882
7883 if(!capable(CAP_NET_ADMIN))
7884 return -EPERM;
7885 if (copy_from_user(&new_line, line, size))
7886 return -EFAULT;
7887
7888 switch (new_line.clock_type)
7889 {
7890 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7891 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7892 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7893 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7894 case CLOCK_DEFAULT: flags = info->params.flags &
7895 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7896 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7897 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7898 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7899 default: return -EINVAL;
7900 }
7901
7902 if (new_line.loopback != 0 && new_line.loopback != 1)
7903 return -EINVAL;
7904
7905 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7906 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7907 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7908 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7909 info->params.flags |= flags;
7910
7911 info->params.loopback = new_line.loopback;
7912
7913 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7914 info->params.clock_speed = new_line.clock_rate;
7915 else
7916 info->params.clock_speed = 0;
7917
7918 /* if network interface up, reprogram hardware */
7919 if (info->netcount)
7920 mgsl_program_hw(info);
7921 return 0;
7922
7923 default:
7924 return hdlc_ioctl(dev, ifr, cmd);
7925 }
7926}
7927
7928/**
7929 * called by network layer when transmit timeout is detected
7930 *
7931 * dev pointer to network device structure
7932 */
7933static void hdlcdev_tx_timeout(struct net_device *dev)
7934{
7935 struct mgsl_struct *info = dev_to_port(dev);
1da177e4
LT		 7936 unsigned long flags;
7937
7938 if (debug_level >= DEBUG_LEVEL_INFO)
7939 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7940
198191c4
KH		 7941 dev->stats.tx_errors++;
7942 dev->stats.tx_aborted_errors++;
1da177e4
LT		 7943
7944 spin_lock_irqsave(&info->irq_spinlock,flags);
7945 usc_stop_transmitter(info);
7946 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7947
7948 netif_wake_queue(dev);
7949}
7950
7951/**
7952 * called by device driver when transmit completes
7953 * reenable network layer transmit if stopped
7954 *
7955 * info pointer to device instance information
7956 */
7957static void hdlcdev_tx_done(struct mgsl_struct *info)
7958{
7959 if (netif_queue_stopped(info->netdev))
7960 netif_wake_queue(info->netdev);
7961}
7962
7963/**
7964 * called by device driver when frame received
7965 * pass frame to network layer
7966 *
7967 * info pointer to device instance information
7968 * buf pointer to buffer contianing frame data
7969 * size count of data bytes in buf
7970 */
7971static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7972{
7973 struct sk_buff *skb = dev_alloc_skb(size);
7974 struct net_device *dev = info->netdev;
1da177e4
LT		 7975
7976 if (debug_level >= DEBUG_LEVEL_INFO)
198191c4 7977 printk("hdlcdev_rx(%s)\n", dev->name);
1da177e4
LT		 7978
7979 if (skb == NULL) {
198191c4
KH		 7980 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7981 dev->name);
7982 dev->stats.rx_dropped++;
1da177e4
LT		 7983 return;
7984 }
7985
198191c4 7986 memcpy(skb_put(skb, size), buf, size);
1da177e4 7987
198191c4 7988 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 7989
198191c4
KH		 7990 dev->stats.rx_packets++;
7991 dev->stats.rx_bytes += size;
1da177e4
LT		 7992
7993 netif_rx(skb);
1da177e4
LT		 7994}
7995
991990a1
KH		 7996static const struct net_device_ops hdlcdev_ops = {
7997 .ndo_open = hdlcdev_open,
7998 .ndo_stop = hdlcdev_close,
7999 .ndo_change_mtu = hdlc_change_mtu,
8000 .ndo_start_xmit = hdlc_start_xmit,
8001 .ndo_do_ioctl = hdlcdev_ioctl,
8002 .ndo_tx_timeout = hdlcdev_tx_timeout,
8003};
8004
1da177e4
LT		 8005/**
8006 * called by device driver when adding device instance
8007 * do generic HDLC initialization
8008 *
8009 * info pointer to device instance information
8010 *
8011 * returns 0 if success, otherwise error code
8012 */
8013static int hdlcdev_init(struct mgsl_struct *info)
8014{
8015 int rc;
8016 struct net_device *dev;
8017 hdlc_device *hdlc;
8018
8019 /* allocate and initialize network and HDLC layer objects */
8020
8021 if (!(dev = alloc_hdlcdev(info))) {
8022 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8023 return -ENOMEM;
8024 }
8025
8026 /* for network layer reporting purposes only */
8027 dev->base_addr = info->io_base;
8028 dev->irq = info->irq_level;
8029 dev->dma = info->dma_level;
8030
8031 /* network layer callbacks and settings */
991990a1
KH		 8032 dev->netdev_ops = &hdlcdev_ops;
8033 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 8034 dev->tx_queue_len = 50;
8035
8036 /* generic HDLC layer callbacks and settings */
8037 hdlc = dev_to_hdlc(dev);
8038 hdlc->attach = hdlcdev_attach;
8039 hdlc->xmit = hdlcdev_xmit;
8040
8041 /* register objects with HDLC layer */
8042 if ((rc = register_hdlc_device(dev))) {
8043 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8044 free_netdev(dev);
8045 return rc;
8046 }
8047
8048 info->netdev = dev;
8049 return 0;
8050}
8051
8052/**
8053 * called by device driver when removing device instance
8054 * do generic HDLC cleanup
8055 *
8056 * info pointer to device instance information
8057 */
8058static void hdlcdev_exit(struct mgsl_struct *info)
8059{
8060 unregister_hdlc_device(info->netdev);
8061 free_netdev(info->netdev);
8062 info->netdev = NULL;
8063}
8064
8065#endif /* CONFIG_HDLC */
8066
8067
9671f099 8068static int synclink_init_one (struct pci_dev *dev,
1da177e4
LT		 8069 const struct pci_device_id *ent)
8070{
8071 struct mgsl_struct *info;
8072
8073 if (pci_enable_device(dev)) {
8074 printk("error enabling pci device %p\n", dev);
8075 return -EIO;
8076 }
8077
8078 if (!(info = mgsl_allocate_device())) {
8079 printk("can't allocate device instance data.\n");
8080 return -EIO;
8081 }
8082
8083 /* Copy user configuration info to device instance data */
8084
8085 info->io_base = pci_resource_start(dev, 2);
8086 info->irq_level = dev->irq;
8087 info->phys_memory_base = pci_resource_start(dev, 3);
8088
8089 /* Because veremap only works on page boundaries we must map
8090 * a larger area than is actually implemented for the LCR
8091 * memory range. We map a full page starting at the page boundary.
8092 */
8093 info->phys_lcr_base = pci_resource_start(dev, 0);
8094 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8095 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8096
8097 info->bus_type = MGSL_BUS_TYPE_PCI;
8098 info->io_addr_size = 8;
0f2ed4c6 8099 info->irq_flags = IRQF_SHARED;
1da177e4
LT		 8100
8101 if (dev->device == 0x0210) {
8102 /* Version 1 PCI9030 based universal PCI adapter */
8103 info->misc_ctrl_value = 0x007c4080;
8104 info->hw_version = 1;
8105 } else {
8106 /* Version 0 PCI9050 based 5V PCI adapter
8107 * A PCI9050 bug prevents reading LCR registers if
8108 * LCR base address bit 7 is set. Maintain shadow
8109 * value so we can write to LCR misc control reg.
8110 */
8111 info->misc_ctrl_value = 0x087e4546;
8112 info->hw_version = 0;
8113 }
8114
8115 mgsl_add_device(info);
8116
8117 return 0;
8118}
8119
ae8d8a14 8120static void synclink_remove_one (struct pci_dev *dev)
1da177e4
LT		 8121{
8122}
8123
Linux kernel - Deliverables
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