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tty: Replace ASYNC_CTS_FLOW bit and update atomically
[deliverable/linux.git] / drivers / tty / synclinkmp.c
CommitLineData
1da177e4 1/*
7f3edb94 2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
1da177e4
LT		 3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29#if defined(__i386__)
30# define BREAKPOINT() asm(" int $3");
31#else
32# define BREAKPOINT() { }
33#endif
34
35#define MAX_DEVICES 12
36
1da177e4
LT		 37#include <linux/module.h>
38#include <linux/errno.h>
39#include <linux/signal.h>
40#include <linux/sched.h>
41#include <linux/timer.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/tty.h>
45#include <linux/tty_flip.h>
46#include <linux/serial.h>
47#include <linux/major.h>
48#include <linux/string.h>
49#include <linux/fcntl.h>
50#include <linux/ptrace.h>
51#include <linux/ioport.h>
52#include <linux/mm.h>
e6c8dd8a 53#include <linux/seq_file.h>
1da177e4
LT		 54#include <linux/slab.h>
55#include <linux/netdevice.h>
56#include <linux/vmalloc.h>
57#include <linux/init.h>
1da177e4
LT		 58#include <linux/delay.h>
59#include <linux/ioctl.h>
60
1da177e4
LT		 61#include <asm/io.h>
62#include <asm/irq.h>
63#include <asm/dma.h>
64#include <linux/bitops.h>
65#include <asm/types.h>
66#include <linux/termios.h>
67#include <linux/workqueue.h>
68#include <linux/hdlc.h>
3dd1247f 69#include <linux/synclink.h>
1da177e4 70
af69c7f9
PF		 71#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72#define SYNCLINK_GENERIC_HDLC 1
73#else
74#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 75#endif
76
77#define GET_USER(error,value,addr) error = get_user(value,addr)
78#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79#define PUT_USER(error,value,addr) error = put_user(value,addr)
80#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82#include <asm/uaccess.h>
83
1da177e4
LT		 84static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98};
99
100/* size in bytes of DMA data buffers */
101#define SCABUFSIZE 1024
102#define SCA_MEM_SIZE 0x40000
103#define SCA_BASE_SIZE 512
104#define SCA_REG_SIZE 16
105#define SCA_MAX_PORTS 4
106#define SCAMAXDESC 128
107
108#define BUFFERLISTSIZE 4096
109
110/* SCA-I style DMA buffer descriptor */
111typedef struct _SCADESC
112{
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120} SCADESC, *PSCADESC;
121
122typedef struct _SCADESC_EX
123{
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127} SCADESC_EX, *PSCADESC_EX;
128
129/* The queue of BH actions to be performed */
130
131#define BH_RECEIVE 1
132#define BH_TRANSMIT 2
133#define BH_STATUS 4
134
135#define IO_PIN_SHUTDOWN_LIMIT 100
136
1da177e4
LT		 137struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146};
147
148/*
149 * Device instance data structure
150 */
151typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
8fb06c77 154 struct tty_port port;
1da177e4
LT		 155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
1da177e4
LT		 161 int timeout;
162 int x_char; /* xon/xoff character */
1da177e4
LT		 163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
1da177e4
LT		 172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
0fab6de0 185 bool bh_running; /* Protection from multiple */
1da177e4 186 int isr_overflow;
0fab6de0 187 bool bh_requested;
1da177e4
LT		 188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
0fab6de0
JP		 210 bool rx_enabled;
211 bool rx_overflow;
1da177e4 212
0fab6de0
JP		 213 bool tx_enabled;
214 bool tx_active;
1da177e4
LT		 215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
0fab6de0 235 bool irq_requested; /* true if IRQ requested */
1da177e4
LT		 236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
0fab6de0 241 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
0fab6de0 252 bool sca_base_requested;
1da177e4
LT		 253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
0fab6de0 262 bool sca_statctrl_requested;
1da177e4
LT		 263
264 u32 misc_ctrl_value;
a6b68a69 265 char *flag_buf;
0fab6de0 266 bool drop_rts_on_tx_done;
1da177e4
LT		 267
268 struct _input_signal_events input_signal_events;
269
270 /* SPPP/Cisco HDLC device parts */
271 int netcount;
1da177e4
LT		 272 spinlock_t netlock;
273
af69c7f9 274#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 275 struct net_device *netdev;
276#endif
277
278} SLMP_INFO;
279
280#define MGSL_MAGIC 0x5401
281
282/*
283 * define serial signal status change macros
284 */
285#define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
286#define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
287#define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
288#define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
289
290/* Common Register macros */
291#define LPR 0x00
292#define PABR0 0x02
293#define PABR1 0x03
294#define WCRL 0x04
295#define WCRM 0x05
296#define WCRH 0x06
297#define DPCR 0x08
298#define DMER 0x09
299#define ISR0 0x10
300#define ISR1 0x11
301#define ISR2 0x12
302#define IER0 0x14
303#define IER1 0x15
304#define IER2 0x16
305#define ITCR 0x18
306#define INTVR 0x1a
307#define IMVR 0x1c
308
309/* MSCI Register macros */
310#define TRB 0x20
311#define TRBL 0x20
312#define TRBH 0x21
313#define SR0 0x22
314#define SR1 0x23
315#define SR2 0x24
316#define SR3 0x25
317#define FST 0x26
318#define IE0 0x28
319#define IE1 0x29
320#define IE2 0x2a
321#define FIE 0x2b
322#define CMD 0x2c
323#define MD0 0x2e
324#define MD1 0x2f
325#define MD2 0x30
326#define CTL 0x31
327#define SA0 0x32
328#define SA1 0x33
329#define IDL 0x34
330#define TMC 0x35
331#define RXS 0x36
332#define TXS 0x37
333#define TRC0 0x38
334#define TRC1 0x39
335#define RRC 0x3a
336#define CST0 0x3c
337#define CST1 0x3d
338
339/* Timer Register Macros */
340#define TCNT 0x60
341#define TCNTL 0x60
342#define TCNTH 0x61
343#define TCONR 0x62
344#define TCONRL 0x62
345#define TCONRH 0x63
346#define TMCS 0x64
347#define TEPR 0x65
348
349/* DMA Controller Register macros */
350#define DARL 0x80
351#define DARH 0x81
352#define DARB 0x82
353#define BAR 0x80
354#define BARL 0x80
355#define BARH 0x81
356#define BARB 0x82
357#define SAR 0x84
358#define SARL 0x84
359#define SARH 0x85
360#define SARB 0x86
361#define CPB 0x86
362#define CDA 0x88
363#define CDAL 0x88
364#define CDAH 0x89
365#define EDA 0x8a
366#define EDAL 0x8a
367#define EDAH 0x8b
368#define BFL 0x8c
369#define BFLL 0x8c
370#define BFLH 0x8d
371#define BCR 0x8e
372#define BCRL 0x8e
373#define BCRH 0x8f
374#define DSR 0x90
375#define DMR 0x91
376#define FCT 0x93
377#define DIR 0x94
378#define DCMD 0x95
379
380/* combine with timer or DMA register address */
381#define TIMER0 0x00
382#define TIMER1 0x08
383#define TIMER2 0x10
384#define TIMER3 0x18
385#define RXDMA 0x00
386#define TXDMA 0x20
387
388/* SCA Command Codes */
389#define NOOP 0x00
390#define TXRESET 0x01
391#define TXENABLE 0x02
392#define TXDISABLE 0x03
393#define TXCRCINIT 0x04
394#define TXCRCEXCL 0x05
395#define TXEOM 0x06
396#define TXABORT 0x07
397#define MPON 0x08
398#define TXBUFCLR 0x09
399#define RXRESET 0x11
400#define RXENABLE 0x12
401#define RXDISABLE 0x13
402#define RXCRCINIT 0x14
403#define RXREJECT 0x15
404#define SEARCHMP 0x16
405#define RXCRCEXCL 0x17
406#define RXCRCCALC 0x18
407#define CHRESET 0x21
408#define HUNT 0x31
409
410/* DMA command codes */
411#define SWABORT 0x01
412#define FEICLEAR 0x02
413
414/* IE0 */
415#define TXINTE BIT7
416#define RXINTE BIT6
417#define TXRDYE BIT1
418#define RXRDYE BIT0
419
420/* IE1 & SR1 */
421#define UDRN BIT7
422#define IDLE BIT6
423#define SYNCD BIT4
424#define FLGD BIT4
425#define CCTS BIT3
426#define CDCD BIT2
427#define BRKD BIT1
428#define ABTD BIT1
429#define GAPD BIT1
430#define BRKE BIT0
431#define IDLD BIT0
432
433/* IE2 & SR2 */
434#define EOM BIT7
435#define PMP BIT6
436#define SHRT BIT6
437#define PE BIT5
438#define ABT BIT5
439#define FRME BIT4
440#define RBIT BIT4
441#define OVRN BIT3
442#define CRCE BIT2
443
444
445/*
446 * Global linked list of SyncLink devices
447 */
448static SLMP_INFO *synclinkmp_device_list = NULL;
449static int synclinkmp_adapter_count = -1;
450static int synclinkmp_device_count = 0;
451
452/*
453 * Set this param to non-zero to load eax with the
454 * .text section address and breakpoint on module load.
455 * This is useful for use with gdb and add-symbol-file command.
456 */
90ab5ee9 457static bool break_on_load = 0;
1da177e4
LT		 458
459/*
460 * Driver major number, defaults to zero to get auto
461 * assigned major number. May be forced as module parameter.
462 */
8fb06c77 463static int ttymajor = 0;
1da177e4
LT		 464
465/*
466 * Array of user specified options for ISA adapters.
467 */
468static int debug_level = 0;
469static int maxframe[MAX_DEVICES] = {0,};
1da177e4
LT		 470
471module_param(break_on_load, bool, 0);
472module_param(ttymajor, int, 0);
473module_param(debug_level, int, 0);
474module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 475
476static char *driver_name = "SyncLink MultiPort driver";
7f3edb94 477static char *driver_version = "$Revision: 4.38 $";
1da177e4
LT		 478
479static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480static void synclinkmp_remove_one(struct pci_dev *dev);
481
482static struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, }, /* terminate list */
485};
486MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487
488MODULE_LICENSE("GPL");
489
490static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
91116cba 494 .remove = synclinkmp_remove_one,
1da177e4
LT		 495};
496
497
498static struct tty_driver *serial_driver;
499
500/* number of characters left in xmit buffer before we ask for more */
501#define WAKEUP_CHARS 256
502
503
504/* tty callbacks */
505
506static int open(struct tty_struct *tty, struct file * filp);
507static void close(struct tty_struct *tty, struct file * filp);
508static void hangup(struct tty_struct *tty);
606d099c 509static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
1da177e4
LT		 510
511static int write(struct tty_struct *tty, const unsigned char *buf, int count);
55da7789 512static int put_char(struct tty_struct *tty, unsigned char ch);
1da177e4
LT		 513static void send_xchar(struct tty_struct *tty, char ch);
514static void wait_until_sent(struct tty_struct *tty, int timeout);
515static int write_room(struct tty_struct *tty);
516static void flush_chars(struct tty_struct *tty);
517static void flush_buffer(struct tty_struct *tty);
518static void tx_hold(struct tty_struct *tty);
519static void tx_release(struct tty_struct *tty);
520
6caa76b7 521static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
1da177e4
LT		 522static int chars_in_buffer(struct tty_struct *tty);
523static void throttle(struct tty_struct * tty);
524static void unthrottle(struct tty_struct * tty);
9e98966c 525static int set_break(struct tty_struct *tty, int break_state);
1da177e4 526
af69c7f9 527#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 528#define dev_to_port(D) (dev_to_hdlc(D)->priv)
529static void hdlcdev_tx_done(SLMP_INFO *info);
530static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531static int hdlcdev_init(SLMP_INFO *info);
532static void hdlcdev_exit(SLMP_INFO *info);
533#endif
534
535/* ioctl handlers */
536
537static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541static int set_txidle(SLMP_INFO *info, int idle_mode);
542static int tx_enable(SLMP_INFO *info, int enable);
543static int tx_abort(SLMP_INFO *info);
544static int rx_enable(SLMP_INFO *info, int enable);
1da177e4
LT		 545static int modem_input_wait(SLMP_INFO *info,int arg);
546static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
60b33c13 547static int tiocmget(struct tty_struct *tty);
20b9d177
AC		 548static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
9e98966c 550static int set_break(struct tty_struct *tty, int break_state);
1da177e4 551
b1209983
AK		 552static int add_device(SLMP_INFO *info);
553static int device_init(int adapter_num, struct pci_dev *pdev);
1da177e4
LT		 554static int claim_resources(SLMP_INFO *info);
555static void release_resources(SLMP_INFO *info);
556
557static int startup(SLMP_INFO *info);
558static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
31f35939 559static int carrier_raised(struct tty_port *port);
1da177e4
LT		 560static void shutdown(SLMP_INFO *info);
561static void program_hw(SLMP_INFO *info);
562static void change_params(SLMP_INFO *info);
563
0fab6de0
JP		 564static bool init_adapter(SLMP_INFO *info);
565static bool register_test(SLMP_INFO *info);
566static bool irq_test(SLMP_INFO *info);
567static bool loopback_test(SLMP_INFO *info);
1da177e4 568static int adapter_test(SLMP_INFO *info);
0fab6de0 569static bool memory_test(SLMP_INFO *info);
1da177e4
LT		 570
571static void reset_adapter(SLMP_INFO *info);
572static void reset_port(SLMP_INFO *info);
573static void async_mode(SLMP_INFO *info);
574static void hdlc_mode(SLMP_INFO *info);
575
576static void rx_stop(SLMP_INFO *info);
577static void rx_start(SLMP_INFO *info);
578static void rx_reset_buffers(SLMP_INFO *info);
579static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
0fab6de0 580static bool rx_get_frame(SLMP_INFO *info);
1da177e4
LT		 581
582static void tx_start(SLMP_INFO *info);
583static void tx_stop(SLMP_INFO *info);
584static void tx_load_fifo(SLMP_INFO *info);
585static void tx_set_idle(SLMP_INFO *info);
586static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587
588static void get_signals(SLMP_INFO *info);
589static void set_signals(SLMP_INFO *info);
590static void enable_loopback(SLMP_INFO *info, int enable);
591static void set_rate(SLMP_INFO *info, u32 data_rate);
592
593static int bh_action(SLMP_INFO *info);
c4028958 594static void bh_handler(struct work_struct *work);
1da177e4
LT		 595static void bh_receive(SLMP_INFO *info);
596static void bh_transmit(SLMP_INFO *info);
597static void bh_status(SLMP_INFO *info);
598static void isr_timer(SLMP_INFO *info);
599static void isr_rxint(SLMP_INFO *info);
600static void isr_rxrdy(SLMP_INFO *info);
601static void isr_txint(SLMP_INFO *info);
602static void isr_txrdy(SLMP_INFO *info);
603static void isr_rxdmaok(SLMP_INFO *info);
604static void isr_rxdmaerror(SLMP_INFO *info);
605static void isr_txdmaok(SLMP_INFO *info);
606static void isr_txdmaerror(SLMP_INFO *info);
607static void isr_io_pin(SLMP_INFO *info, u16 status);
608
609static int alloc_dma_bufs(SLMP_INFO *info);
610static void free_dma_bufs(SLMP_INFO *info);
611static int alloc_buf_list(SLMP_INFO *info);
612static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613static int alloc_tmp_rx_buf(SLMP_INFO *info);
614static void free_tmp_rx_buf(SLMP_INFO *info);
615
616static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618static void tx_timeout(unsigned long context);
619static void status_timeout(unsigned long context);
620
621static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625static unsigned char read_status_reg(SLMP_INFO * info);
626static void write_control_reg(SLMP_INFO * info);
627
628
629static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
632
633static u32 misc_ctrl_value = 0x007e4040;
761a444d 634static u32 lcr1_brdr_value = 0x00800028;
1da177e4
LT		 635
636static u32 read_ahead_count = 8;
637
638/* DPCR, DMA Priority Control
639 *
640 * 07..05 Not used, must be 0
641 * 04 BRC, bus release condition: 0=all transfers complete
642 * 1=release after 1 xfer on all channels
643 * 03 CCC, channel change condition: 0=every cycle
644 * 1=after each channel completes all xfers
645 * 02..00 PR<2..0>, priority 100=round robin
646 *
647 * 00000100 = 0x00
648 */
649static unsigned char dma_priority = 0x04;
650
651// Number of bytes that can be written to shared RAM
652// in a single write operation
653static u32 sca_pci_load_interval = 64;
654
655/*
656 * 1st function defined in .text section. Calling this function in
657 * init_module() followed by a breakpoint allows a remote debugger
658 * (gdb) to get the .text address for the add-symbol-file command.
659 * This allows remote debugging of dynamically loadable modules.
660 */
661static void* synclinkmp_get_text_ptr(void);
662static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663
664static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
666{
667#ifdef SANITY_CHECK
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
672
673 if (!info) {
674 printk(badinfo, name, routine);
675 return 1;
676 }
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
679 return 1;
680 }
681#else
682 if (!info)
683 return 1;
684#endif
685 return 0;
686}
687
688/**
689 * line discipline callback wrappers
690 *
691 * The wrappers maintain line discipline references
692 * while calling into the line discipline.
693 *
694 * ldisc_receive_buf - pass receive data to line discipline
695 */
696
697static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
699{
700 struct tty_ldisc *ld;
701 if (!tty)
702 return;
703 ld = tty_ldisc_ref(tty);
704 if (ld) {
a352def2
AC		 705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 707 tty_ldisc_deref(ld);
708 }
709}
710
711/* tty callbacks */
712
ee3b48da 713static int install(struct tty_driver *driver, struct tty_struct *tty)
1da177e4
LT		 714{
715 SLMP_INFO *info;
ee3b48da 716 int line = tty->index;
1da177e4 717
410235fd 718 if (line >= synclinkmp_device_count) {
1da177e4
LT		 719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
721 return -ENODEV;
722 }
723
724 info = synclinkmp_device_list;
ee3b48da 725 while (info && info->line != line)
1da177e4
LT		 726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
728 return -ENODEV;
ee3b48da 729 if (info->init_error) {
1da177e4 730 printk("%s(%d):%s device is not allocated, init error=%d\n",
ee3b48da
JS		 731 __FILE__, __LINE__, info->device_name,
732 info->init_error);
1da177e4
LT		 733 return -ENODEV;
734 }
735
736 tty->driver_data = info;
ee3b48da
JS		 737
738 return tty_port_install(&info->port, driver, tty);
739}
740
741/* Called when a port is opened. Init and enable port.
742 */
743static int open(struct tty_struct *tty, struct file *filp)
744{
745 SLMP_INFO *info = tty->driver_data;
746 unsigned long flags;
747 int retval;
748
8fb06c77 749 info->port.tty = tty;
1da177e4
LT		 750
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
8fb06c77 753 __FILE__,__LINE__,tty->driver->name, info->port.count);
1da177e4 754
d6c53c0e 755 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 756
757 spin_lock_irqsave(&info->netlock, flags);
758 if (info->netcount) {
759 retval = -EBUSY;
760 spin_unlock_irqrestore(&info->netlock, flags);
761 goto cleanup;
762 }
8fb06c77 763 info->port.count++;
1da177e4
LT		 764 spin_unlock_irqrestore(&info->netlock, flags);
765
8fb06c77 766 if (info->port.count == 1) {
1da177e4
LT		 767 /* 1st open on this device, init hardware */
768 retval = startup(info);
769 if (retval < 0)
770 goto cleanup;
771 }
772
773 retval = block_til_ready(tty, filp, info);
774 if (retval) {
775 if (debug_level >= DEBUG_LEVEL_INFO)
776 printk("%s(%d):%s block_til_ready() returned %d\n",
777 __FILE__,__LINE__, info->device_name, retval);
778 goto cleanup;
779 }
780
781 if (debug_level >= DEBUG_LEVEL_INFO)
782 printk("%s(%d):%s open() success\n",
783 __FILE__,__LINE__, info->device_name);
784 retval = 0;
785
786cleanup:
787 if (retval) {
788 if (tty->count == 1)
8fb06c77
AC		 789 info->port.tty = NULL; /* tty layer will release tty struct */
790 if(info->port.count)
791 info->port.count--;
1da177e4
LT		 792 }
793
794 return retval;
795}
796
797/* Called when port is closed. Wait for remaining data to be
798 * sent. Disable port and free resources.
799 */
800static void close(struct tty_struct *tty, struct file *filp)
801{
c9f19e96 802 SLMP_INFO * info = tty->driver_data;
1da177e4
LT		 803
804 if (sanity_check(info, tty->name, "close"))
805 return;
806
807 if (debug_level >= DEBUG_LEVEL_INFO)
808 printk("%s(%d):%s close() entry, count=%d\n",
8fb06c77 809 __FILE__,__LINE__, info->device_name, info->port.count);
1da177e4 810
a6614999 811 if (tty_port_close_start(&info->port, tty, filp) == 0)
1da177e4 812 goto cleanup;
a360fae6
AC		 813
814 mutex_lock(&info->port.mutex);
8fb06c77 815 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4
LT		 816 wait_until_sent(tty, info->timeout);
817
978e595f 818 flush_buffer(tty);
1da177e4 819 tty_ldisc_flush(tty);
1da177e4 820 shutdown(info);
a360fae6 821 mutex_unlock(&info->port.mutex);
1da177e4 822
a6614999 823 tty_port_close_end(&info->port, tty);
8fb06c77 824 info->port.tty = NULL;
1da177e4
LT		 825cleanup:
826 if (debug_level >= DEBUG_LEVEL_INFO)
827 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
8fb06c77 828 tty->driver->name, info->port.count);
1da177e4
LT		 829}
830
831/* Called by tty_hangup() when a hangup is signaled.
832 * This is the same as closing all open descriptors for the port.
833 */
834static void hangup(struct tty_struct *tty)
835{
c9f19e96 836 SLMP_INFO *info = tty->driver_data;
a360fae6 837 unsigned long flags;
1da177e4
LT		 838
839 if (debug_level >= DEBUG_LEVEL_INFO)
840 printk("%s(%d):%s hangup()\n",
841 __FILE__,__LINE__, info->device_name );
842
843 if (sanity_check(info, tty->name, "hangup"))
844 return;
845
a360fae6 846 mutex_lock(&info->port.mutex);
1da177e4
LT		 847 flush_buffer(tty);
848 shutdown(info);
849
a360fae6 850 spin_lock_irqsave(&info->port.lock, flags);
8fb06c77
AC		 851 info->port.count = 0;
852 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
853 info->port.tty = NULL;
a360fae6
AC		 854 spin_unlock_irqrestore(&info->port.lock, flags);
855 mutex_unlock(&info->port.mutex);
1da177e4 856
8fb06c77 857 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 858}
859
860/* Set new termios settings
861 */
606d099c 862static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4 863{
c9f19e96 864 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 865 unsigned long flags;
866
867 if (debug_level >= DEBUG_LEVEL_INFO)
868 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
869 tty->driver->name );
870
1da177e4
LT		 871 change_params(info);
872
873 /* Handle transition to B0 status */
9db276f8 874 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
9fe8074b 875 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 876 spin_lock_irqsave(&info->lock,flags);
877 set_signals(info);
878 spin_unlock_irqrestore(&info->lock,flags);
879 }
880
881 /* Handle transition away from B0 status */
9db276f8 882 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1da177e4 883 info->serial_signals |= SerialSignal_DTR;
97ef38b8 884 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
1da177e4 885 info->serial_signals |= SerialSignal_RTS;
1da177e4
LT		 886 spin_lock_irqsave(&info->lock,flags);
887 set_signals(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891 /* Handle turning off CRTSCTS */
9db276f8 892 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
1da177e4
LT		 893 tty->hw_stopped = 0;
894 tx_release(tty);
895 }
896}
897
898/* Send a block of data
899 *
900 * Arguments:
901 *
902 * tty pointer to tty information structure
903 * buf pointer to buffer containing send data
904 * count size of send data in bytes
905 *
906 * Return Value: number of characters written
907 */
908static int write(struct tty_struct *tty,
909 const unsigned char *buf, int count)
910{
911 int c, ret = 0;
c9f19e96 912 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 913 unsigned long flags;
914
915 if (debug_level >= DEBUG_LEVEL_INFO)
916 printk("%s(%d):%s write() count=%d\n",
917 __FILE__,__LINE__,info->device_name,count);
918
919 if (sanity_check(info, tty->name, "write"))
920 goto cleanup;
921
326f28e9 922 if (!info->tx_buf)
1da177e4
LT		 923 goto cleanup;
924
925 if (info->params.mode == MGSL_MODE_HDLC) {
926 if (count > info->max_frame_size) {
927 ret = -EIO;
928 goto cleanup;
929 }
930 if (info->tx_active)
931 goto cleanup;
932 if (info->tx_count) {
933 /* send accumulated data from send_char() calls */
934 /* as frame and wait before accepting more data. */
935 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
936 goto start;
937 }
938 ret = info->tx_count = count;
939 tx_load_dma_buffer(info, buf, count);
940 goto start;
941 }
942
943 for (;;) {
944 c = min_t(int, count,
945 min(info->max_frame_size - info->tx_count - 1,
946 info->max_frame_size - info->tx_put));
947 if (c <= 0)
948 break;
949
950 memcpy(info->tx_buf + info->tx_put, buf, c);
951
952 spin_lock_irqsave(&info->lock,flags);
953 info->tx_put += c;
954 if (info->tx_put >= info->max_frame_size)
955 info->tx_put -= info->max_frame_size;
956 info->tx_count += c;
957 spin_unlock_irqrestore(&info->lock,flags);
958
959 buf += c;
960 count -= c;
961 ret += c;
962 }
963
964 if (info->params.mode == MGSL_MODE_HDLC) {
965 if (count) {
966 ret = info->tx_count = 0;
967 goto cleanup;
968 }
969 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
970 }
971start:
972 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 tx_start(info);
976 spin_unlock_irqrestore(&info->lock,flags);
977 }
978
979cleanup:
980 if (debug_level >= DEBUG_LEVEL_INFO)
981 printk( "%s(%d):%s write() returning=%d\n",
982 __FILE__,__LINE__,info->device_name,ret);
983 return ret;
984}
985
986/* Add a character to the transmit buffer.
987 */
55da7789 988static int put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 989{
c9f19e96 990 SLMP_INFO *info = tty->driver_data;
1da177e4 991 unsigned long flags;
55da7789 992 int ret = 0;
1da177e4
LT		 993
994 if ( debug_level >= DEBUG_LEVEL_INFO ) {
995 printk( "%s(%d):%s put_char(%d)\n",
996 __FILE__,__LINE__,info->device_name,ch);
997 }
998
999 if (sanity_check(info, tty->name, "put_char"))
55da7789 1000 return 0;
1da177e4 1001
326f28e9 1002 if (!info->tx_buf)
55da7789 1003 return 0;
1da177e4
LT		 1004
1005 spin_lock_irqsave(&info->lock,flags);
1006
1007 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008 !info->tx_active ) {
1009
1010 if (info->tx_count < info->max_frame_size - 1) {
1011 info->tx_buf[info->tx_put++] = ch;
1012 if (info->tx_put >= info->max_frame_size)
1013 info->tx_put -= info->max_frame_size;
1014 info->tx_count++;
55da7789 1015 ret = 1;
1da177e4
LT		 1016 }
1017 }
1018
1019 spin_unlock_irqrestore(&info->lock,flags);
55da7789 1020 return ret;
1da177e4
LT		 1021}
1022
1023/* Send a high-priority XON/XOFF character
1024 */
1025static void send_xchar(struct tty_struct *tty, char ch)
1026{
c9f19e96 1027 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1028 unsigned long flags;
1029
1030 if (debug_level >= DEBUG_LEVEL_INFO)
1031 printk("%s(%d):%s send_xchar(%d)\n",
1032 __FILE__,__LINE__, info->device_name, ch );
1033
1034 if (sanity_check(info, tty->name, "send_xchar"))
1035 return;
1036
1037 info->x_char = ch;
1038 if (ch) {
1039 /* Make sure transmit interrupts are on */
1040 spin_lock_irqsave(&info->lock,flags);
1041 if (!info->tx_enabled)
1042 tx_start(info);
1043 spin_unlock_irqrestore(&info->lock,flags);
1044 }
1045}
1046
1047/* Wait until the transmitter is empty.
1048 */
1049static void wait_until_sent(struct tty_struct *tty, int timeout)
1050{
c9f19e96 1051 SLMP_INFO * info = tty->driver_data;
1da177e4
LT		 1052 unsigned long orig_jiffies, char_time;
1053
1054 if (!info )
1055 return;
1056
1057 if (debug_level >= DEBUG_LEVEL_INFO)
1058 printk("%s(%d):%s wait_until_sent() entry\n",
1059 __FILE__,__LINE__, info->device_name );
1060
1061 if (sanity_check(info, tty->name, "wait_until_sent"))
1062 return;
1063
f602501d 1064 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1da177e4
LT		 1065 goto exit;
1066
1067 orig_jiffies = jiffies;
1068
1069 /* Set check interval to 1/5 of estimated time to
1070 * send a character, and make it at least 1. The check
1071 * interval should also be less than the timeout.
1072 * Note: use tight timings here to satisfy the NIST-PCTS.
1073 */
1074
1075 if ( info->params.data_rate ) {
1076 char_time = info->timeout/(32 * 5);
1077 if (!char_time)
1078 char_time++;
1079 } else
1080 char_time = 1;
1081
1082 if (timeout)
1083 char_time = min_t(unsigned long, char_time, timeout);
1084
1085 if ( info->params.mode == MGSL_MODE_HDLC ) {
1086 while (info->tx_active) {
1087 msleep_interruptible(jiffies_to_msecs(char_time));
1088 if (signal_pending(current))
1089 break;
1090 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1091 break;
1092 }
1093 } else {
f602501d
AC		 1094 /*
1095 * TODO: determine if there is something similar to USC16C32
1096 * TXSTATUS_ALL_SENT status
1097 */
1da177e4
LT		 1098 while ( info->tx_active && info->tx_enabled) {
1099 msleep_interruptible(jiffies_to_msecs(char_time));
1100 if (signal_pending(current))
1101 break;
1102 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103 break;
1104 }
1105 }
1106
1107exit:
1108 if (debug_level >= DEBUG_LEVEL_INFO)
1109 printk("%s(%d):%s wait_until_sent() exit\n",
1110 __FILE__,__LINE__, info->device_name );
1111}
1112
1113/* Return the count of free bytes in transmit buffer
1114 */
1115static int write_room(struct tty_struct *tty)
1116{
c9f19e96 1117 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1118 int ret;
1119
1120 if (sanity_check(info, tty->name, "write_room"))
1121 return 0;
1122
1123 if (info->params.mode == MGSL_MODE_HDLC) {
1124 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1125 } else {
1126 ret = info->max_frame_size - info->tx_count - 1;
1127 if (ret < 0)
1128 ret = 0;
1129 }
1130
1131 if (debug_level >= DEBUG_LEVEL_INFO)
1132 printk("%s(%d):%s write_room()=%d\n",
1133 __FILE__, __LINE__, info->device_name, ret);
1134
1135 return ret;
1136}
1137
1138/* enable transmitter and send remaining buffered characters
1139 */
1140static void flush_chars(struct tty_struct *tty)
1141{
c9f19e96 1142 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1143 unsigned long flags;
1144
1145 if ( debug_level >= DEBUG_LEVEL_INFO )
1146 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147 __FILE__,__LINE__,info->device_name,info->tx_count);
1148
1149 if (sanity_check(info, tty->name, "flush_chars"))
1150 return;
1151
1152 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1153 !info->tx_buf)
1154 return;
1155
1156 if ( debug_level >= DEBUG_LEVEL_INFO )
1157 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158 __FILE__,__LINE__,info->device_name );
1159
1160 spin_lock_irqsave(&info->lock,flags);
1161
1162 if (!info->tx_active) {
1163 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1164 info->tx_count ) {
1165 /* operating in synchronous (frame oriented) mode */
1166 /* copy data from circular tx_buf to */
1167 /* transmit DMA buffer. */
1168 tx_load_dma_buffer(info,
1169 info->tx_buf,info->tx_count);
1170 }
1171 tx_start(info);
1172 }
1173
1174 spin_unlock_irqrestore(&info->lock,flags);
1175}
1176
1177/* Discard all data in the send buffer
1178 */
1179static void flush_buffer(struct tty_struct *tty)
1180{
c9f19e96 1181 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1182 unsigned long flags;
1183
1184 if (debug_level >= DEBUG_LEVEL_INFO)
1185 printk("%s(%d):%s flush_buffer() entry\n",
1186 __FILE__,__LINE__, info->device_name );
1187
1188 if (sanity_check(info, tty->name, "flush_buffer"))
1189 return;
1190
1191 spin_lock_irqsave(&info->lock,flags);
1192 info->tx_count = info->tx_put = info->tx_get = 0;
1193 del_timer(&info->tx_timer);
1194 spin_unlock_irqrestore(&info->lock,flags);
1195
1da177e4
LT		 1196 tty_wakeup(tty);
1197}
1198
1199/* throttle (stop) transmitter
1200 */
1201static void tx_hold(struct tty_struct *tty)
1202{
c9f19e96 1203 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1204 unsigned long flags;
1205
1206 if (sanity_check(info, tty->name, "tx_hold"))
1207 return;
1208
1209 if ( debug_level >= DEBUG_LEVEL_INFO )
1210 printk("%s(%d):%s tx_hold()\n",
1211 __FILE__,__LINE__,info->device_name);
1212
1213 spin_lock_irqsave(&info->lock,flags);
1214 if (info->tx_enabled)
1215 tx_stop(info);
1216 spin_unlock_irqrestore(&info->lock,flags);
1217}
1218
1219/* release (start) transmitter
1220 */
1221static void tx_release(struct tty_struct *tty)
1222{
c9f19e96 1223 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1224 unsigned long flags;
1225
1226 if (sanity_check(info, tty->name, "tx_release"))
1227 return;
1228
1229 if ( debug_level >= DEBUG_LEVEL_INFO )
1230 printk("%s(%d):%s tx_release()\n",
1231 __FILE__,__LINE__,info->device_name);
1232
1233 spin_lock_irqsave(&info->lock,flags);
1234 if (!info->tx_enabled)
1235 tx_start(info);
1236 spin_unlock_irqrestore(&info->lock,flags);
1237}
1238
1239/* Service an IOCTL request
1240 *
1241 * Arguments:
1242 *
1243 * tty pointer to tty instance data
1da177e4
LT		 1244 * cmd IOCTL command code
1245 * arg command argument/context
1246 *
1247 * Return Value: 0 if success, otherwise error code
1248 */
6caa76b7 1249static int ioctl(struct tty_struct *tty,
1da177e4
LT		 1250 unsigned int cmd, unsigned long arg)
1251{
c9f19e96 1252 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1253 void __user *argp = (void __user *)arg;
1254
1255 if (debug_level >= DEBUG_LEVEL_INFO)
1256 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257 info->device_name, cmd );
1258
1259 if (sanity_check(info, tty->name, "ioctl"))
1260 return -ENODEV;
1261
1262 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
0587102c 1263 (cmd != TIOCMIWAIT)) {
18900ca6 1264 if (tty_io_error(tty))
1da177e4
LT		 1265 return -EIO;
1266 }
1267
1268 switch (cmd) {
1269 case MGSL_IOCGPARAMS:
1270 return get_params(info, argp);
1271 case MGSL_IOCSPARAMS:
1272 return set_params(info, argp);
1273 case MGSL_IOCGTXIDLE:
1274 return get_txidle(info, argp);
1275 case MGSL_IOCSTXIDLE:
1276 return set_txidle(info, (int)arg);
1277 case MGSL_IOCTXENABLE:
1278 return tx_enable(info, (int)arg);
1279 case MGSL_IOCRXENABLE:
1280 return rx_enable(info, (int)arg);
1281 case MGSL_IOCTXABORT:
1282 return tx_abort(info);
1283 case MGSL_IOCGSTATS:
1284 return get_stats(info, argp);
1285 case MGSL_IOCWAITEVENT:
1286 return wait_mgsl_event(info, argp);
1287 case MGSL_IOCLOOPTXDONE:
1288 return 0; // TODO: Not supported, need to document
1289 /* Wait for modem input (DCD,RI,DSR,CTS) change
1290 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1291 */
1292 case TIOCMIWAIT:
1293 return modem_input_wait(info,(int)arg);
1294
1295 /*
1296 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1297 * Return: write counters to the user passed counter struct
1298 * NB: both 1->0 and 0->1 transitions are counted except for
1299 * RI where only 0->1 is counted.
1300 */
1da177e4
LT		 1301 default:
1302 return -ENOIOCTLCMD;
1303 }
1304 return 0;
1305}
1306
0587102c
AC		 1307static int get_icount(struct tty_struct *tty,
1308 struct serial_icounter_struct *icount)
1309{
1310 SLMP_INFO *info = tty->driver_data;
1311 struct mgsl_icount cnow; /* kernel counter temps */
1312 unsigned long flags;
1313
1314 spin_lock_irqsave(&info->lock,flags);
1315 cnow = info->icount;
1316 spin_unlock_irqrestore(&info->lock,flags);
1317
1318 icount->cts = cnow.cts;
1319 icount->dsr = cnow.dsr;
1320 icount->rng = cnow.rng;
1321 icount->dcd = cnow.dcd;
1322 icount->rx = cnow.rx;
1323 icount->tx = cnow.tx;
1324 icount->frame = cnow.frame;
1325 icount->overrun = cnow.overrun;
1326 icount->parity = cnow.parity;
1327 icount->brk = cnow.brk;
1328 icount->buf_overrun = cnow.buf_overrun;
1329
1330 return 0;
1331}
1332
1da177e4
LT		 1333/*
1334 * /proc fs routines....
1335 */
1336
e6c8dd8a 1337static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1da177e4
LT		 1338{
1339 char stat_buf[30];
1da177e4
LT		 1340 unsigned long flags;
1341
e6c8dd8a 1342 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1da177e4
LT		 1343 "\tIRQ=%d MaxFrameSize=%u\n",
1344 info->device_name,
1345 info->phys_sca_base,
1346 info->phys_memory_base,
1347 info->phys_statctrl_base,
1348 info->phys_lcr_base,
1349 info->irq_level,
1350 info->max_frame_size );
1351
1352 /* output current serial signal states */
1353 spin_lock_irqsave(&info->lock,flags);
1354 get_signals(info);
1355 spin_unlock_irqrestore(&info->lock,flags);
1356
1357 stat_buf[0] = 0;
1358 stat_buf[1] = 0;
1359 if (info->serial_signals & SerialSignal_RTS)
1360 strcat(stat_buf, "|RTS");
1361 if (info->serial_signals & SerialSignal_CTS)
1362 strcat(stat_buf, "|CTS");
1363 if (info->serial_signals & SerialSignal_DTR)
1364 strcat(stat_buf, "|DTR");
1365 if (info->serial_signals & SerialSignal_DSR)
1366 strcat(stat_buf, "|DSR");
1367 if (info->serial_signals & SerialSignal_DCD)
1368 strcat(stat_buf, "|CD");
1369 if (info->serial_signals & SerialSignal_RI)
1370 strcat(stat_buf, "|RI");
1371
1372 if (info->params.mode == MGSL_MODE_HDLC) {
e6c8dd8a 1373 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1da177e4
LT		 1374 info->icount.txok, info->icount.rxok);
1375 if (info->icount.txunder)
e6c8dd8a 1376 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 1377 if (info->icount.txabort)
e6c8dd8a 1378 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 1379 if (info->icount.rxshort)
e6c8dd8a 1380 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 1381 if (info->icount.rxlong)
e6c8dd8a 1382 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 1383 if (info->icount.rxover)
e6c8dd8a 1384 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 1385 if (info->icount.rxcrc)
e6c8dd8a 1386 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1da177e4 1387 } else {
e6c8dd8a 1388 seq_printf(m, "\tASYNC tx:%d rx:%d",
1da177e4
LT		 1389 info->icount.tx, info->icount.rx);
1390 if (info->icount.frame)
e6c8dd8a 1391 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 1392 if (info->icount.parity)
e6c8dd8a 1393 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 1394 if (info->icount.brk)
e6c8dd8a 1395 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 1396 if (info->icount.overrun)
e6c8dd8a 1397 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4
LT		 1398 }
1399
1400 /* Append serial signal status to end */
e6c8dd8a 1401 seq_printf(m, " %s\n", stat_buf+1);
1da177e4 1402
e6c8dd8a 1403 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 1404 info->tx_active,info->bh_requested,info->bh_running,
1405 info->pending_bh);
1da177e4
LT		 1406}
1407
1408/* Called to print information about devices
1409 */
e6c8dd8a 1410static int synclinkmp_proc_show(struct seq_file *m, void *v)
1da177e4 1411{
1da177e4
LT		 1412 SLMP_INFO *info;
1413
e6c8dd8a 1414 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1da177e4
LT		 1415
1416 info = synclinkmp_device_list;
1417 while( info ) {
e6c8dd8a 1418 line_info(m, info);
1da177e4
LT		 1419 info = info->next_device;
1420 }
e6c8dd8a
AD		 1421 return 0;
1422}
1da177e4 1423
e6c8dd8a
AD		 1424static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1425{
1426 return single_open(file, synclinkmp_proc_show, NULL);
1da177e4
LT		 1427}
1428
e6c8dd8a
AD		 1429static const struct file_operations synclinkmp_proc_fops = {
1430 .owner = THIS_MODULE,
1431 .open = synclinkmp_proc_open,
1432 .read = seq_read,
1433 .llseek = seq_lseek,
1434 .release = single_release,
1435};
1436
1da177e4
LT		 1437/* Return the count of bytes in transmit buffer
1438 */
1439static int chars_in_buffer(struct tty_struct *tty)
1440{
c9f19e96 1441 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1442
1443 if (sanity_check(info, tty->name, "chars_in_buffer"))
1444 return 0;
1445
1446 if (debug_level >= DEBUG_LEVEL_INFO)
1447 printk("%s(%d):%s chars_in_buffer()=%d\n",
1448 __FILE__, __LINE__, info->device_name, info->tx_count);
1449
1450 return info->tx_count;
1451}
1452
1453/* Signal remote device to throttle send data (our receive data)
1454 */
1455static void throttle(struct tty_struct * tty)
1456{
c9f19e96 1457 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1458 unsigned long flags;
1459
1460 if (debug_level >= DEBUG_LEVEL_INFO)
1461 printk("%s(%d):%s throttle() entry\n",
1462 __FILE__,__LINE__, info->device_name );
1463
1464 if (sanity_check(info, tty->name, "throttle"))
1465 return;
1466
1467 if (I_IXOFF(tty))
1468 send_xchar(tty, STOP_CHAR(tty));
1469
9db276f8 1470 if (C_CRTSCTS(tty)) {
1da177e4
LT		 1471 spin_lock_irqsave(&info->lock,flags);
1472 info->serial_signals &= ~SerialSignal_RTS;
1473 set_signals(info);
1474 spin_unlock_irqrestore(&info->lock,flags);
1475 }
1476}
1477
1478/* Signal remote device to stop throttling send data (our receive data)
1479 */
1480static void unthrottle(struct tty_struct * tty)
1481{
c9f19e96 1482 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 1483 unsigned long flags;
1484
1485 if (debug_level >= DEBUG_LEVEL_INFO)
1486 printk("%s(%d):%s unthrottle() entry\n",
1487 __FILE__,__LINE__, info->device_name );
1488
1489 if (sanity_check(info, tty->name, "unthrottle"))
1490 return;
1491
1492 if (I_IXOFF(tty)) {
1493 if (info->x_char)
1494 info->x_char = 0;
1495 else
1496 send_xchar(tty, START_CHAR(tty));
1497 }
1498
9db276f8 1499 if (C_CRTSCTS(tty)) {
1da177e4
LT		 1500 spin_lock_irqsave(&info->lock,flags);
1501 info->serial_signals |= SerialSignal_RTS;
1502 set_signals(info);
1503 spin_unlock_irqrestore(&info->lock,flags);
1504 }
1505}
1506
1507/* set or clear transmit break condition
1508 * break_state -1=set break condition, 0=clear
1509 */
9e98966c 1510static int set_break(struct tty_struct *tty, int break_state)
1da177e4
LT		 1511{
1512 unsigned char RegValue;
c9f19e96 1513 SLMP_INFO * info = tty->driver_data;
1da177e4
LT		 1514 unsigned long flags;
1515
1516 if (debug_level >= DEBUG_LEVEL_INFO)
1517 printk("%s(%d):%s set_break(%d)\n",
1518 __FILE__,__LINE__, info->device_name, break_state);
1519
1520 if (sanity_check(info, tty->name, "set_break"))
9e98966c 1521 return -EINVAL;
1da177e4
LT		 1522
1523 spin_lock_irqsave(&info->lock,flags);
1524 RegValue = read_reg(info, CTL);
1525 if (break_state == -1)
1526 RegValue |= BIT3;
1527 else
1528 RegValue &= ~BIT3;
1529 write_reg(info, CTL, RegValue);
1530 spin_unlock_irqrestore(&info->lock,flags);
9e98966c 1531 return 0;
1da177e4
LT		 1532}
1533
af69c7f9 1534#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 1535
1536/**
1537 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1538 * set encoding and frame check sequence (FCS) options
1539 *
1540 * dev pointer to network device structure
1541 * encoding serial encoding setting
1542 * parity FCS setting
1543 *
1544 * returns 0 if success, otherwise error code
1545 */
1546static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1547 unsigned short parity)
1548{
1549 SLMP_INFO *info = dev_to_port(dev);
1550 unsigned char new_encoding;
1551 unsigned short new_crctype;
1552
1553 /* return error if TTY interface open */
8fb06c77 1554 if (info->port.count)
1da177e4
LT		 1555 return -EBUSY;
1556
1557 switch (encoding)
1558 {
1559 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1560 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1561 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1562 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1563 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1564 default: return -EINVAL;
1565 }
1566
1567 switch (parity)
1568 {
1569 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1570 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1571 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1572 default: return -EINVAL;
1573 }
1574
1575 info->params.encoding = new_encoding;
53b3531b 1576 info->params.crc_type = new_crctype;
1da177e4
LT		 1577
1578 /* if network interface up, reprogram hardware */
1579 if (info->netcount)
1580 program_hw(info);
1581
1582 return 0;
1583}
1584
1585/**
1586 * called by generic HDLC layer to send frame
1587 *
1588 * skb socket buffer containing HDLC frame
1589 * dev pointer to network device structure
1da177e4 1590 */
4c5d502d
SH		 1591static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1592 struct net_device *dev)
1da177e4
LT		 1593{
1594 SLMP_INFO *info = dev_to_port(dev);
1da177e4
LT		 1595 unsigned long flags;
1596
1597 if (debug_level >= DEBUG_LEVEL_INFO)
1598 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1599
1600 /* stop sending until this frame completes */
1601 netif_stop_queue(dev);
1602
1603 /* copy data to device buffers */
1604 info->tx_count = skb->len;
1605 tx_load_dma_buffer(info, skb->data, skb->len);
1606
1607 /* update network statistics */
198191c4
KH		 1608 dev->stats.tx_packets++;
1609 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 1610
1611 /* done with socket buffer, so free it */
1612 dev_kfree_skb(skb);
1613
1614 /* save start time for transmit timeout detection */
1615 dev->trans_start = jiffies;
1616
1617 /* start hardware transmitter if necessary */
1618 spin_lock_irqsave(&info->lock,flags);
1619 if (!info->tx_active)
1620 tx_start(info);
1621 spin_unlock_irqrestore(&info->lock,flags);
1622
4c5d502d 1623 return NETDEV_TX_OK;
1da177e4
LT		 1624}
1625
1626/**
1627 * called by network layer when interface enabled
1628 * claim resources and initialize hardware
1629 *
1630 * dev pointer to network device structure
1631 *
1632 * returns 0 if success, otherwise error code
1633 */
1634static int hdlcdev_open(struct net_device *dev)
1635{
1636 SLMP_INFO *info = dev_to_port(dev);
1637 int rc;
1638 unsigned long flags;
1639
1640 if (debug_level >= DEBUG_LEVEL_INFO)
1641 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1642
1643 /* generic HDLC layer open processing */
485e148d
GKH		 1644 rc = hdlc_open(dev);
1645 if (rc)
1da177e4
LT		 1646 return rc;
1647
1648 /* arbitrate between network and tty opens */
1649 spin_lock_irqsave(&info->netlock, flags);
8fb06c77 1650 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 1651 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1652 spin_unlock_irqrestore(&info->netlock, flags);
1653 return -EBUSY;
1654 }
1655 info->netcount=1;
1656 spin_unlock_irqrestore(&info->netlock, flags);
1657
1658 /* claim resources and init adapter */
1659 if ((rc = startup(info)) != 0) {
1660 spin_lock_irqsave(&info->netlock, flags);
1661 info->netcount=0;
1662 spin_unlock_irqrestore(&info->netlock, flags);
1663 return rc;
1664 }
1665
9fe8074b
JP		 1666 /* assert RTS and DTR, apply hardware settings */
1667 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1da177e4
LT		 1668 program_hw(info);
1669
1670 /* enable network layer transmit */
1671 dev->trans_start = jiffies;
1672 netif_start_queue(dev);
1673
1674 /* inform generic HDLC layer of current DCD status */
1675 spin_lock_irqsave(&info->lock, flags);
1676 get_signals(info);
1677 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 1678 if (info->serial_signals & SerialSignal_DCD)
1679 netif_carrier_on(dev);
1680 else
1681 netif_carrier_off(dev);
1da177e4
LT		 1682 return 0;
1683}
1684
1685/**
1686 * called by network layer when interface is disabled
1687 * shutdown hardware and release resources
1688 *
1689 * dev pointer to network device structure
1690 *
1691 * returns 0 if success, otherwise error code
1692 */
1693static int hdlcdev_close(struct net_device *dev)
1694{
1695 SLMP_INFO *info = dev_to_port(dev);
1696 unsigned long flags;
1697
1698 if (debug_level >= DEBUG_LEVEL_INFO)
1699 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1700
1701 netif_stop_queue(dev);
1702
1703 /* shutdown adapter and release resources */
1704 shutdown(info);
1705
1706 hdlc_close(dev);
1707
1708 spin_lock_irqsave(&info->netlock, flags);
1709 info->netcount=0;
1710 spin_unlock_irqrestore(&info->netlock, flags);
1711
1712 return 0;
1713}
1714
1715/**
1716 * called by network layer to process IOCTL call to network device
1717 *
1718 * dev pointer to network device structure
1719 * ifr pointer to network interface request structure
1720 * cmd IOCTL command code
1721 *
1722 * returns 0 if success, otherwise error code
1723 */
1724static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1725{
1726 const size_t size = sizeof(sync_serial_settings);
1727 sync_serial_settings new_line;
1728 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1729 SLMP_INFO *info = dev_to_port(dev);
1730 unsigned int flags;
1731
1732 if (debug_level >= DEBUG_LEVEL_INFO)
1733 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1734
1735 /* return error if TTY interface open */
8fb06c77 1736 if (info->port.count)
1da177e4
LT		 1737 return -EBUSY;
1738
1739 if (cmd != SIOCWANDEV)
1740 return hdlc_ioctl(dev, ifr, cmd);
1741
1742 switch(ifr->ifr_settings.type) {
1743 case IF_GET_IFACE: /* return current sync_serial_settings */
1744
1745 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1746 if (ifr->ifr_settings.size < size) {
1747 ifr->ifr_settings.size = size; /* data size wanted */
1748 return -ENOBUFS;
1749 }
1750
1751 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1752 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1753 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1754 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1755
b19a47e0 1756 memset(&new_line, 0, sizeof(new_line));
1da177e4
LT		 1757 switch (flags){
1758 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1759 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1760 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1761 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1762 default: new_line.clock_type = CLOCK_DEFAULT;
1763 }
1764
1765 new_line.clock_rate = info->params.clock_speed;
1766 new_line.loopback = info->params.loopback ? 1:0;
1767
1768 if (copy_to_user(line, &new_line, size))
1769 return -EFAULT;
1770 return 0;
1771
1772 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1773
1774 if(!capable(CAP_NET_ADMIN))
1775 return -EPERM;
1776 if (copy_from_user(&new_line, line, size))
1777 return -EFAULT;
1778
1779 switch (new_line.clock_type)
1780 {
1781 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1782 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1783 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1784 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1785 case CLOCK_DEFAULT: flags = info->params.flags &
1786 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1787 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1788 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1789 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1790 default: return -EINVAL;
1791 }
1792
1793 if (new_line.loopback != 0 && new_line.loopback != 1)
1794 return -EINVAL;
1795
1796 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1797 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1798 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1799 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1800 info->params.flags |= flags;
1801
1802 info->params.loopback = new_line.loopback;
1803
1804 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1805 info->params.clock_speed = new_line.clock_rate;
1806 else
1807 info->params.clock_speed = 0;
1808
1809 /* if network interface up, reprogram hardware */
1810 if (info->netcount)
1811 program_hw(info);
1812 return 0;
1813
1814 default:
1815 return hdlc_ioctl(dev, ifr, cmd);
1816 }
1817}
1818
1819/**
1820 * called by network layer when transmit timeout is detected
1821 *
1822 * dev pointer to network device structure
1823 */
1824static void hdlcdev_tx_timeout(struct net_device *dev)
1825{
1826 SLMP_INFO *info = dev_to_port(dev);
1da177e4
LT		 1827 unsigned long flags;
1828
1829 if (debug_level >= DEBUG_LEVEL_INFO)
1830 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1831
198191c4
KH		 1832 dev->stats.tx_errors++;
1833 dev->stats.tx_aborted_errors++;
1da177e4
LT		 1834
1835 spin_lock_irqsave(&info->lock,flags);
1836 tx_stop(info);
1837 spin_unlock_irqrestore(&info->lock,flags);
1838
1839 netif_wake_queue(dev);
1840}
1841
1842/**
1843 * called by device driver when transmit completes
1844 * reenable network layer transmit if stopped
1845 *
1846 * info pointer to device instance information
1847 */
1848static void hdlcdev_tx_done(SLMP_INFO *info)
1849{
1850 if (netif_queue_stopped(info->netdev))
1851 netif_wake_queue(info->netdev);
1852}
1853
1854/**
1855 * called by device driver when frame received
1856 * pass frame to network layer
1857 *
1858 * info pointer to device instance information
1859 * buf pointer to buffer contianing frame data
1860 * size count of data bytes in buf
1861 */
1862static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1863{
1864 struct sk_buff *skb = dev_alloc_skb(size);
1865 struct net_device *dev = info->netdev;
1da177e4
LT		 1866
1867 if (debug_level >= DEBUG_LEVEL_INFO)
1868 printk("hdlcdev_rx(%s)\n",dev->name);
1869
1870 if (skb == NULL) {
198191c4
KH		 1871 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1872 dev->name);
1873 dev->stats.rx_dropped++;
1da177e4
LT		 1874 return;
1875 }
1876
198191c4 1877 memcpy(skb_put(skb, size), buf, size);
1da177e4 1878
198191c4 1879 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 1880
198191c4
KH		 1881 dev->stats.rx_packets++;
1882 dev->stats.rx_bytes += size;
1da177e4
LT		 1883
1884 netif_rx(skb);
1da177e4
LT		 1885}
1886
991990a1
KH		 1887static const struct net_device_ops hdlcdev_ops = {
1888 .ndo_open = hdlcdev_open,
1889 .ndo_stop = hdlcdev_close,
1890 .ndo_change_mtu = hdlc_change_mtu,
1891 .ndo_start_xmit = hdlc_start_xmit,
1892 .ndo_do_ioctl = hdlcdev_ioctl,
1893 .ndo_tx_timeout = hdlcdev_tx_timeout,
1894};
1895
1da177e4
LT		 1896/**
1897 * called by device driver when adding device instance
1898 * do generic HDLC initialization
1899 *
1900 * info pointer to device instance information
1901 *
1902 * returns 0 if success, otherwise error code
1903 */
1904static int hdlcdev_init(SLMP_INFO *info)
1905{
1906 int rc;
1907 struct net_device *dev;
1908 hdlc_device *hdlc;
1909
1910 /* allocate and initialize network and HDLC layer objects */
1911
485e148d
GKH		 1912 dev = alloc_hdlcdev(info);
1913 if (!dev) {
1da177e4
LT		 1914 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1915 return -ENOMEM;
1916 }
1917
1918 /* for network layer reporting purposes only */
1919 dev->mem_start = info->phys_sca_base;
1920 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1921 dev->irq = info->irq_level;
1922
1923 /* network layer callbacks and settings */
991990a1
KH		 1924 dev->netdev_ops = &hdlcdev_ops;
1925 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 1926 dev->tx_queue_len = 50;
1927
1928 /* generic HDLC layer callbacks and settings */
1929 hdlc = dev_to_hdlc(dev);
1930 hdlc->attach = hdlcdev_attach;
1931 hdlc->xmit = hdlcdev_xmit;
1932
1933 /* register objects with HDLC layer */
485e148d
GKH		 1934 rc = register_hdlc_device(dev);
1935 if (rc) {
1da177e4
LT		 1936 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1937 free_netdev(dev);
1938 return rc;
1939 }
1940
1941 info->netdev = dev;
1942 return 0;
1943}
1944
1945/**
1946 * called by device driver when removing device instance
1947 * do generic HDLC cleanup
1948 *
1949 * info pointer to device instance information
1950 */
1951static void hdlcdev_exit(SLMP_INFO *info)
1952{
1953 unregister_hdlc_device(info->netdev);
1954 free_netdev(info->netdev);
1955 info->netdev = NULL;
1956}
1957
1958#endif /* CONFIG_HDLC */
1959
1960
1961/* Return next bottom half action to perform.
1962 * Return Value: BH action code or 0 if nothing to do.
1963 */
ce9f9f73 1964static int bh_action(SLMP_INFO *info)
1da177e4
LT		 1965{
1966 unsigned long flags;
1967 int rc = 0;
1968
1969 spin_lock_irqsave(&info->lock,flags);
1970
1971 if (info->pending_bh & BH_RECEIVE) {
1972 info->pending_bh &= ~BH_RECEIVE;
1973 rc = BH_RECEIVE;
1974 } else if (info->pending_bh & BH_TRANSMIT) {
1975 info->pending_bh &= ~BH_TRANSMIT;
1976 rc = BH_TRANSMIT;
1977 } else if (info->pending_bh & BH_STATUS) {
1978 info->pending_bh &= ~BH_STATUS;
1979 rc = BH_STATUS;
1980 }
1981
1982 if (!rc) {
1983 /* Mark BH routine as complete */
0fab6de0
JP		 1984 info->bh_running = false;
1985 info->bh_requested = false;
1da177e4
LT		 1986 }
1987
1988 spin_unlock_irqrestore(&info->lock,flags);
1989
1990 return rc;
1991}
1992
1993/* Perform bottom half processing of work items queued by ISR.
1994 */
ce9f9f73 1995static void bh_handler(struct work_struct *work)
1da177e4 1996{
c4028958 1997 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1da177e4
LT		 1998 int action;
1999
1da177e4
LT		 2000 if ( debug_level >= DEBUG_LEVEL_BH )
2001 printk( "%s(%d):%s bh_handler() entry\n",
2002 __FILE__,__LINE__,info->device_name);
2003
0fab6de0 2004 info->bh_running = true;
1da177e4
LT		 2005
2006 while((action = bh_action(info)) != 0) {
2007
2008 /* Process work item */
2009 if ( debug_level >= DEBUG_LEVEL_BH )
2010 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2011 __FILE__,__LINE__,info->device_name, action);
2012
2013 switch (action) {
2014
2015 case BH_RECEIVE:
2016 bh_receive(info);
2017 break;
2018 case BH_TRANSMIT:
2019 bh_transmit(info);
2020 break;
2021 case BH_STATUS:
2022 bh_status(info);
2023 break;
2024 default:
2025 /* unknown work item ID */
2026 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2027 __FILE__,__LINE__,info->device_name,action);
2028 break;
2029 }
2030 }
2031
2032 if ( debug_level >= DEBUG_LEVEL_BH )
2033 printk( "%s(%d):%s bh_handler() exit\n",
2034 __FILE__,__LINE__,info->device_name);
2035}
2036
ce9f9f73 2037static void bh_receive(SLMP_INFO *info)
1da177e4
LT		 2038{
2039 if ( debug_level >= DEBUG_LEVEL_BH )
2040 printk( "%s(%d):%s bh_receive()\n",
2041 __FILE__,__LINE__,info->device_name);
2042
2043 while( rx_get_frame(info) );
2044}
2045
ce9f9f73 2046static void bh_transmit(SLMP_INFO *info)
1da177e4 2047{
8fb06c77 2048 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 2049
2050 if ( debug_level >= DEBUG_LEVEL_BH )
2051 printk( "%s(%d):%s bh_transmit() entry\n",
2052 __FILE__,__LINE__,info->device_name);
2053
b963a844 2054 if (tty)
1da177e4 2055 tty_wakeup(tty);
1da177e4
LT		 2056}
2057
ce9f9f73 2058static void bh_status(SLMP_INFO *info)
1da177e4
LT		 2059{
2060 if ( debug_level >= DEBUG_LEVEL_BH )
2061 printk( "%s(%d):%s bh_status() entry\n",
2062 __FILE__,__LINE__,info->device_name);
2063
2064 info->ri_chkcount = 0;
2065 info->dsr_chkcount = 0;
2066 info->dcd_chkcount = 0;
2067 info->cts_chkcount = 0;
2068}
2069
ce9f9f73 2070static void isr_timer(SLMP_INFO * info)
1da177e4
LT		 2071{
2072 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2073
2074 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2075 write_reg(info, IER2, 0);
2076
2077 /* TMCS, Timer Control/Status Register
2078 *
2079 * 07 CMF, Compare match flag (read only) 1=match
2080 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2081 * 05 Reserved, must be 0
2082 * 04 TME, Timer Enable
2083 * 03..00 Reserved, must be 0
2084 *
2085 * 0000 0000
2086 */
2087 write_reg(info, (unsigned char)(timer + TMCS), 0);
2088
0fab6de0 2089 info->irq_occurred = true;
1da177e4
LT		 2090
2091 if ( debug_level >= DEBUG_LEVEL_ISR )
2092 printk("%s(%d):%s isr_timer()\n",
2093 __FILE__,__LINE__,info->device_name);
2094}
2095
ce9f9f73 2096static void isr_rxint(SLMP_INFO * info)
1da177e4 2097{
8fb06c77 2098 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 2099 struct mgsl_icount *icount = &info->icount;
2100 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2101 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2102
2103 /* clear status bits */
2104 if (status)
2105 write_reg(info, SR1, status);
2106
2107 if (status2)
2108 write_reg(info, SR2, status2);
2109
2110 if ( debug_level >= DEBUG_LEVEL_ISR )
2111 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2112 __FILE__,__LINE__,info->device_name,status,status2);
2113
2114 if (info->params.mode == MGSL_MODE_ASYNC) {
2115 if (status & BRKD) {
2116 icount->brk++;
2117
2118 /* process break detection if tty control
2119 * is not set to ignore it
2120 */
92a19f9c
JS		 2121 if (!(status & info->ignore_status_mask1)) {
2122 if (info->read_status_mask1 & BRKD) {
2123 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2124 if (tty && (info->port.flags & ASYNC_SAK))
2125 do_SAK(tty);
1da177e4
LT		 2126 }
2127 }
2128 }
2129 }
2130 else {
2131 if (status & (FLGD|IDLD)) {
2132 if (status & FLGD)
2133 info->icount.exithunt++;
2134 else if (status & IDLD)
2135 info->icount.rxidle++;
2136 wake_up_interruptible(&info->event_wait_q);
2137 }
2138 }
2139
2140 if (status & CDCD) {
2141 /* simulate a common modem status change interrupt
2142 * for our handler
2143 */
2144 get_signals( info );
2145 isr_io_pin(info,
2146 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2147 }
2148}
2149
2150/*
2151 * handle async rx data interrupts
2152 */
ce9f9f73 2153static void isr_rxrdy(SLMP_INFO * info)
1da177e4
LT		 2154{
2155 u16 status;
2156 unsigned char DataByte;
1da177e4
LT		 2157 struct mgsl_icount *icount = &info->icount;
2158
2159 if ( debug_level >= DEBUG_LEVEL_ISR )
2160 printk("%s(%d):%s isr_rxrdy\n",
2161 __FILE__,__LINE__,info->device_name);
2162
2163 while((status = read_reg(info,CST0)) & BIT0)
2164 {
33f0f88f 2165 int flag = 0;
0fab6de0 2166 bool over = false;
1da177e4
LT		 2167 DataByte = read_reg(info,TRB);
2168
1da177e4
LT		 2169 icount->rx++;
2170
2171 if ( status & (PE + FRME + OVRN) ) {
2172 printk("%s(%d):%s rxerr=%04X\n",
2173 __FILE__,__LINE__,info->device_name,status);
2174
2175 /* update error statistics */
2176 if (status & PE)
2177 icount->parity++;
2178 else if (status & FRME)
2179 icount->frame++;
2180 else if (status & OVRN)
2181 icount->overrun++;
2182
2183 /* discard char if tty control flags say so */
2184 if (status & info->ignore_status_mask2)
2185 continue;
2186
2187 status &= info->read_status_mask2;
2188
92a19f9c
JS		 2189 if (status & PE)
2190 flag = TTY_PARITY;
2191 else if (status & FRME)
2192 flag = TTY_FRAME;
2193 if (status & OVRN) {
2194 /* Overrun is special, since it's
2195 * reported immediately, and doesn't
2196 * affect the current character
2197 */
2198 over = true;
1da177e4
LT		 2199 }
2200 } /* end of if (error) */
2201
92a19f9c
JS		 2202 tty_insert_flip_char(&info->port, DataByte, flag);
2203 if (over)
2204 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
1da177e4
LT		 2205 }
2206
2207 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1da177e4
LT		 2208 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2209 __FILE__,__LINE__,info->device_name,
2210 icount->rx,icount->brk,icount->parity,
2211 icount->frame,icount->overrun);
2212 }
2213
2e124b4a 2214 tty_flip_buffer_push(&info->port);
1da177e4
LT		 2215}
2216
2217static void isr_txeom(SLMP_INFO * info, unsigned char status)
2218{
2219 if ( debug_level >= DEBUG_LEVEL_ISR )
2220 printk("%s(%d):%s isr_txeom status=%02x\n",
2221 __FILE__,__LINE__,info->device_name,status);
2222
2223 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2224 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2225 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2226
2227 if (status & UDRN) {
2228 write_reg(info, CMD, TXRESET);
2229 write_reg(info, CMD, TXENABLE);
2230 } else
2231 write_reg(info, CMD, TXBUFCLR);
2232
2233 /* disable and clear tx interrupts */
2234 info->ie0_value &= ~TXRDYE;
2235 info->ie1_value &= ~(IDLE + UDRN);
2236 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2237 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2238
2239 if ( info->tx_active ) {
2240 if (info->params.mode != MGSL_MODE_ASYNC) {
2241 if (status & UDRN)
2242 info->icount.txunder++;
2243 else if (status & IDLE)
2244 info->icount.txok++;
2245 }
2246
0fab6de0 2247 info->tx_active = false;
1da177e4
LT		 2248 info->tx_count = info->tx_put = info->tx_get = 0;
2249
2250 del_timer(&info->tx_timer);
2251
2252 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2253 info->serial_signals &= ~SerialSignal_RTS;
0fab6de0 2254 info->drop_rts_on_tx_done = false;
1da177e4
LT		 2255 set_signals(info);
2256 }
2257
af69c7f9 2258#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2259 if (info->netcount)
2260 hdlcdev_tx_done(info);
2261 else
2262#endif
2263 {
8fb06c77 2264 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
1da177e4
LT		 2265 tx_stop(info);
2266 return;
2267 }
2268 info->pending_bh |= BH_TRANSMIT;
2269 }
2270 }
2271}
2272
2273
2274/*
2275 * handle tx status interrupts
2276 */
ce9f9f73 2277static void isr_txint(SLMP_INFO * info)
1da177e4
LT		 2278{
2279 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2280
2281 /* clear status bits */
2282 write_reg(info, SR1, status);
2283
2284 if ( debug_level >= DEBUG_LEVEL_ISR )
2285 printk("%s(%d):%s isr_txint status=%02x\n",
2286 __FILE__,__LINE__,info->device_name,status);
2287
2288 if (status & (UDRN + IDLE))
2289 isr_txeom(info, status);
2290
2291 if (status & CCTS) {
2292 /* simulate a common modem status change interrupt
2293 * for our handler
2294 */
2295 get_signals( info );
2296 isr_io_pin(info,
2297 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2298
2299 }
2300}
2301
2302/*
2303 * handle async tx data interrupts
2304 */
ce9f9f73 2305static void isr_txrdy(SLMP_INFO * info)
1da177e4
LT		 2306{
2307 if ( debug_level >= DEBUG_LEVEL_ISR )
2308 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2309 __FILE__,__LINE__,info->device_name,info->tx_count);
2310
2311 if (info->params.mode != MGSL_MODE_ASYNC) {
2312 /* disable TXRDY IRQ, enable IDLE IRQ */
2313 info->ie0_value &= ~TXRDYE;
2314 info->ie1_value |= IDLE;
2315 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2316 return;
2317 }
2318
8fb06c77 2319 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
1da177e4
LT		 2320 tx_stop(info);
2321 return;
2322 }
2323
2324 if ( info->tx_count )
2325 tx_load_fifo( info );
2326 else {
0fab6de0 2327 info->tx_active = false;
1da177e4
LT		 2328 info->ie0_value &= ~TXRDYE;
2329 write_reg(info, IE0, info->ie0_value);
2330 }
2331
2332 if (info->tx_count < WAKEUP_CHARS)
2333 info->pending_bh |= BH_TRANSMIT;
2334}
2335
ce9f9f73 2336static void isr_rxdmaok(SLMP_INFO * info)
1da177e4
LT		 2337{
2338 /* BIT7 = EOT (end of transfer)
2339 * BIT6 = EOM (end of message/frame)
2340 */
2341 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2342
2343 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2344 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2345
2346 if ( debug_level >= DEBUG_LEVEL_ISR )
2347 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2348 __FILE__,__LINE__,info->device_name,status);
2349
2350 info->pending_bh |= BH_RECEIVE;
2351}
2352
ce9f9f73 2353static void isr_rxdmaerror(SLMP_INFO * info)
1da177e4
LT		 2354{
2355 /* BIT5 = BOF (buffer overflow)
2356 * BIT4 = COF (counter overflow)
2357 */
2358 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2359
2360 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2361 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2362
2363 if ( debug_level >= DEBUG_LEVEL_ISR )
2364 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2365 __FILE__,__LINE__,info->device_name,status);
2366
0fab6de0 2367 info->rx_overflow = true;
1da177e4
LT		 2368 info->pending_bh |= BH_RECEIVE;
2369}
2370
ce9f9f73 2371static void isr_txdmaok(SLMP_INFO * info)
1da177e4
LT		 2372{
2373 unsigned char status_reg1 = read_reg(info, SR1);
2374
2375 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2376 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2377 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2378
2379 if ( debug_level >= DEBUG_LEVEL_ISR )
2380 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2381 __FILE__,__LINE__,info->device_name,status_reg1);
2382
2383 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2384 write_reg16(info, TRC0, 0);
2385 info->ie0_value |= TXRDYE;
2386 write_reg(info, IE0, info->ie0_value);
2387}
2388
ce9f9f73 2389static void isr_txdmaerror(SLMP_INFO * info)
1da177e4
LT		 2390{
2391 /* BIT5 = BOF (buffer overflow)
2392 * BIT4 = COF (counter overflow)
2393 */
2394 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2395
2396 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2397 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2398
2399 if ( debug_level >= DEBUG_LEVEL_ISR )
2400 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2401 __FILE__,__LINE__,info->device_name,status);
2402}
2403
2404/* handle input serial signal changes
2405 */
ce9f9f73 2406static void isr_io_pin( SLMP_INFO *info, u16 status )
1da177e4
LT		 2407{
2408 struct mgsl_icount *icount;
2409
2410 if ( debug_level >= DEBUG_LEVEL_ISR )
2411 printk("%s(%d):isr_io_pin status=%04X\n",
2412 __FILE__,__LINE__,status);
2413
2414 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2415 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2416 icount = &info->icount;
2417 /* update input line counters */
2418 if (status & MISCSTATUS_RI_LATCHED) {
2419 icount->rng++;
2420 if ( status & SerialSignal_RI )
2421 info->input_signal_events.ri_up++;
2422 else
2423 info->input_signal_events.ri_down++;
2424 }
2425 if (status & MISCSTATUS_DSR_LATCHED) {
2426 icount->dsr++;
2427 if ( status & SerialSignal_DSR )
2428 info->input_signal_events.dsr_up++;
2429 else
2430 info->input_signal_events.dsr_down++;
2431 }
2432 if (status & MISCSTATUS_DCD_LATCHED) {
2433 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2434 info->ie1_value &= ~CDCD;
2435 write_reg(info, IE1, info->ie1_value);
2436 }
2437 icount->dcd++;
2438 if (status & SerialSignal_DCD) {
2439 info->input_signal_events.dcd_up++;
2440 } else
2441 info->input_signal_events.dcd_down++;
af69c7f9 2442#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 2443 if (info->netcount) {
2444 if (status & SerialSignal_DCD)
2445 netif_carrier_on(info->netdev);
2446 else
2447 netif_carrier_off(info->netdev);
2448 }
1da177e4
LT		 2449#endif
2450 }
2451 if (status & MISCSTATUS_CTS_LATCHED)
2452 {
2453 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2454 info->ie1_value &= ~CCTS;
2455 write_reg(info, IE1, info->ie1_value);
2456 }
2457 icount->cts++;
2458 if ( status & SerialSignal_CTS )
2459 info->input_signal_events.cts_up++;
2460 else
2461 info->input_signal_events.cts_down++;
2462 }
2463 wake_up_interruptible(&info->status_event_wait_q);
2464 wake_up_interruptible(&info->event_wait_q);
2465
8fb06c77 2466 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1da177e4
LT		 2467 (status & MISCSTATUS_DCD_LATCHED) ) {
2468 if ( debug_level >= DEBUG_LEVEL_ISR )
2469 printk("%s CD now %s...", info->device_name,
2470 (status & SerialSignal_DCD) ? "on" : "off");
2471 if (status & SerialSignal_DCD)
8fb06c77 2472 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 2473 else {
2474 if ( debug_level >= DEBUG_LEVEL_ISR )
2475 printk("doing serial hangup...");
8fb06c77
AC		 2476 if (info->port.tty)
2477 tty_hangup(info->port.tty);
1da177e4
LT		 2478 }
2479 }
2480
f21ec3d2 2481 if (tty_port_cts_enabled(&info->port) &&
1da177e4 2482 (status & MISCSTATUS_CTS_LATCHED) ) {
8fb06c77
AC		 2483 if ( info->port.tty ) {
2484 if (info->port.tty->hw_stopped) {
1da177e4
LT		 2485 if (status & SerialSignal_CTS) {
2486 if ( debug_level >= DEBUG_LEVEL_ISR )
2487 printk("CTS tx start...");
8fb06c77 2488 info->port.tty->hw_stopped = 0;
1da177e4
LT		 2489 tx_start(info);
2490 info->pending_bh |= BH_TRANSMIT;
2491 return;
2492 }
2493 } else {
2494 if (!(status & SerialSignal_CTS)) {
2495 if ( debug_level >= DEBUG_LEVEL_ISR )
2496 printk("CTS tx stop...");
8fb06c77 2497 info->port.tty->hw_stopped = 1;
1da177e4
LT		 2498 tx_stop(info);
2499 }
2500 }
2501 }
2502 }
2503 }
2504
2505 info->pending_bh |= BH_STATUS;
2506}
2507
2508/* Interrupt service routine entry point.
2509 *
2510 * Arguments:
2511 * irq interrupt number that caused interrupt
2512 * dev_id device ID supplied during interrupt registration
2513 * regs interrupted processor context
2514 */
a6f97b29 2515static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
1da177e4 2516{
a6f97b29 2517 SLMP_INFO *info = dev_id;
1da177e4
LT		 2518 unsigned char status, status0, status1=0;
2519 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2520 unsigned char timerstatus0, timerstatus1=0;
2521 unsigned char shift;
2522 unsigned int i;
2523 unsigned short tmp;
2524
2525 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 2526 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2527 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 2528
2529 spin_lock(&info->lock);
2530
2531 for(;;) {
2532
2533 /* get status for SCA0 (ports 0-1) */
2534 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2535 status0 = (unsigned char)tmp;
2536 dmastatus0 = (unsigned char)(tmp>>8);
2537 timerstatus0 = read_reg(info, ISR2);
2538
2539 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 2540 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2541 __FILE__, __LINE__, info->device_name,
2542 status0, dmastatus0, timerstatus0);
1da177e4
LT		 2543
2544 if (info->port_count == 4) {
2545 /* get status for SCA1 (ports 2-3) */
2546 tmp = read_reg16(info->port_array[2], ISR0);
2547 status1 = (unsigned char)tmp;
2548 dmastatus1 = (unsigned char)(tmp>>8);
2549 timerstatus1 = read_reg(info->port_array[2], ISR2);
2550
2551 if ( debug_level >= DEBUG_LEVEL_ISR )
2552 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2553 __FILE__,__LINE__,info->device_name,
2554 status1,dmastatus1,timerstatus1);
2555 }
2556
2557 if (!status0 && !dmastatus0 && !timerstatus0 &&
2558 !status1 && !dmastatus1 && !timerstatus1)
2559 break;
2560
2561 for(i=0; i < info->port_count ; i++) {
2562 if (info->port_array[i] == NULL)
2563 continue;
2564 if (i < 2) {
2565 status = status0;
2566 dmastatus = dmastatus0;
2567 } else {
2568 status = status1;
2569 dmastatus = dmastatus1;
2570 }
2571
2572 shift = i & 1 ? 4 :0;
2573
2574 if (status & BIT0 << shift)
2575 isr_rxrdy(info->port_array[i]);
2576 if (status & BIT1 << shift)
2577 isr_txrdy(info->port_array[i]);
2578 if (status & BIT2 << shift)
2579 isr_rxint(info->port_array[i]);
2580 if (status & BIT3 << shift)
2581 isr_txint(info->port_array[i]);
2582
2583 if (dmastatus & BIT0 << shift)
2584 isr_rxdmaerror(info->port_array[i]);
2585 if (dmastatus & BIT1 << shift)
2586 isr_rxdmaok(info->port_array[i]);
2587 if (dmastatus & BIT2 << shift)
2588 isr_txdmaerror(info->port_array[i]);
2589 if (dmastatus & BIT3 << shift)
2590 isr_txdmaok(info->port_array[i]);
2591 }
2592
2593 if (timerstatus0 & (BIT5 | BIT4))
2594 isr_timer(info->port_array[0]);
2595 if (timerstatus0 & (BIT7 | BIT6))
2596 isr_timer(info->port_array[1]);
2597 if (timerstatus1 & (BIT5 | BIT4))
2598 isr_timer(info->port_array[2]);
2599 if (timerstatus1 & (BIT7 | BIT6))
2600 isr_timer(info->port_array[3]);
2601 }
2602
2603 for(i=0; i < info->port_count ; i++) {
2604 SLMP_INFO * port = info->port_array[i];
2605
2606 /* Request bottom half processing if there's something
2607 * for it to do and the bh is not already running.
2608 *
2609 * Note: startup adapter diags require interrupts.
2610 * do not request bottom half processing if the
2611 * device is not open in a normal mode.
2612 */
8fb06c77 2613 if ( port && (port->port.count || port->netcount) &&
1da177e4
LT		 2614 port->pending_bh && !port->bh_running &&
2615 !port->bh_requested ) {
2616 if ( debug_level >= DEBUG_LEVEL_ISR )
2617 printk("%s(%d):%s queueing bh task.\n",
2618 __FILE__,__LINE__,port->device_name);
2619 schedule_work(&port->task);
0fab6de0 2620 port->bh_requested = true;
1da177e4
LT		 2621 }
2622 }
2623
2624 spin_unlock(&info->lock);
2625
2626 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 2627 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2628 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 2629 return IRQ_HANDLED;
2630}
2631
2632/* Initialize and start device.
2633 */
2634static int startup(SLMP_INFO * info)
2635{
2636 if ( debug_level >= DEBUG_LEVEL_INFO )
2637 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2638
8fb06c77 2639 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4
LT		 2640 return 0;
2641
2642 if (!info->tx_buf) {
5cbded58 2643 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
1da177e4
LT		 2644 if (!info->tx_buf) {
2645 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2646 __FILE__,__LINE__,info->device_name);
2647 return -ENOMEM;
2648 }
2649 }
2650
2651 info->pending_bh = 0;
2652
166692e4
PF		 2653 memset(&info->icount, 0, sizeof(info->icount));
2654
1da177e4
LT		 2655 /* program hardware for current parameters */
2656 reset_port(info);
2657
2658 change_params(info);
2659
40565f19 2660 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
1da177e4 2661
8fb06c77
AC		 2662 if (info->port.tty)
2663 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 2664
8fb06c77 2665 info->port.flags |= ASYNC_INITIALIZED;
1da177e4
LT		 2666
2667 return 0;
2668}
2669
2670/* Called by close() and hangup() to shutdown hardware
2671 */
2672static void shutdown(SLMP_INFO * info)
2673{
2674 unsigned long flags;
2675
8fb06c77 2676 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 2677 return;
2678
2679 if (debug_level >= DEBUG_LEVEL_INFO)
2680 printk("%s(%d):%s synclinkmp_shutdown()\n",
2681 __FILE__,__LINE__, info->device_name );
2682
2683 /* clear status wait queue because status changes */
2684 /* can't happen after shutting down the hardware */
2685 wake_up_interruptible(&info->status_event_wait_q);
2686 wake_up_interruptible(&info->event_wait_q);
2687
2688 del_timer(&info->tx_timer);
2689 del_timer(&info->status_timer);
2690
735d5661
JJ		 2691 kfree(info->tx_buf);
2692 info->tx_buf = NULL;
1da177e4
LT		 2693
2694 spin_lock_irqsave(&info->lock,flags);
2695
2696 reset_port(info);
2697
adc8d746 2698 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
9fe8074b 2699 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 2700 set_signals(info);
2701 }
2702
2703 spin_unlock_irqrestore(&info->lock,flags);
2704
8fb06c77
AC		 2705 if (info->port.tty)
2706 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 2707
8fb06c77 2708 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4
LT		 2709}
2710
2711static void program_hw(SLMP_INFO *info)
2712{
2713 unsigned long flags;
2714
2715 spin_lock_irqsave(&info->lock,flags);
2716
2717 rx_stop(info);
2718 tx_stop(info);
2719
2720 info->tx_count = info->tx_put = info->tx_get = 0;
2721
2722 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2723 hdlc_mode(info);
2724 else
2725 async_mode(info);
2726
2727 set_signals(info);
2728
2729 info->dcd_chkcount = 0;
2730 info->cts_chkcount = 0;
2731 info->ri_chkcount = 0;
2732 info->dsr_chkcount = 0;
2733
2734 info->ie1_value |= (CDCD|CCTS);
2735 write_reg(info, IE1, info->ie1_value);
2736
2737 get_signals(info);
2738
adc8d746 2739 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
1da177e4
LT		 2740 rx_start(info);
2741
2742 spin_unlock_irqrestore(&info->lock,flags);
2743}
2744
2745/* Reconfigure adapter based on new parameters
2746 */
2747static void change_params(SLMP_INFO *info)
2748{
2749 unsigned cflag;
2750 int bits_per_char;
2751
adc8d746 2752 if (!info->port.tty)
1da177e4
LT		 2753 return;
2754
2755 if (debug_level >= DEBUG_LEVEL_INFO)
2756 printk("%s(%d):%s change_params()\n",
2757 __FILE__,__LINE__, info->device_name );
2758
adc8d746 2759 cflag = info->port.tty->termios.c_cflag;
1da177e4 2760
9fe8074b
JP		 2761 /* if B0 rate (hangup) specified then negate RTS and DTR */
2762 /* otherwise assert RTS and DTR */
1da177e4 2763 if (cflag & CBAUD)
9fe8074b 2764 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1da177e4 2765 else
9fe8074b 2766 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 2767
2768 /* byte size and parity */
2769
2770 switch (cflag & CSIZE) {
2771 case CS5: info->params.data_bits = 5; break;
2772 case CS6: info->params.data_bits = 6; break;
2773 case CS7: info->params.data_bits = 7; break;
2774 case CS8: info->params.data_bits = 8; break;
2775 /* Never happens, but GCC is too dumb to figure it out */
2776 default: info->params.data_bits = 7; break;
2777 }
2778
2779 if (cflag & CSTOPB)
2780 info->params.stop_bits = 2;
2781 else
2782 info->params.stop_bits = 1;
2783
2784 info->params.parity = ASYNC_PARITY_NONE;
2785 if (cflag & PARENB) {
2786 if (cflag & PARODD)
2787 info->params.parity = ASYNC_PARITY_ODD;
2788 else
2789 info->params.parity = ASYNC_PARITY_EVEN;
2790#ifdef CMSPAR
2791 if (cflag & CMSPAR)
2792 info->params.parity = ASYNC_PARITY_SPACE;
2793#endif
2794 }
2795
2796 /* calculate number of jiffies to transmit a full
2797 * FIFO (32 bytes) at specified data rate
2798 */
2799 bits_per_char = info->params.data_bits +
2800 info->params.stop_bits + 1;
2801
2802 /* if port data rate is set to 460800 or less then
2803 * allow tty settings to override, otherwise keep the
2804 * current data rate.
2805 */
2806 if (info->params.data_rate <= 460800) {
8fb06c77 2807 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1da177e4
LT		 2808 }
2809
2810 if ( info->params.data_rate ) {
2811 info->timeout = (32*HZ*bits_per_char) /
2812 info->params.data_rate;
2813 }
2814 info->timeout += HZ/50; /* Add .02 seconds of slop */
2815
5604a98e 2816 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
1da177e4
LT		 2817
2818 if (cflag & CLOCAL)
8fb06c77 2819 info->port.flags &= ~ASYNC_CHECK_CD;
1da177e4 2820 else
8fb06c77 2821 info->port.flags |= ASYNC_CHECK_CD;
1da177e4
LT		 2822
2823 /* process tty input control flags */
2824
2825 info->read_status_mask2 = OVRN;
8fb06c77 2826 if (I_INPCK(info->port.tty))
1da177e4 2827 info->read_status_mask2 |= PE | FRME;
8fb06c77 2828 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1da177e4 2829 info->read_status_mask1 |= BRKD;
8fb06c77 2830 if (I_IGNPAR(info->port.tty))
1da177e4 2831 info->ignore_status_mask2 |= PE | FRME;
8fb06c77 2832 if (I_IGNBRK(info->port.tty)) {
1da177e4
LT		 2833 info->ignore_status_mask1 |= BRKD;
2834 /* If ignoring parity and break indicators, ignore
2835 * overruns too. (For real raw support).
2836 */
8fb06c77 2837 if (I_IGNPAR(info->port.tty))
1da177e4
LT		 2838 info->ignore_status_mask2 |= OVRN;
2839 }
2840
2841 program_hw(info);
2842}
2843
2844static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2845{
2846 int err;
2847
2848 if (debug_level >= DEBUG_LEVEL_INFO)
2849 printk("%s(%d):%s get_params()\n",
2850 __FILE__,__LINE__, info->device_name);
2851
166692e4
PF		 2852 if (!user_icount) {
2853 memset(&info->icount, 0, sizeof(info->icount));
2854 } else {
f602501d 2855 mutex_lock(&info->port.mutex);
166692e4 2856 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
f602501d 2857 mutex_unlock(&info->port.mutex);
166692e4
PF		 2858 if (err)
2859 return -EFAULT;
1da177e4
LT		 2860 }
2861
2862 return 0;
2863}
2864
2865static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2866{
2867 int err;
2868 if (debug_level >= DEBUG_LEVEL_INFO)
2869 printk("%s(%d):%s get_params()\n",
2870 __FILE__,__LINE__, info->device_name);
2871
f602501d 2872 mutex_lock(&info->port.mutex);
1da177e4 2873 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
f602501d 2874 mutex_unlock(&info->port.mutex);
1da177e4
LT		 2875 if (err) {
2876 if ( debug_level >= DEBUG_LEVEL_INFO )
2877 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2878 __FILE__,__LINE__,info->device_name);
2879 return -EFAULT;
2880 }
2881
2882 return 0;
2883}
2884
2885static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2886{
2887 unsigned long flags;
2888 MGSL_PARAMS tmp_params;
2889 int err;
2890
2891 if (debug_level >= DEBUG_LEVEL_INFO)
2892 printk("%s(%d):%s set_params\n",
2893 __FILE__,__LINE__,info->device_name );
2894 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2895 if (err) {
2896 if ( debug_level >= DEBUG_LEVEL_INFO )
2897 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2898 __FILE__,__LINE__,info->device_name);
2899 return -EFAULT;
2900 }
2901
f602501d 2902 mutex_lock(&info->port.mutex);
1da177e4
LT		 2903 spin_lock_irqsave(&info->lock,flags);
2904 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2905 spin_unlock_irqrestore(&info->lock,flags);
2906
2907 change_params(info);
f602501d 2908 mutex_unlock(&info->port.mutex);
1da177e4
LT		 2909
2910 return 0;
2911}
2912
2913static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2914{
2915 int err;
2916
2917 if (debug_level >= DEBUG_LEVEL_INFO)
2918 printk("%s(%d):%s get_txidle()=%d\n",
2919 __FILE__,__LINE__, info->device_name, info->idle_mode);
2920
2921 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2922 if (err) {
2923 if ( debug_level >= DEBUG_LEVEL_INFO )
2924 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2925 __FILE__,__LINE__,info->device_name);
2926 return -EFAULT;
2927 }
2928
2929 return 0;
2930}
2931
2932static int set_txidle(SLMP_INFO * info, int idle_mode)
2933{
2934 unsigned long flags;
2935
2936 if (debug_level >= DEBUG_LEVEL_INFO)
2937 printk("%s(%d):%s set_txidle(%d)\n",
2938 __FILE__,__LINE__,info->device_name, idle_mode );
2939
2940 spin_lock_irqsave(&info->lock,flags);
2941 info->idle_mode = idle_mode;
2942 tx_set_idle( info );
2943 spin_unlock_irqrestore(&info->lock,flags);
2944 return 0;
2945}
2946
2947static int tx_enable(SLMP_INFO * info, int enable)
2948{
2949 unsigned long flags;
2950
2951 if (debug_level >= DEBUG_LEVEL_INFO)
2952 printk("%s(%d):%s tx_enable(%d)\n",
2953 __FILE__,__LINE__,info->device_name, enable);
2954
2955 spin_lock_irqsave(&info->lock,flags);
2956 if ( enable ) {
2957 if ( !info->tx_enabled ) {
2958 tx_start(info);
2959 }
2960 } else {
2961 if ( info->tx_enabled )
2962 tx_stop(info);
2963 }
2964 spin_unlock_irqrestore(&info->lock,flags);
2965 return 0;
2966}
2967
2968/* abort send HDLC frame
2969 */
2970static int tx_abort(SLMP_INFO * info)
2971{
2972 unsigned long flags;
2973
2974 if (debug_level >= DEBUG_LEVEL_INFO)
2975 printk("%s(%d):%s tx_abort()\n",
2976 __FILE__,__LINE__,info->device_name);
2977
2978 spin_lock_irqsave(&info->lock,flags);
2979 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2980 info->ie1_value &= ~UDRN;
2981 info->ie1_value |= IDLE;
2982 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2983 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2984
2985 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2986 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2987
2988 write_reg(info, CMD, TXABORT);
2989 }
2990 spin_unlock_irqrestore(&info->lock,flags);
2991 return 0;
2992}
2993
2994static int rx_enable(SLMP_INFO * info, int enable)
2995{
2996 unsigned long flags;
2997
2998 if (debug_level >= DEBUG_LEVEL_INFO)
2999 printk("%s(%d):%s rx_enable(%d)\n",
3000 __FILE__,__LINE__,info->device_name,enable);
3001
3002 spin_lock_irqsave(&info->lock,flags);
3003 if ( enable ) {
3004 if ( !info->rx_enabled )
3005 rx_start(info);
3006 } else {
3007 if ( info->rx_enabled )
3008 rx_stop(info);
3009 }
3010 spin_unlock_irqrestore(&info->lock,flags);
3011 return 0;
3012}
3013
1da177e4
LT		 3014/* wait for specified event to occur
3015 */
3016static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3017{
3018 unsigned long flags;
3019 int s;
3020 int rc=0;
3021 struct mgsl_icount cprev, cnow;
3022 int events;
3023 int mask;
3024 struct _input_signal_events oldsigs, newsigs;
3025 DECLARE_WAITQUEUE(wait, current);
3026
3027 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3028 if (rc) {
3029 return -EFAULT;
3030 }
3031
3032 if (debug_level >= DEBUG_LEVEL_INFO)
3033 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3034 __FILE__,__LINE__,info->device_name,mask);
3035
3036 spin_lock_irqsave(&info->lock,flags);
3037
3038 /* return immediately if state matches requested events */
3039 get_signals(info);
7f3edb94 3040 s = info->serial_signals;
1da177e4
LT		 3041
3042 events = mask &
3043 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3044 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3045 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3046 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3047 if (events) {
3048 spin_unlock_irqrestore(&info->lock,flags);
3049 goto exit;
3050 }
3051
3052 /* save current irq counts */
3053 cprev = info->icount;
3054 oldsigs = info->input_signal_events;
3055
3056 /* enable hunt and idle irqs if needed */
3057 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3058 unsigned char oldval = info->ie1_value;
3059 unsigned char newval = oldval +
3060 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3061 (mask & MgslEvent_IdleReceived ? IDLD:0);
3062 if ( oldval != newval ) {
3063 info->ie1_value = newval;
3064 write_reg(info, IE1, info->ie1_value);
3065 }
3066 }
3067
3068 set_current_state(TASK_INTERRUPTIBLE);
3069 add_wait_queue(&info->event_wait_q, &wait);
3070
3071 spin_unlock_irqrestore(&info->lock,flags);
3072
3073 for(;;) {
3074 schedule();
3075 if (signal_pending(current)) {
3076 rc = -ERESTARTSYS;
3077 break;
3078 }
3079
3080 /* get current irq counts */
3081 spin_lock_irqsave(&info->lock,flags);
3082 cnow = info->icount;
3083 newsigs = info->input_signal_events;
3084 set_current_state(TASK_INTERRUPTIBLE);
3085 spin_unlock_irqrestore(&info->lock,flags);
3086
3087 /* if no change, wait aborted for some reason */
3088 if (newsigs.dsr_up == oldsigs.dsr_up &&
3089 newsigs.dsr_down == oldsigs.dsr_down &&
3090 newsigs.dcd_up == oldsigs.dcd_up &&
3091 newsigs.dcd_down == oldsigs.dcd_down &&
3092 newsigs.cts_up == oldsigs.cts_up &&
3093 newsigs.cts_down == oldsigs.cts_down &&
3094 newsigs.ri_up == oldsigs.ri_up &&
3095 newsigs.ri_down == oldsigs.ri_down &&
3096 cnow.exithunt == cprev.exithunt &&
3097 cnow.rxidle == cprev.rxidle) {
3098 rc = -EIO;
3099 break;
3100 }
3101
3102 events = mask &
3103 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3104 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3105 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3106 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3107 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3108 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3109 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3110 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3111 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3112 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3113 if (events)
3114 break;
3115
3116 cprev = cnow;
3117 oldsigs = newsigs;
3118 }
3119
3120 remove_wait_queue(&info->event_wait_q, &wait);
3121 set_current_state(TASK_RUNNING);
3122
3123
3124 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3125 spin_lock_irqsave(&info->lock,flags);
3126 if (!waitqueue_active(&info->event_wait_q)) {
3127 /* disable enable exit hunt mode/idle rcvd IRQs */
3128 info->ie1_value &= ~(FLGD|IDLD);
3129 write_reg(info, IE1, info->ie1_value);
3130 }
3131 spin_unlock_irqrestore(&info->lock,flags);
3132 }
3133exit:
3134 if ( rc == 0 )
3135 PUT_USER(rc, events, mask_ptr);
3136
3137 return rc;
3138}
3139
3140static int modem_input_wait(SLMP_INFO *info,int arg)
3141{
3142 unsigned long flags;
3143 int rc;
3144 struct mgsl_icount cprev, cnow;
3145 DECLARE_WAITQUEUE(wait, current);
3146
3147 /* save current irq counts */
3148 spin_lock_irqsave(&info->lock,flags);
3149 cprev = info->icount;
3150 add_wait_queue(&info->status_event_wait_q, &wait);
3151 set_current_state(TASK_INTERRUPTIBLE);
3152 spin_unlock_irqrestore(&info->lock,flags);
3153
3154 for(;;) {
3155 schedule();
3156 if (signal_pending(current)) {
3157 rc = -ERESTARTSYS;
3158 break;
3159 }
3160
3161 /* get new irq counts */
3162 spin_lock_irqsave(&info->lock,flags);
3163 cnow = info->icount;
3164 set_current_state(TASK_INTERRUPTIBLE);
3165 spin_unlock_irqrestore(&info->lock,flags);
3166
3167 /* if no change, wait aborted for some reason */
3168 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3169 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3170 rc = -EIO;
3171 break;
3172 }
3173
3174 /* check for change in caller specified modem input */
3175 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3176 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3177 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3178 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3179 rc = 0;
3180 break;
3181 }
3182
3183 cprev = cnow;
3184 }
3185 remove_wait_queue(&info->status_event_wait_q, &wait);
3186 set_current_state(TASK_RUNNING);
3187 return rc;
3188}
3189
3190/* return the state of the serial control and status signals
3191 */
60b33c13 3192static int tiocmget(struct tty_struct *tty)
1da177e4 3193{
c9f19e96 3194 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 3195 unsigned int result;
3196 unsigned long flags;
3197
3198 spin_lock_irqsave(&info->lock,flags);
3199 get_signals(info);
3200 spin_unlock_irqrestore(&info->lock,flags);
3201
9fe8074b
JP		 3202 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3203 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3204 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3205 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3206 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3207 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
1da177e4
LT		 3208
3209 if (debug_level >= DEBUG_LEVEL_INFO)
3210 printk("%s(%d):%s tiocmget() value=%08X\n",
3211 __FILE__,__LINE__, info->device_name, result );
3212 return result;
3213}
3214
3215/* set modem control signals (DTR/RTS)
3216 */
20b9d177
AC		 3217static int tiocmset(struct tty_struct *tty,
3218 unsigned int set, unsigned int clear)
1da177e4 3219{
c9f19e96 3220 SLMP_INFO *info = tty->driver_data;
1da177e4
LT		 3221 unsigned long flags;
3222
3223 if (debug_level >= DEBUG_LEVEL_INFO)
3224 printk("%s(%d):%s tiocmset(%x,%x)\n",
3225 __FILE__,__LINE__,info->device_name, set, clear);
3226
3227 if (set & TIOCM_RTS)
3228 info->serial_signals |= SerialSignal_RTS;
3229 if (set & TIOCM_DTR)
3230 info->serial_signals |= SerialSignal_DTR;
3231 if (clear & TIOCM_RTS)
3232 info->serial_signals &= ~SerialSignal_RTS;
3233 if (clear & TIOCM_DTR)
3234 info->serial_signals &= ~SerialSignal_DTR;
3235
3236 spin_lock_irqsave(&info->lock,flags);
3237 set_signals(info);
3238 spin_unlock_irqrestore(&info->lock,flags);
3239
3240 return 0;
3241}
3242
31f35939
AC		 3243static int carrier_raised(struct tty_port *port)
3244{
3245 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3246 unsigned long flags;
1da177e4 3247
31f35939
AC		 3248 spin_lock_irqsave(&info->lock,flags);
3249 get_signals(info);
3250 spin_unlock_irqrestore(&info->lock,flags);
3251
3252 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3253}
1da177e4 3254
fcc8ac18 3255static void dtr_rts(struct tty_port *port, int on)
3e61696b
AC		 3256{
3257 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3258 unsigned long flags;
3259
3260 spin_lock_irqsave(&info->lock,flags);
fcc8ac18 3261 if (on)
9fe8074b 3262 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
fcc8ac18 3263 else
9fe8074b 3264 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3e61696b
AC		 3265 set_signals(info);
3266 spin_unlock_irqrestore(&info->lock,flags);
3267}
3268
1da177e4
LT		 3269/* Block the current process until the specified port is ready to open.
3270 */
3271static int block_til_ready(struct tty_struct *tty, struct file *filp,
3272 SLMP_INFO *info)
3273{
3274 DECLARE_WAITQUEUE(wait, current);
3275 int retval;
0fab6de0 3276 bool do_clocal = false;
1da177e4 3277 unsigned long flags;
31f35939
AC		 3278 int cd;
3279 struct tty_port *port = &info->port;
1da177e4
LT		 3280
3281 if (debug_level >= DEBUG_LEVEL_INFO)
3282 printk("%s(%d):%s block_til_ready()\n",
3283 __FILE__,__LINE__, tty->driver->name );
3284
18900ca6 3285 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
1da177e4
LT		 3286 /* nonblock mode is set or port is not enabled */
3287 /* just verify that callout device is not active */
31f35939 3288 port->flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3289 return 0;
3290 }
3291
9db276f8 3292 if (C_CLOCAL(tty))
0fab6de0 3293 do_clocal = true;
1da177e4
LT		 3294
3295 /* Wait for carrier detect and the line to become
3296 * free (i.e., not in use by the callout). While we are in
31f35939 3297 * this loop, port->count is dropped by one, so that
1da177e4
LT		 3298 * close() knows when to free things. We restore it upon
3299 * exit, either normal or abnormal.
3300 */
3301
3302 retval = 0;
31f35939 3303 add_wait_queue(&port->open_wait, &wait);
1da177e4
LT		 3304
3305 if (debug_level >= DEBUG_LEVEL_INFO)
3306 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
31f35939 3307 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4
LT		 3308
3309 spin_lock_irqsave(&info->lock, flags);
e359a4e3 3310 port->count--;
1da177e4 3311 spin_unlock_irqrestore(&info->lock, flags);
31f35939 3312 port->blocked_open++;
1da177e4
LT		 3313
3314 while (1) {
53a72d57 3315 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3e61696b 3316 tty_port_raise_dtr_rts(port);
1da177e4
LT		 3317
3318 set_current_state(TASK_INTERRUPTIBLE);
3319
31f35939
AC		 3320 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3321 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 3322 -EAGAIN : -ERESTARTSYS;
3323 break;
3324 }
3325
31f35939 3326 cd = tty_port_carrier_raised(port);
fef062cb
PH		 3327 if (do_clocal || cd)
3328 break;
1da177e4
LT		 3329
3330 if (signal_pending(current)) {
3331 retval = -ERESTARTSYS;
3332 break;
3333 }
3334
3335 if (debug_level >= DEBUG_LEVEL_INFO)
3336 printk("%s(%d):%s block_til_ready() count=%d\n",
31f35939 3337 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4 3338
89c8d91e 3339 tty_unlock(tty);
1da177e4 3340 schedule();
89c8d91e 3341 tty_lock(tty);
1da177e4
LT		 3342 }
3343
3344 set_current_state(TASK_RUNNING);
31f35939 3345 remove_wait_queue(&port->open_wait, &wait);
e359a4e3 3346 if (!tty_hung_up_p(filp))
31f35939
AC		 3347 port->count++;
3348 port->blocked_open--;
1da177e4
LT		 3349
3350 if (debug_level >= DEBUG_LEVEL_INFO)
3351 printk("%s(%d):%s block_til_ready() after, count=%d\n",
31f35939 3352 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4
LT		 3353
3354 if (!retval)
31f35939 3355 port->flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3356
3357 return retval;
3358}
3359
ce9f9f73 3360static int alloc_dma_bufs(SLMP_INFO *info)
1da177e4
LT		 3361{
3362 unsigned short BuffersPerFrame;
3363 unsigned short BufferCount;
3364
3365 // Force allocation to start at 64K boundary for each port.
3366 // This is necessary because *all* buffer descriptors for a port
3367 // *must* be in the same 64K block. All descriptors on a port
3368 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3369 // into the CBP register.
3370 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3371
3372 /* Calculate the number of DMA buffers necessary to hold the */
3373 /* largest allowable frame size. Note: If the max frame size is */
3374 /* not an even multiple of the DMA buffer size then we need to */
3375 /* round the buffer count per frame up one. */
3376
3377 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3378 if ( info->max_frame_size % SCABUFSIZE )
3379 BuffersPerFrame++;
3380
3381 /* calculate total number of data buffers (SCABUFSIZE) possible
3382 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3383 * for the descriptor list (BUFFERLISTSIZE).
3384 */
3385 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3386
3387 /* limit number of buffers to maximum amount of descriptors */
3388 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3389 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3390
3391 /* use enough buffers to transmit one max size frame */
3392 info->tx_buf_count = BuffersPerFrame + 1;
3393
3394 /* never use more than half the available buffers for transmit */
3395 if (info->tx_buf_count > (BufferCount/2))
3396 info->tx_buf_count = BufferCount/2;
3397
3398 if (info->tx_buf_count > SCAMAXDESC)
3399 info->tx_buf_count = SCAMAXDESC;
3400
3401 /* use remaining buffers for receive */
3402 info->rx_buf_count = BufferCount - info->tx_buf_count;
3403
3404 if (info->rx_buf_count > SCAMAXDESC)
3405 info->rx_buf_count = SCAMAXDESC;
3406
3407 if ( debug_level >= DEBUG_LEVEL_INFO )
3408 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3409 __FILE__,__LINE__, info->device_name,
3410 info->tx_buf_count,info->rx_buf_count);
3411
3412 if ( alloc_buf_list( info ) < 0 ||
3413 alloc_frame_bufs(info,
3414 info->rx_buf_list,
3415 info->rx_buf_list_ex,
3416 info->rx_buf_count) < 0 ||
3417 alloc_frame_bufs(info,
3418 info->tx_buf_list,
3419 info->tx_buf_list_ex,
3420 info->tx_buf_count) < 0 ||
3421 alloc_tmp_rx_buf(info) < 0 ) {
3422 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3423 __FILE__,__LINE__, info->device_name);
3424 return -ENOMEM;
3425 }
3426
3427 rx_reset_buffers( info );
3428
3429 return 0;
3430}
3431
3432/* Allocate DMA buffers for the transmit and receive descriptor lists.
3433 */
ce9f9f73 3434static int alloc_buf_list(SLMP_INFO *info)
1da177e4
LT		 3435{
3436 unsigned int i;
3437
3438 /* build list in adapter shared memory */
3439 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3440 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3441 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3442
3443 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3444
3445 /* Save virtual address pointers to the receive and */
3446 /* transmit buffer lists. (Receive 1st). These pointers will */
3447 /* be used by the processor to access the lists. */
3448 info->rx_buf_list = (SCADESC *)info->buffer_list;
3449
3450 info->tx_buf_list = (SCADESC *)info->buffer_list;
3451 info->tx_buf_list += info->rx_buf_count;
3452
3453 /* Build links for circular buffer entry lists (tx and rx)
3454 *
3455 * Note: links are physical addresses read by the SCA device
3456 * to determine the next buffer entry to use.
3457 */
3458
3459 for ( i = 0; i < info->rx_buf_count; i++ ) {
3460 /* calculate and store physical address of this buffer entry */
3461 info->rx_buf_list_ex[i].phys_entry =
2652c216 3462 info->buffer_list_phys + (i * SCABUFSIZE);
1da177e4
LT		 3463
3464 /* calculate and store physical address of */
3465 /* next entry in cirular list of entries */
3466 info->rx_buf_list[i].next = info->buffer_list_phys;
3467 if ( i < info->rx_buf_count - 1 )
3468 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3469
3470 info->rx_buf_list[i].length = SCABUFSIZE;
3471 }
3472
3473 for ( i = 0; i < info->tx_buf_count; i++ ) {
3474 /* calculate and store physical address of this buffer entry */
3475 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3476 ((info->rx_buf_count + i) * sizeof(SCADESC));
3477
3478 /* calculate and store physical address of */
3479 /* next entry in cirular list of entries */
3480
3481 info->tx_buf_list[i].next = info->buffer_list_phys +
3482 info->rx_buf_count * sizeof(SCADESC);
3483
3484 if ( i < info->tx_buf_count - 1 )
3485 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3486 }
3487
3488 return 0;
3489}
3490
3491/* Allocate the frame DMA buffers used by the specified buffer list.
3492 */
ce9f9f73 3493static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
1da177e4
LT		 3494{
3495 int i;
3496 unsigned long phys_addr;
3497
3498 for ( i = 0; i < count; i++ ) {
3499 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3500 phys_addr = info->port_array[0]->last_mem_alloc;
3501 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3502
3503 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3504 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3505 }
3506
3507 return 0;
3508}
3509
ce9f9f73 3510static void free_dma_bufs(SLMP_INFO *info)
1da177e4
LT		 3511{
3512 info->buffer_list = NULL;
3513 info->rx_buf_list = NULL;
3514 info->tx_buf_list = NULL;
3515}
3516
3517/* allocate buffer large enough to hold max_frame_size.
3518 * This buffer is used to pass an assembled frame to the line discipline.
3519 */
ce9f9f73 3520static int alloc_tmp_rx_buf(SLMP_INFO *info)
1da177e4
LT		 3521{
3522 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3523 if (info->tmp_rx_buf == NULL)
3524 return -ENOMEM;
a6b68a69
PF		 3525 /* unused flag buffer to satisfy receive_buf calling interface */
3526 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3527 if (!info->flag_buf) {
3528 kfree(info->tmp_rx_buf);
3529 info->tmp_rx_buf = NULL;
3530 return -ENOMEM;
3531 }
1da177e4
LT		 3532 return 0;
3533}
3534
ce9f9f73 3535static void free_tmp_rx_buf(SLMP_INFO *info)
1da177e4 3536{
735d5661 3537 kfree(info->tmp_rx_buf);
1da177e4 3538 info->tmp_rx_buf = NULL;
a6b68a69
PF		 3539 kfree(info->flag_buf);
3540 info->flag_buf = NULL;
1da177e4
LT		 3541}
3542
ce9f9f73 3543static int claim_resources(SLMP_INFO *info)
1da177e4
LT		 3544{
3545 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3546 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3547 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3548 info->init_error = DiagStatus_AddressConflict;
3549 goto errout;
3550 }
3551 else
0fab6de0 3552 info->shared_mem_requested = true;
1da177e4
LT		 3553
3554 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3555 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3556 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3557 info->init_error = DiagStatus_AddressConflict;
3558 goto errout;
3559 }
3560 else
0fab6de0 3561 info->lcr_mem_requested = true;
1da177e4
LT		 3562
3563 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3564 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3565 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3566 info->init_error = DiagStatus_AddressConflict;
3567 goto errout;
3568 }
3569 else
0fab6de0 3570 info->sca_base_requested = true;
1da177e4
LT		 3571
3572 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3573 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3574 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3575 info->init_error = DiagStatus_AddressConflict;
3576 goto errout;
3577 }
3578 else
0fab6de0 3579 info->sca_statctrl_requested = true;
1da177e4 3580
24cb2335
AC		 3581 info->memory_base = ioremap_nocache(info->phys_memory_base,
3582 SCA_MEM_SIZE);
1da177e4 3583 if (!info->memory_base) {
25985edc 3584 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
1da177e4
LT		 3585 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3586 info->init_error = DiagStatus_CantAssignPciResources;
3587 goto errout;
3588 }
3589
24cb2335 3590 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
1da177e4 3591 if (!info->lcr_base) {
25985edc 3592 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
1da177e4
LT		 3593 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3594 info->init_error = DiagStatus_CantAssignPciResources;
3595 goto errout;
3596 }
3597 info->lcr_base += info->lcr_offset;
3598
24cb2335 3599 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
1da177e4 3600 if (!info->sca_base) {
25985edc 3601 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
1da177e4
LT		 3602 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3603 info->init_error = DiagStatus_CantAssignPciResources;
3604 goto errout;
3605 }
3606 info->sca_base += info->sca_offset;
3607
24cb2335
AC		 3608 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3609 PAGE_SIZE);
1da177e4 3610 if (!info->statctrl_base) {
25985edc 3611 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
1da177e4
LT		 3612 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3613 info->init_error = DiagStatus_CantAssignPciResources;
3614 goto errout;
3615 }
3616 info->statctrl_base += info->statctrl_offset;
3617
3618 if ( !memory_test(info) ) {
3619 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3620 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3621 info->init_error = DiagStatus_MemoryError;
3622 goto errout;
3623 }
3624
3625 return 0;
3626
3627errout:
3628 release_resources( info );
3629 return -ENODEV;
3630}
3631
ce9f9f73 3632static void release_resources(SLMP_INFO *info)
1da177e4
LT		 3633{
3634 if ( debug_level >= DEBUG_LEVEL_INFO )
3635 printk( "%s(%d):%s release_resources() entry\n",
3636 __FILE__,__LINE__,info->device_name );
3637
3638 if ( info->irq_requested ) {
3639 free_irq(info->irq_level, info);
0fab6de0 3640 info->irq_requested = false;
1da177e4
LT		 3641 }
3642
3643 if ( info->shared_mem_requested ) {
3644 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
0fab6de0 3645 info->shared_mem_requested = false;
1da177e4
LT		 3646 }
3647 if ( info->lcr_mem_requested ) {
3648 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
0fab6de0 3649 info->lcr_mem_requested = false;
1da177e4
LT		 3650 }
3651 if ( info->sca_base_requested ) {
3652 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
0fab6de0 3653 info->sca_base_requested = false;
1da177e4
LT		 3654 }
3655 if ( info->sca_statctrl_requested ) {
3656 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
0fab6de0 3657 info->sca_statctrl_requested = false;
1da177e4
LT		 3658 }
3659
3660 if (info->memory_base){
3661 iounmap(info->memory_base);
3662 info->memory_base = NULL;
3663 }
3664
3665 if (info->sca_base) {
3666 iounmap(info->sca_base - info->sca_offset);
3667 info->sca_base=NULL;
3668 }
3669
3670 if (info->statctrl_base) {
3671 iounmap(info->statctrl_base - info->statctrl_offset);
3672 info->statctrl_base=NULL;
3673 }
3674
3675 if (info->lcr_base){
3676 iounmap(info->lcr_base - info->lcr_offset);
3677 info->lcr_base = NULL;
3678 }
3679
3680 if ( debug_level >= DEBUG_LEVEL_INFO )
3681 printk( "%s(%d):%s release_resources() exit\n",
3682 __FILE__,__LINE__,info->device_name );
3683}
3684
3685/* Add the specified device instance data structure to the
3686 * global linked list of devices and increment the device count.
3687 */
b1209983 3688static int add_device(SLMP_INFO *info)
1da177e4
LT		 3689{
3690 info->next_device = NULL;
3691 info->line = synclinkmp_device_count;
3692 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3693
3694 if (info->line < MAX_DEVICES) {
3695 if (maxframe[info->line])
3696 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 3697 }
3698
3699 synclinkmp_device_count++;
3700
3701 if ( !synclinkmp_device_list )
3702 synclinkmp_device_list = info;
3703 else {
3704 SLMP_INFO *current_dev = synclinkmp_device_list;
3705 while( current_dev->next_device )
3706 current_dev = current_dev->next_device;
3707 current_dev->next_device = info;
3708 }
3709
3710 if ( info->max_frame_size < 4096 )
3711 info->max_frame_size = 4096;
3712 else if ( info->max_frame_size > 65535 )
3713 info->max_frame_size = 65535;
3714
3715 printk( "SyncLink MultiPort %s: "
3716 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3717 info->device_name,
3718 info->phys_sca_base,
3719 info->phys_memory_base,
3720 info->phys_statctrl_base,
3721 info->phys_lcr_base,
3722 info->irq_level,
3723 info->max_frame_size );
3724
af69c7f9 3725#if SYNCLINK_GENERIC_HDLC
b1209983
AK		 3726 return hdlcdev_init(info);
3727#else
3728 return 0;
1da177e4
LT		 3729#endif
3730}
3731
31f35939
AC		 3732static const struct tty_port_operations port_ops = {
3733 .carrier_raised = carrier_raised,
fcc8ac18 3734 .dtr_rts = dtr_rts,
31f35939
AC		 3735};
3736
1da177e4
LT		 3737/* Allocate and initialize a device instance structure
3738 *
3739 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3740 */
3741static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3742{
3743 SLMP_INFO *info;
3744
dd00cc48 3745 info = kzalloc(sizeof(SLMP_INFO),
1da177e4
LT		 3746 GFP_KERNEL);
3747
3748 if (!info) {
3749 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3750 __FILE__,__LINE__, adapter_num, port_num);
3751 } else {
44b7d1b3 3752 tty_port_init(&info->port);
31f35939 3753 info->port.ops = &port_ops;
1da177e4 3754 info->magic = MGSL_MAGIC;
c4028958 3755 INIT_WORK(&info->task, bh_handler);
1da177e4 3756 info->max_frame_size = 4096;
44b7d1b3
AC		 3757 info->port.close_delay = 5*HZ/10;
3758 info->port.closing_wait = 30*HZ;
1da177e4
LT		 3759 init_waitqueue_head(&info->status_event_wait_q);
3760 init_waitqueue_head(&info->event_wait_q);
3761 spin_lock_init(&info->netlock);
3762 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3763 info->idle_mode = HDLC_TXIDLE_FLAGS;
3764 info->adapter_num = adapter_num;
3765 info->port_num = port_num;
3766
3767 /* Copy configuration info to device instance data */
3768 info->irq_level = pdev->irq;
3769 info->phys_lcr_base = pci_resource_start(pdev,0);
3770 info->phys_sca_base = pci_resource_start(pdev,2);
3771 info->phys_memory_base = pci_resource_start(pdev,3);
3772 info->phys_statctrl_base = pci_resource_start(pdev,4);
3773
3774 /* Because veremap only works on page boundaries we must map
3775 * a larger area than is actually implemented for the LCR
3776 * memory range. We map a full page starting at the page boundary.
3777 */
3778 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3779 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3780
3781 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3782 info->phys_sca_base &= ~(PAGE_SIZE-1);
3783
3784 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3785 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3786
3787 info->bus_type = MGSL_BUS_TYPE_PCI;
0f2ed4c6 3788 info->irq_flags = IRQF_SHARED;
1da177e4 3789
40565f19
JS		 3790 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3791 setup_timer(&info->status_timer, status_timeout,
3792 (unsigned long)info);
1da177e4
LT		 3793
3794 /* Store the PCI9050 misc control register value because a flaw
3795 * in the PCI9050 prevents LCR registers from being read if
3796 * BIOS assigns an LCR base address with bit 7 set.
3797 *
3798 * Only the misc control register is accessed for which only
3799 * write access is needed, so set an initial value and change
3800 * bits to the device instance data as we write the value
3801 * to the actual misc control register.
3802 */
3803 info->misc_ctrl_value = 0x087e4546;
3804
3805 /* initial port state is unknown - if startup errors
3806 * occur, init_error will be set to indicate the
3807 * problem. Once the port is fully initialized,
3808 * this value will be set to 0 to indicate the
3809 * port is available.
3810 */
3811 info->init_error = -1;
3812 }
3813
3814 return info;
3815}
3816
b1209983 3817static int device_init(int adapter_num, struct pci_dev *pdev)
1da177e4
LT		 3818{
3819 SLMP_INFO *port_array[SCA_MAX_PORTS];
b1209983 3820 int port, rc;
1da177e4
LT		 3821
3822 /* allocate device instances for up to SCA_MAX_PORTS devices */
3823 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3824 port_array[port] = alloc_dev(adapter_num,port,pdev);
3825 if( port_array[port] == NULL ) {
191c5f10
JS		 3826 for (--port; port >= 0; --port) {
3827 tty_port_destroy(&port_array[port]->port);
1da177e4 3828 kfree(port_array[port]);
191c5f10 3829 }
b1209983 3830 return -ENOMEM;
1da177e4
LT		 3831 }
3832 }
3833
3834 /* give copy of port_array to all ports and add to device list */
3835 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3836 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
b1209983
AK		 3837 rc = add_device( port_array[port] );
3838 if (rc)
3839 goto err_add;
1da177e4
LT		 3840 spin_lock_init(&port_array[port]->lock);
3841 }
3842
3843 /* Allocate and claim adapter resources */
3844 if ( !claim_resources(port_array[0]) ) {
3845
3846 alloc_dma_bufs(port_array[0]);
3847
3848 /* copy resource information from first port to others */
3849 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3850 port_array[port]->lock = port_array[0]->lock;
3851 port_array[port]->irq_level = port_array[0]->irq_level;
3852 port_array[port]->memory_base = port_array[0]->memory_base;
3853 port_array[port]->sca_base = port_array[0]->sca_base;
3854 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3855 port_array[port]->lcr_base = port_array[0]->lcr_base;
3856 alloc_dma_bufs(port_array[port]);
3857 }
3858
b1209983 3859 rc = request_irq(port_array[0]->irq_level,
1da177e4
LT		 3860 synclinkmp_interrupt,
3861 port_array[0]->irq_flags,
3862 port_array[0]->device_name,
b1209983
AK		 3863 port_array[0]);
3864 if ( rc ) {
25985edc 3865 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
1da177e4
LT		 3866 __FILE__,__LINE__,
3867 port_array[0]->device_name,
3868 port_array[0]->irq_level );
b1209983 3869 goto err_irq;
1da177e4 3870 }
b1209983
AK		 3871 port_array[0]->irq_requested = true;
3872 adapter_test(port_array[0]);
1da177e4 3873 }
b1209983
AK		 3874 return 0;
3875err_irq:
3876 release_resources( port_array[0] );
3877err_add:
3878 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3879 tty_port_destroy(&port_array[port]->port);
3880 kfree(port_array[port]);
3881 }
3882 return rc;
1da177e4
LT		 3883}
3884
b68e31d0 3885static const struct tty_operations ops = {
ee3b48da 3886 .install = install,
1da177e4
LT		 3887 .open = open,
3888 .close = close,
3889 .write = write,
3890 .put_char = put_char,
3891 .flush_chars = flush_chars,
3892 .write_room = write_room,
3893 .chars_in_buffer = chars_in_buffer,
3894 .flush_buffer = flush_buffer,
3895 .ioctl = ioctl,
3896 .throttle = throttle,
3897 .unthrottle = unthrottle,
3898 .send_xchar = send_xchar,
3899 .break_ctl = set_break,
3900 .wait_until_sent = wait_until_sent,
1da177e4
LT		 3901 .set_termios = set_termios,
3902 .stop = tx_hold,
3903 .start = tx_release,
3904 .hangup = hangup,
3905 .tiocmget = tiocmget,
3906 .tiocmset = tiocmset,
0587102c 3907 .get_icount = get_icount,
e6c8dd8a 3908 .proc_fops = &synclinkmp_proc_fops,
1da177e4
LT		 3909};
3910
31f35939 3911
1da177e4
LT		 3912static void synclinkmp_cleanup(void)
3913{
3914 int rc;
3915 SLMP_INFO *info;
3916 SLMP_INFO *tmp;
3917
3918 printk("Unloading %s %s\n", driver_name, driver_version);
3919
3920 if (serial_driver) {
485e148d
GKH		 3921 rc = tty_unregister_driver(serial_driver);
3922 if (rc)
1da177e4
LT		 3923 printk("%s(%d) failed to unregister tty driver err=%d\n",
3924 __FILE__,__LINE__,rc);
3925 put_tty_driver(serial_driver);
3926 }
3927
3928 /* reset devices */
3929 info = synclinkmp_device_list;
3930 while(info) {
3931 reset_port(info);
3932 info = info->next_device;
3933 }
3934
3935 /* release devices */
3936 info = synclinkmp_device_list;
3937 while(info) {
af69c7f9 3938#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3939 hdlcdev_exit(info);
3940#endif
3941 free_dma_bufs(info);
3942 free_tmp_rx_buf(info);
3943 if ( info->port_num == 0 ) {
3944 if (info->sca_base)
3945 write_reg(info, LPR, 1); /* set low power mode */
3946 release_resources(info);
3947 }
3948 tmp = info;
3949 info = info->next_device;
191c5f10 3950 tty_port_destroy(&tmp->port);
1da177e4
LT		 3951 kfree(tmp);
3952 }
3953
3954 pci_unregister_driver(&synclinkmp_pci_driver);
3955}
3956
3957/* Driver initialization entry point.
3958 */
3959
3960static int __init synclinkmp_init(void)
3961{
3962 int rc;
3963
3964 if (break_on_load) {
3965 synclinkmp_get_text_ptr();
3966 BREAKPOINT();
3967 }
3968
3969 printk("%s %s\n", driver_name, driver_version);
3970
3971 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3972 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3973 return rc;
3974 }
3975
3976 serial_driver = alloc_tty_driver(128);
3977 if (!serial_driver) {
3978 rc = -ENOMEM;
3979 goto error;
3980 }
3981
3982 /* Initialize the tty_driver structure */
3983
1da177e4
LT		 3984 serial_driver->driver_name = "synclinkmp";
3985 serial_driver->name = "ttySLM";
3986 serial_driver->major = ttymajor;
3987 serial_driver->minor_start = 64;
3988 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3989 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3990 serial_driver->init_termios = tty_std_termios;
3991 serial_driver->init_termios.c_cflag =
3992 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 3993 serial_driver->init_termios.c_ispeed = 9600;
3994 serial_driver->init_termios.c_ospeed = 9600;
1da177e4
LT		 3995 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3996 tty_set_operations(serial_driver, &ops);
3997 if ((rc = tty_register_driver(serial_driver)) < 0) {
3998 printk("%s(%d):Couldn't register serial driver\n",
3999 __FILE__,__LINE__);
4000 put_tty_driver(serial_driver);
4001 serial_driver = NULL;
4002 goto error;
4003 }
4004
4005 printk("%s %s, tty major#%d\n",
4006 driver_name, driver_version,
4007 serial_driver->major);
4008
4009 return 0;
4010
4011error:
4012 synclinkmp_cleanup();
4013 return rc;
4014}
4015
4016static void __exit synclinkmp_exit(void)
4017{
4018 synclinkmp_cleanup();
4019}
4020
4021module_init(synclinkmp_init);
4022module_exit(synclinkmp_exit);
4023
4024/* Set the port for internal loopback mode.
4025 * The TxCLK and RxCLK signals are generated from the BRG and
4026 * the TxD is looped back to the RxD internally.
4027 */
ce9f9f73 4028static void enable_loopback(SLMP_INFO *info, int enable)
1da177e4
LT		 4029{
4030 if (enable) {
4031 /* MD2 (Mode Register 2)
4032 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4033 */
4034 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4035
4036 /* degate external TxC clock source */
4037 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4038 write_control_reg(info);
4039
4040 /* RXS/TXS (Rx/Tx clock source)
4041 * 07 Reserved, must be 0
4042 * 06..04 Clock Source, 100=BRG
4043 * 03..00 Clock Divisor, 0000=1
4044 */
4045 write_reg(info, RXS, 0x40);
4046 write_reg(info, TXS, 0x40);
4047
4048 } else {
4049 /* MD2 (Mode Register 2)
4050 * 01..00 CNCT<1..0> Channel connection, 0=normal
4051 */
4052 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4053
4054 /* RXS/TXS (Rx/Tx clock source)
4055 * 07 Reserved, must be 0
4056 * 06..04 Clock Source, 000=RxC/TxC Pin
4057 * 03..00 Clock Divisor, 0000=1
4058 */
4059 write_reg(info, RXS, 0x00);
4060 write_reg(info, TXS, 0x00);
4061 }
4062
4063 /* set LinkSpeed if available, otherwise default to 2Mbps */
4064 if (info->params.clock_speed)
4065 set_rate(info, info->params.clock_speed);
4066 else
4067 set_rate(info, 3686400);
4068}
4069
4070/* Set the baud rate register to the desired speed
4071 *
4072 * data_rate data rate of clock in bits per second
4073 * A data rate of 0 disables the AUX clock.
4074 */
ce9f9f73 4075static void set_rate( SLMP_INFO *info, u32 data_rate )
1da177e4
LT		 4076{
4077 u32 TMCValue;
4078 unsigned char BRValue;
4079 u32 Divisor=0;
4080
4081 /* fBRG = fCLK/(TMC * 2^BR)
4082 */
4083 if (data_rate != 0) {
4084 Divisor = 14745600/data_rate;
4085 if (!Divisor)
4086 Divisor = 1;
4087
4088 TMCValue = Divisor;
4089
4090 BRValue = 0;
4091 if (TMCValue != 1 && TMCValue != 2) {
4092 /* BRValue of 0 provides 50/50 duty cycle *only* when
4093 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4094 * 50/50 duty cycle.
4095 */
4096 BRValue = 1;
4097 TMCValue >>= 1;
4098 }
4099
4100 /* while TMCValue is too big for TMC register, divide
4101 * by 2 and increment BR exponent.
4102 */
4103 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4104 TMCValue >>= 1;
4105
4106 write_reg(info, TXS,
4107 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4108 write_reg(info, RXS,
4109 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4110 write_reg(info, TMC, (unsigned char)TMCValue);
4111 }
4112 else {
4113 write_reg(info, TXS,0);
4114 write_reg(info, RXS,0);
4115 write_reg(info, TMC, 0);
4116 }
4117}
4118
4119/* Disable receiver
4120 */
ce9f9f73 4121static void rx_stop(SLMP_INFO *info)
1da177e4
LT		 4122{
4123 if (debug_level >= DEBUG_LEVEL_ISR)
4124 printk("%s(%d):%s rx_stop()\n",
4125 __FILE__,__LINE__, info->device_name );
4126
4127 write_reg(info, CMD, RXRESET);
4128
4129 info->ie0_value &= ~RXRDYE;
4130 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4131
4132 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4133 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4134 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4135
0fab6de0
JP		 4136 info->rx_enabled = false;
4137 info->rx_overflow = false;
1da177e4
LT		 4138}
4139
4140/* enable the receiver
4141 */
ce9f9f73 4142static void rx_start(SLMP_INFO *info)
1da177e4
LT		 4143{
4144 int i;
4145
4146 if (debug_level >= DEBUG_LEVEL_ISR)
4147 printk("%s(%d):%s rx_start()\n",
4148 __FILE__,__LINE__, info->device_name );
4149
4150 write_reg(info, CMD, RXRESET);
4151
4152 if ( info->params.mode == MGSL_MODE_HDLC ) {
4153 /* HDLC, disabe IRQ on rxdata */
4154 info->ie0_value &= ~RXRDYE;
4155 write_reg(info, IE0, info->ie0_value);
4156
4157 /* Reset all Rx DMA buffers and program rx dma */
4158 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4159 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4160
4161 for (i = 0; i < info->rx_buf_count; i++) {
4162 info->rx_buf_list[i].status = 0xff;
4163
4164 // throttle to 4 shared memory writes at a time to prevent
4165 // hogging local bus (keep latency time for DMA requests low).
4166 if (!(i % 4))
4167 read_status_reg(info);
4168 }
4169 info->current_rx_buf = 0;
4170
4171 /* set current/1st descriptor address */
4172 write_reg16(info, RXDMA + CDA,
4173 info->rx_buf_list_ex[0].phys_entry);
4174
4175 /* set new last rx descriptor address */
4176 write_reg16(info, RXDMA + EDA,
4177 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4178
4179 /* set buffer length (shared by all rx dma data buffers) */
4180 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4181
4182 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4183 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4184 } else {
4185 /* async, enable IRQ on rxdata */
4186 info->ie0_value |= RXRDYE;
4187 write_reg(info, IE0, info->ie0_value);
4188 }
4189
4190 write_reg(info, CMD, RXENABLE);
4191
0fab6de0
JP		 4192 info->rx_overflow = false;
4193 info->rx_enabled = true;
1da177e4
LT		 4194}
4195
4196/* Enable the transmitter and send a transmit frame if
4197 * one is loaded in the DMA buffers.
4198 */
ce9f9f73 4199static void tx_start(SLMP_INFO *info)
1da177e4
LT		 4200{
4201 if (debug_level >= DEBUG_LEVEL_ISR)
4202 printk("%s(%d):%s tx_start() tx_count=%d\n",
4203 __FILE__,__LINE__, info->device_name,info->tx_count );
4204
4205 if (!info->tx_enabled ) {
4206 write_reg(info, CMD, TXRESET);
4207 write_reg(info, CMD, TXENABLE);
0fab6de0 4208 info->tx_enabled = true;
1da177e4
LT		 4209 }
4210
4211 if ( info->tx_count ) {
4212
4213 /* If auto RTS enabled and RTS is inactive, then assert */
4214 /* RTS and set a flag indicating that the driver should */
4215 /* negate RTS when the transmission completes. */
4216
0fab6de0 4217 info->drop_rts_on_tx_done = false;
1da177e4
LT		 4218
4219 if (info->params.mode != MGSL_MODE_ASYNC) {
4220
4221 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4222 get_signals( info );
4223 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4224 info->serial_signals |= SerialSignal_RTS;
4225 set_signals( info );
0fab6de0 4226 info->drop_rts_on_tx_done = true;
1da177e4
LT		 4227 }
4228 }
4229
4230 write_reg16(info, TRC0,
4231 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4232
4233 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4234 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4235
4236 /* set TX CDA (current descriptor address) */
4237 write_reg16(info, TXDMA + CDA,
4238 info->tx_buf_list_ex[0].phys_entry);
4239
4240 /* set TX EDA (last descriptor address) */
4241 write_reg16(info, TXDMA + EDA,
4242 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4243
4244 /* enable underrun IRQ */
4245 info->ie1_value &= ~IDLE;
4246 info->ie1_value |= UDRN;
4247 write_reg(info, IE1, info->ie1_value);
4248 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4249
4250 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4251 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4252
40565f19
JS		 4253 mod_timer(&info->tx_timer, jiffies +
4254 msecs_to_jiffies(5000));
1da177e4
LT		 4255 }
4256 else {
4257 tx_load_fifo(info);
4258 /* async, enable IRQ on txdata */
4259 info->ie0_value |= TXRDYE;
4260 write_reg(info, IE0, info->ie0_value);
4261 }
4262
0fab6de0 4263 info->tx_active = true;
1da177e4
LT		 4264 }
4265}
4266
4267/* stop the transmitter and DMA
4268 */
ce9f9f73 4269static void tx_stop( SLMP_INFO *info )
1da177e4
LT		 4270{
4271 if (debug_level >= DEBUG_LEVEL_ISR)
4272 printk("%s(%d):%s tx_stop()\n",
4273 __FILE__,__LINE__, info->device_name );
4274
4275 del_timer(&info->tx_timer);
4276
4277 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4278 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4279
4280 write_reg(info, CMD, TXRESET);
4281
4282 info->ie1_value &= ~(UDRN + IDLE);
4283 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4284 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4285
4286 info->ie0_value &= ~TXRDYE;
4287 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4288
0fab6de0
JP		 4289 info->tx_enabled = false;
4290 info->tx_active = false;
1da177e4
LT		 4291}
4292
4293/* Fill the transmit FIFO until the FIFO is full or
4294 * there is no more data to load.
4295 */
ce9f9f73 4296static void tx_load_fifo(SLMP_INFO *info)
1da177e4
LT		 4297{
4298 u8 TwoBytes[2];
4299
4300 /* do nothing is now tx data available and no XON/XOFF pending */
4301
4302 if ( !info->tx_count && !info->x_char )
4303 return;
4304
4305 /* load the Transmit FIFO until FIFOs full or all data sent */
4306
4307 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4308
4309 /* there is more space in the transmit FIFO and */
4310 /* there is more data in transmit buffer */
4311
4312 if ( (info->tx_count > 1) && !info->x_char ) {
4313 /* write 16-bits */
4314 TwoBytes[0] = info->tx_buf[info->tx_get++];
4315 if (info->tx_get >= info->max_frame_size)
4316 info->tx_get -= info->max_frame_size;
4317 TwoBytes[1] = info->tx_buf[info->tx_get++];
4318 if (info->tx_get >= info->max_frame_size)
4319 info->tx_get -= info->max_frame_size;
4320
4321 write_reg16(info, TRB, *((u16 *)TwoBytes));
4322
4323 info->tx_count -= 2;
4324 info->icount.tx += 2;
4325 } else {
4326 /* only 1 byte left to transmit or 1 FIFO slot left */
4327
4328 if (info->x_char) {
4329 /* transmit pending high priority char */
4330 write_reg(info, TRB, info->x_char);
4331 info->x_char = 0;
4332 } else {
4333 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4334 if (info->tx_get >= info->max_frame_size)
4335 info->tx_get -= info->max_frame_size;
4336 info->tx_count--;
4337 }
4338 info->icount.tx++;
4339 }
4340 }
4341}
4342
4343/* Reset a port to a known state
4344 */
ce9f9f73 4345static void reset_port(SLMP_INFO *info)
1da177e4
LT		 4346{
4347 if (info->sca_base) {
4348
4349 tx_stop(info);
4350 rx_stop(info);
4351
9fe8074b 4352 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 4353 set_signals(info);
4354
4355 /* disable all port interrupts */
4356 info->ie0_value = 0;
4357 info->ie1_value = 0;
4358 info->ie2_value = 0;
4359 write_reg(info, IE0, info->ie0_value);
4360 write_reg(info, IE1, info->ie1_value);
4361 write_reg(info, IE2, info->ie2_value);
4362
4363 write_reg(info, CMD, CHRESET);
4364 }
4365}
4366
4367/* Reset all the ports to a known state.
4368 */
ce9f9f73 4369static void reset_adapter(SLMP_INFO *info)
1da177e4
LT		 4370{
4371 int i;
4372
4373 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4374 if (info->port_array[i])
4375 reset_port(info->port_array[i]);
4376 }
4377}
4378
4379/* Program port for asynchronous communications.
4380 */
ce9f9f73 4381static void async_mode(SLMP_INFO *info)
1da177e4
LT		 4382{
4383
4384 unsigned char RegValue;
4385
4386 tx_stop(info);
4387 rx_stop(info);
4388
4389 /* MD0, Mode Register 0
4390 *
4391 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4392 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4393 * 03 Reserved, must be 0
4394 * 02 CRCCC, CRC Calculation, 0=disabled
4395 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4396 *
4397 * 0000 0000
4398 */
4399 RegValue = 0x00;
4400 if (info->params.stop_bits != 1)
4401 RegValue |= BIT1;
4402 write_reg(info, MD0, RegValue);
4403
4404 /* MD1, Mode Register 1
4405 *
4406 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4407 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4408 * 03..02 RXCHR<1..0>, rx char size
4409 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4410 *
4411 * 0100 0000
4412 */
4413 RegValue = 0x40;
4414 switch (info->params.data_bits) {
4415 case 7: RegValue |= BIT4 + BIT2; break;
4416 case 6: RegValue |= BIT5 + BIT3; break;
4417 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4418 }
4419 if (info->params.parity != ASYNC_PARITY_NONE) {
4420 RegValue |= BIT1;
4421 if (info->params.parity == ASYNC_PARITY_ODD)
4422 RegValue |= BIT0;
4423 }
4424 write_reg(info, MD1, RegValue);
4425
4426 /* MD2, Mode Register 2
4427 *
4428 * 07..02 Reserved, must be 0
6e8dcee3 4429 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
1da177e4
LT		 4430 *
4431 * 0000 0000
4432 */
4433 RegValue = 0x00;
6e8dcee3
PF		 4434 if (info->params.loopback)
4435 RegValue |= (BIT1 + BIT0);
1da177e4
LT		 4436 write_reg(info, MD2, RegValue);
4437
4438 /* RXS, Receive clock source
4439 *
4440 * 07 Reserved, must be 0
4441 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4442 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4443 */
4444 RegValue=BIT6;
4445 write_reg(info, RXS, RegValue);
4446
4447 /* TXS, Transmit clock source
4448 *
4449 * 07 Reserved, must be 0
4450 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4451 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4452 */
4453 RegValue=BIT6;
4454 write_reg(info, TXS, RegValue);
4455
4456 /* Control Register
4457 *
4458 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4459 */
4460 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4461 write_control_reg(info);
4462
4463 tx_set_idle(info);
4464
4465 /* RRC Receive Ready Control 0
4466 *
4467 * 07..05 Reserved, must be 0
4468 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4469 */
4470 write_reg(info, RRC, 0x00);
4471
4472 /* TRC0 Transmit Ready Control 0
4473 *
4474 * 07..05 Reserved, must be 0
4475 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4476 */
4477 write_reg(info, TRC0, 0x10);
4478
4479 /* TRC1 Transmit Ready Control 1
4480 *
4481 * 07..05 Reserved, must be 0
4482 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4483 */
4484 write_reg(info, TRC1, 0x1e);
4485
4486 /* CTL, MSCI control register
4487 *
4488 * 07..06 Reserved, set to 0
4489 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4490 * 04 IDLC, idle control, 0=mark 1=idle register
4491 * 03 BRK, break, 0=off 1 =on (async)
4492 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4493 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4494 * 00 RTS, RTS output control, 0=active 1=inactive
4495 *
4496 * 0001 0001
4497 */
4498 RegValue = 0x10;
4499 if (!(info->serial_signals & SerialSignal_RTS))
4500 RegValue |= 0x01;
4501 write_reg(info, CTL, RegValue);
4502
4503 /* enable status interrupts */
4504 info->ie0_value |= TXINTE + RXINTE;
4505 write_reg(info, IE0, info->ie0_value);
4506
4507 /* enable break detect interrupt */
4508 info->ie1_value = BRKD;
4509 write_reg(info, IE1, info->ie1_value);
4510
4511 /* enable rx overrun interrupt */
4512 info->ie2_value = OVRN;
4513 write_reg(info, IE2, info->ie2_value);
4514
4515 set_rate( info, info->params.data_rate * 16 );
1da177e4
LT		 4516}
4517
4518/* Program the SCA for HDLC communications.
4519 */
ce9f9f73 4520static void hdlc_mode(SLMP_INFO *info)
1da177e4
LT		 4521{
4522 unsigned char RegValue;
4523 u32 DpllDivisor;
4524
4525 // Can't use DPLL because SCA outputs recovered clock on RxC when
4526 // DPLL mode selected. This causes output contention with RxC receiver.
4527 // Use of DPLL would require external hardware to disable RxC receiver
4528 // when DPLL mode selected.
4529 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4530
4531 /* disable DMA interrupts */
4532 write_reg(info, TXDMA + DIR, 0);
4533 write_reg(info, RXDMA + DIR, 0);
4534
4535 /* MD0, Mode Register 0
4536 *
4537 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4538 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4539 * 03 Reserved, must be 0
4540 * 02 CRCCC, CRC Calculation, 1=enabled
4541 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4542 * 00 CRC0, CRC initial value, 1 = all 1s
4543 *
4544 * 1000 0001
4545 */
4546 RegValue = 0x81;
4547 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4548 RegValue |= BIT4;
4549 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4550 RegValue |= BIT4;
4551 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4552 RegValue |= BIT2 + BIT1;
4553 write_reg(info, MD0, RegValue);
4554
4555 /* MD1, Mode Register 1
4556 *
4557 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4558 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4559 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4560 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4561 *
4562 * 0000 0000
4563 */
4564 RegValue = 0x00;
4565 write_reg(info, MD1, RegValue);
4566
4567 /* MD2, Mode Register 2
4568 *
4569 * 07 NRZFM, 0=NRZ, 1=FM
4570 * 06..05 CODE<1..0> Encoding, 00=NRZ
4571 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4572 * 02 Reserved, must be 0
4573 * 01..00 CNCT<1..0> Channel connection, 0=normal
4574 *
4575 * 0000 0000
4576 */
4577 RegValue = 0x00;
4578 switch(info->params.encoding) {
4579 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4580 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4581 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4582 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4583#if 0
4584 case HDLC_ENCODING_NRZB: /* not supported */
4585 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4586 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4587#endif
4588 }
4589 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4590 DpllDivisor = 16;
4591 RegValue |= BIT3;
4592 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4593 DpllDivisor = 8;
4594 } else {
4595 DpllDivisor = 32;
4596 RegValue |= BIT4;
4597 }
4598 write_reg(info, MD2, RegValue);
4599
4600
4601 /* RXS, Receive clock source
4602 *
4603 * 07 Reserved, must be 0
4604 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4605 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4606 */
4607 RegValue=0;
4608 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4609 RegValue |= BIT6;
4610 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4611 RegValue |= BIT6 + BIT5;
4612 write_reg(info, RXS, RegValue);
4613
4614 /* TXS, Transmit clock source
4615 *
4616 * 07 Reserved, must be 0
4617 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4618 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4619 */
4620 RegValue=0;
4621 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4622 RegValue |= BIT6;
4623 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4624 RegValue |= BIT6 + BIT5;
4625 write_reg(info, TXS, RegValue);
4626
4627 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4628 set_rate(info, info->params.clock_speed * DpllDivisor);
4629 else
4630 set_rate(info, info->params.clock_speed);
4631
4632 /* GPDATA (General Purpose I/O Data Register)
4633 *
4634 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4635 */
4636 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4637 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4638 else
4639 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4640 write_control_reg(info);
4641
4642 /* RRC Receive Ready Control 0
4643 *
4644 * 07..05 Reserved, must be 0
4645 * 04..00 RRC<4..0> Rx FIFO trigger active
4646 */
4647 write_reg(info, RRC, rx_active_fifo_level);
4648
4649 /* TRC0 Transmit Ready Control 0
4650 *
4651 * 07..05 Reserved, must be 0
4652 * 04..00 TRC<4..0> Tx FIFO trigger active
4653 */
4654 write_reg(info, TRC0, tx_active_fifo_level);
4655
4656 /* TRC1 Transmit Ready Control 1
4657 *
4658 * 07..05 Reserved, must be 0
4659 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4660 */
4661 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4662
4663 /* DMR, DMA Mode Register
4664 *
4665 * 07..05 Reserved, must be 0
4666 * 04 TMOD, Transfer Mode: 1=chained-block
4667 * 03 Reserved, must be 0
4668 * 02 NF, Number of Frames: 1=multi-frame
4669 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4670 * 00 Reserved, must be 0
4671 *
4672 * 0001 0100
4673 */
4674 write_reg(info, TXDMA + DMR, 0x14);
4675 write_reg(info, RXDMA + DMR, 0x14);
4676
4677 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4678 write_reg(info, RXDMA + CPB,
4679 (unsigned char)(info->buffer_list_phys >> 16));
4680
4681 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4682 write_reg(info, TXDMA + CPB,
4683 (unsigned char)(info->buffer_list_phys >> 16));
4684
4685 /* enable status interrupts. other code enables/disables
4686 * the individual sources for these two interrupt classes.
4687 */
4688 info->ie0_value |= TXINTE + RXINTE;
4689 write_reg(info, IE0, info->ie0_value);
4690
4691 /* CTL, MSCI control register
4692 *
4693 * 07..06 Reserved, set to 0
4694 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4695 * 04 IDLC, idle control, 0=mark 1=idle register
4696 * 03 BRK, break, 0=off 1 =on (async)
4697 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4698 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4699 * 00 RTS, RTS output control, 0=active 1=inactive
4700 *
4701 * 0001 0001
4702 */
4703 RegValue = 0x10;
4704 if (!(info->serial_signals & SerialSignal_RTS))
4705 RegValue |= 0x01;
4706 write_reg(info, CTL, RegValue);
4707
4708 /* preamble not supported ! */
4709
4710 tx_set_idle(info);
4711 tx_stop(info);
4712 rx_stop(info);
4713
4714 set_rate(info, info->params.clock_speed);
4715
4716 if (info->params.loopback)
4717 enable_loopback(info,1);
4718}
4719
4720/* Set the transmit HDLC idle mode
4721 */
ce9f9f73 4722static void tx_set_idle(SLMP_INFO *info)
1da177e4
LT		 4723{
4724 unsigned char RegValue = 0xff;
4725
4726 /* Map API idle mode to SCA register bits */
4727 switch(info->idle_mode) {
4728 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4729 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4730 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4731 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4732 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4733 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4734 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4735 }
4736
4737 write_reg(info, IDL, RegValue);
4738}
4739
4740/* Query the adapter for the state of the V24 status (input) signals.
4741 */
ce9f9f73 4742static void get_signals(SLMP_INFO *info)
1da177e4
LT		 4743{
4744 u16 status = read_reg(info, SR3);
4745 u16 gpstatus = read_status_reg(info);
4746 u16 testbit;
4747
9fe8074b
JP		 4748 /* clear all serial signals except RTS and DTR */
4749 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
1da177e4
LT		 4750
4751 /* set serial signal bits to reflect MISR */
4752
4753 if (!(status & BIT3))
4754 info->serial_signals |= SerialSignal_CTS;
4755
4756 if ( !(status & BIT2))
4757 info->serial_signals |= SerialSignal_DCD;
4758
4759 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4760 if (!(gpstatus & testbit))
4761 info->serial_signals |= SerialSignal_RI;
4762
4763 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4764 if (!(gpstatus & testbit))
4765 info->serial_signals |= SerialSignal_DSR;
4766}
4767
9fe8074b 4768/* Set the state of RTS and DTR based on contents of
1da177e4
LT		 4769 * serial_signals member of device context.
4770 */
ce9f9f73 4771static void set_signals(SLMP_INFO *info)
1da177e4
LT		 4772{
4773 unsigned char RegValue;
4774 u16 EnableBit;
4775
4776 RegValue = read_reg(info, CTL);
4777 if (info->serial_signals & SerialSignal_RTS)
4778 RegValue &= ~BIT0;
4779 else
4780 RegValue |= BIT0;
4781 write_reg(info, CTL, RegValue);
4782
4783 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4784 EnableBit = BIT1 << (info->port_num*2);
4785 if (info->serial_signals & SerialSignal_DTR)
4786 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4787 else
4788 info->port_array[0]->ctrlreg_value |= EnableBit;
4789 write_control_reg(info);
4790}
4791
4792/*******************/
4793/* DMA Buffer Code */
4794/*******************/
4795
4796/* Set the count for all receive buffers to SCABUFSIZE
4797 * and set the current buffer to the first buffer. This effectively
4798 * makes all buffers free and discards any data in buffers.
4799 */
ce9f9f73 4800static void rx_reset_buffers(SLMP_INFO *info)
1da177e4
LT		 4801{
4802 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4803}
4804
4805/* Free the buffers used by a received frame
4806 *
4807 * info pointer to device instance data
4808 * first index of 1st receive buffer of frame
4809 * last index of last receive buffer of frame
4810 */
ce9f9f73 4811static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
1da177e4 4812{
0fab6de0 4813 bool done = false;
1da177e4
LT		 4814
4815 while(!done) {
4816 /* reset current buffer for reuse */
4817 info->rx_buf_list[first].status = 0xff;
4818
4819 if (first == last) {
0fab6de0 4820 done = true;
1da177e4
LT		 4821 /* set new last rx descriptor address */
4822 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4823 }
4824
4825 first++;
4826 if (first == info->rx_buf_count)
4827 first = 0;
4828 }
4829
4830 /* set current buffer to next buffer after last buffer of frame */
4831 info->current_rx_buf = first;
4832}
4833
4834/* Return a received frame from the receive DMA buffers.
4835 * Only frames received without errors are returned.
4836 *
0fab6de0 4837 * Return Value: true if frame returned, otherwise false
1da177e4 4838 */
ce9f9f73 4839static bool rx_get_frame(SLMP_INFO *info)
1da177e4
LT		 4840{
4841 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4842 unsigned short status;
4843 unsigned int framesize = 0;
0fab6de0 4844 bool ReturnCode = false;
1da177e4 4845 unsigned long flags;
8fb06c77 4846 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 4847 unsigned char addr_field = 0xff;
4848 SCADESC *desc;
4849 SCADESC_EX *desc_ex;
4850
4851CheckAgain:
4852 /* assume no frame returned, set zero length */
4853 framesize = 0;
4854 addr_field = 0xff;
4855
4856 /*
4857 * current_rx_buf points to the 1st buffer of the next available
4858 * receive frame. To find the last buffer of the frame look for
4859 * a non-zero status field in the buffer entries. (The status
4860 * field is set by the 16C32 after completing a receive frame.
4861 */
4862 StartIndex = EndIndex = info->current_rx_buf;
4863
4864 for ( ;; ) {
4865 desc = &info->rx_buf_list[EndIndex];
4866 desc_ex = &info->rx_buf_list_ex[EndIndex];
4867
4868 if (desc->status == 0xff)
4869 goto Cleanup; /* current desc still in use, no frames available */
4870
4871 if (framesize == 0 && info->params.addr_filter != 0xff)
4872 addr_field = desc_ex->virt_addr[0];
4873
4874 framesize += desc->length;
4875
4876 /* Status != 0 means last buffer of frame */
4877 if (desc->status)
4878 break;
4879
4880 EndIndex++;
4881 if (EndIndex == info->rx_buf_count)
4882 EndIndex = 0;
4883
4884 if (EndIndex == info->current_rx_buf) {
4885 /* all buffers have been 'used' but none mark */
4886 /* the end of a frame. Reset buffers and receiver. */
4887 if ( info->rx_enabled ){
4888 spin_lock_irqsave(&info->lock,flags);
4889 rx_start(info);
4890 spin_unlock_irqrestore(&info->lock,flags);
4891 }
4892 goto Cleanup;
4893 }
4894
4895 }
4896
4897 /* check status of receive frame */
4898
4899 /* frame status is byte stored after frame data
4900 *
4901 * 7 EOM (end of msg), 1 = last buffer of frame
4902 * 6 Short Frame, 1 = short frame
4903 * 5 Abort, 1 = frame aborted
4904 * 4 Residue, 1 = last byte is partial
4905 * 3 Overrun, 1 = overrun occurred during frame reception
4906 * 2 CRC, 1 = CRC error detected
4907 *
4908 */
4909 status = desc->status;
4910
4911 /* ignore CRC bit if not using CRC (bit is undefined) */
4912 /* Note:CRC is not save to data buffer */
4913 if (info->params.crc_type == HDLC_CRC_NONE)
4914 status &= ~BIT2;
4915
4916 if (framesize == 0 ||
4917 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4918 /* discard 0 byte frames, this seems to occur sometime
4919 * when remote is idling flags.
4920 */
4921 rx_free_frame_buffers(info, StartIndex, EndIndex);
4922 goto CheckAgain;
4923 }
4924
4925 if (framesize < 2)
4926 status |= BIT6;
4927
4928 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4929 /* received frame has errors,
4930 * update counts and mark frame size as 0
4931 */
4932 if (status & BIT6)
4933 info->icount.rxshort++;
4934 else if (status & BIT5)
4935 info->icount.rxabort++;
4936 else if (status & BIT3)
4937 info->icount.rxover++;
4938 else
4939 info->icount.rxcrc++;
4940
4941 framesize = 0;
af69c7f9 4942#if SYNCLINK_GENERIC_HDLC
1da177e4 4943 {
198191c4
KH		 4944 info->netdev->stats.rx_errors++;
4945 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 4946 }
4947#endif
4948 }
4949
4950 if ( debug_level >= DEBUG_LEVEL_BH )
4951 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4952 __FILE__,__LINE__,info->device_name,status,framesize);
4953
4954 if ( debug_level >= DEBUG_LEVEL_DATA )
4955 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
53d785cc 4956 min_t(unsigned int, framesize, SCABUFSIZE), 0);
1da177e4
LT		 4957
4958 if (framesize) {
4959 if (framesize > info->max_frame_size)
4960 info->icount.rxlong++;
4961 else {
4962 /* copy dma buffer(s) to contiguous intermediate buffer */
4963 int copy_count = framesize;
4964 int index = StartIndex;
4965 unsigned char *ptmp = info->tmp_rx_buf;
4966 info->tmp_rx_buf_count = framesize;
4967
4968 info->icount.rxok++;
4969
4970 while(copy_count) {
4971 int partial_count = min(copy_count,SCABUFSIZE);
4972 memcpy( ptmp,
4973 info->rx_buf_list_ex[index].virt_addr,
4974 partial_count );
4975 ptmp += partial_count;
4976 copy_count -= partial_count;
4977
4978 if ( ++index == info->rx_buf_count )
4979 index = 0;
4980 }
4981
af69c7f9 4982#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 4983 if (info->netcount)
4984 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4985 else
4986#endif
4987 ldisc_receive_buf(tty,info->tmp_rx_buf,
4988 info->flag_buf, framesize);
4989 }
4990 }
4991 /* Free the buffers used by this frame. */
4992 rx_free_frame_buffers( info, StartIndex, EndIndex );
4993
0fab6de0 4994 ReturnCode = true;
1da177e4
LT		 4995
4996Cleanup:
4997 if ( info->rx_enabled && info->rx_overflow ) {
4998 /* Receiver is enabled, but needs to restarted due to
4999 * rx buffer overflow. If buffers are empty, restart receiver.
5000 */
5001 if (info->rx_buf_list[EndIndex].status == 0xff) {
5002 spin_lock_irqsave(&info->lock,flags);
5003 rx_start(info);
5004 spin_unlock_irqrestore(&info->lock,flags);
5005 }
5006 }
5007
5008 return ReturnCode;
5009}
5010
5011/* load the transmit DMA buffer with data
5012 */
ce9f9f73 5013static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
1da177e4
LT		 5014{
5015 unsigned short copy_count;
5016 unsigned int i = 0;
5017 SCADESC *desc;
5018 SCADESC_EX *desc_ex;
5019
5020 if ( debug_level >= DEBUG_LEVEL_DATA )
53d785cc 5021 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
1da177e4
LT		 5022
5023 /* Copy source buffer to one or more DMA buffers, starting with
5024 * the first transmit dma buffer.
5025 */
5026 for(i=0;;)
5027 {
53d785cc 5028 copy_count = min_t(unsigned int, count, SCABUFSIZE);
1da177e4
LT		 5029
5030 desc = &info->tx_buf_list[i];
5031 desc_ex = &info->tx_buf_list_ex[i];
5032
5033 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5034
5035 desc->length = copy_count;
5036 desc->status = 0;
5037
5038 buf += copy_count;
5039 count -= copy_count;
5040
5041 if (!count)
5042 break;
5043
5044 i++;
5045 if (i >= info->tx_buf_count)
5046 i = 0;
5047 }
5048
5049 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5050 info->last_tx_buf = ++i;
5051}
5052
ce9f9f73 5053static bool register_test(SLMP_INFO *info)
1da177e4
LT		 5054{
5055 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
fe971071 5056 static unsigned int count = ARRAY_SIZE(testval);
1da177e4 5057 unsigned int i;
0fab6de0 5058 bool rc = true;
1da177e4
LT		 5059 unsigned long flags;
5060
5061 spin_lock_irqsave(&info->lock,flags);
5062 reset_port(info);
5063
5064 /* assume failure */
5065 info->init_error = DiagStatus_AddressFailure;
5066
5067 /* Write bit patterns to various registers but do it out of */
5068 /* sync, then read back and verify values. */
5069
5070 for (i = 0 ; i < count ; i++) {
5071 write_reg(info, TMC, testval[i]);
5072 write_reg(info, IDL, testval[(i+1)%count]);
5073 write_reg(info, SA0, testval[(i+2)%count]);
5074 write_reg(info, SA1, testval[(i+3)%count]);
5075
5076 if ( (read_reg(info, TMC) != testval[i]) ||
5077 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5078 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5079 (read_reg(info, SA1) != testval[(i+3)%count]) )
5080 {
0fab6de0 5081 rc = false;
1da177e4
LT		 5082 break;
5083 }
5084 }
5085
5086 reset_port(info);
5087 spin_unlock_irqrestore(&info->lock,flags);
5088
5089 return rc;
5090}
5091
ce9f9f73 5092static bool irq_test(SLMP_INFO *info)
1da177e4
LT		 5093{
5094 unsigned long timeout;
5095 unsigned long flags;
5096
5097 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5098
5099 spin_lock_irqsave(&info->lock,flags);
5100 reset_port(info);
5101
5102 /* assume failure */
5103 info->init_error = DiagStatus_IrqFailure;
0fab6de0 5104 info->irq_occurred = false;
1da177e4
LT		 5105
5106 /* setup timer0 on SCA0 to interrupt */
5107
5108 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5109 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5110
5111 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5112 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5113
5114
5115 /* TMCS, Timer Control/Status Register
5116 *
5117 * 07 CMF, Compare match flag (read only) 1=match
5118 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5119 * 05 Reserved, must be 0
5120 * 04 TME, Timer Enable
5121 * 03..00 Reserved, must be 0
5122 *
5123 * 0101 0000
5124 */
5125 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5126
5127 spin_unlock_irqrestore(&info->lock,flags);
5128
5129 timeout=100;
5130 while( timeout-- && !info->irq_occurred ) {
5131 msleep_interruptible(10);
5132 }
5133
5134 spin_lock_irqsave(&info->lock,flags);
5135 reset_port(info);
5136 spin_unlock_irqrestore(&info->lock,flags);
5137
5138 return info->irq_occurred;
5139}
5140
5141/* initialize individual SCA device (2 ports)
5142 */
0fab6de0 5143static bool sca_init(SLMP_INFO *info)
1da177e4
LT		 5144{
5145 /* set wait controller to single mem partition (low), no wait states */
5146 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5147 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5148 write_reg(info, WCRL, 0); /* wait controller low range */
5149 write_reg(info, WCRM, 0); /* wait controller mid range */
5150 write_reg(info, WCRH, 0); /* wait controller high range */
5151
5152 /* DPCR, DMA Priority Control
5153 *
5154 * 07..05 Not used, must be 0
5155 * 04 BRC, bus release condition: 0=all transfers complete
5156 * 03 CCC, channel change condition: 0=every cycle
5157 * 02..00 PR<2..0>, priority 100=round robin
5158 *
5159 * 00000100 = 0x04
5160 */
5161 write_reg(info, DPCR, dma_priority);
5162
5163 /* DMA Master Enable, BIT7: 1=enable all channels */
5164 write_reg(info, DMER, 0x80);
5165
5166 /* enable all interrupt classes */
5167 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5168 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5169 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5170
5171 /* ITCR, interrupt control register
5172 * 07 IPC, interrupt priority, 0=MSCI->DMA
5173 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5174 * 04 VOS, Vector Output, 0=unmodified vector
5175 * 03..00 Reserved, must be 0
5176 */
5177 write_reg(info, ITCR, 0);
5178
0fab6de0 5179 return true;
1da177e4
LT		 5180}
5181
5182/* initialize adapter hardware
5183 */
ce9f9f73 5184static bool init_adapter(SLMP_INFO *info)
1da177e4
LT		 5185{
5186 int i;
5187
5188 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5189 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5190 u32 readval;
5191
5192 info->misc_ctrl_value |= BIT30;
5193 *MiscCtrl = info->misc_ctrl_value;
5194
5195 /*
5196 * Force at least 170ns delay before clearing
5197 * reset bit. Each read from LCR takes at least
5198 * 30ns so 10 times for 300ns to be safe.
5199 */
5200 for(i=0;i<10;i++)
5201 readval = *MiscCtrl;
5202
5203 info->misc_ctrl_value &= ~BIT30;
5204 *MiscCtrl = info->misc_ctrl_value;
5205
5206 /* init control reg (all DTRs off, all clksel=input) */
5207 info->ctrlreg_value = 0xaa;
5208 write_control_reg(info);
5209
5210 {
5211 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5212 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5213
5214 switch(read_ahead_count)
5215 {
5216 case 16:
5217 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5218 break;
5219 case 8:
5220 lcr1_brdr_value |= BIT5 + BIT4;
5221 break;
5222 case 4:
5223 lcr1_brdr_value |= BIT5 + BIT3;
5224 break;
5225 case 0:
5226 lcr1_brdr_value |= BIT5;
5227 break;
5228 }
5229
5230 *LCR1BRDR = lcr1_brdr_value;
5231 *MiscCtrl = misc_ctrl_value;
5232 }
5233
5234 sca_init(info->port_array[0]);
5235 sca_init(info->port_array[2]);
5236
0fab6de0 5237 return true;
1da177e4
LT		 5238}
5239
5240/* Loopback an HDLC frame to test the hardware
5241 * interrupt and DMA functions.
5242 */
ce9f9f73 5243static bool loopback_test(SLMP_INFO *info)
1da177e4
LT		 5244{
5245#define TESTFRAMESIZE 20
5246
5247 unsigned long timeout;
5248 u16 count = TESTFRAMESIZE;
5249 unsigned char buf[TESTFRAMESIZE];
0fab6de0 5250 bool rc = false;
1da177e4
LT		 5251 unsigned long flags;
5252
8fb06c77 5253 struct tty_struct *oldtty = info->port.tty;
1da177e4
LT		 5254 u32 speed = info->params.clock_speed;
5255
5256 info->params.clock_speed = 3686400;
8fb06c77 5257 info->port.tty = NULL;
1da177e4
LT		 5258
5259 /* assume failure */
5260 info->init_error = DiagStatus_DmaFailure;
5261
5262 /* build and send transmit frame */
5263 for (count = 0; count < TESTFRAMESIZE;++count)
5264 buf[count] = (unsigned char)count;
5265
5266 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5267
5268 /* program hardware for HDLC and enabled receiver */
5269 spin_lock_irqsave(&info->lock,flags);
5270 hdlc_mode(info);
5271 enable_loopback(info,1);
5272 rx_start(info);
5273 info->tx_count = count;
5274 tx_load_dma_buffer(info,buf,count);
5275 tx_start(info);
5276 spin_unlock_irqrestore(&info->lock,flags);
5277
5278 /* wait for receive complete */
5279 /* Set a timeout for waiting for interrupt. */
5280 for ( timeout = 100; timeout; --timeout ) {
5281 msleep_interruptible(10);
5282
5283 if (rx_get_frame(info)) {
0fab6de0 5284 rc = true;
1da177e4
LT		 5285 break;
5286 }
5287 }
5288
5289 /* verify received frame length and contents */
0fab6de0
JP		 5290 if (rc &&
5291 ( info->tmp_rx_buf_count != count ||
5292 memcmp(buf, info->tmp_rx_buf,count))) {
5293 rc = false;
1da177e4
LT		 5294 }
5295
5296 spin_lock_irqsave(&info->lock,flags);
5297 reset_adapter(info);
5298 spin_unlock_irqrestore(&info->lock,flags);
5299
5300 info->params.clock_speed = speed;
8fb06c77 5301 info->port.tty = oldtty;
1da177e4
LT		 5302
5303 return rc;
5304}
5305
5306/* Perform diagnostics on hardware
5307 */
ce9f9f73 5308static int adapter_test( SLMP_INFO *info )
1da177e4
LT		 5309{
5310 unsigned long flags;
5311 if ( debug_level >= DEBUG_LEVEL_INFO )
5312 printk( "%s(%d):Testing device %s\n",
5313 __FILE__,__LINE__,info->device_name );
5314
5315 spin_lock_irqsave(&info->lock,flags);
5316 init_adapter(info);
5317 spin_unlock_irqrestore(&info->lock,flags);
5318
5319 info->port_array[0]->port_count = 0;
5320
5321 if ( register_test(info->port_array[0]) &&
5322 register_test(info->port_array[1])) {
5323
5324 info->port_array[0]->port_count = 2;
5325
5326 if ( register_test(info->port_array[2]) &&
5327 register_test(info->port_array[3]) )
5328 info->port_array[0]->port_count += 2;
5329 }
5330 else {
5331 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5332 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5333 return -ENODEV;
5334 }
5335
5336 if ( !irq_test(info->port_array[0]) ||
5337 !irq_test(info->port_array[1]) ||
5338 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5339 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5340 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5341 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5342 return -ENODEV;
5343 }
5344
5345 if (!loopback_test(info->port_array[0]) ||
5346 !loopback_test(info->port_array[1]) ||
5347 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5348 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5349 printk( "%s(%d):DMA test failure for device %s\n",
5350 __FILE__,__LINE__,info->device_name);
5351 return -ENODEV;
5352 }
5353
5354 if ( debug_level >= DEBUG_LEVEL_INFO )
5355 printk( "%s(%d):device %s passed diagnostics\n",
5356 __FILE__,__LINE__,info->device_name );
5357
5358 info->port_array[0]->init_error = 0;
5359 info->port_array[1]->init_error = 0;
5360 if ( info->port_count > 2 ) {
5361 info->port_array[2]->init_error = 0;
5362 info->port_array[3]->init_error = 0;
5363 }
5364
5365 return 0;
5366}
5367
5368/* Test the shared memory on a PCI adapter.
5369 */
ce9f9f73 5370static bool memory_test(SLMP_INFO *info)
1da177e4
LT		 5371{
5372 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5373 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
fe971071 5374 unsigned long count = ARRAY_SIZE(testval);
1da177e4
LT		 5375 unsigned long i;
5376 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5377 unsigned long * addr = (unsigned long *)info->memory_base;
5378
5379 /* Test data lines with test pattern at one location. */
5380
5381 for ( i = 0 ; i < count ; i++ ) {
5382 *addr = testval[i];
5383 if ( *addr != testval[i] )
0fab6de0 5384 return false;
1da177e4
LT		 5385 }
5386
5387 /* Test address lines with incrementing pattern over */
5388 /* entire address range. */
5389
5390 for ( i = 0 ; i < limit ; i++ ) {
5391 *addr = i * 4;
5392 addr++;
5393 }
5394
5395 addr = (unsigned long *)info->memory_base;
5396
5397 for ( i = 0 ; i < limit ; i++ ) {
5398 if ( *addr != i * 4 )
0fab6de0 5399 return false;
1da177e4
LT		 5400 addr++;
5401 }
5402
5403 memset( info->memory_base, 0, SCA_MEM_SIZE );
0fab6de0 5404 return true;
1da177e4
LT		 5405}
5406
5407/* Load data into PCI adapter shared memory.
5408 *
5409 * The PCI9050 releases control of the local bus
5410 * after completing the current read or write operation.
5411 *
5412 * While the PCI9050 write FIFO not empty, the
5413 * PCI9050 treats all of the writes as a single transaction
5414 * and does not release the bus. This causes DMA latency problems
5415 * at high speeds when copying large data blocks to the shared memory.
5416 *
5417 * This function breaks a write into multiple transations by
5418 * interleaving a read which flushes the write FIFO and 'completes'
5419 * the write transation. This allows any pending DMA request to gain control
5420 * of the local bus in a timely fasion.
5421 */
ce9f9f73 5422static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
1da177e4
LT		 5423{
5424 /* A load interval of 16 allows for 4 32-bit writes at */
5425 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5426
5427 unsigned short interval = count / sca_pci_load_interval;
5428 unsigned short i;
5429
5430 for ( i = 0 ; i < interval ; i++ )
5431 {
5432 memcpy(dest, src, sca_pci_load_interval);
5433 read_status_reg(info);
5434 dest += sca_pci_load_interval;
5435 src += sca_pci_load_interval;
5436 }
5437
5438 memcpy(dest, src, count % sca_pci_load_interval);
5439}
5440
ce9f9f73 5441static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
1da177e4
LT		 5442{
5443 int i;
5444 int linecount;
5445 if (xmit)
5446 printk("%s tx data:\n",info->device_name);
5447 else
5448 printk("%s rx data:\n",info->device_name);
5449
5450 while(count) {
5451 if (count > 16)
5452 linecount = 16;
5453 else
5454 linecount = count;
5455
5456 for(i=0;i<linecount;i++)
5457 printk("%02X ",(unsigned char)data[i]);
5458 for(;i<17;i++)
5459 printk(" ");
5460 for(i=0;i<linecount;i++) {
5461 if (data[i]>=040 && data[i]<=0176)
5462 printk("%c",data[i]);
5463 else
5464 printk(".");
5465 }
5466 printk("\n");
5467
5468 data += linecount;
5469 count -= linecount;
5470 }
5471} /* end of trace_block() */
5472
5473/* called when HDLC frame times out
5474 * update stats and do tx completion processing
5475 */
ce9f9f73 5476static void tx_timeout(unsigned long context)
1da177e4
LT		 5477{
5478 SLMP_INFO *info = (SLMP_INFO*)context;
5479 unsigned long flags;
5480
5481 if ( debug_level >= DEBUG_LEVEL_INFO )
5482 printk( "%s(%d):%s tx_timeout()\n",
5483 __FILE__,__LINE__,info->device_name);
5484 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5485 info->icount.txtimeout++;
5486 }
5487 spin_lock_irqsave(&info->lock,flags);
0fab6de0 5488 info->tx_active = false;
1da177e4
LT		 5489 info->tx_count = info->tx_put = info->tx_get = 0;
5490
5491 spin_unlock_irqrestore(&info->lock,flags);
5492
af69c7f9 5493#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 5494 if (info->netcount)
5495 hdlcdev_tx_done(info);
5496 else
5497#endif
5498 bh_transmit(info);
5499}
5500
5501/* called to periodically check the DSR/RI modem signal input status
5502 */
ce9f9f73 5503static void status_timeout(unsigned long context)
1da177e4
LT		 5504{
5505 u16 status = 0;
5506 SLMP_INFO *info = (SLMP_INFO*)context;
5507 unsigned long flags;
5508 unsigned char delta;
5509
5510
5511 spin_lock_irqsave(&info->lock,flags);
5512 get_signals(info);
5513 spin_unlock_irqrestore(&info->lock,flags);
5514
5515 /* check for DSR/RI state change */
5516
5517 delta = info->old_signals ^ info->serial_signals;
5518 info->old_signals = info->serial_signals;
5519
5520 if (delta & SerialSignal_DSR)
5521 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5522
5523 if (delta & SerialSignal_RI)
5524 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5525
5526 if (delta & SerialSignal_DCD)
5527 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5528
5529 if (delta & SerialSignal_CTS)
5530 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5531
5532 if (status)
5533 isr_io_pin(info,status);
5534
40565f19 5535 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
1da177e4
LT		 5536}
5537
5538
5539/* Register Access Routines -
5540 * All registers are memory mapped
5541 */
5542#define CALC_REGADDR() \
5543 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5544 if (info->port_num > 1) \
5545 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5546 if ( info->port_num & 1) { \
5547 if (Addr > 0x7f) \
5548 RegAddr += 0x40; /* DMA access */ \
5549 else if (Addr > 0x1f && Addr < 0x60) \
5550 RegAddr += 0x20; /* MSCI access */ \
5551 }
5552
5553
ce9f9f73 5554static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
1da177e4
LT		 5555{
5556 CALC_REGADDR();
5557 return *RegAddr;
5558}
ce9f9f73 5559static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
1da177e4
LT		 5560{
5561 CALC_REGADDR();
5562 *RegAddr = Value;
5563}
5564
ce9f9f73 5565static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
1da177e4
LT		 5566{
5567 CALC_REGADDR();
5568 return *((u16 *)RegAddr);
5569}
5570
ce9f9f73 5571static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
1da177e4
LT		 5572{
5573 CALC_REGADDR();
5574 *((u16 *)RegAddr) = Value;
5575}
5576
ce9f9f73 5577static unsigned char read_status_reg(SLMP_INFO * info)
1da177e4
LT		 5578{
5579 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5580 return *RegAddr;
5581}
5582
ce9f9f73 5583static void write_control_reg(SLMP_INFO * info)
1da177e4
LT		 5584{
5585 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5586 *RegAddr = info->port_array[0]->ctrlreg_value;
5587}
5588
5589
9671f099 5590static int synclinkmp_init_one (struct pci_dev *dev,
1da177e4
LT		 5591 const struct pci_device_id *ent)
5592{
5593 if (pci_enable_device(dev)) {
5594 printk("error enabling pci device %p\n", dev);
5595 return -EIO;
5596 }
b1209983 5597 return device_init( ++synclinkmp_adapter_count, dev );
1da177e4
LT		 5598}
5599
ae8d8a14 5600static void synclinkmp_remove_one (struct pci_dev *dev)
1da177e4
LT		 5601{
5602}
Linux kernel - Deliverables
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