[deliverable/linux.git] / drivers / usb / chipidea / ci.h

/*
 * ci.h - common structures, functions, and macros of the ChipIdea driver
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
#define __DRIVERS_USB_CHIPIDEA_CI_H

#include <linux/list.h>
#include <linux/irqreturn.h>
#include <linux/usb.h>
#include <linux/usb/gadget.h>

/******************************************************************************
 * DEFINE
 *****************************************************************************/
#define TD_PAGE_COUNT      5
#define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
#define ENDPT_MAX          32

/******************************************************************************
 * STRUCTURES
 *****************************************************************************/
/**
 * struct ci_hw_ep - endpoint representation
 * @ep: endpoint structure for gadget drivers
 * @dir: endpoint direction (TX/RX)
 * @num: endpoint number
 * @type: endpoint type
 * @name: string description of the endpoint
 * @qh: queue head for this endpoint
 * @wedge: is the endpoint wedged
 * @ci: pointer to the controller
 * @lock: pointer to controller's spinlock
 * @td_pool: pointer to controller's TD pool
 */
struct ci_hw_ep {
	struct usb_ep				ep;
	u8					dir;
	u8					num;
	u8					type;
	char					name[16];
	struct {
		struct list_head	queue;
		struct ci_hw_qh		*ptr;
		dma_addr_t		dma;
	}					qh;
	int					wedge;

	/* global resources */
	struct ci_hdrc				*ci;
	spinlock_t				*lock;
	struct dma_pool				*td_pool;
	struct td_node				*pending_td;
};

enum ci_role {
	CI_ROLE_HOST = 0,
	CI_ROLE_GADGET,
	CI_ROLE_END,
};

/**
 * struct ci_role_driver - host/gadget role driver
 * start: start this role
 * stop: stop this role
 * irq: irq handler for this role
 * name: role name string (host/gadget)
 */
struct ci_role_driver {
	int		(*start)(struct ci_hdrc *);
	void		(*stop)(struct ci_hdrc *);
	irqreturn_t	(*irq)(struct ci_hdrc *);
	const char	*name;
};

/**
 * struct hw_bank - hardware register mapping representation
 * @lpm: set if the device is LPM capable
 * @phys: physical address of the controller's registers
 * @abs: absolute address of the beginning of register window
 * @cap: capability registers
 * @op: operational registers
 * @size: size of the register window
 * @regmap: register lookup table
 */
struct hw_bank {
	unsigned	lpm;
	resource_size_t	phys;
	void __iomem	*abs;
	void __iomem	*cap;
	void __iomem	*op;
	size_t		size;
	void __iomem	**regmap;
};

/**
 * struct ci_hdrc - chipidea device representation
 * @dev: pointer to parent device
 * @lock: access synchronization
 * @hw_bank: hardware register mapping
 * @irq: IRQ number
 * @roles: array of supported roles for this controller
 * @role: current role
 * @is_otg: if the device is otg-capable
 * @work: work for role changing
 * @wq: workqueue thread
 * @qh_pool: allocation pool for queue heads
 * @td_pool: allocation pool for transfer descriptors
 * @gadget: device side representation for peripheral controller
 * @driver: gadget driver
 * @hw_ep_max: total number of endpoints supported by hardware
 * @ci_hw_ep: array of endpoints
 * @ep0_dir: ep0 direction
 * @ep0out: pointer to ep0 OUT endpoint
 * @ep0in: pointer to ep0 IN endpoint
 * @status: ep0 status request
 * @setaddr: if we should set the address on status completion
 * @address: usb address received from the host
 * @remote_wakeup: host-enabled remote wakeup
 * @suspended: suspended by host
 * @test_mode: the selected test mode
 * @platdata: platform specific information supplied by parent device
 * @vbus_active: is VBUS active
 * @transceiver: pointer to USB PHY, if any
 * @hcd: pointer to usb_hcd for ehci host driver
 * @debugfs: root dentry for this controller in debugfs
 * @id_event: indicates there is an id event, and handled at ci_otg_work
 * @b_sess_valid_event: indicates there is a vbus event, and handled
 * at ci_otg_work
 */
struct ci_hdrc {
	struct device			*dev;
	spinlock_t			lock;
	struct hw_bank			hw_bank;
	int				irq;
	struct ci_role_driver		*roles[CI_ROLE_END];
	enum ci_role			role;
	bool				is_otg;
	struct work_struct		work;
	struct workqueue_struct		*wq;

	struct dma_pool			*qh_pool;
	struct dma_pool			*td_pool;

	struct usb_gadget		gadget;
	struct usb_gadget_driver	*driver;
	unsigned			hw_ep_max;
	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
	u32				ep0_dir;
	struct ci_hw_ep			*ep0out, *ep0in;

	struct usb_request		*status;
	bool				setaddr;
	u8				address;
	u8				remote_wakeup;
	u8				suspended;
	u8				test_mode;

	struct ci_hdrc_platform_data	*platdata;
	int				vbus_active;
	/* FIXME: some day, we'll not use global phy */
	bool				global_phy;
	struct usb_phy			*transceiver;
	struct usb_hcd			*hcd;
	struct dentry			*debugfs;
	bool				id_event;
	bool				b_sess_valid_event;
};

static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
{
	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
	return ci->roles[ci->role];
}

static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
{
	int ret;

	if (role >= CI_ROLE_END)
		return -EINVAL;

	if (!ci->roles[role])
		return -ENXIO;

	ret = ci->roles[role]->start(ci);
	if (!ret)
		ci->role = role;
	return ret;
}

static inline void ci_role_stop(struct ci_hdrc *ci)
{
	enum ci_role role = ci->role;

	if (role == CI_ROLE_END)
		return;

	ci->role = CI_ROLE_END;

	ci->roles[role]->stop(ci);
}

/******************************************************************************
 * REGISTERS
 *****************************************************************************/
/* register size */
#define REG_BITS   (32)

/* register indices */
enum ci_hw_regs {
	CAP_CAPLENGTH,
	CAP_HCCPARAMS,
	CAP_DCCPARAMS,
	CAP_TESTMODE,
	CAP_LAST = CAP_TESTMODE,
	OP_USBCMD,
	OP_USBSTS,
	OP_USBINTR,
	OP_DEVICEADDR,
	OP_ENDPTLISTADDR,
	OP_PORTSC,
	OP_DEVLC,
	OP_OTGSC,
	OP_USBMODE,
	OP_ENDPTSETUPSTAT,
	OP_ENDPTPRIME,
	OP_ENDPTFLUSH,
	OP_ENDPTSTAT,
	OP_ENDPTCOMPLETE,
	OP_ENDPTCTRL,
	/* endptctrl1..15 follow */
	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
};

/**
 * hw_read: reads from a hw register
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
{
	return ioread32(ci->hw_bank.regmap[reg]) & mask;
}

/**
 * hw_write: writes to a hw register
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 */
static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
			    u32 mask, u32 data)
{
	if (~mask)
		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
			| (data & mask);

	iowrite32(data, ci->hw_bank.regmap[reg]);
}

/**
 * hw_test_and_clear: tests & clears a hw register
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask)
{
	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;

	iowrite32(val, ci->hw_bank.regmap[reg]);
	return val;
}

/**
 * hw_test_and_write: tests & writes a hw register
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask, u32 data)
{
	u32 val = hw_read(ci, reg, ~0);

	hw_write(ci, reg, mask, data);
	return (val & mask) >> __ffs(mask);
}

int hw_device_reset(struct ci_hdrc *ci, u32 mode);

int hw_port_test_set(struct ci_hdrc *ci, u8 mode);

u8 hw_port_test_get(struct ci_hdrc *ci);

int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
				u32 value, unsigned int timeout_ms);

#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
Commit	Line	Data
e443b333 AS	1	/*
	2	* ci.h - common structures, functions, and macros of the ChipIdea driver
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
	14	#define __DRIVERS_USB_CHIPIDEA_CI_H
	15
	16	#include <linux/list.h>
5f36e231	17	#include <linux/irqreturn.h>
eb70e5ab	18	#include <linux/usb.h>
e443b333 AS	19	#include <linux/usb/gadget.h>
	20
	21	/******************************************************************************
	22	* DEFINE
	23	*****************************************************************************/
b983e51a	24	#define TD_PAGE_COUNT 5
8e22978c	25	#define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
e443b333 AS	26	#define ENDPT_MAX 32
	27
	28	/******************************************************************************
	29	* STRUCTURES
	30	*****************************************************************************/
551a8ac6	31	/**
8e22978c	32	* struct ci_hw_ep - endpoint representation
551a8ac6 AS	33	* @ep: endpoint structure for gadget drivers
	34	* @dir: endpoint direction (TX/RX)
	35	* @num: endpoint number
	36	* @type: endpoint type
	37	* @name: string description of the endpoint
	38	* @qh: queue head for this endpoint
	39	* @wedge: is the endpoint wedged
26c696c6	40	* @ci: pointer to the controller
551a8ac6	41	* @lock: pointer to controller's spinlock
551a8ac6 AS	42	* @td_pool: pointer to controller's TD pool
551a8ac6 AS	43	*/
8e22978c	44	struct ci_hw_ep {
551a8ac6 AS	45	struct usb_ep ep;
	46	u8 dir;
	47	u8 num;
	48	u8 type;
	49	char name[16];
e443b333	50	struct {
551a8ac6	51	struct list_head queue;
8e22978c	52	struct ci_hw_qh *ptr;
551a8ac6 AS	53	dma_addr_t dma;
	54	} qh;
	55	int wedge;
e443b333 AS	56
e443b333 AS	57	/* global resources */
8e22978c	58	struct ci_hdrc *ci;
551a8ac6	59	spinlock_t *lock;
551a8ac6	60	struct dma_pool *td_pool;
2e270412	61	struct td_node *pending_td;
e443b333 AS	62	};
e443b333 AS	63
5f36e231 AS	64	enum ci_role {
	65	CI_ROLE_HOST = 0,
	66	CI_ROLE_GADGET,
	67	CI_ROLE_END,
	68	};
	69
	70	/**
	71	* struct ci_role_driver - host/gadget role driver
	72	* start: start this role
	73	* stop: stop this role
	74	* irq: irq handler for this role
	75	* name: role name string (host/gadget)
	76	*/
	77	struct ci_role_driver {
8e22978c AS	78	int (start)(struct ci_hdrc );
	79	void (stop)(struct ci_hdrc );
	80	irqreturn_t (irq)(struct ci_hdrc );
5f36e231 AS	81	const char *name;
	82	};
	83
551a8ac6 AS	84	/**
	85	* struct hw_bank - hardware register mapping representation
	86	* @lpm: set if the device is LPM capable
eb70e5ab	87	* @phys: physical address of the controller's registers
551a8ac6 AS	88	* @abs: absolute address of the beginning of register window
	89	* @cap: capability registers
	90	* @op: operational registers
	91	* @size: size of the register window
	92	* @regmap: register lookup table
	93	*/
e443b333	94	struct hw_bank {
551a8ac6	95	unsigned lpm;
eb70e5ab	96	resource_size_t phys;
551a8ac6 AS	97	void __iomem *abs;
	98	void __iomem *cap;
	99	void __iomem *op;
	100	size_t size;
	101	void __iomem **regmap;
e443b333 AS	102	};
e443b333 AS	103
551a8ac6	104	/**
8e22978c	105	* struct ci_hdrc - chipidea device representation
551a8ac6 AS	106	* @dev: pointer to parent device
	107	* @lock: access synchronization
	108	* @hw_bank: hardware register mapping
	109	* @irq: IRQ number
	110	* @roles: array of supported roles for this controller
	111	* @role: current role
	112	* @is_otg: if the device is otg-capable
	113	* @work: work for role changing
	114	* @wq: workqueue thread
	115	* @qh_pool: allocation pool for queue heads
	116	* @td_pool: allocation pool for transfer descriptors
	117	* @gadget: device side representation for peripheral controller
	118	* @driver: gadget driver
	119	* @hw_ep_max: total number of endpoints supported by hardware
8e22978c	120	* @ci_hw_ep: array of endpoints
551a8ac6 AS	121	* @ep0_dir: ep0 direction
	122	* @ep0out: pointer to ep0 OUT endpoint
	123	* @ep0in: pointer to ep0 IN endpoint
	124	* @status: ep0 status request
	125	* @setaddr: if we should set the address on status completion
	126	* @address: usb address received from the host
	127	* @remote_wakeup: host-enabled remote wakeup
	128	* @suspended: suspended by host
	129	* @test_mode: the selected test mode
77c4400f	130	* @platdata: platform specific information supplied by parent device
551a8ac6 AS	131	* @vbus_active: is VBUS active
551a8ac6 AS	132	* @transceiver: pointer to USB PHY, if any
eb70e5ab	133	* @hcd: pointer to usb_hcd for ehci host driver
2d651289	134	* @debugfs: root dentry for this controller in debugfs
a107f8c5 PC	135	* @id_event: indicates there is an id event, and handled at ci_otg_work
	136	* @b_sess_valid_event: indicates there is a vbus event, and handled
	137	* at ci_otg_work
551a8ac6	138	*/
8e22978c	139	struct ci_hdrc {
551a8ac6 AS	140	struct device *dev;
	141	spinlock_t lock;
	142	struct hw_bank hw_bank;
	143	int irq;
	144	struct ci_role_driver *roles[CI_ROLE_END];
	145	enum ci_role role;
	146	bool is_otg;
	147	struct work_struct work;
	148	struct workqueue_struct *wq;
	149
	150	struct dma_pool *qh_pool;
	151	struct dma_pool *td_pool;
	152
	153	struct usb_gadget gadget;
	154	struct usb_gadget_driver *driver;
	155	unsigned hw_ep_max;
8e22978c	156	struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
551a8ac6	157	u32 ep0_dir;
8e22978c	158	struct ci_hw_ep ep0out, ep0in;
551a8ac6 AS	159
	160	struct usb_request *status;
	161	bool setaddr;
	162	u8 address;
	163	u8 remote_wakeup;
	164	u8 suspended;
	165	u8 test_mode;
	166
8e22978c	167	struct ci_hdrc_platform_data *platdata;
551a8ac6	168	int vbus_active;
a2c3d690 RZ	169	/* FIXME: some day, we'll not use global phy */
a2c3d690 RZ	170	bool global_phy;
551a8ac6	171	struct usb_phy *transceiver;
eb70e5ab	172	struct usb_hcd *hcd;
2d651289	173	struct dentry *debugfs;
a107f8c5 PC	174	bool id_event;
a107f8c5 PC	175	bool b_sess_valid_event;
e443b333 AS	176	};
e443b333 AS	177
8e22978c	178	static inline struct ci_role_driver ci_role(struct ci_hdrc ci)
5f36e231 AS	179	{
	180	BUG_ON(ci->role >= CI_ROLE_END \|\| !ci->roles[ci->role]);
	181	return ci->roles[ci->role];
	182	}
	183
8e22978c	184	static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
5f36e231 AS	185	{
	186	int ret;
	187
	188	if (role >= CI_ROLE_END)
	189	return -EINVAL;
	190
	191	if (!ci->roles[role])
	192	return -ENXIO;
	193
	194	ret = ci->roles[role]->start(ci);
	195	if (!ret)
	196	ci->role = role;
	197	return ret;
	198	}
	199
8e22978c	200	static inline void ci_role_stop(struct ci_hdrc *ci)
5f36e231 AS	201	{
	202	enum ci_role role = ci->role;
	203
	204	if (role == CI_ROLE_END)
	205	return;
	206
	207	ci->role = CI_ROLE_END;
	208
	209	ci->roles[role]->stop(ci);
	210	}
	211
e443b333 AS	212	/******************************************************************************
	213	* REGISTERS
	214	*****************************************************************************/
	215	/* register size */
	216	#define REG_BITS (32)
	217
	218	/* register indices */
8e22978c	219	enum ci_hw_regs {
e443b333 AS	220	CAP_CAPLENGTH,
	221	CAP_HCCPARAMS,
	222	CAP_DCCPARAMS,
	223	CAP_TESTMODE,
	224	CAP_LAST = CAP_TESTMODE,
	225	OP_USBCMD,
	226	OP_USBSTS,
	227	OP_USBINTR,
	228	OP_DEVICEADDR,
	229	OP_ENDPTLISTADDR,
	230	OP_PORTSC,
	231	OP_DEVLC,
5f36e231	232	OP_OTGSC,
e443b333 AS	233	OP_USBMODE,
	234	OP_ENDPTSETUPSTAT,
	235	OP_ENDPTPRIME,
	236	OP_ENDPTFLUSH,
	237	OP_ENDPTSTAT,
	238	OP_ENDPTCOMPLETE,
	239	OP_ENDPTCTRL,
	240	/* endptctrl1..15 follow */
	241	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
	242	};
	243
e443b333 AS	244	/**
	245	* hw_read: reads from a hw register
	246	* @reg: register index
	247	* @mask: bitfield mask
	248	*
	249	* This function returns register contents
	250	*/
8e22978c	251	static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
e443b333	252	{
26c696c6	253	return ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333 AS	254	}
	255
	256	/**
	257	* hw_write: writes to a hw register
	258	* @reg: register index
	259	* @mask: bitfield mask
	260	* @data: new value
	261	*/
8e22978c	262	static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	263	u32 mask, u32 data)
	264	{
	265	if (~mask)
26c696c6	266	data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
e443b333 AS	267	\| (data & mask);
e443b333 AS	268
26c696c6	269	iowrite32(data, ci->hw_bank.regmap[reg]);
e443b333 AS	270	}
	271
	272	/**
	273	* hw_test_and_clear: tests & clears a hw register
	274	* @reg: register index
	275	* @mask: bitfield mask
	276	*
	277	* This function returns register contents
	278	*/
8e22978c	279	static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	280	u32 mask)
e443b333 AS	281	{
26c696c6	282	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333	283
26c696c6	284	iowrite32(val, ci->hw_bank.regmap[reg]);
e443b333 AS	285	return val;
	286	}
	287
	288	/**
	289	* hw_test_and_write: tests & writes a hw register
	290	* @reg: register index
	291	* @mask: bitfield mask
	292	* @data: new value
	293	*
	294	* This function returns register contents
	295	*/
8e22978c	296	static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	297	u32 mask, u32 data)
e443b333 AS	298	{
26c696c6	299	u32 val = hw_read(ci, reg, ~0);
e443b333	300
26c696c6	301	hw_write(ci, reg, mask, data);
727b4ddb	302	return (val & mask) >> __ffs(mask);
e443b333 AS	303	}
e443b333 AS	304
8e22978c	305	int hw_device_reset(struct ci_hdrc *ci, u32 mode);
e443b333	306
8e22978c	307	int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
e443b333	308
8e22978c	309	u8 hw_port_test_get(struct ci_hdrc *ci);
e443b333	310
22fa8445 PC	311	int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
	312	u32 value, unsigned int timeout_ms);
	313
e443b333	314	#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */