Commit | Line | Data |
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e443b333 AS |
1 | /* |
2 | * core.c - ChipIdea USB IP core family device controller | |
3 | * | |
4 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. | |
5 | * | |
6 | * Author: David Lopo | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Description: ChipIdea USB IP core family device controller | |
15 | * | |
16 | * This driver is composed of several blocks: | |
17 | * - HW: hardware interface | |
18 | * - DBG: debug facilities (optional) | |
19 | * - UTIL: utilities | |
20 | * - ISR: interrupts handling | |
21 | * - ENDPT: endpoint operations (Gadget API) | |
22 | * - GADGET: gadget operations (Gadget API) | |
23 | * - BUS: bus glue code, bus abstraction layer | |
24 | * | |
25 | * Compile Options | |
e443b333 AS |
26 | * - STALL_IN: non-empty bulk-in pipes cannot be halted |
27 | * if defined mass storage compliance succeeds but with warnings | |
28 | * => case 4: Hi > Dn | |
29 | * => case 5: Hi > Di | |
30 | * => case 8: Hi <> Do | |
31 | * if undefined usbtest 13 fails | |
32 | * - TRACE: enable function tracing (depends on DEBUG) | |
33 | * | |
34 | * Main Features | |
35 | * - Chapter 9 & Mass Storage Compliance with Gadget File Storage | |
36 | * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) | |
37 | * - Normal & LPM support | |
38 | * | |
39 | * USBTEST Report | |
40 | * - OK: 0-12, 13 (STALL_IN defined) & 14 | |
41 | * - Not Supported: 15 & 16 (ISO) | |
42 | * | |
43 | * TODO List | |
e443b333 AS |
44 | * - Suspend & Remote Wakeup |
45 | */ | |
46 | #include <linux/delay.h> | |
47 | #include <linux/device.h> | |
e443b333 | 48 | #include <linux/dma-mapping.h> |
3ecb3e09 | 49 | #include <linux/extcon.h> |
1e5e2d3d | 50 | #include <linux/phy/phy.h> |
e443b333 AS |
51 | #include <linux/platform_device.h> |
52 | #include <linux/module.h> | |
fe6e125e | 53 | #include <linux/idr.h> |
e443b333 AS |
54 | #include <linux/interrupt.h> |
55 | #include <linux/io.h> | |
e443b333 AS |
56 | #include <linux/kernel.h> |
57 | #include <linux/slab.h> | |
58 | #include <linux/pm_runtime.h> | |
59 | #include <linux/usb/ch9.h> | |
60 | #include <linux/usb/gadget.h> | |
61 | #include <linux/usb/otg.h> | |
62 | #include <linux/usb/chipidea.h> | |
40dcd0e8 | 63 | #include <linux/usb/of.h> |
4f6743d5 | 64 | #include <linux/of.h> |
40dcd0e8 | 65 | #include <linux/phy.h> |
1542d9c3 | 66 | #include <linux/regulator/consumer.h> |
8022d3d5 | 67 | #include <linux/usb/ehci_def.h> |
e443b333 AS |
68 | |
69 | #include "ci.h" | |
70 | #include "udc.h" | |
71 | #include "bits.h" | |
eb70e5ab | 72 | #include "host.h" |
c10b4f03 | 73 | #include "otg.h" |
4dcf720c | 74 | #include "otg_fsm.h" |
e443b333 | 75 | |
5f36e231 | 76 | /* Controller register map */ |
987e7bc3 MKB |
77 | static const u8 ci_regs_nolpm[] = { |
78 | [CAP_CAPLENGTH] = 0x00U, | |
79 | [CAP_HCCPARAMS] = 0x08U, | |
80 | [CAP_DCCPARAMS] = 0x24U, | |
81 | [CAP_TESTMODE] = 0x38U, | |
82 | [OP_USBCMD] = 0x00U, | |
83 | [OP_USBSTS] = 0x04U, | |
84 | [OP_USBINTR] = 0x08U, | |
85 | [OP_DEVICEADDR] = 0x14U, | |
86 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 87 | [OP_TTCTRL] = 0x1CU, |
96625ead | 88 | [OP_BURSTSIZE] = 0x20U, |
987e7bc3 MKB |
89 | [OP_PORTSC] = 0x44U, |
90 | [OP_DEVLC] = 0x84U, | |
91 | [OP_OTGSC] = 0x64U, | |
92 | [OP_USBMODE] = 0x68U, | |
93 | [OP_ENDPTSETUPSTAT] = 0x6CU, | |
94 | [OP_ENDPTPRIME] = 0x70U, | |
95 | [OP_ENDPTFLUSH] = 0x74U, | |
96 | [OP_ENDPTSTAT] = 0x78U, | |
97 | [OP_ENDPTCOMPLETE] = 0x7CU, | |
98 | [OP_ENDPTCTRL] = 0x80U, | |
e443b333 AS |
99 | }; |
100 | ||
987e7bc3 MKB |
101 | static const u8 ci_regs_lpm[] = { |
102 | [CAP_CAPLENGTH] = 0x00U, | |
103 | [CAP_HCCPARAMS] = 0x08U, | |
104 | [CAP_DCCPARAMS] = 0x24U, | |
105 | [CAP_TESTMODE] = 0xFCU, | |
106 | [OP_USBCMD] = 0x00U, | |
107 | [OP_USBSTS] = 0x04U, | |
108 | [OP_USBINTR] = 0x08U, | |
109 | [OP_DEVICEADDR] = 0x14U, | |
110 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 111 | [OP_TTCTRL] = 0x1CU, |
96625ead | 112 | [OP_BURSTSIZE] = 0x20U, |
987e7bc3 MKB |
113 | [OP_PORTSC] = 0x44U, |
114 | [OP_DEVLC] = 0x84U, | |
115 | [OP_OTGSC] = 0xC4U, | |
116 | [OP_USBMODE] = 0xC8U, | |
117 | [OP_ENDPTSETUPSTAT] = 0xD8U, | |
118 | [OP_ENDPTPRIME] = 0xDCU, | |
119 | [OP_ENDPTFLUSH] = 0xE0U, | |
120 | [OP_ENDPTSTAT] = 0xE4U, | |
121 | [OP_ENDPTCOMPLETE] = 0xE8U, | |
122 | [OP_ENDPTCTRL] = 0xECU, | |
e443b333 AS |
123 | }; |
124 | ||
158ec071 | 125 | static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) |
e443b333 AS |
126 | { |
127 | int i; | |
128 | ||
e443b333 | 129 | for (i = 0; i < OP_ENDPTCTRL; i++) |
5f36e231 AS |
130 | ci->hw_bank.regmap[i] = |
131 | (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + | |
e443b333 AS |
132 | (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); |
133 | ||
134 | for (; i <= OP_LAST; i++) | |
5f36e231 | 135 | ci->hw_bank.regmap[i] = ci->hw_bank.op + |
e443b333 AS |
136 | 4 * (i - OP_ENDPTCTRL) + |
137 | (is_lpm | |
138 | ? ci_regs_lpm[OP_ENDPTCTRL] | |
139 | : ci_regs_nolpm[OP_ENDPTCTRL]); | |
140 | ||
e443b333 AS |
141 | } |
142 | ||
cb271f3c PC |
143 | static enum ci_revision ci_get_revision(struct ci_hdrc *ci) |
144 | { | |
145 | int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); | |
146 | enum ci_revision rev = CI_REVISION_UNKNOWN; | |
147 | ||
148 | if (ver == 0x2) { | |
149 | rev = hw_read_id_reg(ci, ID_ID, REVISION) | |
150 | >> __ffs(REVISION); | |
151 | rev += CI_REVISION_20; | |
152 | } else if (ver == 0x0) { | |
153 | rev = CI_REVISION_1X; | |
154 | } | |
155 | ||
156 | return rev; | |
157 | } | |
158 | ||
36304b06 LJ |
159 | /** |
160 | * hw_read_intr_enable: returns interrupt enable register | |
161 | * | |
19353881 PC |
162 | * @ci: the controller |
163 | * | |
36304b06 LJ |
164 | * This function returns register data |
165 | */ | |
166 | u32 hw_read_intr_enable(struct ci_hdrc *ci) | |
167 | { | |
168 | return hw_read(ci, OP_USBINTR, ~0); | |
169 | } | |
170 | ||
171 | /** | |
172 | * hw_read_intr_status: returns interrupt status register | |
173 | * | |
19353881 PC |
174 | * @ci: the controller |
175 | * | |
36304b06 LJ |
176 | * This function returns register data |
177 | */ | |
178 | u32 hw_read_intr_status(struct ci_hdrc *ci) | |
179 | { | |
180 | return hw_read(ci, OP_USBSTS, ~0); | |
181 | } | |
182 | ||
e443b333 AS |
183 | /** |
184 | * hw_port_test_set: writes port test mode (execute without interruption) | |
185 | * @mode: new value | |
186 | * | |
187 | * This function returns an error code | |
188 | */ | |
8e22978c | 189 | int hw_port_test_set(struct ci_hdrc *ci, u8 mode) |
e443b333 AS |
190 | { |
191 | const u8 TEST_MODE_MAX = 7; | |
192 | ||
193 | if (mode > TEST_MODE_MAX) | |
194 | return -EINVAL; | |
195 | ||
727b4ddb | 196 | hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); |
e443b333 AS |
197 | return 0; |
198 | } | |
199 | ||
200 | /** | |
201 | * hw_port_test_get: reads port test mode value | |
202 | * | |
19353881 PC |
203 | * @ci: the controller |
204 | * | |
e443b333 AS |
205 | * This function returns port test mode value |
206 | */ | |
8e22978c | 207 | u8 hw_port_test_get(struct ci_hdrc *ci) |
e443b333 | 208 | { |
727b4ddb | 209 | return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); |
e443b333 AS |
210 | } |
211 | ||
b82613cf PC |
212 | static void hw_wait_phy_stable(void) |
213 | { | |
214 | /* | |
215 | * The phy needs some delay to output the stable status from low | |
216 | * power mode. And for OTGSC, the status inputs are debounced | |
217 | * using a 1 ms time constant, so, delay 2ms for controller to get | |
218 | * the stable status, like vbus and id when the phy leaves low power. | |
219 | */ | |
220 | usleep_range(2000, 2500); | |
221 | } | |
222 | ||
864cf949 PC |
223 | /* The PHY enters/leaves low power mode */ |
224 | static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) | |
225 | { | |
226 | enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; | |
227 | bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); | |
228 | ||
6d037db6 | 229 | if (enable && !lpm) |
864cf949 PC |
230 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
231 | PORTSC_PHCD(ci->hw_bank.lpm)); | |
6d037db6 | 232 | else if (!enable && lpm) |
864cf949 PC |
233 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
234 | 0); | |
864cf949 PC |
235 | } |
236 | ||
8e22978c | 237 | static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) |
e443b333 AS |
238 | { |
239 | u32 reg; | |
240 | ||
241 | /* bank is a module variable */ | |
5f36e231 | 242 | ci->hw_bank.abs = base; |
e443b333 | 243 | |
5f36e231 | 244 | ci->hw_bank.cap = ci->hw_bank.abs; |
77c4400f | 245 | ci->hw_bank.cap += ci->platdata->capoffset; |
938d323f | 246 | ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); |
e443b333 | 247 | |
5f36e231 AS |
248 | hw_alloc_regmap(ci, false); |
249 | reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> | |
727b4ddb | 250 | __ffs(HCCPARAMS_LEN); |
5f36e231 | 251 | ci->hw_bank.lpm = reg; |
aeb2c121 CR |
252 | if (reg) |
253 | hw_alloc_regmap(ci, !!reg); | |
5f36e231 AS |
254 | ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; |
255 | ci->hw_bank.size += OP_LAST; | |
256 | ci->hw_bank.size /= sizeof(u32); | |
e443b333 | 257 | |
5f36e231 | 258 | reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> |
727b4ddb | 259 | __ffs(DCCPARAMS_DEN); |
5f36e231 | 260 | ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ |
e443b333 | 261 | |
09c94e62 | 262 | if (ci->hw_ep_max > ENDPT_MAX) |
e443b333 AS |
263 | return -ENODEV; |
264 | ||
864cf949 PC |
265 | ci_hdrc_enter_lpm(ci, false); |
266 | ||
c344b518 PC |
267 | /* Disable all interrupts bits */ |
268 | hw_write(ci, OP_USBINTR, 0xffffffff, 0); | |
269 | ||
270 | /* Clear all interrupts status bits*/ | |
271 | hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); | |
272 | ||
cb271f3c PC |
273 | ci->rev = ci_get_revision(ci); |
274 | ||
275 | dev_dbg(ci->dev, | |
276 | "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n", | |
277 | ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); | |
e443b333 AS |
278 | |
279 | /* setup lock mode ? */ | |
280 | ||
281 | /* ENDPTSETUPSTAT is '0' by default */ | |
282 | ||
283 | /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
8e22978c | 288 | static void hw_phymode_configure(struct ci_hdrc *ci) |
40dcd0e8 | 289 | { |
3b5d3e68 | 290 | u32 portsc, lpm, sts = 0; |
40dcd0e8 MG |
291 | |
292 | switch (ci->platdata->phy_mode) { | |
293 | case USBPHY_INTERFACE_MODE_UTMI: | |
294 | portsc = PORTSC_PTS(PTS_UTMI); | |
295 | lpm = DEVLC_PTS(PTS_UTMI); | |
296 | break; | |
297 | case USBPHY_INTERFACE_MODE_UTMIW: | |
298 | portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; | |
299 | lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; | |
300 | break; | |
301 | case USBPHY_INTERFACE_MODE_ULPI: | |
302 | portsc = PORTSC_PTS(PTS_ULPI); | |
303 | lpm = DEVLC_PTS(PTS_ULPI); | |
304 | break; | |
305 | case USBPHY_INTERFACE_MODE_SERIAL: | |
306 | portsc = PORTSC_PTS(PTS_SERIAL); | |
307 | lpm = DEVLC_PTS(PTS_SERIAL); | |
308 | sts = 1; | |
309 | break; | |
310 | case USBPHY_INTERFACE_MODE_HSIC: | |
311 | portsc = PORTSC_PTS(PTS_HSIC); | |
312 | lpm = DEVLC_PTS(PTS_HSIC); | |
313 | break; | |
314 | default: | |
315 | return; | |
316 | } | |
317 | ||
318 | if (ci->hw_bank.lpm) { | |
319 | hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); | |
3b5d3e68 CR |
320 | if (sts) |
321 | hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); | |
40dcd0e8 MG |
322 | } else { |
323 | hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); | |
3b5d3e68 CR |
324 | if (sts) |
325 | hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); | |
40dcd0e8 MG |
326 | } |
327 | } | |
328 | ||
1e5e2d3d AT |
329 | /** |
330 | * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy | |
331 | * interfaces | |
332 | * @ci: the controller | |
333 | * | |
334 | * This function returns an error code if the phy failed to init | |
335 | */ | |
336 | static int _ci_usb_phy_init(struct ci_hdrc *ci) | |
337 | { | |
338 | int ret; | |
339 | ||
340 | if (ci->phy) { | |
341 | ret = phy_init(ci->phy); | |
342 | if (ret) | |
343 | return ret; | |
344 | ||
345 | ret = phy_power_on(ci->phy); | |
346 | if (ret) { | |
347 | phy_exit(ci->phy); | |
348 | return ret; | |
349 | } | |
350 | } else { | |
351 | ret = usb_phy_init(ci->usb_phy); | |
352 | } | |
353 | ||
354 | return ret; | |
355 | } | |
356 | ||
357 | /** | |
358 | * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy | |
359 | * interfaces | |
360 | * @ci: the controller | |
361 | */ | |
362 | static void ci_usb_phy_exit(struct ci_hdrc *ci) | |
363 | { | |
364 | if (ci->phy) { | |
365 | phy_power_off(ci->phy); | |
366 | phy_exit(ci->phy); | |
367 | } else { | |
368 | usb_phy_shutdown(ci->usb_phy); | |
369 | } | |
370 | } | |
371 | ||
d03cccff PC |
372 | /** |
373 | * ci_usb_phy_init: initialize phy according to different phy type | |
374 | * @ci: the controller | |
19353881 | 375 | * |
d03cccff PC |
376 | * This function returns an error code if usb_phy_init has failed |
377 | */ | |
378 | static int ci_usb_phy_init(struct ci_hdrc *ci) | |
379 | { | |
380 | int ret; | |
381 | ||
382 | switch (ci->platdata->phy_mode) { | |
383 | case USBPHY_INTERFACE_MODE_UTMI: | |
384 | case USBPHY_INTERFACE_MODE_UTMIW: | |
385 | case USBPHY_INTERFACE_MODE_HSIC: | |
1e5e2d3d | 386 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
387 | if (!ret) |
388 | hw_wait_phy_stable(); | |
389 | else | |
d03cccff PC |
390 | return ret; |
391 | hw_phymode_configure(ci); | |
392 | break; | |
393 | case USBPHY_INTERFACE_MODE_ULPI: | |
394 | case USBPHY_INTERFACE_MODE_SERIAL: | |
395 | hw_phymode_configure(ci); | |
1e5e2d3d | 396 | ret = _ci_usb_phy_init(ci); |
d03cccff PC |
397 | if (ret) |
398 | return ret; | |
399 | break; | |
400 | default: | |
1e5e2d3d | 401 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
402 | if (!ret) |
403 | hw_wait_phy_stable(); | |
d03cccff PC |
404 | } |
405 | ||
406 | return ret; | |
407 | } | |
408 | ||
bf9c85e7 PC |
409 | |
410 | /** | |
411 | * ci_platform_configure: do controller configure | |
412 | * @ci: the controller | |
413 | * | |
414 | */ | |
415 | void ci_platform_configure(struct ci_hdrc *ci) | |
416 | { | |
8022d3d5 PC |
417 | bool is_device_mode, is_host_mode; |
418 | ||
419 | is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; | |
420 | is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; | |
421 | ||
422 | if (is_device_mode && | |
423 | (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)) | |
424 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); | |
425 | ||
426 | if (is_host_mode && | |
427 | (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)) | |
bf9c85e7 PC |
428 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); |
429 | ||
430 | if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { | |
431 | if (ci->hw_bank.lpm) | |
432 | hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); | |
433 | else | |
434 | hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); | |
435 | } | |
436 | ||
437 | if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) | |
438 | hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); | |
df96ed8d PC |
439 | |
440 | hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); | |
441 | ||
65668718 PC |
442 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) |
443 | hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, | |
444 | ci->platdata->ahb_burst_config); | |
96625ead PC |
445 | |
446 | /* override burst size, take effect only when ahb_burst_config is 0 */ | |
447 | if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { | |
448 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) | |
449 | hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, | |
450 | ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); | |
451 | ||
452 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) | |
453 | hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, | |
454 | ci->platdata->rx_burst_size); | |
455 | } | |
bf9c85e7 PC |
456 | } |
457 | ||
e443b333 | 458 | /** |
cdd278f2 | 459 | * hw_controller_reset: do controller reset |
e443b333 AS |
460 | * @ci: the controller |
461 | * | |
462 | * This function returns an error code | |
463 | */ | |
cdd278f2 PC |
464 | static int hw_controller_reset(struct ci_hdrc *ci) |
465 | { | |
466 | int count = 0; | |
467 | ||
468 | hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); | |
469 | while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { | |
470 | udelay(10); | |
471 | if (count++ > 1000) | |
472 | return -ETIMEDOUT; | |
473 | } | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
478 | /** | |
479 | * hw_device_reset: resets chip (execute without interruption) | |
480 | * @ci: the controller | |
481 | * | |
482 | * This function returns an error code | |
483 | */ | |
5b157300 | 484 | int hw_device_reset(struct ci_hdrc *ci) |
e443b333 | 485 | { |
cdd278f2 PC |
486 | int ret; |
487 | ||
e443b333 AS |
488 | /* should flush & stop before reset */ |
489 | hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); | |
490 | hw_write(ci, OP_USBCMD, USBCMD_RS, 0); | |
491 | ||
cdd278f2 PC |
492 | ret = hw_controller_reset(ci); |
493 | if (ret) { | |
494 | dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); | |
495 | return ret; | |
496 | } | |
e443b333 | 497 | |
77c4400f RZ |
498 | if (ci->platdata->notify_event) |
499 | ci->platdata->notify_event(ci, | |
8e22978c | 500 | CI_HDRC_CONTROLLER_RESET_EVENT); |
e443b333 | 501 | |
e443b333 AS |
502 | /* USBMODE should be configured step by step */ |
503 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); | |
5b157300 | 504 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); |
e443b333 AS |
505 | /* HW >= 2.3 */ |
506 | hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); | |
507 | ||
5b157300 PC |
508 | if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { |
509 | pr_err("cannot enter in %s device mode", ci_role(ci)->name); | |
e443b333 AS |
510 | pr_err("lpm = %i", ci->hw_bank.lpm); |
511 | return -ENODEV; | |
512 | } | |
513 | ||
bf9c85e7 PC |
514 | ci_platform_configure(ci); |
515 | ||
e443b333 AS |
516 | return 0; |
517 | } | |
518 | ||
22fa8445 PC |
519 | /** |
520 | * hw_wait_reg: wait the register value | |
521 | * | |
522 | * Sometimes, it needs to wait register value before going on. | |
523 | * Eg, when switch to device mode, the vbus value should be lower | |
524 | * than OTGSC_BSV before connects to host. | |
525 | * | |
526 | * @ci: the controller | |
527 | * @reg: register index | |
528 | * @mask: mast bit | |
529 | * @value: the bit value to wait | |
530 | * @timeout_ms: timeout in millisecond | |
531 | * | |
532 | * This function returns an error code if timeout | |
533 | */ | |
534 | int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, | |
535 | u32 value, unsigned int timeout_ms) | |
536 | { | |
537 | unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); | |
538 | ||
539 | while (hw_read(ci, reg, mask) != value) { | |
540 | if (time_after(jiffies, elapse)) { | |
541 | dev_err(ci->dev, "timeout waiting for %08x in %d\n", | |
542 | mask, reg); | |
543 | return -ETIMEDOUT; | |
544 | } | |
545 | msleep(20); | |
546 | } | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
5f36e231 AS |
551 | static irqreturn_t ci_irq(int irq, void *data) |
552 | { | |
8e22978c | 553 | struct ci_hdrc *ci = data; |
5f36e231 | 554 | irqreturn_t ret = IRQ_NONE; |
b183c19f | 555 | u32 otgsc = 0; |
5f36e231 | 556 | |
1f874edc PC |
557 | if (ci->in_lpm) { |
558 | disable_irq_nosync(irq); | |
559 | ci->wakeup_int = true; | |
560 | pm_runtime_get(ci->dev); | |
561 | return IRQ_HANDLED; | |
562 | } | |
563 | ||
4dcf720c | 564 | if (ci->is_otg) { |
0c33bf78 | 565 | otgsc = hw_read_otgsc(ci, ~0); |
4dcf720c LJ |
566 | if (ci_otg_is_fsm_mode(ci)) { |
567 | ret = ci_otg_fsm_irq(ci); | |
568 | if (ret == IRQ_HANDLED) | |
569 | return ret; | |
570 | } | |
571 | } | |
5f36e231 | 572 | |
a107f8c5 PC |
573 | /* |
574 | * Handle id change interrupt, it indicates device/host function | |
575 | * switch. | |
576 | */ | |
577 | if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { | |
578 | ci->id_event = true; | |
0c33bf78 LJ |
579 | /* Clear ID change irq status */ |
580 | hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); | |
be6b0c1b | 581 | ci_otg_queue_work(ci); |
a107f8c5 PC |
582 | return IRQ_HANDLED; |
583 | } | |
b183c19f | 584 | |
a107f8c5 PC |
585 | /* |
586 | * Handle vbus change interrupt, it indicates device connection | |
587 | * and disconnection events. | |
588 | */ | |
589 | if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { | |
590 | ci->b_sess_valid_event = true; | |
0c33bf78 LJ |
591 | /* Clear BSV irq */ |
592 | hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); | |
be6b0c1b | 593 | ci_otg_queue_work(ci); |
a107f8c5 | 594 | return IRQ_HANDLED; |
5f36e231 AS |
595 | } |
596 | ||
a107f8c5 PC |
597 | /* Handle device/host interrupt */ |
598 | if (ci->role != CI_ROLE_END) | |
599 | ret = ci_role(ci)->irq(ci); | |
600 | ||
b183c19f | 601 | return ret; |
5f36e231 AS |
602 | } |
603 | ||
3ecb3e09 II |
604 | static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event, |
605 | void *ptr) | |
606 | { | |
607 | struct ci_hdrc_cable *vbus = container_of(nb, struct ci_hdrc_cable, nb); | |
608 | struct ci_hdrc *ci = vbus->ci; | |
609 | ||
610 | if (event) | |
611 | vbus->state = true; | |
612 | else | |
613 | vbus->state = false; | |
614 | ||
615 | vbus->changed = true; | |
616 | ||
617 | ci_irq(ci->irq, ci); | |
618 | return NOTIFY_DONE; | |
619 | } | |
620 | ||
621 | static int ci_id_notifier(struct notifier_block *nb, unsigned long event, | |
622 | void *ptr) | |
623 | { | |
624 | struct ci_hdrc_cable *id = container_of(nb, struct ci_hdrc_cable, nb); | |
625 | struct ci_hdrc *ci = id->ci; | |
626 | ||
627 | if (event) | |
628 | id->state = false; | |
629 | else | |
630 | id->state = true; | |
631 | ||
632 | id->changed = true; | |
633 | ||
634 | ci_irq(ci->irq, ci); | |
635 | return NOTIFY_DONE; | |
636 | } | |
637 | ||
1542d9c3 PC |
638 | static int ci_get_platdata(struct device *dev, |
639 | struct ci_hdrc_platform_data *platdata) | |
640 | { | |
3ecb3e09 II |
641 | struct extcon_dev *ext_vbus, *ext_id; |
642 | struct ci_hdrc_cable *cable; | |
79742351 LJ |
643 | int ret; |
644 | ||
c22600c3 PC |
645 | if (!platdata->phy_mode) |
646 | platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); | |
647 | ||
648 | if (!platdata->dr_mode) | |
06e7114f | 649 | platdata->dr_mode = usb_get_dr_mode(dev); |
c22600c3 PC |
650 | |
651 | if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) | |
652 | platdata->dr_mode = USB_DR_MODE_OTG; | |
653 | ||
c2ec3a73 PC |
654 | if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { |
655 | /* Get the vbus regulator */ | |
656 | platdata->reg_vbus = devm_regulator_get(dev, "vbus"); | |
657 | if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { | |
658 | return -EPROBE_DEFER; | |
659 | } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { | |
6629467b | 660 | /* no vbus regulator is needed */ |
c2ec3a73 PC |
661 | platdata->reg_vbus = NULL; |
662 | } else if (IS_ERR(platdata->reg_vbus)) { | |
663 | dev_err(dev, "Getting regulator error: %ld\n", | |
664 | PTR_ERR(platdata->reg_vbus)); | |
665 | return PTR_ERR(platdata->reg_vbus); | |
666 | } | |
f6a9ff07 PC |
667 | /* Get TPL support */ |
668 | if (!platdata->tpl_support) | |
669 | platdata->tpl_support = | |
670 | of_usb_host_tpl_support(dev->of_node); | |
c2ec3a73 PC |
671 | } |
672 | ||
79742351 LJ |
673 | if (platdata->dr_mode == USB_DR_MODE_OTG) { |
674 | /* We can support HNP and SRP of OTG 2.0 */ | |
675 | platdata->ci_otg_caps.otg_rev = 0x0200; | |
676 | platdata->ci_otg_caps.hnp_support = true; | |
677 | platdata->ci_otg_caps.srp_support = true; | |
678 | ||
679 | /* Update otg capabilities by DT properties */ | |
680 | ret = of_usb_update_otg_caps(dev->of_node, | |
681 | &platdata->ci_otg_caps); | |
682 | if (ret) | |
683 | return ret; | |
684 | } | |
685 | ||
63863b98 | 686 | if (usb_get_maximum_speed(dev) == USB_SPEED_FULL) |
4f6743d5 MG |
687 | platdata->flags |= CI_HDRC_FORCE_FULLSPEED; |
688 | ||
4b19b78a | 689 | of_property_read_u32(dev->of_node, "phy-clkgate-delay-us", |
1fbf4628 FE |
690 | &platdata->phy_clkgate_delay_us); |
691 | ||
df96ed8d | 692 | platdata->itc_setting = 1; |
df96ed8d | 693 | |
4b19b78a SS |
694 | of_property_read_u32(dev->of_node, "itc-setting", |
695 | &platdata->itc_setting); | |
696 | ||
697 | ret = of_property_read_u32(dev->of_node, "ahb-burst-config", | |
698 | &platdata->ahb_burst_config); | |
699 | if (!ret) { | |
65668718 | 700 | platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; |
4b19b78a SS |
701 | } else if (ret != -EINVAL) { |
702 | dev_err(dev, "failed to get ahb-burst-config\n"); | |
703 | return ret; | |
65668718 PC |
704 | } |
705 | ||
4b19b78a SS |
706 | ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", |
707 | &platdata->tx_burst_size); | |
708 | if (!ret) { | |
96625ead | 709 | platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; |
4b19b78a SS |
710 | } else if (ret != -EINVAL) { |
711 | dev_err(dev, "failed to get tx-burst-size-dword\n"); | |
712 | return ret; | |
96625ead PC |
713 | } |
714 | ||
4b19b78a SS |
715 | ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", |
716 | &platdata->rx_burst_size); | |
717 | if (!ret) { | |
96625ead | 718 | platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; |
4b19b78a SS |
719 | } else if (ret != -EINVAL) { |
720 | dev_err(dev, "failed to get rx-burst-size-dword\n"); | |
721 | return ret; | |
96625ead PC |
722 | } |
723 | ||
aa738187 PC |
724 | if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL)) |
725 | platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA; | |
726 | ||
3ecb3e09 II |
727 | ext_id = ERR_PTR(-ENODEV); |
728 | ext_vbus = ERR_PTR(-ENODEV); | |
729 | if (of_property_read_bool(dev->of_node, "extcon")) { | |
730 | /* Each one of them is not mandatory */ | |
731 | ext_vbus = extcon_get_edev_by_phandle(dev, 0); | |
732 | if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) | |
733 | return PTR_ERR(ext_vbus); | |
734 | ||
735 | ext_id = extcon_get_edev_by_phandle(dev, 1); | |
736 | if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) | |
737 | return PTR_ERR(ext_id); | |
738 | } | |
739 | ||
740 | cable = &platdata->vbus_extcon; | |
741 | cable->nb.notifier_call = ci_vbus_notifier; | |
742 | cable->edev = ext_vbus; | |
743 | ||
744 | if (!IS_ERR(ext_vbus)) { | |
745 | ret = extcon_get_cable_state_(cable->edev, EXTCON_USB); | |
746 | if (ret) | |
747 | cable->state = true; | |
748 | else | |
749 | cable->state = false; | |
750 | } | |
751 | ||
752 | cable = &platdata->id_extcon; | |
753 | cable->nb.notifier_call = ci_id_notifier; | |
754 | cable->edev = ext_id; | |
755 | ||
756 | if (!IS_ERR(ext_id)) { | |
757 | ret = extcon_get_cable_state_(cable->edev, EXTCON_USB_HOST); | |
758 | if (ret) | |
759 | cable->state = false; | |
760 | else | |
761 | cable->state = true; | |
762 | } | |
1542d9c3 PC |
763 | return 0; |
764 | } | |
765 | ||
3ecb3e09 II |
766 | static int ci_extcon_register(struct ci_hdrc *ci) |
767 | { | |
768 | struct ci_hdrc_cable *id, *vbus; | |
769 | int ret; | |
770 | ||
771 | id = &ci->platdata->id_extcon; | |
772 | id->ci = ci; | |
773 | if (!IS_ERR(id->edev)) { | |
774 | ret = extcon_register_notifier(id->edev, EXTCON_USB_HOST, | |
775 | &id->nb); | |
776 | if (ret < 0) { | |
777 | dev_err(ci->dev, "register ID failed\n"); | |
778 | return ret; | |
779 | } | |
780 | } | |
781 | ||
782 | vbus = &ci->platdata->vbus_extcon; | |
783 | vbus->ci = ci; | |
784 | if (!IS_ERR(vbus->edev)) { | |
785 | ret = extcon_register_notifier(vbus->edev, EXTCON_USB, | |
786 | &vbus->nb); | |
787 | if (ret < 0) { | |
788 | extcon_unregister_notifier(id->edev, EXTCON_USB_HOST, | |
789 | &id->nb); | |
790 | dev_err(ci->dev, "register VBUS failed\n"); | |
791 | return ret; | |
792 | } | |
793 | } | |
794 | ||
1542d9c3 PC |
795 | return 0; |
796 | } | |
797 | ||
3ecb3e09 II |
798 | static void ci_extcon_unregister(struct ci_hdrc *ci) |
799 | { | |
800 | struct ci_hdrc_cable *cable; | |
801 | ||
802 | cable = &ci->platdata->id_extcon; | |
803 | if (!IS_ERR(cable->edev)) | |
804 | extcon_unregister_notifier(cable->edev, EXTCON_USB_HOST, | |
805 | &cable->nb); | |
806 | ||
807 | cable = &ci->platdata->vbus_extcon; | |
808 | if (!IS_ERR(cable->edev)) | |
809 | extcon_unregister_notifier(cable->edev, EXTCON_USB, &cable->nb); | |
810 | } | |
811 | ||
fe6e125e RZ |
812 | static DEFINE_IDA(ci_ida); |
813 | ||
8e22978c | 814 | struct platform_device *ci_hdrc_add_device(struct device *dev, |
cbc6dc2a | 815 | struct resource *res, int nres, |
8e22978c | 816 | struct ci_hdrc_platform_data *platdata) |
cbc6dc2a RZ |
817 | { |
818 | struct platform_device *pdev; | |
fe6e125e | 819 | int id, ret; |
cbc6dc2a | 820 | |
1542d9c3 PC |
821 | ret = ci_get_platdata(dev, platdata); |
822 | if (ret) | |
823 | return ERR_PTR(ret); | |
824 | ||
fe6e125e RZ |
825 | id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); |
826 | if (id < 0) | |
827 | return ERR_PTR(id); | |
828 | ||
829 | pdev = platform_device_alloc("ci_hdrc", id); | |
830 | if (!pdev) { | |
831 | ret = -ENOMEM; | |
832 | goto put_id; | |
833 | } | |
cbc6dc2a RZ |
834 | |
835 | pdev->dev.parent = dev; | |
836 | pdev->dev.dma_mask = dev->dma_mask; | |
837 | pdev->dev.dma_parms = dev->dma_parms; | |
838 | dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); | |
839 | ||
840 | ret = platform_device_add_resources(pdev, res, nres); | |
841 | if (ret) | |
842 | goto err; | |
843 | ||
844 | ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); | |
845 | if (ret) | |
846 | goto err; | |
847 | ||
848 | ret = platform_device_add(pdev); | |
849 | if (ret) | |
850 | goto err; | |
851 | ||
852 | return pdev; | |
853 | ||
854 | err: | |
855 | platform_device_put(pdev); | |
fe6e125e RZ |
856 | put_id: |
857 | ida_simple_remove(&ci_ida, id); | |
cbc6dc2a RZ |
858 | return ERR_PTR(ret); |
859 | } | |
8e22978c | 860 | EXPORT_SYMBOL_GPL(ci_hdrc_add_device); |
cbc6dc2a | 861 | |
8e22978c | 862 | void ci_hdrc_remove_device(struct platform_device *pdev) |
cbc6dc2a | 863 | { |
98c35534 | 864 | int id = pdev->id; |
cbc6dc2a | 865 | platform_device_unregister(pdev); |
98c35534 | 866 | ida_simple_remove(&ci_ida, id); |
cbc6dc2a | 867 | } |
8e22978c | 868 | EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); |
cbc6dc2a | 869 | |
3f124d23 PC |
870 | static inline void ci_role_destroy(struct ci_hdrc *ci) |
871 | { | |
872 | ci_hdrc_gadget_destroy(ci); | |
873 | ci_hdrc_host_destroy(ci); | |
cbec6bd5 PC |
874 | if (ci->is_otg) |
875 | ci_hdrc_otg_destroy(ci); | |
3f124d23 PC |
876 | } |
877 | ||
577b232f PC |
878 | static void ci_get_otg_capable(struct ci_hdrc *ci) |
879 | { | |
880 | if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) | |
881 | ci->is_otg = false; | |
882 | else | |
883 | ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, | |
884 | DCCPARAMS_DC | DCCPARAMS_HC) | |
885 | == (DCCPARAMS_DC | DCCPARAMS_HC)); | |
2e37cfd8 | 886 | if (ci->is_otg) { |
577b232f | 887 | dev_dbg(ci->dev, "It is OTG capable controller\n"); |
2e37cfd8 PC |
888 | /* Disable and clear all OTG irq */ |
889 | hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, | |
890 | OTGSC_INT_STATUS_BITS); | |
891 | } | |
577b232f PC |
892 | } |
893 | ||
41ac7b3a | 894 | static int ci_hdrc_probe(struct platform_device *pdev) |
e443b333 AS |
895 | { |
896 | struct device *dev = &pdev->dev; | |
8e22978c | 897 | struct ci_hdrc *ci; |
e443b333 AS |
898 | struct resource *res; |
899 | void __iomem *base; | |
900 | int ret; | |
691962d1 | 901 | enum usb_dr_mode dr_mode; |
e443b333 | 902 | |
fad56745 | 903 | if (!dev_get_platdata(dev)) { |
e443b333 AS |
904 | dev_err(dev, "platform data missing\n"); |
905 | return -ENODEV; | |
906 | } | |
907 | ||
908 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
19290816 FB |
909 | base = devm_ioremap_resource(dev, res); |
910 | if (IS_ERR(base)) | |
911 | return PTR_ERR(base); | |
e443b333 | 912 | |
5f36e231 | 913 | ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); |
d0f99249 | 914 | if (!ci) |
5f36e231 | 915 | return -ENOMEM; |
5f36e231 AS |
916 | |
917 | ci->dev = dev; | |
fad56745 | 918 | ci->platdata = dev_get_platdata(dev); |
ed8f8318 PC |
919 | ci->imx28_write_fix = !!(ci->platdata->flags & |
920 | CI_HDRC_IMX28_WRITE_FIX); | |
1f874edc PC |
921 | ci->supports_runtime_pm = !!(ci->platdata->flags & |
922 | CI_HDRC_SUPPORTS_RUNTIME_PM); | |
5f36e231 AS |
923 | |
924 | ret = hw_device_init(ci, base); | |
925 | if (ret < 0) { | |
926 | dev_err(dev, "can't initialize hardware\n"); | |
927 | return -ENODEV; | |
928 | } | |
e443b333 | 929 | |
1e5e2d3d AT |
930 | if (ci->platdata->phy) { |
931 | ci->phy = ci->platdata->phy; | |
932 | } else if (ci->platdata->usb_phy) { | |
ef44cb42 | 933 | ci->usb_phy = ci->platdata->usb_phy; |
1e5e2d3d | 934 | } else { |
21a5b579 AT |
935 | ci->phy = devm_phy_get(dev->parent, "usb-phy"); |
936 | ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); | |
c859aa65 | 937 | |
1e5e2d3d AT |
938 | /* if both generic PHY and USB PHY layers aren't enabled */ |
939 | if (PTR_ERR(ci->phy) == -ENOSYS && | |
940 | PTR_ERR(ci->usb_phy) == -ENXIO) | |
941 | return -ENXIO; | |
942 | ||
943 | if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) | |
944 | return -EPROBE_DEFER; | |
c859aa65 | 945 | |
1e5e2d3d AT |
946 | if (IS_ERR(ci->phy)) |
947 | ci->phy = NULL; | |
948 | else if (IS_ERR(ci->usb_phy)) | |
949 | ci->usb_phy = NULL; | |
c859aa65 PC |
950 | } |
951 | ||
d03cccff | 952 | ret = ci_usb_phy_init(ci); |
74475ede PC |
953 | if (ret) { |
954 | dev_err(dev, "unable to init phy: %d\n", ret); | |
955 | return ret; | |
956 | } | |
957 | ||
eb70e5ab AS |
958 | ci->hw_bank.phys = res->start; |
959 | ||
5f36e231 AS |
960 | ci->irq = platform_get_irq(pdev, 0); |
961 | if (ci->irq < 0) { | |
e443b333 | 962 | dev_err(dev, "missing IRQ\n"); |
42d18212 | 963 | ret = ci->irq; |
c859aa65 | 964 | goto deinit_phy; |
5f36e231 AS |
965 | } |
966 | ||
577b232f PC |
967 | ci_get_otg_capable(ci); |
968 | ||
691962d1 | 969 | dr_mode = ci->platdata->dr_mode; |
5f36e231 | 970 | /* initialize role(s) before the interrupt is requested */ |
691962d1 SH |
971 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { |
972 | ret = ci_hdrc_host_init(ci); | |
973 | if (ret) | |
974 | dev_info(dev, "doesn't support host\n"); | |
975 | } | |
eb70e5ab | 976 | |
691962d1 SH |
977 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { |
978 | ret = ci_hdrc_gadget_init(ci); | |
979 | if (ret) | |
980 | dev_info(dev, "doesn't support gadget\n"); | |
981 | } | |
5f36e231 AS |
982 | |
983 | if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { | |
984 | dev_err(dev, "no supported roles\n"); | |
74475ede | 985 | ret = -ENODEV; |
c859aa65 | 986 | goto deinit_phy; |
cbec6bd5 PC |
987 | } |
988 | ||
27c62c2d | 989 | if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { |
cbec6bd5 PC |
990 | ret = ci_hdrc_otg_init(ci); |
991 | if (ret) { | |
992 | dev_err(dev, "init otg fails, ret = %d\n", ret); | |
993 | goto stop; | |
994 | } | |
5f36e231 AS |
995 | } |
996 | ||
997 | if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { | |
577b232f | 998 | if (ci->is_otg) { |
577b232f | 999 | ci->role = ci_otg_role(ci); |
0c33bf78 LJ |
1000 | /* Enable ID change irq */ |
1001 | hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); | |
577b232f PC |
1002 | } else { |
1003 | /* | |
1004 | * If the controller is not OTG capable, but support | |
1005 | * role switch, the defalt role is gadget, and the | |
1006 | * user can switch it through debugfs. | |
1007 | */ | |
1008 | ci->role = CI_ROLE_GADGET; | |
1009 | } | |
5f36e231 AS |
1010 | } else { |
1011 | ci->role = ci->roles[CI_ROLE_HOST] | |
1012 | ? CI_ROLE_HOST | |
1013 | : CI_ROLE_GADGET; | |
1014 | } | |
1015 | ||
4dcf720c | 1016 | if (!ci_otg_is_fsm_mode(ci)) { |
961ea496 LJ |
1017 | /* only update vbus status for peripheral */ |
1018 | if (ci->role == CI_ROLE_GADGET) | |
1019 | ci_handle_vbus_change(ci); | |
1020 | ||
4dcf720c LJ |
1021 | ret = ci_role_start(ci, ci->role); |
1022 | if (ret) { | |
1023 | dev_err(dev, "can't start %s role\n", | |
1024 | ci_role(ci)->name); | |
1025 | goto stop; | |
1026 | } | |
e443b333 AS |
1027 | } |
1028 | ||
24c498df | 1029 | platform_set_drvdata(pdev, ci); |
4c503dd5 PC |
1030 | ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, |
1031 | ci->platdata->name, ci); | |
5f36e231 AS |
1032 | if (ret) |
1033 | goto stop; | |
e443b333 | 1034 | |
3ecb3e09 II |
1035 | ret = ci_extcon_register(ci); |
1036 | if (ret) | |
1037 | goto stop; | |
1038 | ||
1f874edc PC |
1039 | if (ci->supports_runtime_pm) { |
1040 | pm_runtime_set_active(&pdev->dev); | |
1041 | pm_runtime_enable(&pdev->dev); | |
1042 | pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); | |
1043 | pm_runtime_mark_last_busy(ci->dev); | |
1044 | pm_runtime_use_autosuspend(&pdev->dev); | |
1045 | } | |
1046 | ||
4dcf720c LJ |
1047 | if (ci_otg_is_fsm_mode(ci)) |
1048 | ci_hdrc_otg_fsm_start(ci); | |
1049 | ||
f8efa766 PC |
1050 | device_set_wakeup_capable(&pdev->dev, true); |
1051 | ||
adf0f735 AS |
1052 | ret = dbg_create_files(ci); |
1053 | if (!ret) | |
1054 | return 0; | |
5f36e231 | 1055 | |
3ecb3e09 | 1056 | ci_extcon_unregister(ci); |
5f36e231 | 1057 | stop: |
3f124d23 | 1058 | ci_role_destroy(ci); |
c859aa65 | 1059 | deinit_phy: |
1e5e2d3d | 1060 | ci_usb_phy_exit(ci); |
e443b333 AS |
1061 | |
1062 | return ret; | |
1063 | } | |
1064 | ||
fb4e98ab | 1065 | static int ci_hdrc_remove(struct platform_device *pdev) |
e443b333 | 1066 | { |
8e22978c | 1067 | struct ci_hdrc *ci = platform_get_drvdata(pdev); |
e443b333 | 1068 | |
1f874edc PC |
1069 | if (ci->supports_runtime_pm) { |
1070 | pm_runtime_get_sync(&pdev->dev); | |
1071 | pm_runtime_disable(&pdev->dev); | |
1072 | pm_runtime_put_noidle(&pdev->dev); | |
1073 | } | |
1074 | ||
adf0f735 | 1075 | dbg_remove_files(ci); |
3ecb3e09 | 1076 | ci_extcon_unregister(ci); |
3f124d23 | 1077 | ci_role_destroy(ci); |
864cf949 | 1078 | ci_hdrc_enter_lpm(ci, true); |
1e5e2d3d | 1079 | ci_usb_phy_exit(ci); |
e443b333 AS |
1080 | |
1081 | return 0; | |
1082 | } | |
1083 | ||
1f874edc | 1084 | #ifdef CONFIG_PM |
961ea496 LJ |
1085 | /* Prepare wakeup by SRP before suspend */ |
1086 | static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) | |
1087 | { | |
1088 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
1089 | !hw_read_otgsc(ci, OTGSC_ID)) { | |
1090 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, | |
1091 | PORTSC_PP); | |
1092 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, | |
1093 | PORTSC_WKCN); | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | /* Handle SRP when wakeup by data pulse */ | |
1098 | static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) | |
1099 | { | |
1100 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
1101 | (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { | |
1102 | if (!hw_read_otgsc(ci, OTGSC_ID)) { | |
1103 | ci->fsm.a_srp_det = 1; | |
1104 | ci->fsm.a_bus_drop = 0; | |
1105 | } else { | |
1106 | ci->fsm.id = 1; | |
1107 | } | |
1108 | ci_otg_queue_work(ci); | |
1109 | } | |
1110 | } | |
1111 | ||
8076932f PC |
1112 | static void ci_controller_suspend(struct ci_hdrc *ci) |
1113 | { | |
1f874edc | 1114 | disable_irq(ci->irq); |
8076932f | 1115 | ci_hdrc_enter_lpm(ci, true); |
1fbf4628 FE |
1116 | if (ci->platdata->phy_clkgate_delay_us) |
1117 | usleep_range(ci->platdata->phy_clkgate_delay_us, | |
1118 | ci->platdata->phy_clkgate_delay_us + 50); | |
1f874edc PC |
1119 | usb_phy_set_suspend(ci->usb_phy, 1); |
1120 | ci->in_lpm = true; | |
1121 | enable_irq(ci->irq); | |
8076932f PC |
1122 | } |
1123 | ||
1124 | static int ci_controller_resume(struct device *dev) | |
1125 | { | |
1126 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
1127 | ||
1128 | dev_dbg(dev, "at %s\n", __func__); | |
1129 | ||
1f874edc PC |
1130 | if (!ci->in_lpm) { |
1131 | WARN_ON(1); | |
1132 | return 0; | |
1133 | } | |
8076932f | 1134 | |
1f874edc | 1135 | ci_hdrc_enter_lpm(ci, false); |
8076932f PC |
1136 | if (ci->usb_phy) { |
1137 | usb_phy_set_suspend(ci->usb_phy, 0); | |
1138 | usb_phy_set_wakeup(ci->usb_phy, false); | |
1139 | hw_wait_phy_stable(); | |
1140 | } | |
1141 | ||
1f874edc PC |
1142 | ci->in_lpm = false; |
1143 | if (ci->wakeup_int) { | |
1144 | ci->wakeup_int = false; | |
1145 | pm_runtime_mark_last_busy(ci->dev); | |
1146 | pm_runtime_put_autosuspend(ci->dev); | |
1147 | enable_irq(ci->irq); | |
961ea496 LJ |
1148 | if (ci_otg_is_fsm_mode(ci)) |
1149 | ci_otg_fsm_wakeup_by_srp(ci); | |
1f874edc PC |
1150 | } |
1151 | ||
8076932f PC |
1152 | return 0; |
1153 | } | |
1154 | ||
1f874edc | 1155 | #ifdef CONFIG_PM_SLEEP |
8076932f PC |
1156 | static int ci_suspend(struct device *dev) |
1157 | { | |
1158 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
1159 | ||
1160 | if (ci->wq) | |
1161 | flush_workqueue(ci->wq); | |
1f874edc PC |
1162 | /* |
1163 | * Controller needs to be active during suspend, otherwise the core | |
1164 | * may run resume when the parent is at suspend if other driver's | |
1165 | * suspend fails, it occurs before parent's suspend has not started, | |
1166 | * but the core suspend has finished. | |
1167 | */ | |
1168 | if (ci->in_lpm) | |
1169 | pm_runtime_resume(dev); | |
1170 | ||
1171 | if (ci->in_lpm) { | |
1172 | WARN_ON(1); | |
1173 | return 0; | |
1174 | } | |
8076932f | 1175 | |
f8efa766 | 1176 | if (device_may_wakeup(dev)) { |
961ea496 LJ |
1177 | if (ci_otg_is_fsm_mode(ci)) |
1178 | ci_otg_fsm_suspend_for_srp(ci); | |
1179 | ||
f8efa766 PC |
1180 | usb_phy_set_wakeup(ci->usb_phy, true); |
1181 | enable_irq_wake(ci->irq); | |
1182 | } | |
1183 | ||
8076932f PC |
1184 | ci_controller_suspend(ci); |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | static int ci_resume(struct device *dev) | |
1190 | { | |
1f874edc PC |
1191 | struct ci_hdrc *ci = dev_get_drvdata(dev); |
1192 | int ret; | |
1193 | ||
f8efa766 PC |
1194 | if (device_may_wakeup(dev)) |
1195 | disable_irq_wake(ci->irq); | |
1196 | ||
1f874edc PC |
1197 | ret = ci_controller_resume(dev); |
1198 | if (ret) | |
1199 | return ret; | |
1200 | ||
1201 | if (ci->supports_runtime_pm) { | |
1202 | pm_runtime_disable(dev); | |
1203 | pm_runtime_set_active(dev); | |
1204 | pm_runtime_enable(dev); | |
1205 | } | |
1206 | ||
1207 | return ret; | |
8076932f PC |
1208 | } |
1209 | #endif /* CONFIG_PM_SLEEP */ | |
1210 | ||
1f874edc PC |
1211 | static int ci_runtime_suspend(struct device *dev) |
1212 | { | |
1213 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
1214 | ||
1215 | dev_dbg(dev, "at %s\n", __func__); | |
1216 | ||
1217 | if (ci->in_lpm) { | |
1218 | WARN_ON(1); | |
1219 | return 0; | |
1220 | } | |
1221 | ||
961ea496 LJ |
1222 | if (ci_otg_is_fsm_mode(ci)) |
1223 | ci_otg_fsm_suspend_for_srp(ci); | |
1224 | ||
1f874edc PC |
1225 | usb_phy_set_wakeup(ci->usb_phy, true); |
1226 | ci_controller_suspend(ci); | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
1231 | static int ci_runtime_resume(struct device *dev) | |
1232 | { | |
1233 | return ci_controller_resume(dev); | |
1234 | } | |
1235 | ||
1236 | #endif /* CONFIG_PM */ | |
8076932f PC |
1237 | static const struct dev_pm_ops ci_pm_ops = { |
1238 | SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) | |
1f874edc | 1239 | SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) |
8076932f | 1240 | }; |
1f874edc | 1241 | |
5f36e231 AS |
1242 | static struct platform_driver ci_hdrc_driver = { |
1243 | .probe = ci_hdrc_probe, | |
7690417d | 1244 | .remove = ci_hdrc_remove, |
e443b333 | 1245 | .driver = { |
5f36e231 | 1246 | .name = "ci_hdrc", |
8076932f | 1247 | .pm = &ci_pm_ops, |
e443b333 AS |
1248 | }, |
1249 | }; | |
1250 | ||
2f01a33b PC |
1251 | static int __init ci_hdrc_platform_register(void) |
1252 | { | |
1253 | ci_hdrc_host_driver_init(); | |
1254 | return platform_driver_register(&ci_hdrc_driver); | |
1255 | } | |
1256 | module_init(ci_hdrc_platform_register); | |
1257 | ||
1258 | static void __exit ci_hdrc_platform_unregister(void) | |
1259 | { | |
1260 | platform_driver_unregister(&ci_hdrc_driver); | |
1261 | } | |
1262 | module_exit(ci_hdrc_platform_unregister); | |
e443b333 | 1263 | |
5f36e231 | 1264 | MODULE_ALIAS("platform:ci_hdrc"); |
e443b333 AS |
1265 | MODULE_LICENSE("GPL v2"); |
1266 | MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); | |
5f36e231 | 1267 | MODULE_DESCRIPTION("ChipIdea HDRC Driver"); |