Commit | Line | Data |
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e443b333 AS |
1 | /* |
2 | * core.c - ChipIdea USB IP core family device controller | |
3 | * | |
4 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. | |
5 | * | |
6 | * Author: David Lopo | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Description: ChipIdea USB IP core family device controller | |
15 | * | |
16 | * This driver is composed of several blocks: | |
17 | * - HW: hardware interface | |
18 | * - DBG: debug facilities (optional) | |
19 | * - UTIL: utilities | |
20 | * - ISR: interrupts handling | |
21 | * - ENDPT: endpoint operations (Gadget API) | |
22 | * - GADGET: gadget operations (Gadget API) | |
23 | * - BUS: bus glue code, bus abstraction layer | |
24 | * | |
25 | * Compile Options | |
58ce8499 | 26 | * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities |
e443b333 AS |
27 | * - STALL_IN: non-empty bulk-in pipes cannot be halted |
28 | * if defined mass storage compliance succeeds but with warnings | |
29 | * => case 4: Hi > Dn | |
30 | * => case 5: Hi > Di | |
31 | * => case 8: Hi <> Do | |
32 | * if undefined usbtest 13 fails | |
33 | * - TRACE: enable function tracing (depends on DEBUG) | |
34 | * | |
35 | * Main Features | |
36 | * - Chapter 9 & Mass Storage Compliance with Gadget File Storage | |
37 | * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) | |
38 | * - Normal & LPM support | |
39 | * | |
40 | * USBTEST Report | |
41 | * - OK: 0-12, 13 (STALL_IN defined) & 14 | |
42 | * - Not Supported: 15 & 16 (ISO) | |
43 | * | |
44 | * TODO List | |
e443b333 AS |
45 | * - Suspend & Remote Wakeup |
46 | */ | |
47 | #include <linux/delay.h> | |
48 | #include <linux/device.h> | |
e443b333 | 49 | #include <linux/dma-mapping.h> |
1e5e2d3d | 50 | #include <linux/phy/phy.h> |
e443b333 AS |
51 | #include <linux/platform_device.h> |
52 | #include <linux/module.h> | |
fe6e125e | 53 | #include <linux/idr.h> |
e443b333 AS |
54 | #include <linux/interrupt.h> |
55 | #include <linux/io.h> | |
e443b333 AS |
56 | #include <linux/kernel.h> |
57 | #include <linux/slab.h> | |
58 | #include <linux/pm_runtime.h> | |
59 | #include <linux/usb/ch9.h> | |
60 | #include <linux/usb/gadget.h> | |
61 | #include <linux/usb/otg.h> | |
62 | #include <linux/usb/chipidea.h> | |
40dcd0e8 | 63 | #include <linux/usb/of.h> |
4f6743d5 | 64 | #include <linux/of.h> |
40dcd0e8 | 65 | #include <linux/phy.h> |
1542d9c3 | 66 | #include <linux/regulator/consumer.h> |
8022d3d5 | 67 | #include <linux/usb/ehci_def.h> |
e443b333 AS |
68 | |
69 | #include "ci.h" | |
70 | #include "udc.h" | |
71 | #include "bits.h" | |
eb70e5ab | 72 | #include "host.h" |
e443b333 | 73 | #include "debug.h" |
c10b4f03 | 74 | #include "otg.h" |
4dcf720c | 75 | #include "otg_fsm.h" |
e443b333 | 76 | |
5f36e231 | 77 | /* Controller register map */ |
987e7bc3 MKB |
78 | static const u8 ci_regs_nolpm[] = { |
79 | [CAP_CAPLENGTH] = 0x00U, | |
80 | [CAP_HCCPARAMS] = 0x08U, | |
81 | [CAP_DCCPARAMS] = 0x24U, | |
82 | [CAP_TESTMODE] = 0x38U, | |
83 | [OP_USBCMD] = 0x00U, | |
84 | [OP_USBSTS] = 0x04U, | |
85 | [OP_USBINTR] = 0x08U, | |
86 | [OP_DEVICEADDR] = 0x14U, | |
87 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 88 | [OP_TTCTRL] = 0x1CU, |
987e7bc3 MKB |
89 | [OP_PORTSC] = 0x44U, |
90 | [OP_DEVLC] = 0x84U, | |
91 | [OP_OTGSC] = 0x64U, | |
92 | [OP_USBMODE] = 0x68U, | |
93 | [OP_ENDPTSETUPSTAT] = 0x6CU, | |
94 | [OP_ENDPTPRIME] = 0x70U, | |
95 | [OP_ENDPTFLUSH] = 0x74U, | |
96 | [OP_ENDPTSTAT] = 0x78U, | |
97 | [OP_ENDPTCOMPLETE] = 0x7CU, | |
98 | [OP_ENDPTCTRL] = 0x80U, | |
e443b333 AS |
99 | }; |
100 | ||
987e7bc3 MKB |
101 | static const u8 ci_regs_lpm[] = { |
102 | [CAP_CAPLENGTH] = 0x00U, | |
103 | [CAP_HCCPARAMS] = 0x08U, | |
104 | [CAP_DCCPARAMS] = 0x24U, | |
105 | [CAP_TESTMODE] = 0xFCU, | |
106 | [OP_USBCMD] = 0x00U, | |
107 | [OP_USBSTS] = 0x04U, | |
108 | [OP_USBINTR] = 0x08U, | |
109 | [OP_DEVICEADDR] = 0x14U, | |
110 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 111 | [OP_TTCTRL] = 0x1CU, |
987e7bc3 MKB |
112 | [OP_PORTSC] = 0x44U, |
113 | [OP_DEVLC] = 0x84U, | |
114 | [OP_OTGSC] = 0xC4U, | |
115 | [OP_USBMODE] = 0xC8U, | |
116 | [OP_ENDPTSETUPSTAT] = 0xD8U, | |
117 | [OP_ENDPTPRIME] = 0xDCU, | |
118 | [OP_ENDPTFLUSH] = 0xE0U, | |
119 | [OP_ENDPTSTAT] = 0xE4U, | |
120 | [OP_ENDPTCOMPLETE] = 0xE8U, | |
121 | [OP_ENDPTCTRL] = 0xECU, | |
e443b333 AS |
122 | }; |
123 | ||
158ec071 | 124 | static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) |
e443b333 AS |
125 | { |
126 | int i; | |
127 | ||
e443b333 | 128 | for (i = 0; i < OP_ENDPTCTRL; i++) |
5f36e231 AS |
129 | ci->hw_bank.regmap[i] = |
130 | (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + | |
e443b333 AS |
131 | (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); |
132 | ||
133 | for (; i <= OP_LAST; i++) | |
5f36e231 | 134 | ci->hw_bank.regmap[i] = ci->hw_bank.op + |
e443b333 AS |
135 | 4 * (i - OP_ENDPTCTRL) + |
136 | (is_lpm | |
137 | ? ci_regs_lpm[OP_ENDPTCTRL] | |
138 | : ci_regs_nolpm[OP_ENDPTCTRL]); | |
139 | ||
e443b333 AS |
140 | } |
141 | ||
cb271f3c PC |
142 | static enum ci_revision ci_get_revision(struct ci_hdrc *ci) |
143 | { | |
144 | int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); | |
145 | enum ci_revision rev = CI_REVISION_UNKNOWN; | |
146 | ||
147 | if (ver == 0x2) { | |
148 | rev = hw_read_id_reg(ci, ID_ID, REVISION) | |
149 | >> __ffs(REVISION); | |
150 | rev += CI_REVISION_20; | |
151 | } else if (ver == 0x0) { | |
152 | rev = CI_REVISION_1X; | |
153 | } | |
154 | ||
155 | return rev; | |
156 | } | |
157 | ||
36304b06 LJ |
158 | /** |
159 | * hw_read_intr_enable: returns interrupt enable register | |
160 | * | |
19353881 PC |
161 | * @ci: the controller |
162 | * | |
36304b06 LJ |
163 | * This function returns register data |
164 | */ | |
165 | u32 hw_read_intr_enable(struct ci_hdrc *ci) | |
166 | { | |
167 | return hw_read(ci, OP_USBINTR, ~0); | |
168 | } | |
169 | ||
170 | /** | |
171 | * hw_read_intr_status: returns interrupt status register | |
172 | * | |
19353881 PC |
173 | * @ci: the controller |
174 | * | |
36304b06 LJ |
175 | * This function returns register data |
176 | */ | |
177 | u32 hw_read_intr_status(struct ci_hdrc *ci) | |
178 | { | |
179 | return hw_read(ci, OP_USBSTS, ~0); | |
180 | } | |
181 | ||
e443b333 AS |
182 | /** |
183 | * hw_port_test_set: writes port test mode (execute without interruption) | |
184 | * @mode: new value | |
185 | * | |
186 | * This function returns an error code | |
187 | */ | |
8e22978c | 188 | int hw_port_test_set(struct ci_hdrc *ci, u8 mode) |
e443b333 AS |
189 | { |
190 | const u8 TEST_MODE_MAX = 7; | |
191 | ||
192 | if (mode > TEST_MODE_MAX) | |
193 | return -EINVAL; | |
194 | ||
727b4ddb | 195 | hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); |
e443b333 AS |
196 | return 0; |
197 | } | |
198 | ||
199 | /** | |
200 | * hw_port_test_get: reads port test mode value | |
201 | * | |
19353881 PC |
202 | * @ci: the controller |
203 | * | |
e443b333 AS |
204 | * This function returns port test mode value |
205 | */ | |
8e22978c | 206 | u8 hw_port_test_get(struct ci_hdrc *ci) |
e443b333 | 207 | { |
727b4ddb | 208 | return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); |
e443b333 AS |
209 | } |
210 | ||
b82613cf PC |
211 | static void hw_wait_phy_stable(void) |
212 | { | |
213 | /* | |
214 | * The phy needs some delay to output the stable status from low | |
215 | * power mode. And for OTGSC, the status inputs are debounced | |
216 | * using a 1 ms time constant, so, delay 2ms for controller to get | |
217 | * the stable status, like vbus and id when the phy leaves low power. | |
218 | */ | |
219 | usleep_range(2000, 2500); | |
220 | } | |
221 | ||
864cf949 PC |
222 | /* The PHY enters/leaves low power mode */ |
223 | static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) | |
224 | { | |
225 | enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; | |
226 | bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); | |
227 | ||
6d037db6 | 228 | if (enable && !lpm) |
864cf949 PC |
229 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
230 | PORTSC_PHCD(ci->hw_bank.lpm)); | |
6d037db6 | 231 | else if (!enable && lpm) |
864cf949 PC |
232 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
233 | 0); | |
864cf949 PC |
234 | } |
235 | ||
8e22978c | 236 | static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) |
e443b333 AS |
237 | { |
238 | u32 reg; | |
239 | ||
240 | /* bank is a module variable */ | |
5f36e231 | 241 | ci->hw_bank.abs = base; |
e443b333 | 242 | |
5f36e231 | 243 | ci->hw_bank.cap = ci->hw_bank.abs; |
77c4400f | 244 | ci->hw_bank.cap += ci->platdata->capoffset; |
938d323f | 245 | ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); |
e443b333 | 246 | |
5f36e231 AS |
247 | hw_alloc_regmap(ci, false); |
248 | reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> | |
727b4ddb | 249 | __ffs(HCCPARAMS_LEN); |
5f36e231 | 250 | ci->hw_bank.lpm = reg; |
aeb2c121 CR |
251 | if (reg) |
252 | hw_alloc_regmap(ci, !!reg); | |
5f36e231 AS |
253 | ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; |
254 | ci->hw_bank.size += OP_LAST; | |
255 | ci->hw_bank.size /= sizeof(u32); | |
e443b333 | 256 | |
5f36e231 | 257 | reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> |
727b4ddb | 258 | __ffs(DCCPARAMS_DEN); |
5f36e231 | 259 | ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ |
e443b333 | 260 | |
09c94e62 | 261 | if (ci->hw_ep_max > ENDPT_MAX) |
e443b333 AS |
262 | return -ENODEV; |
263 | ||
864cf949 PC |
264 | ci_hdrc_enter_lpm(ci, false); |
265 | ||
c344b518 PC |
266 | /* Disable all interrupts bits */ |
267 | hw_write(ci, OP_USBINTR, 0xffffffff, 0); | |
268 | ||
269 | /* Clear all interrupts status bits*/ | |
270 | hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); | |
271 | ||
cb271f3c PC |
272 | ci->rev = ci_get_revision(ci); |
273 | ||
274 | dev_dbg(ci->dev, | |
275 | "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n", | |
276 | ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); | |
e443b333 AS |
277 | |
278 | /* setup lock mode ? */ | |
279 | ||
280 | /* ENDPTSETUPSTAT is '0' by default */ | |
281 | ||
282 | /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
8e22978c | 287 | static void hw_phymode_configure(struct ci_hdrc *ci) |
40dcd0e8 | 288 | { |
3b5d3e68 | 289 | u32 portsc, lpm, sts = 0; |
40dcd0e8 MG |
290 | |
291 | switch (ci->platdata->phy_mode) { | |
292 | case USBPHY_INTERFACE_MODE_UTMI: | |
293 | portsc = PORTSC_PTS(PTS_UTMI); | |
294 | lpm = DEVLC_PTS(PTS_UTMI); | |
295 | break; | |
296 | case USBPHY_INTERFACE_MODE_UTMIW: | |
297 | portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; | |
298 | lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; | |
299 | break; | |
300 | case USBPHY_INTERFACE_MODE_ULPI: | |
301 | portsc = PORTSC_PTS(PTS_ULPI); | |
302 | lpm = DEVLC_PTS(PTS_ULPI); | |
303 | break; | |
304 | case USBPHY_INTERFACE_MODE_SERIAL: | |
305 | portsc = PORTSC_PTS(PTS_SERIAL); | |
306 | lpm = DEVLC_PTS(PTS_SERIAL); | |
307 | sts = 1; | |
308 | break; | |
309 | case USBPHY_INTERFACE_MODE_HSIC: | |
310 | portsc = PORTSC_PTS(PTS_HSIC); | |
311 | lpm = DEVLC_PTS(PTS_HSIC); | |
312 | break; | |
313 | default: | |
314 | return; | |
315 | } | |
316 | ||
317 | if (ci->hw_bank.lpm) { | |
318 | hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); | |
3b5d3e68 CR |
319 | if (sts) |
320 | hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); | |
40dcd0e8 MG |
321 | } else { |
322 | hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); | |
3b5d3e68 CR |
323 | if (sts) |
324 | hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); | |
40dcd0e8 MG |
325 | } |
326 | } | |
327 | ||
1e5e2d3d AT |
328 | /** |
329 | * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy | |
330 | * interfaces | |
331 | * @ci: the controller | |
332 | * | |
333 | * This function returns an error code if the phy failed to init | |
334 | */ | |
335 | static int _ci_usb_phy_init(struct ci_hdrc *ci) | |
336 | { | |
337 | int ret; | |
338 | ||
339 | if (ci->phy) { | |
340 | ret = phy_init(ci->phy); | |
341 | if (ret) | |
342 | return ret; | |
343 | ||
344 | ret = phy_power_on(ci->phy); | |
345 | if (ret) { | |
346 | phy_exit(ci->phy); | |
347 | return ret; | |
348 | } | |
349 | } else { | |
350 | ret = usb_phy_init(ci->usb_phy); | |
351 | } | |
352 | ||
353 | return ret; | |
354 | } | |
355 | ||
356 | /** | |
357 | * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy | |
358 | * interfaces | |
359 | * @ci: the controller | |
360 | */ | |
361 | static void ci_usb_phy_exit(struct ci_hdrc *ci) | |
362 | { | |
363 | if (ci->phy) { | |
364 | phy_power_off(ci->phy); | |
365 | phy_exit(ci->phy); | |
366 | } else { | |
367 | usb_phy_shutdown(ci->usb_phy); | |
368 | } | |
369 | } | |
370 | ||
d03cccff PC |
371 | /** |
372 | * ci_usb_phy_init: initialize phy according to different phy type | |
373 | * @ci: the controller | |
19353881 | 374 | * |
d03cccff PC |
375 | * This function returns an error code if usb_phy_init has failed |
376 | */ | |
377 | static int ci_usb_phy_init(struct ci_hdrc *ci) | |
378 | { | |
379 | int ret; | |
380 | ||
381 | switch (ci->platdata->phy_mode) { | |
382 | case USBPHY_INTERFACE_MODE_UTMI: | |
383 | case USBPHY_INTERFACE_MODE_UTMIW: | |
384 | case USBPHY_INTERFACE_MODE_HSIC: | |
1e5e2d3d | 385 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
386 | if (!ret) |
387 | hw_wait_phy_stable(); | |
388 | else | |
d03cccff PC |
389 | return ret; |
390 | hw_phymode_configure(ci); | |
391 | break; | |
392 | case USBPHY_INTERFACE_MODE_ULPI: | |
393 | case USBPHY_INTERFACE_MODE_SERIAL: | |
394 | hw_phymode_configure(ci); | |
1e5e2d3d | 395 | ret = _ci_usb_phy_init(ci); |
d03cccff PC |
396 | if (ret) |
397 | return ret; | |
398 | break; | |
399 | default: | |
1e5e2d3d | 400 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
401 | if (!ret) |
402 | hw_wait_phy_stable(); | |
d03cccff PC |
403 | } |
404 | ||
405 | return ret; | |
406 | } | |
407 | ||
bf9c85e7 PC |
408 | |
409 | /** | |
410 | * ci_platform_configure: do controller configure | |
411 | * @ci: the controller | |
412 | * | |
413 | */ | |
414 | void ci_platform_configure(struct ci_hdrc *ci) | |
415 | { | |
8022d3d5 PC |
416 | bool is_device_mode, is_host_mode; |
417 | ||
418 | is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; | |
419 | is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; | |
420 | ||
421 | if (is_device_mode && | |
422 | (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)) | |
423 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); | |
424 | ||
425 | if (is_host_mode && | |
426 | (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)) | |
bf9c85e7 PC |
427 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); |
428 | ||
429 | if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { | |
430 | if (ci->hw_bank.lpm) | |
431 | hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); | |
432 | else | |
433 | hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); | |
434 | } | |
435 | ||
436 | if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) | |
437 | hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); | |
df96ed8d PC |
438 | |
439 | hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); | |
440 | ||
65668718 PC |
441 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) |
442 | hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, | |
443 | ci->platdata->ahb_burst_config); | |
bf9c85e7 PC |
444 | } |
445 | ||
e443b333 | 446 | /** |
cdd278f2 | 447 | * hw_controller_reset: do controller reset |
e443b333 AS |
448 | * @ci: the controller |
449 | * | |
450 | * This function returns an error code | |
451 | */ | |
cdd278f2 PC |
452 | static int hw_controller_reset(struct ci_hdrc *ci) |
453 | { | |
454 | int count = 0; | |
455 | ||
456 | hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); | |
457 | while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { | |
458 | udelay(10); | |
459 | if (count++ > 1000) | |
460 | return -ETIMEDOUT; | |
461 | } | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | /** | |
467 | * hw_device_reset: resets chip (execute without interruption) | |
468 | * @ci: the controller | |
469 | * | |
470 | * This function returns an error code | |
471 | */ | |
5b157300 | 472 | int hw_device_reset(struct ci_hdrc *ci) |
e443b333 | 473 | { |
cdd278f2 PC |
474 | int ret; |
475 | ||
e443b333 AS |
476 | /* should flush & stop before reset */ |
477 | hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); | |
478 | hw_write(ci, OP_USBCMD, USBCMD_RS, 0); | |
479 | ||
cdd278f2 PC |
480 | ret = hw_controller_reset(ci); |
481 | if (ret) { | |
482 | dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); | |
483 | return ret; | |
484 | } | |
e443b333 | 485 | |
77c4400f RZ |
486 | if (ci->platdata->notify_event) |
487 | ci->platdata->notify_event(ci, | |
8e22978c | 488 | CI_HDRC_CONTROLLER_RESET_EVENT); |
e443b333 | 489 | |
e443b333 AS |
490 | /* USBMODE should be configured step by step */ |
491 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); | |
5b157300 | 492 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); |
e443b333 AS |
493 | /* HW >= 2.3 */ |
494 | hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); | |
495 | ||
5b157300 PC |
496 | if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { |
497 | pr_err("cannot enter in %s device mode", ci_role(ci)->name); | |
e443b333 AS |
498 | pr_err("lpm = %i", ci->hw_bank.lpm); |
499 | return -ENODEV; | |
500 | } | |
501 | ||
bf9c85e7 PC |
502 | ci_platform_configure(ci); |
503 | ||
e443b333 AS |
504 | return 0; |
505 | } | |
506 | ||
22fa8445 PC |
507 | /** |
508 | * hw_wait_reg: wait the register value | |
509 | * | |
510 | * Sometimes, it needs to wait register value before going on. | |
511 | * Eg, when switch to device mode, the vbus value should be lower | |
512 | * than OTGSC_BSV before connects to host. | |
513 | * | |
514 | * @ci: the controller | |
515 | * @reg: register index | |
516 | * @mask: mast bit | |
517 | * @value: the bit value to wait | |
518 | * @timeout_ms: timeout in millisecond | |
519 | * | |
520 | * This function returns an error code if timeout | |
521 | */ | |
522 | int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, | |
523 | u32 value, unsigned int timeout_ms) | |
524 | { | |
525 | unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); | |
526 | ||
527 | while (hw_read(ci, reg, mask) != value) { | |
528 | if (time_after(jiffies, elapse)) { | |
529 | dev_err(ci->dev, "timeout waiting for %08x in %d\n", | |
530 | mask, reg); | |
531 | return -ETIMEDOUT; | |
532 | } | |
533 | msleep(20); | |
534 | } | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
5f36e231 AS |
539 | static irqreturn_t ci_irq(int irq, void *data) |
540 | { | |
8e22978c | 541 | struct ci_hdrc *ci = data; |
5f36e231 | 542 | irqreturn_t ret = IRQ_NONE; |
b183c19f | 543 | u32 otgsc = 0; |
5f36e231 | 544 | |
1f874edc PC |
545 | if (ci->in_lpm) { |
546 | disable_irq_nosync(irq); | |
547 | ci->wakeup_int = true; | |
548 | pm_runtime_get(ci->dev); | |
549 | return IRQ_HANDLED; | |
550 | } | |
551 | ||
4dcf720c | 552 | if (ci->is_otg) { |
0c33bf78 | 553 | otgsc = hw_read_otgsc(ci, ~0); |
4dcf720c LJ |
554 | if (ci_otg_is_fsm_mode(ci)) { |
555 | ret = ci_otg_fsm_irq(ci); | |
556 | if (ret == IRQ_HANDLED) | |
557 | return ret; | |
558 | } | |
559 | } | |
5f36e231 | 560 | |
a107f8c5 PC |
561 | /* |
562 | * Handle id change interrupt, it indicates device/host function | |
563 | * switch. | |
564 | */ | |
565 | if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { | |
566 | ci->id_event = true; | |
0c33bf78 LJ |
567 | /* Clear ID change irq status */ |
568 | hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); | |
be6b0c1b | 569 | ci_otg_queue_work(ci); |
a107f8c5 PC |
570 | return IRQ_HANDLED; |
571 | } | |
b183c19f | 572 | |
a107f8c5 PC |
573 | /* |
574 | * Handle vbus change interrupt, it indicates device connection | |
575 | * and disconnection events. | |
576 | */ | |
577 | if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { | |
578 | ci->b_sess_valid_event = true; | |
0c33bf78 LJ |
579 | /* Clear BSV irq */ |
580 | hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); | |
be6b0c1b | 581 | ci_otg_queue_work(ci); |
a107f8c5 | 582 | return IRQ_HANDLED; |
5f36e231 AS |
583 | } |
584 | ||
a107f8c5 PC |
585 | /* Handle device/host interrupt */ |
586 | if (ci->role != CI_ROLE_END) | |
587 | ret = ci_role(ci)->irq(ci); | |
588 | ||
b183c19f | 589 | return ret; |
5f36e231 AS |
590 | } |
591 | ||
1542d9c3 PC |
592 | static int ci_get_platdata(struct device *dev, |
593 | struct ci_hdrc_platform_data *platdata) | |
594 | { | |
df96ed8d PC |
595 | int ret; |
596 | ||
c22600c3 PC |
597 | if (!platdata->phy_mode) |
598 | platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); | |
599 | ||
600 | if (!platdata->dr_mode) | |
601 | platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); | |
602 | ||
603 | if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) | |
604 | platdata->dr_mode = USB_DR_MODE_OTG; | |
605 | ||
c2ec3a73 PC |
606 | if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { |
607 | /* Get the vbus regulator */ | |
608 | platdata->reg_vbus = devm_regulator_get(dev, "vbus"); | |
609 | if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { | |
610 | return -EPROBE_DEFER; | |
611 | } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { | |
6629467b | 612 | /* no vbus regulator is needed */ |
c2ec3a73 PC |
613 | platdata->reg_vbus = NULL; |
614 | } else if (IS_ERR(platdata->reg_vbus)) { | |
615 | dev_err(dev, "Getting regulator error: %ld\n", | |
616 | PTR_ERR(platdata->reg_vbus)); | |
617 | return PTR_ERR(platdata->reg_vbus); | |
618 | } | |
f6a9ff07 PC |
619 | /* Get TPL support */ |
620 | if (!platdata->tpl_support) | |
621 | platdata->tpl_support = | |
622 | of_usb_host_tpl_support(dev->of_node); | |
c2ec3a73 PC |
623 | } |
624 | ||
4f6743d5 MG |
625 | if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL) |
626 | platdata->flags |= CI_HDRC_FORCE_FULLSPEED; | |
627 | ||
df96ed8d PC |
628 | platdata->itc_setting = 1; |
629 | if (of_find_property(dev->of_node, "itc-setting", NULL)) { | |
630 | ret = of_property_read_u32(dev->of_node, "itc-setting", | |
631 | &platdata->itc_setting); | |
632 | if (ret) { | |
633 | dev_err(dev, | |
634 | "failed to get itc-setting\n"); | |
635 | return ret; | |
636 | } | |
637 | } | |
638 | ||
65668718 PC |
639 | if (of_find_property(dev->of_node, "ahb-burst-config", NULL)) { |
640 | ret = of_property_read_u32(dev->of_node, "ahb-burst-config", | |
641 | &platdata->ahb_burst_config); | |
642 | if (ret) { | |
643 | dev_err(dev, | |
644 | "failed to get ahb-burst-config\n"); | |
645 | return ret; | |
646 | } | |
647 | platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; | |
648 | } | |
649 | ||
1542d9c3 PC |
650 | return 0; |
651 | } | |
652 | ||
fe6e125e RZ |
653 | static DEFINE_IDA(ci_ida); |
654 | ||
8e22978c | 655 | struct platform_device *ci_hdrc_add_device(struct device *dev, |
cbc6dc2a | 656 | struct resource *res, int nres, |
8e22978c | 657 | struct ci_hdrc_platform_data *platdata) |
cbc6dc2a RZ |
658 | { |
659 | struct platform_device *pdev; | |
fe6e125e | 660 | int id, ret; |
cbc6dc2a | 661 | |
1542d9c3 PC |
662 | ret = ci_get_platdata(dev, platdata); |
663 | if (ret) | |
664 | return ERR_PTR(ret); | |
665 | ||
fe6e125e RZ |
666 | id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); |
667 | if (id < 0) | |
668 | return ERR_PTR(id); | |
669 | ||
670 | pdev = platform_device_alloc("ci_hdrc", id); | |
671 | if (!pdev) { | |
672 | ret = -ENOMEM; | |
673 | goto put_id; | |
674 | } | |
cbc6dc2a RZ |
675 | |
676 | pdev->dev.parent = dev; | |
677 | pdev->dev.dma_mask = dev->dma_mask; | |
678 | pdev->dev.dma_parms = dev->dma_parms; | |
679 | dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); | |
680 | ||
681 | ret = platform_device_add_resources(pdev, res, nres); | |
682 | if (ret) | |
683 | goto err; | |
684 | ||
685 | ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); | |
686 | if (ret) | |
687 | goto err; | |
688 | ||
689 | ret = platform_device_add(pdev); | |
690 | if (ret) | |
691 | goto err; | |
692 | ||
693 | return pdev; | |
694 | ||
695 | err: | |
696 | platform_device_put(pdev); | |
fe6e125e RZ |
697 | put_id: |
698 | ida_simple_remove(&ci_ida, id); | |
cbc6dc2a RZ |
699 | return ERR_PTR(ret); |
700 | } | |
8e22978c | 701 | EXPORT_SYMBOL_GPL(ci_hdrc_add_device); |
cbc6dc2a | 702 | |
8e22978c | 703 | void ci_hdrc_remove_device(struct platform_device *pdev) |
cbc6dc2a | 704 | { |
98c35534 | 705 | int id = pdev->id; |
cbc6dc2a | 706 | platform_device_unregister(pdev); |
98c35534 | 707 | ida_simple_remove(&ci_ida, id); |
cbc6dc2a | 708 | } |
8e22978c | 709 | EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); |
cbc6dc2a | 710 | |
3f124d23 PC |
711 | static inline void ci_role_destroy(struct ci_hdrc *ci) |
712 | { | |
713 | ci_hdrc_gadget_destroy(ci); | |
714 | ci_hdrc_host_destroy(ci); | |
cbec6bd5 PC |
715 | if (ci->is_otg) |
716 | ci_hdrc_otg_destroy(ci); | |
3f124d23 PC |
717 | } |
718 | ||
577b232f PC |
719 | static void ci_get_otg_capable(struct ci_hdrc *ci) |
720 | { | |
721 | if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) | |
722 | ci->is_otg = false; | |
723 | else | |
724 | ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, | |
725 | DCCPARAMS_DC | DCCPARAMS_HC) | |
726 | == (DCCPARAMS_DC | DCCPARAMS_HC)); | |
2e37cfd8 | 727 | if (ci->is_otg) { |
577b232f | 728 | dev_dbg(ci->dev, "It is OTG capable controller\n"); |
2e37cfd8 PC |
729 | /* Disable and clear all OTG irq */ |
730 | hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, | |
731 | OTGSC_INT_STATUS_BITS); | |
732 | } | |
577b232f PC |
733 | } |
734 | ||
41ac7b3a | 735 | static int ci_hdrc_probe(struct platform_device *pdev) |
e443b333 AS |
736 | { |
737 | struct device *dev = &pdev->dev; | |
8e22978c | 738 | struct ci_hdrc *ci; |
e443b333 AS |
739 | struct resource *res; |
740 | void __iomem *base; | |
741 | int ret; | |
691962d1 | 742 | enum usb_dr_mode dr_mode; |
e443b333 | 743 | |
fad56745 | 744 | if (!dev_get_platdata(dev)) { |
e443b333 AS |
745 | dev_err(dev, "platform data missing\n"); |
746 | return -ENODEV; | |
747 | } | |
748 | ||
749 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
19290816 FB |
750 | base = devm_ioremap_resource(dev, res); |
751 | if (IS_ERR(base)) | |
752 | return PTR_ERR(base); | |
e443b333 | 753 | |
5f36e231 | 754 | ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); |
d0f99249 | 755 | if (!ci) |
5f36e231 | 756 | return -ENOMEM; |
5f36e231 AS |
757 | |
758 | ci->dev = dev; | |
fad56745 | 759 | ci->platdata = dev_get_platdata(dev); |
ed8f8318 PC |
760 | ci->imx28_write_fix = !!(ci->platdata->flags & |
761 | CI_HDRC_IMX28_WRITE_FIX); | |
1f874edc PC |
762 | ci->supports_runtime_pm = !!(ci->platdata->flags & |
763 | CI_HDRC_SUPPORTS_RUNTIME_PM); | |
5f36e231 AS |
764 | |
765 | ret = hw_device_init(ci, base); | |
766 | if (ret < 0) { | |
767 | dev_err(dev, "can't initialize hardware\n"); | |
768 | return -ENODEV; | |
769 | } | |
e443b333 | 770 | |
1e5e2d3d AT |
771 | if (ci->platdata->phy) { |
772 | ci->phy = ci->platdata->phy; | |
773 | } else if (ci->platdata->usb_phy) { | |
ef44cb42 | 774 | ci->usb_phy = ci->platdata->usb_phy; |
1e5e2d3d | 775 | } else { |
21a5b579 AT |
776 | ci->phy = devm_phy_get(dev->parent, "usb-phy"); |
777 | ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); | |
c859aa65 | 778 | |
1e5e2d3d AT |
779 | /* if both generic PHY and USB PHY layers aren't enabled */ |
780 | if (PTR_ERR(ci->phy) == -ENOSYS && | |
781 | PTR_ERR(ci->usb_phy) == -ENXIO) | |
782 | return -ENXIO; | |
783 | ||
784 | if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) | |
785 | return -EPROBE_DEFER; | |
c859aa65 | 786 | |
1e5e2d3d AT |
787 | if (IS_ERR(ci->phy)) |
788 | ci->phy = NULL; | |
789 | else if (IS_ERR(ci->usb_phy)) | |
790 | ci->usb_phy = NULL; | |
c859aa65 PC |
791 | } |
792 | ||
d03cccff | 793 | ret = ci_usb_phy_init(ci); |
74475ede PC |
794 | if (ret) { |
795 | dev_err(dev, "unable to init phy: %d\n", ret); | |
796 | return ret; | |
797 | } | |
798 | ||
eb70e5ab AS |
799 | ci->hw_bank.phys = res->start; |
800 | ||
5f36e231 AS |
801 | ci->irq = platform_get_irq(pdev, 0); |
802 | if (ci->irq < 0) { | |
e443b333 | 803 | dev_err(dev, "missing IRQ\n"); |
42d18212 | 804 | ret = ci->irq; |
c859aa65 | 805 | goto deinit_phy; |
5f36e231 AS |
806 | } |
807 | ||
577b232f PC |
808 | ci_get_otg_capable(ci); |
809 | ||
691962d1 | 810 | dr_mode = ci->platdata->dr_mode; |
5f36e231 | 811 | /* initialize role(s) before the interrupt is requested */ |
691962d1 SH |
812 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { |
813 | ret = ci_hdrc_host_init(ci); | |
814 | if (ret) | |
815 | dev_info(dev, "doesn't support host\n"); | |
816 | } | |
eb70e5ab | 817 | |
691962d1 SH |
818 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { |
819 | ret = ci_hdrc_gadget_init(ci); | |
820 | if (ret) | |
821 | dev_info(dev, "doesn't support gadget\n"); | |
822 | } | |
5f36e231 AS |
823 | |
824 | if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { | |
825 | dev_err(dev, "no supported roles\n"); | |
74475ede | 826 | ret = -ENODEV; |
c859aa65 | 827 | goto deinit_phy; |
cbec6bd5 PC |
828 | } |
829 | ||
27c62c2d | 830 | if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { |
cbec6bd5 PC |
831 | ret = ci_hdrc_otg_init(ci); |
832 | if (ret) { | |
833 | dev_err(dev, "init otg fails, ret = %d\n", ret); | |
834 | goto stop; | |
835 | } | |
5f36e231 AS |
836 | } |
837 | ||
838 | if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { | |
577b232f | 839 | if (ci->is_otg) { |
577b232f | 840 | ci->role = ci_otg_role(ci); |
0c33bf78 LJ |
841 | /* Enable ID change irq */ |
842 | hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); | |
577b232f PC |
843 | } else { |
844 | /* | |
845 | * If the controller is not OTG capable, but support | |
846 | * role switch, the defalt role is gadget, and the | |
847 | * user can switch it through debugfs. | |
848 | */ | |
849 | ci->role = CI_ROLE_GADGET; | |
850 | } | |
5f36e231 AS |
851 | } else { |
852 | ci->role = ci->roles[CI_ROLE_HOST] | |
853 | ? CI_ROLE_HOST | |
854 | : CI_ROLE_GADGET; | |
855 | } | |
856 | ||
4dcf720c | 857 | if (!ci_otg_is_fsm_mode(ci)) { |
961ea496 LJ |
858 | /* only update vbus status for peripheral */ |
859 | if (ci->role == CI_ROLE_GADGET) | |
860 | ci_handle_vbus_change(ci); | |
861 | ||
4dcf720c LJ |
862 | ret = ci_role_start(ci, ci->role); |
863 | if (ret) { | |
864 | dev_err(dev, "can't start %s role\n", | |
865 | ci_role(ci)->name); | |
866 | goto stop; | |
867 | } | |
e443b333 AS |
868 | } |
869 | ||
24c498df | 870 | platform_set_drvdata(pdev, ci); |
4c503dd5 PC |
871 | ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, |
872 | ci->platdata->name, ci); | |
5f36e231 AS |
873 | if (ret) |
874 | goto stop; | |
e443b333 | 875 | |
1f874edc PC |
876 | if (ci->supports_runtime_pm) { |
877 | pm_runtime_set_active(&pdev->dev); | |
878 | pm_runtime_enable(&pdev->dev); | |
879 | pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); | |
880 | pm_runtime_mark_last_busy(ci->dev); | |
881 | pm_runtime_use_autosuspend(&pdev->dev); | |
882 | } | |
883 | ||
4dcf720c LJ |
884 | if (ci_otg_is_fsm_mode(ci)) |
885 | ci_hdrc_otg_fsm_start(ci); | |
886 | ||
f8efa766 PC |
887 | device_set_wakeup_capable(&pdev->dev, true); |
888 | ||
adf0f735 AS |
889 | ret = dbg_create_files(ci); |
890 | if (!ret) | |
891 | return 0; | |
5f36e231 | 892 | |
5f36e231 | 893 | stop: |
3f124d23 | 894 | ci_role_destroy(ci); |
c859aa65 | 895 | deinit_phy: |
1e5e2d3d | 896 | ci_usb_phy_exit(ci); |
e443b333 AS |
897 | |
898 | return ret; | |
899 | } | |
900 | ||
fb4e98ab | 901 | static int ci_hdrc_remove(struct platform_device *pdev) |
e443b333 | 902 | { |
8e22978c | 903 | struct ci_hdrc *ci = platform_get_drvdata(pdev); |
e443b333 | 904 | |
1f874edc PC |
905 | if (ci->supports_runtime_pm) { |
906 | pm_runtime_get_sync(&pdev->dev); | |
907 | pm_runtime_disable(&pdev->dev); | |
908 | pm_runtime_put_noidle(&pdev->dev); | |
909 | } | |
910 | ||
adf0f735 | 911 | dbg_remove_files(ci); |
3f124d23 | 912 | ci_role_destroy(ci); |
864cf949 | 913 | ci_hdrc_enter_lpm(ci, true); |
1e5e2d3d | 914 | ci_usb_phy_exit(ci); |
e443b333 AS |
915 | |
916 | return 0; | |
917 | } | |
918 | ||
1f874edc | 919 | #ifdef CONFIG_PM |
961ea496 LJ |
920 | /* Prepare wakeup by SRP before suspend */ |
921 | static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) | |
922 | { | |
923 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
924 | !hw_read_otgsc(ci, OTGSC_ID)) { | |
925 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, | |
926 | PORTSC_PP); | |
927 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, | |
928 | PORTSC_WKCN); | |
929 | } | |
930 | } | |
931 | ||
932 | /* Handle SRP when wakeup by data pulse */ | |
933 | static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) | |
934 | { | |
935 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
936 | (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { | |
937 | if (!hw_read_otgsc(ci, OTGSC_ID)) { | |
938 | ci->fsm.a_srp_det = 1; | |
939 | ci->fsm.a_bus_drop = 0; | |
940 | } else { | |
941 | ci->fsm.id = 1; | |
942 | } | |
943 | ci_otg_queue_work(ci); | |
944 | } | |
945 | } | |
946 | ||
8076932f PC |
947 | static void ci_controller_suspend(struct ci_hdrc *ci) |
948 | { | |
1f874edc | 949 | disable_irq(ci->irq); |
8076932f | 950 | ci_hdrc_enter_lpm(ci, true); |
1f874edc PC |
951 | usb_phy_set_suspend(ci->usb_phy, 1); |
952 | ci->in_lpm = true; | |
953 | enable_irq(ci->irq); | |
8076932f PC |
954 | } |
955 | ||
956 | static int ci_controller_resume(struct device *dev) | |
957 | { | |
958 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
959 | ||
960 | dev_dbg(dev, "at %s\n", __func__); | |
961 | ||
1f874edc PC |
962 | if (!ci->in_lpm) { |
963 | WARN_ON(1); | |
964 | return 0; | |
965 | } | |
8076932f | 966 | |
1f874edc | 967 | ci_hdrc_enter_lpm(ci, false); |
8076932f PC |
968 | if (ci->usb_phy) { |
969 | usb_phy_set_suspend(ci->usb_phy, 0); | |
970 | usb_phy_set_wakeup(ci->usb_phy, false); | |
971 | hw_wait_phy_stable(); | |
972 | } | |
973 | ||
1f874edc PC |
974 | ci->in_lpm = false; |
975 | if (ci->wakeup_int) { | |
976 | ci->wakeup_int = false; | |
977 | pm_runtime_mark_last_busy(ci->dev); | |
978 | pm_runtime_put_autosuspend(ci->dev); | |
979 | enable_irq(ci->irq); | |
961ea496 LJ |
980 | if (ci_otg_is_fsm_mode(ci)) |
981 | ci_otg_fsm_wakeup_by_srp(ci); | |
1f874edc PC |
982 | } |
983 | ||
8076932f PC |
984 | return 0; |
985 | } | |
986 | ||
1f874edc | 987 | #ifdef CONFIG_PM_SLEEP |
8076932f PC |
988 | static int ci_suspend(struct device *dev) |
989 | { | |
990 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
991 | ||
992 | if (ci->wq) | |
993 | flush_workqueue(ci->wq); | |
1f874edc PC |
994 | /* |
995 | * Controller needs to be active during suspend, otherwise the core | |
996 | * may run resume when the parent is at suspend if other driver's | |
997 | * suspend fails, it occurs before parent's suspend has not started, | |
998 | * but the core suspend has finished. | |
999 | */ | |
1000 | if (ci->in_lpm) | |
1001 | pm_runtime_resume(dev); | |
1002 | ||
1003 | if (ci->in_lpm) { | |
1004 | WARN_ON(1); | |
1005 | return 0; | |
1006 | } | |
8076932f | 1007 | |
f8efa766 | 1008 | if (device_may_wakeup(dev)) { |
961ea496 LJ |
1009 | if (ci_otg_is_fsm_mode(ci)) |
1010 | ci_otg_fsm_suspend_for_srp(ci); | |
1011 | ||
f8efa766 PC |
1012 | usb_phy_set_wakeup(ci->usb_phy, true); |
1013 | enable_irq_wake(ci->irq); | |
1014 | } | |
1015 | ||
8076932f PC |
1016 | ci_controller_suspend(ci); |
1017 | ||
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | static int ci_resume(struct device *dev) | |
1022 | { | |
1f874edc PC |
1023 | struct ci_hdrc *ci = dev_get_drvdata(dev); |
1024 | int ret; | |
1025 | ||
f8efa766 PC |
1026 | if (device_may_wakeup(dev)) |
1027 | disable_irq_wake(ci->irq); | |
1028 | ||
1f874edc PC |
1029 | ret = ci_controller_resume(dev); |
1030 | if (ret) | |
1031 | return ret; | |
1032 | ||
1033 | if (ci->supports_runtime_pm) { | |
1034 | pm_runtime_disable(dev); | |
1035 | pm_runtime_set_active(dev); | |
1036 | pm_runtime_enable(dev); | |
1037 | } | |
1038 | ||
1039 | return ret; | |
8076932f PC |
1040 | } |
1041 | #endif /* CONFIG_PM_SLEEP */ | |
1042 | ||
1f874edc PC |
1043 | static int ci_runtime_suspend(struct device *dev) |
1044 | { | |
1045 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
1046 | ||
1047 | dev_dbg(dev, "at %s\n", __func__); | |
1048 | ||
1049 | if (ci->in_lpm) { | |
1050 | WARN_ON(1); | |
1051 | return 0; | |
1052 | } | |
1053 | ||
961ea496 LJ |
1054 | if (ci_otg_is_fsm_mode(ci)) |
1055 | ci_otg_fsm_suspend_for_srp(ci); | |
1056 | ||
1f874edc PC |
1057 | usb_phy_set_wakeup(ci->usb_phy, true); |
1058 | ci_controller_suspend(ci); | |
1059 | ||
1060 | return 0; | |
1061 | } | |
1062 | ||
1063 | static int ci_runtime_resume(struct device *dev) | |
1064 | { | |
1065 | return ci_controller_resume(dev); | |
1066 | } | |
1067 | ||
1068 | #endif /* CONFIG_PM */ | |
8076932f PC |
1069 | static const struct dev_pm_ops ci_pm_ops = { |
1070 | SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) | |
1f874edc | 1071 | SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) |
8076932f | 1072 | }; |
1f874edc | 1073 | |
5f36e231 AS |
1074 | static struct platform_driver ci_hdrc_driver = { |
1075 | .probe = ci_hdrc_probe, | |
7690417d | 1076 | .remove = ci_hdrc_remove, |
e443b333 | 1077 | .driver = { |
5f36e231 | 1078 | .name = "ci_hdrc", |
8076932f | 1079 | .pm = &ci_pm_ops, |
e443b333 AS |
1080 | }, |
1081 | }; | |
1082 | ||
2f01a33b PC |
1083 | static int __init ci_hdrc_platform_register(void) |
1084 | { | |
1085 | ci_hdrc_host_driver_init(); | |
1086 | return platform_driver_register(&ci_hdrc_driver); | |
1087 | } | |
1088 | module_init(ci_hdrc_platform_register); | |
1089 | ||
1090 | static void __exit ci_hdrc_platform_unregister(void) | |
1091 | { | |
1092 | platform_driver_unregister(&ci_hdrc_driver); | |
1093 | } | |
1094 | module_exit(ci_hdrc_platform_unregister); | |
e443b333 | 1095 | |
5f36e231 | 1096 | MODULE_ALIAS("platform:ci_hdrc"); |
e443b333 AS |
1097 | MODULE_LICENSE("GPL v2"); |
1098 | MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); | |
5f36e231 | 1099 | MODULE_DESCRIPTION("ChipIdea HDRC Driver"); |