Commit | Line | Data |
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e443b333 AS |
1 | /* |
2 | * core.c - ChipIdea USB IP core family device controller | |
3 | * | |
4 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. | |
5 | * | |
6 | * Author: David Lopo | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Description: ChipIdea USB IP core family device controller | |
15 | * | |
16 | * This driver is composed of several blocks: | |
17 | * - HW: hardware interface | |
18 | * - DBG: debug facilities (optional) | |
19 | * - UTIL: utilities | |
20 | * - ISR: interrupts handling | |
21 | * - ENDPT: endpoint operations (Gadget API) | |
22 | * - GADGET: gadget operations (Gadget API) | |
23 | * - BUS: bus glue code, bus abstraction layer | |
24 | * | |
25 | * Compile Options | |
58ce8499 | 26 | * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities |
e443b333 AS |
27 | * - STALL_IN: non-empty bulk-in pipes cannot be halted |
28 | * if defined mass storage compliance succeeds but with warnings | |
29 | * => case 4: Hi > Dn | |
30 | * => case 5: Hi > Di | |
31 | * => case 8: Hi <> Do | |
32 | * if undefined usbtest 13 fails | |
33 | * - TRACE: enable function tracing (depends on DEBUG) | |
34 | * | |
35 | * Main Features | |
36 | * - Chapter 9 & Mass Storage Compliance with Gadget File Storage | |
37 | * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) | |
38 | * - Normal & LPM support | |
39 | * | |
40 | * USBTEST Report | |
41 | * - OK: 0-12, 13 (STALL_IN defined) & 14 | |
42 | * - Not Supported: 15 & 16 (ISO) | |
43 | * | |
44 | * TODO List | |
e443b333 AS |
45 | * - Suspend & Remote Wakeup |
46 | */ | |
47 | #include <linux/delay.h> | |
48 | #include <linux/device.h> | |
e443b333 | 49 | #include <linux/dma-mapping.h> |
1e5e2d3d | 50 | #include <linux/phy/phy.h> |
e443b333 AS |
51 | #include <linux/platform_device.h> |
52 | #include <linux/module.h> | |
fe6e125e | 53 | #include <linux/idr.h> |
e443b333 AS |
54 | #include <linux/interrupt.h> |
55 | #include <linux/io.h> | |
e443b333 AS |
56 | #include <linux/kernel.h> |
57 | #include <linux/slab.h> | |
58 | #include <linux/pm_runtime.h> | |
59 | #include <linux/usb/ch9.h> | |
60 | #include <linux/usb/gadget.h> | |
61 | #include <linux/usb/otg.h> | |
62 | #include <linux/usb/chipidea.h> | |
40dcd0e8 | 63 | #include <linux/usb/of.h> |
4f6743d5 | 64 | #include <linux/of.h> |
40dcd0e8 | 65 | #include <linux/phy.h> |
1542d9c3 | 66 | #include <linux/regulator/consumer.h> |
8022d3d5 | 67 | #include <linux/usb/ehci_def.h> |
e443b333 AS |
68 | |
69 | #include "ci.h" | |
70 | #include "udc.h" | |
71 | #include "bits.h" | |
eb70e5ab | 72 | #include "host.h" |
e443b333 | 73 | #include "debug.h" |
c10b4f03 | 74 | #include "otg.h" |
4dcf720c | 75 | #include "otg_fsm.h" |
e443b333 | 76 | |
5f36e231 | 77 | /* Controller register map */ |
987e7bc3 MKB |
78 | static const u8 ci_regs_nolpm[] = { |
79 | [CAP_CAPLENGTH] = 0x00U, | |
80 | [CAP_HCCPARAMS] = 0x08U, | |
81 | [CAP_DCCPARAMS] = 0x24U, | |
82 | [CAP_TESTMODE] = 0x38U, | |
83 | [OP_USBCMD] = 0x00U, | |
84 | [OP_USBSTS] = 0x04U, | |
85 | [OP_USBINTR] = 0x08U, | |
86 | [OP_DEVICEADDR] = 0x14U, | |
87 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 88 | [OP_TTCTRL] = 0x1CU, |
987e7bc3 MKB |
89 | [OP_PORTSC] = 0x44U, |
90 | [OP_DEVLC] = 0x84U, | |
91 | [OP_OTGSC] = 0x64U, | |
92 | [OP_USBMODE] = 0x68U, | |
93 | [OP_ENDPTSETUPSTAT] = 0x6CU, | |
94 | [OP_ENDPTPRIME] = 0x70U, | |
95 | [OP_ENDPTFLUSH] = 0x74U, | |
96 | [OP_ENDPTSTAT] = 0x78U, | |
97 | [OP_ENDPTCOMPLETE] = 0x7CU, | |
98 | [OP_ENDPTCTRL] = 0x80U, | |
e443b333 AS |
99 | }; |
100 | ||
987e7bc3 MKB |
101 | static const u8 ci_regs_lpm[] = { |
102 | [CAP_CAPLENGTH] = 0x00U, | |
103 | [CAP_HCCPARAMS] = 0x08U, | |
104 | [CAP_DCCPARAMS] = 0x24U, | |
105 | [CAP_TESTMODE] = 0xFCU, | |
106 | [OP_USBCMD] = 0x00U, | |
107 | [OP_USBSTS] = 0x04U, | |
108 | [OP_USBINTR] = 0x08U, | |
109 | [OP_DEVICEADDR] = 0x14U, | |
110 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 111 | [OP_TTCTRL] = 0x1CU, |
987e7bc3 MKB |
112 | [OP_PORTSC] = 0x44U, |
113 | [OP_DEVLC] = 0x84U, | |
114 | [OP_OTGSC] = 0xC4U, | |
115 | [OP_USBMODE] = 0xC8U, | |
116 | [OP_ENDPTSETUPSTAT] = 0xD8U, | |
117 | [OP_ENDPTPRIME] = 0xDCU, | |
118 | [OP_ENDPTFLUSH] = 0xE0U, | |
119 | [OP_ENDPTSTAT] = 0xE4U, | |
120 | [OP_ENDPTCOMPLETE] = 0xE8U, | |
121 | [OP_ENDPTCTRL] = 0xECU, | |
e443b333 AS |
122 | }; |
123 | ||
158ec071 | 124 | static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) |
e443b333 AS |
125 | { |
126 | int i; | |
127 | ||
e443b333 | 128 | for (i = 0; i < OP_ENDPTCTRL; i++) |
5f36e231 AS |
129 | ci->hw_bank.regmap[i] = |
130 | (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + | |
e443b333 AS |
131 | (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); |
132 | ||
133 | for (; i <= OP_LAST; i++) | |
5f36e231 | 134 | ci->hw_bank.regmap[i] = ci->hw_bank.op + |
e443b333 AS |
135 | 4 * (i - OP_ENDPTCTRL) + |
136 | (is_lpm | |
137 | ? ci_regs_lpm[OP_ENDPTCTRL] | |
138 | : ci_regs_nolpm[OP_ENDPTCTRL]); | |
139 | ||
e443b333 AS |
140 | } |
141 | ||
cb271f3c PC |
142 | static enum ci_revision ci_get_revision(struct ci_hdrc *ci) |
143 | { | |
144 | int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); | |
145 | enum ci_revision rev = CI_REVISION_UNKNOWN; | |
146 | ||
147 | if (ver == 0x2) { | |
148 | rev = hw_read_id_reg(ci, ID_ID, REVISION) | |
149 | >> __ffs(REVISION); | |
150 | rev += CI_REVISION_20; | |
151 | } else if (ver == 0x0) { | |
152 | rev = CI_REVISION_1X; | |
153 | } | |
154 | ||
155 | return rev; | |
156 | } | |
157 | ||
36304b06 LJ |
158 | /** |
159 | * hw_read_intr_enable: returns interrupt enable register | |
160 | * | |
19353881 PC |
161 | * @ci: the controller |
162 | * | |
36304b06 LJ |
163 | * This function returns register data |
164 | */ | |
165 | u32 hw_read_intr_enable(struct ci_hdrc *ci) | |
166 | { | |
167 | return hw_read(ci, OP_USBINTR, ~0); | |
168 | } | |
169 | ||
170 | /** | |
171 | * hw_read_intr_status: returns interrupt status register | |
172 | * | |
19353881 PC |
173 | * @ci: the controller |
174 | * | |
36304b06 LJ |
175 | * This function returns register data |
176 | */ | |
177 | u32 hw_read_intr_status(struct ci_hdrc *ci) | |
178 | { | |
179 | return hw_read(ci, OP_USBSTS, ~0); | |
180 | } | |
181 | ||
e443b333 AS |
182 | /** |
183 | * hw_port_test_set: writes port test mode (execute without interruption) | |
184 | * @mode: new value | |
185 | * | |
186 | * This function returns an error code | |
187 | */ | |
8e22978c | 188 | int hw_port_test_set(struct ci_hdrc *ci, u8 mode) |
e443b333 AS |
189 | { |
190 | const u8 TEST_MODE_MAX = 7; | |
191 | ||
192 | if (mode > TEST_MODE_MAX) | |
193 | return -EINVAL; | |
194 | ||
727b4ddb | 195 | hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); |
e443b333 AS |
196 | return 0; |
197 | } | |
198 | ||
199 | /** | |
200 | * hw_port_test_get: reads port test mode value | |
201 | * | |
19353881 PC |
202 | * @ci: the controller |
203 | * | |
e443b333 AS |
204 | * This function returns port test mode value |
205 | */ | |
8e22978c | 206 | u8 hw_port_test_get(struct ci_hdrc *ci) |
e443b333 | 207 | { |
727b4ddb | 208 | return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); |
e443b333 AS |
209 | } |
210 | ||
b82613cf PC |
211 | static void hw_wait_phy_stable(void) |
212 | { | |
213 | /* | |
214 | * The phy needs some delay to output the stable status from low | |
215 | * power mode. And for OTGSC, the status inputs are debounced | |
216 | * using a 1 ms time constant, so, delay 2ms for controller to get | |
217 | * the stable status, like vbus and id when the phy leaves low power. | |
218 | */ | |
219 | usleep_range(2000, 2500); | |
220 | } | |
221 | ||
864cf949 PC |
222 | /* The PHY enters/leaves low power mode */ |
223 | static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) | |
224 | { | |
225 | enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; | |
226 | bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); | |
227 | ||
6d037db6 | 228 | if (enable && !lpm) |
864cf949 PC |
229 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
230 | PORTSC_PHCD(ci->hw_bank.lpm)); | |
6d037db6 | 231 | else if (!enable && lpm) |
864cf949 PC |
232 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
233 | 0); | |
864cf949 PC |
234 | } |
235 | ||
8e22978c | 236 | static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) |
e443b333 AS |
237 | { |
238 | u32 reg; | |
239 | ||
240 | /* bank is a module variable */ | |
5f36e231 | 241 | ci->hw_bank.abs = base; |
e443b333 | 242 | |
5f36e231 | 243 | ci->hw_bank.cap = ci->hw_bank.abs; |
77c4400f | 244 | ci->hw_bank.cap += ci->platdata->capoffset; |
938d323f | 245 | ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); |
e443b333 | 246 | |
5f36e231 AS |
247 | hw_alloc_regmap(ci, false); |
248 | reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> | |
727b4ddb | 249 | __ffs(HCCPARAMS_LEN); |
5f36e231 | 250 | ci->hw_bank.lpm = reg; |
aeb2c121 CR |
251 | if (reg) |
252 | hw_alloc_regmap(ci, !!reg); | |
5f36e231 AS |
253 | ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; |
254 | ci->hw_bank.size += OP_LAST; | |
255 | ci->hw_bank.size /= sizeof(u32); | |
e443b333 | 256 | |
5f36e231 | 257 | reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> |
727b4ddb | 258 | __ffs(DCCPARAMS_DEN); |
5f36e231 | 259 | ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ |
e443b333 | 260 | |
09c94e62 | 261 | if (ci->hw_ep_max > ENDPT_MAX) |
e443b333 AS |
262 | return -ENODEV; |
263 | ||
864cf949 PC |
264 | ci_hdrc_enter_lpm(ci, false); |
265 | ||
c344b518 PC |
266 | /* Disable all interrupts bits */ |
267 | hw_write(ci, OP_USBINTR, 0xffffffff, 0); | |
268 | ||
269 | /* Clear all interrupts status bits*/ | |
270 | hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); | |
271 | ||
cb271f3c PC |
272 | ci->rev = ci_get_revision(ci); |
273 | ||
274 | dev_dbg(ci->dev, | |
275 | "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n", | |
276 | ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); | |
e443b333 AS |
277 | |
278 | /* setup lock mode ? */ | |
279 | ||
280 | /* ENDPTSETUPSTAT is '0' by default */ | |
281 | ||
282 | /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
8e22978c | 287 | static void hw_phymode_configure(struct ci_hdrc *ci) |
40dcd0e8 | 288 | { |
3b5d3e68 | 289 | u32 portsc, lpm, sts = 0; |
40dcd0e8 MG |
290 | |
291 | switch (ci->platdata->phy_mode) { | |
292 | case USBPHY_INTERFACE_MODE_UTMI: | |
293 | portsc = PORTSC_PTS(PTS_UTMI); | |
294 | lpm = DEVLC_PTS(PTS_UTMI); | |
295 | break; | |
296 | case USBPHY_INTERFACE_MODE_UTMIW: | |
297 | portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; | |
298 | lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; | |
299 | break; | |
300 | case USBPHY_INTERFACE_MODE_ULPI: | |
301 | portsc = PORTSC_PTS(PTS_ULPI); | |
302 | lpm = DEVLC_PTS(PTS_ULPI); | |
303 | break; | |
304 | case USBPHY_INTERFACE_MODE_SERIAL: | |
305 | portsc = PORTSC_PTS(PTS_SERIAL); | |
306 | lpm = DEVLC_PTS(PTS_SERIAL); | |
307 | sts = 1; | |
308 | break; | |
309 | case USBPHY_INTERFACE_MODE_HSIC: | |
310 | portsc = PORTSC_PTS(PTS_HSIC); | |
311 | lpm = DEVLC_PTS(PTS_HSIC); | |
312 | break; | |
313 | default: | |
314 | return; | |
315 | } | |
316 | ||
317 | if (ci->hw_bank.lpm) { | |
318 | hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); | |
3b5d3e68 CR |
319 | if (sts) |
320 | hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); | |
40dcd0e8 MG |
321 | } else { |
322 | hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); | |
3b5d3e68 CR |
323 | if (sts) |
324 | hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); | |
40dcd0e8 MG |
325 | } |
326 | } | |
327 | ||
1e5e2d3d AT |
328 | /** |
329 | * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy | |
330 | * interfaces | |
331 | * @ci: the controller | |
332 | * | |
333 | * This function returns an error code if the phy failed to init | |
334 | */ | |
335 | static int _ci_usb_phy_init(struct ci_hdrc *ci) | |
336 | { | |
337 | int ret; | |
338 | ||
339 | if (ci->phy) { | |
340 | ret = phy_init(ci->phy); | |
341 | if (ret) | |
342 | return ret; | |
343 | ||
344 | ret = phy_power_on(ci->phy); | |
345 | if (ret) { | |
346 | phy_exit(ci->phy); | |
347 | return ret; | |
348 | } | |
349 | } else { | |
350 | ret = usb_phy_init(ci->usb_phy); | |
351 | } | |
352 | ||
353 | return ret; | |
354 | } | |
355 | ||
356 | /** | |
357 | * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy | |
358 | * interfaces | |
359 | * @ci: the controller | |
360 | */ | |
361 | static void ci_usb_phy_exit(struct ci_hdrc *ci) | |
362 | { | |
363 | if (ci->phy) { | |
364 | phy_power_off(ci->phy); | |
365 | phy_exit(ci->phy); | |
366 | } else { | |
367 | usb_phy_shutdown(ci->usb_phy); | |
368 | } | |
369 | } | |
370 | ||
d03cccff PC |
371 | /** |
372 | * ci_usb_phy_init: initialize phy according to different phy type | |
373 | * @ci: the controller | |
19353881 | 374 | * |
d03cccff PC |
375 | * This function returns an error code if usb_phy_init has failed |
376 | */ | |
377 | static int ci_usb_phy_init(struct ci_hdrc *ci) | |
378 | { | |
379 | int ret; | |
380 | ||
381 | switch (ci->platdata->phy_mode) { | |
382 | case USBPHY_INTERFACE_MODE_UTMI: | |
383 | case USBPHY_INTERFACE_MODE_UTMIW: | |
384 | case USBPHY_INTERFACE_MODE_HSIC: | |
1e5e2d3d | 385 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
386 | if (!ret) |
387 | hw_wait_phy_stable(); | |
388 | else | |
d03cccff PC |
389 | return ret; |
390 | hw_phymode_configure(ci); | |
391 | break; | |
392 | case USBPHY_INTERFACE_MODE_ULPI: | |
393 | case USBPHY_INTERFACE_MODE_SERIAL: | |
394 | hw_phymode_configure(ci); | |
1e5e2d3d | 395 | ret = _ci_usb_phy_init(ci); |
d03cccff PC |
396 | if (ret) |
397 | return ret; | |
398 | break; | |
399 | default: | |
1e5e2d3d | 400 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
401 | if (!ret) |
402 | hw_wait_phy_stable(); | |
d03cccff PC |
403 | } |
404 | ||
405 | return ret; | |
406 | } | |
407 | ||
bf9c85e7 PC |
408 | |
409 | /** | |
410 | * ci_platform_configure: do controller configure | |
411 | * @ci: the controller | |
412 | * | |
413 | */ | |
414 | void ci_platform_configure(struct ci_hdrc *ci) | |
415 | { | |
8022d3d5 PC |
416 | bool is_device_mode, is_host_mode; |
417 | ||
418 | is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; | |
419 | is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; | |
420 | ||
421 | if (is_device_mode && | |
422 | (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)) | |
423 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); | |
424 | ||
425 | if (is_host_mode && | |
426 | (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)) | |
bf9c85e7 PC |
427 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); |
428 | ||
429 | if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { | |
430 | if (ci->hw_bank.lpm) | |
431 | hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); | |
432 | else | |
433 | hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); | |
434 | } | |
435 | ||
436 | if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) | |
437 | hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); | |
df96ed8d PC |
438 | |
439 | hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); | |
440 | ||
bf9c85e7 PC |
441 | } |
442 | ||
e443b333 | 443 | /** |
cdd278f2 | 444 | * hw_controller_reset: do controller reset |
e443b333 AS |
445 | * @ci: the controller |
446 | * | |
447 | * This function returns an error code | |
448 | */ | |
cdd278f2 PC |
449 | static int hw_controller_reset(struct ci_hdrc *ci) |
450 | { | |
451 | int count = 0; | |
452 | ||
453 | hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); | |
454 | while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { | |
455 | udelay(10); | |
456 | if (count++ > 1000) | |
457 | return -ETIMEDOUT; | |
458 | } | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | /** | |
464 | * hw_device_reset: resets chip (execute without interruption) | |
465 | * @ci: the controller | |
466 | * | |
467 | * This function returns an error code | |
468 | */ | |
5b157300 | 469 | int hw_device_reset(struct ci_hdrc *ci) |
e443b333 | 470 | { |
cdd278f2 PC |
471 | int ret; |
472 | ||
e443b333 AS |
473 | /* should flush & stop before reset */ |
474 | hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); | |
475 | hw_write(ci, OP_USBCMD, USBCMD_RS, 0); | |
476 | ||
cdd278f2 PC |
477 | ret = hw_controller_reset(ci); |
478 | if (ret) { | |
479 | dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); | |
480 | return ret; | |
481 | } | |
e443b333 | 482 | |
77c4400f RZ |
483 | if (ci->platdata->notify_event) |
484 | ci->platdata->notify_event(ci, | |
8e22978c | 485 | CI_HDRC_CONTROLLER_RESET_EVENT); |
e443b333 | 486 | |
e443b333 AS |
487 | /* USBMODE should be configured step by step */ |
488 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); | |
5b157300 | 489 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); |
e443b333 AS |
490 | /* HW >= 2.3 */ |
491 | hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); | |
492 | ||
5b157300 PC |
493 | if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { |
494 | pr_err("cannot enter in %s device mode", ci_role(ci)->name); | |
e443b333 AS |
495 | pr_err("lpm = %i", ci->hw_bank.lpm); |
496 | return -ENODEV; | |
497 | } | |
498 | ||
bf9c85e7 PC |
499 | ci_platform_configure(ci); |
500 | ||
e443b333 AS |
501 | return 0; |
502 | } | |
503 | ||
22fa8445 PC |
504 | /** |
505 | * hw_wait_reg: wait the register value | |
506 | * | |
507 | * Sometimes, it needs to wait register value before going on. | |
508 | * Eg, when switch to device mode, the vbus value should be lower | |
509 | * than OTGSC_BSV before connects to host. | |
510 | * | |
511 | * @ci: the controller | |
512 | * @reg: register index | |
513 | * @mask: mast bit | |
514 | * @value: the bit value to wait | |
515 | * @timeout_ms: timeout in millisecond | |
516 | * | |
517 | * This function returns an error code if timeout | |
518 | */ | |
519 | int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, | |
520 | u32 value, unsigned int timeout_ms) | |
521 | { | |
522 | unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); | |
523 | ||
524 | while (hw_read(ci, reg, mask) != value) { | |
525 | if (time_after(jiffies, elapse)) { | |
526 | dev_err(ci->dev, "timeout waiting for %08x in %d\n", | |
527 | mask, reg); | |
528 | return -ETIMEDOUT; | |
529 | } | |
530 | msleep(20); | |
531 | } | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
5f36e231 AS |
536 | static irqreturn_t ci_irq(int irq, void *data) |
537 | { | |
8e22978c | 538 | struct ci_hdrc *ci = data; |
5f36e231 | 539 | irqreturn_t ret = IRQ_NONE; |
b183c19f | 540 | u32 otgsc = 0; |
5f36e231 | 541 | |
1f874edc PC |
542 | if (ci->in_lpm) { |
543 | disable_irq_nosync(irq); | |
544 | ci->wakeup_int = true; | |
545 | pm_runtime_get(ci->dev); | |
546 | return IRQ_HANDLED; | |
547 | } | |
548 | ||
4dcf720c | 549 | if (ci->is_otg) { |
0c33bf78 | 550 | otgsc = hw_read_otgsc(ci, ~0); |
4dcf720c LJ |
551 | if (ci_otg_is_fsm_mode(ci)) { |
552 | ret = ci_otg_fsm_irq(ci); | |
553 | if (ret == IRQ_HANDLED) | |
554 | return ret; | |
555 | } | |
556 | } | |
5f36e231 | 557 | |
a107f8c5 PC |
558 | /* |
559 | * Handle id change interrupt, it indicates device/host function | |
560 | * switch. | |
561 | */ | |
562 | if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { | |
563 | ci->id_event = true; | |
0c33bf78 LJ |
564 | /* Clear ID change irq status */ |
565 | hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); | |
be6b0c1b | 566 | ci_otg_queue_work(ci); |
a107f8c5 PC |
567 | return IRQ_HANDLED; |
568 | } | |
b183c19f | 569 | |
a107f8c5 PC |
570 | /* |
571 | * Handle vbus change interrupt, it indicates device connection | |
572 | * and disconnection events. | |
573 | */ | |
574 | if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { | |
575 | ci->b_sess_valid_event = true; | |
0c33bf78 LJ |
576 | /* Clear BSV irq */ |
577 | hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); | |
be6b0c1b | 578 | ci_otg_queue_work(ci); |
a107f8c5 | 579 | return IRQ_HANDLED; |
5f36e231 AS |
580 | } |
581 | ||
a107f8c5 PC |
582 | /* Handle device/host interrupt */ |
583 | if (ci->role != CI_ROLE_END) | |
584 | ret = ci_role(ci)->irq(ci); | |
585 | ||
b183c19f | 586 | return ret; |
5f36e231 AS |
587 | } |
588 | ||
1542d9c3 PC |
589 | static int ci_get_platdata(struct device *dev, |
590 | struct ci_hdrc_platform_data *platdata) | |
591 | { | |
df96ed8d PC |
592 | int ret; |
593 | ||
c22600c3 PC |
594 | if (!platdata->phy_mode) |
595 | platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); | |
596 | ||
597 | if (!platdata->dr_mode) | |
598 | platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); | |
599 | ||
600 | if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) | |
601 | platdata->dr_mode = USB_DR_MODE_OTG; | |
602 | ||
c2ec3a73 PC |
603 | if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { |
604 | /* Get the vbus regulator */ | |
605 | platdata->reg_vbus = devm_regulator_get(dev, "vbus"); | |
606 | if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { | |
607 | return -EPROBE_DEFER; | |
608 | } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { | |
6629467b | 609 | /* no vbus regulator is needed */ |
c2ec3a73 PC |
610 | platdata->reg_vbus = NULL; |
611 | } else if (IS_ERR(platdata->reg_vbus)) { | |
612 | dev_err(dev, "Getting regulator error: %ld\n", | |
613 | PTR_ERR(platdata->reg_vbus)); | |
614 | return PTR_ERR(platdata->reg_vbus); | |
615 | } | |
f6a9ff07 PC |
616 | /* Get TPL support */ |
617 | if (!platdata->tpl_support) | |
618 | platdata->tpl_support = | |
619 | of_usb_host_tpl_support(dev->of_node); | |
c2ec3a73 PC |
620 | } |
621 | ||
4f6743d5 MG |
622 | if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL) |
623 | platdata->flags |= CI_HDRC_FORCE_FULLSPEED; | |
624 | ||
df96ed8d PC |
625 | platdata->itc_setting = 1; |
626 | if (of_find_property(dev->of_node, "itc-setting", NULL)) { | |
627 | ret = of_property_read_u32(dev->of_node, "itc-setting", | |
628 | &platdata->itc_setting); | |
629 | if (ret) { | |
630 | dev_err(dev, | |
631 | "failed to get itc-setting\n"); | |
632 | return ret; | |
633 | } | |
634 | } | |
635 | ||
1542d9c3 PC |
636 | return 0; |
637 | } | |
638 | ||
fe6e125e RZ |
639 | static DEFINE_IDA(ci_ida); |
640 | ||
8e22978c | 641 | struct platform_device *ci_hdrc_add_device(struct device *dev, |
cbc6dc2a | 642 | struct resource *res, int nres, |
8e22978c | 643 | struct ci_hdrc_platform_data *platdata) |
cbc6dc2a RZ |
644 | { |
645 | struct platform_device *pdev; | |
fe6e125e | 646 | int id, ret; |
cbc6dc2a | 647 | |
1542d9c3 PC |
648 | ret = ci_get_platdata(dev, platdata); |
649 | if (ret) | |
650 | return ERR_PTR(ret); | |
651 | ||
fe6e125e RZ |
652 | id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); |
653 | if (id < 0) | |
654 | return ERR_PTR(id); | |
655 | ||
656 | pdev = platform_device_alloc("ci_hdrc", id); | |
657 | if (!pdev) { | |
658 | ret = -ENOMEM; | |
659 | goto put_id; | |
660 | } | |
cbc6dc2a RZ |
661 | |
662 | pdev->dev.parent = dev; | |
663 | pdev->dev.dma_mask = dev->dma_mask; | |
664 | pdev->dev.dma_parms = dev->dma_parms; | |
665 | dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); | |
666 | ||
667 | ret = platform_device_add_resources(pdev, res, nres); | |
668 | if (ret) | |
669 | goto err; | |
670 | ||
671 | ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); | |
672 | if (ret) | |
673 | goto err; | |
674 | ||
675 | ret = platform_device_add(pdev); | |
676 | if (ret) | |
677 | goto err; | |
678 | ||
679 | return pdev; | |
680 | ||
681 | err: | |
682 | platform_device_put(pdev); | |
fe6e125e RZ |
683 | put_id: |
684 | ida_simple_remove(&ci_ida, id); | |
cbc6dc2a RZ |
685 | return ERR_PTR(ret); |
686 | } | |
8e22978c | 687 | EXPORT_SYMBOL_GPL(ci_hdrc_add_device); |
cbc6dc2a | 688 | |
8e22978c | 689 | void ci_hdrc_remove_device(struct platform_device *pdev) |
cbc6dc2a | 690 | { |
98c35534 | 691 | int id = pdev->id; |
cbc6dc2a | 692 | platform_device_unregister(pdev); |
98c35534 | 693 | ida_simple_remove(&ci_ida, id); |
cbc6dc2a | 694 | } |
8e22978c | 695 | EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); |
cbc6dc2a | 696 | |
3f124d23 PC |
697 | static inline void ci_role_destroy(struct ci_hdrc *ci) |
698 | { | |
699 | ci_hdrc_gadget_destroy(ci); | |
700 | ci_hdrc_host_destroy(ci); | |
cbec6bd5 PC |
701 | if (ci->is_otg) |
702 | ci_hdrc_otg_destroy(ci); | |
3f124d23 PC |
703 | } |
704 | ||
577b232f PC |
705 | static void ci_get_otg_capable(struct ci_hdrc *ci) |
706 | { | |
707 | if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) | |
708 | ci->is_otg = false; | |
709 | else | |
710 | ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, | |
711 | DCCPARAMS_DC | DCCPARAMS_HC) | |
712 | == (DCCPARAMS_DC | DCCPARAMS_HC)); | |
2e37cfd8 | 713 | if (ci->is_otg) { |
577b232f | 714 | dev_dbg(ci->dev, "It is OTG capable controller\n"); |
2e37cfd8 PC |
715 | /* Disable and clear all OTG irq */ |
716 | hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, | |
717 | OTGSC_INT_STATUS_BITS); | |
718 | } | |
577b232f PC |
719 | } |
720 | ||
41ac7b3a | 721 | static int ci_hdrc_probe(struct platform_device *pdev) |
e443b333 AS |
722 | { |
723 | struct device *dev = &pdev->dev; | |
8e22978c | 724 | struct ci_hdrc *ci; |
e443b333 AS |
725 | struct resource *res; |
726 | void __iomem *base; | |
727 | int ret; | |
691962d1 | 728 | enum usb_dr_mode dr_mode; |
e443b333 | 729 | |
fad56745 | 730 | if (!dev_get_platdata(dev)) { |
e443b333 AS |
731 | dev_err(dev, "platform data missing\n"); |
732 | return -ENODEV; | |
733 | } | |
734 | ||
735 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
19290816 FB |
736 | base = devm_ioremap_resource(dev, res); |
737 | if (IS_ERR(base)) | |
738 | return PTR_ERR(base); | |
e443b333 | 739 | |
5f36e231 | 740 | ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); |
d0f99249 | 741 | if (!ci) |
5f36e231 | 742 | return -ENOMEM; |
5f36e231 AS |
743 | |
744 | ci->dev = dev; | |
fad56745 | 745 | ci->platdata = dev_get_platdata(dev); |
ed8f8318 PC |
746 | ci->imx28_write_fix = !!(ci->platdata->flags & |
747 | CI_HDRC_IMX28_WRITE_FIX); | |
1f874edc PC |
748 | ci->supports_runtime_pm = !!(ci->platdata->flags & |
749 | CI_HDRC_SUPPORTS_RUNTIME_PM); | |
5f36e231 AS |
750 | |
751 | ret = hw_device_init(ci, base); | |
752 | if (ret < 0) { | |
753 | dev_err(dev, "can't initialize hardware\n"); | |
754 | return -ENODEV; | |
755 | } | |
e443b333 | 756 | |
1e5e2d3d AT |
757 | if (ci->platdata->phy) { |
758 | ci->phy = ci->platdata->phy; | |
759 | } else if (ci->platdata->usb_phy) { | |
ef44cb42 | 760 | ci->usb_phy = ci->platdata->usb_phy; |
1e5e2d3d | 761 | } else { |
21a5b579 AT |
762 | ci->phy = devm_phy_get(dev->parent, "usb-phy"); |
763 | ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); | |
c859aa65 | 764 | |
1e5e2d3d AT |
765 | /* if both generic PHY and USB PHY layers aren't enabled */ |
766 | if (PTR_ERR(ci->phy) == -ENOSYS && | |
767 | PTR_ERR(ci->usb_phy) == -ENXIO) | |
768 | return -ENXIO; | |
769 | ||
770 | if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) | |
771 | return -EPROBE_DEFER; | |
c859aa65 | 772 | |
1e5e2d3d AT |
773 | if (IS_ERR(ci->phy)) |
774 | ci->phy = NULL; | |
775 | else if (IS_ERR(ci->usb_phy)) | |
776 | ci->usb_phy = NULL; | |
c859aa65 PC |
777 | } |
778 | ||
d03cccff | 779 | ret = ci_usb_phy_init(ci); |
74475ede PC |
780 | if (ret) { |
781 | dev_err(dev, "unable to init phy: %d\n", ret); | |
782 | return ret; | |
783 | } | |
784 | ||
eb70e5ab AS |
785 | ci->hw_bank.phys = res->start; |
786 | ||
5f36e231 AS |
787 | ci->irq = platform_get_irq(pdev, 0); |
788 | if (ci->irq < 0) { | |
e443b333 | 789 | dev_err(dev, "missing IRQ\n"); |
42d18212 | 790 | ret = ci->irq; |
c859aa65 | 791 | goto deinit_phy; |
5f36e231 AS |
792 | } |
793 | ||
577b232f PC |
794 | ci_get_otg_capable(ci); |
795 | ||
691962d1 | 796 | dr_mode = ci->platdata->dr_mode; |
5f36e231 | 797 | /* initialize role(s) before the interrupt is requested */ |
691962d1 SH |
798 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { |
799 | ret = ci_hdrc_host_init(ci); | |
800 | if (ret) | |
801 | dev_info(dev, "doesn't support host\n"); | |
802 | } | |
eb70e5ab | 803 | |
691962d1 SH |
804 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { |
805 | ret = ci_hdrc_gadget_init(ci); | |
806 | if (ret) | |
807 | dev_info(dev, "doesn't support gadget\n"); | |
808 | } | |
5f36e231 AS |
809 | |
810 | if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { | |
811 | dev_err(dev, "no supported roles\n"); | |
74475ede | 812 | ret = -ENODEV; |
c859aa65 | 813 | goto deinit_phy; |
cbec6bd5 PC |
814 | } |
815 | ||
27c62c2d | 816 | if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { |
cbec6bd5 PC |
817 | ret = ci_hdrc_otg_init(ci); |
818 | if (ret) { | |
819 | dev_err(dev, "init otg fails, ret = %d\n", ret); | |
820 | goto stop; | |
821 | } | |
5f36e231 AS |
822 | } |
823 | ||
824 | if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { | |
577b232f | 825 | if (ci->is_otg) { |
577b232f | 826 | ci->role = ci_otg_role(ci); |
0c33bf78 LJ |
827 | /* Enable ID change irq */ |
828 | hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); | |
577b232f PC |
829 | } else { |
830 | /* | |
831 | * If the controller is not OTG capable, but support | |
832 | * role switch, the defalt role is gadget, and the | |
833 | * user can switch it through debugfs. | |
834 | */ | |
835 | ci->role = CI_ROLE_GADGET; | |
836 | } | |
5f36e231 AS |
837 | } else { |
838 | ci->role = ci->roles[CI_ROLE_HOST] | |
839 | ? CI_ROLE_HOST | |
840 | : CI_ROLE_GADGET; | |
841 | } | |
842 | ||
4dcf720c | 843 | if (!ci_otg_is_fsm_mode(ci)) { |
961ea496 LJ |
844 | /* only update vbus status for peripheral */ |
845 | if (ci->role == CI_ROLE_GADGET) | |
846 | ci_handle_vbus_change(ci); | |
847 | ||
4dcf720c LJ |
848 | ret = ci_role_start(ci, ci->role); |
849 | if (ret) { | |
850 | dev_err(dev, "can't start %s role\n", | |
851 | ci_role(ci)->name); | |
852 | goto stop; | |
853 | } | |
e443b333 AS |
854 | } |
855 | ||
24c498df | 856 | platform_set_drvdata(pdev, ci); |
4c503dd5 PC |
857 | ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, |
858 | ci->platdata->name, ci); | |
5f36e231 AS |
859 | if (ret) |
860 | goto stop; | |
e443b333 | 861 | |
1f874edc PC |
862 | if (ci->supports_runtime_pm) { |
863 | pm_runtime_set_active(&pdev->dev); | |
864 | pm_runtime_enable(&pdev->dev); | |
865 | pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); | |
866 | pm_runtime_mark_last_busy(ci->dev); | |
867 | pm_runtime_use_autosuspend(&pdev->dev); | |
868 | } | |
869 | ||
4dcf720c LJ |
870 | if (ci_otg_is_fsm_mode(ci)) |
871 | ci_hdrc_otg_fsm_start(ci); | |
872 | ||
f8efa766 PC |
873 | device_set_wakeup_capable(&pdev->dev, true); |
874 | ||
adf0f735 AS |
875 | ret = dbg_create_files(ci); |
876 | if (!ret) | |
877 | return 0; | |
5f36e231 | 878 | |
5f36e231 | 879 | stop: |
3f124d23 | 880 | ci_role_destroy(ci); |
c859aa65 | 881 | deinit_phy: |
1e5e2d3d | 882 | ci_usb_phy_exit(ci); |
e443b333 AS |
883 | |
884 | return ret; | |
885 | } | |
886 | ||
fb4e98ab | 887 | static int ci_hdrc_remove(struct platform_device *pdev) |
e443b333 | 888 | { |
8e22978c | 889 | struct ci_hdrc *ci = platform_get_drvdata(pdev); |
e443b333 | 890 | |
1f874edc PC |
891 | if (ci->supports_runtime_pm) { |
892 | pm_runtime_get_sync(&pdev->dev); | |
893 | pm_runtime_disable(&pdev->dev); | |
894 | pm_runtime_put_noidle(&pdev->dev); | |
895 | } | |
896 | ||
adf0f735 | 897 | dbg_remove_files(ci); |
3f124d23 | 898 | ci_role_destroy(ci); |
864cf949 | 899 | ci_hdrc_enter_lpm(ci, true); |
1e5e2d3d | 900 | ci_usb_phy_exit(ci); |
e443b333 AS |
901 | |
902 | return 0; | |
903 | } | |
904 | ||
1f874edc | 905 | #ifdef CONFIG_PM |
961ea496 LJ |
906 | /* Prepare wakeup by SRP before suspend */ |
907 | static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) | |
908 | { | |
909 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
910 | !hw_read_otgsc(ci, OTGSC_ID)) { | |
911 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, | |
912 | PORTSC_PP); | |
913 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, | |
914 | PORTSC_WKCN); | |
915 | } | |
916 | } | |
917 | ||
918 | /* Handle SRP when wakeup by data pulse */ | |
919 | static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) | |
920 | { | |
921 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
922 | (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { | |
923 | if (!hw_read_otgsc(ci, OTGSC_ID)) { | |
924 | ci->fsm.a_srp_det = 1; | |
925 | ci->fsm.a_bus_drop = 0; | |
926 | } else { | |
927 | ci->fsm.id = 1; | |
928 | } | |
929 | ci_otg_queue_work(ci); | |
930 | } | |
931 | } | |
932 | ||
8076932f PC |
933 | static void ci_controller_suspend(struct ci_hdrc *ci) |
934 | { | |
1f874edc | 935 | disable_irq(ci->irq); |
8076932f | 936 | ci_hdrc_enter_lpm(ci, true); |
1f874edc PC |
937 | usb_phy_set_suspend(ci->usb_phy, 1); |
938 | ci->in_lpm = true; | |
939 | enable_irq(ci->irq); | |
8076932f PC |
940 | } |
941 | ||
942 | static int ci_controller_resume(struct device *dev) | |
943 | { | |
944 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
945 | ||
946 | dev_dbg(dev, "at %s\n", __func__); | |
947 | ||
1f874edc PC |
948 | if (!ci->in_lpm) { |
949 | WARN_ON(1); | |
950 | return 0; | |
951 | } | |
8076932f | 952 | |
1f874edc | 953 | ci_hdrc_enter_lpm(ci, false); |
8076932f PC |
954 | if (ci->usb_phy) { |
955 | usb_phy_set_suspend(ci->usb_phy, 0); | |
956 | usb_phy_set_wakeup(ci->usb_phy, false); | |
957 | hw_wait_phy_stable(); | |
958 | } | |
959 | ||
1f874edc PC |
960 | ci->in_lpm = false; |
961 | if (ci->wakeup_int) { | |
962 | ci->wakeup_int = false; | |
963 | pm_runtime_mark_last_busy(ci->dev); | |
964 | pm_runtime_put_autosuspend(ci->dev); | |
965 | enable_irq(ci->irq); | |
961ea496 LJ |
966 | if (ci_otg_is_fsm_mode(ci)) |
967 | ci_otg_fsm_wakeup_by_srp(ci); | |
1f874edc PC |
968 | } |
969 | ||
8076932f PC |
970 | return 0; |
971 | } | |
972 | ||
1f874edc | 973 | #ifdef CONFIG_PM_SLEEP |
8076932f PC |
974 | static int ci_suspend(struct device *dev) |
975 | { | |
976 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
977 | ||
978 | if (ci->wq) | |
979 | flush_workqueue(ci->wq); | |
1f874edc PC |
980 | /* |
981 | * Controller needs to be active during suspend, otherwise the core | |
982 | * may run resume when the parent is at suspend if other driver's | |
983 | * suspend fails, it occurs before parent's suspend has not started, | |
984 | * but the core suspend has finished. | |
985 | */ | |
986 | if (ci->in_lpm) | |
987 | pm_runtime_resume(dev); | |
988 | ||
989 | if (ci->in_lpm) { | |
990 | WARN_ON(1); | |
991 | return 0; | |
992 | } | |
8076932f | 993 | |
f8efa766 | 994 | if (device_may_wakeup(dev)) { |
961ea496 LJ |
995 | if (ci_otg_is_fsm_mode(ci)) |
996 | ci_otg_fsm_suspend_for_srp(ci); | |
997 | ||
f8efa766 PC |
998 | usb_phy_set_wakeup(ci->usb_phy, true); |
999 | enable_irq_wake(ci->irq); | |
1000 | } | |
1001 | ||
8076932f PC |
1002 | ci_controller_suspend(ci); |
1003 | ||
1004 | return 0; | |
1005 | } | |
1006 | ||
1007 | static int ci_resume(struct device *dev) | |
1008 | { | |
1f874edc PC |
1009 | struct ci_hdrc *ci = dev_get_drvdata(dev); |
1010 | int ret; | |
1011 | ||
f8efa766 PC |
1012 | if (device_may_wakeup(dev)) |
1013 | disable_irq_wake(ci->irq); | |
1014 | ||
1f874edc PC |
1015 | ret = ci_controller_resume(dev); |
1016 | if (ret) | |
1017 | return ret; | |
1018 | ||
1019 | if (ci->supports_runtime_pm) { | |
1020 | pm_runtime_disable(dev); | |
1021 | pm_runtime_set_active(dev); | |
1022 | pm_runtime_enable(dev); | |
1023 | } | |
1024 | ||
1025 | return ret; | |
8076932f PC |
1026 | } |
1027 | #endif /* CONFIG_PM_SLEEP */ | |
1028 | ||
1f874edc PC |
1029 | static int ci_runtime_suspend(struct device *dev) |
1030 | { | |
1031 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
1032 | ||
1033 | dev_dbg(dev, "at %s\n", __func__); | |
1034 | ||
1035 | if (ci->in_lpm) { | |
1036 | WARN_ON(1); | |
1037 | return 0; | |
1038 | } | |
1039 | ||
961ea496 LJ |
1040 | if (ci_otg_is_fsm_mode(ci)) |
1041 | ci_otg_fsm_suspend_for_srp(ci); | |
1042 | ||
1f874edc PC |
1043 | usb_phy_set_wakeup(ci->usb_phy, true); |
1044 | ci_controller_suspend(ci); | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static int ci_runtime_resume(struct device *dev) | |
1050 | { | |
1051 | return ci_controller_resume(dev); | |
1052 | } | |
1053 | ||
1054 | #endif /* CONFIG_PM */ | |
8076932f PC |
1055 | static const struct dev_pm_ops ci_pm_ops = { |
1056 | SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) | |
1f874edc | 1057 | SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) |
8076932f | 1058 | }; |
1f874edc | 1059 | |
5f36e231 AS |
1060 | static struct platform_driver ci_hdrc_driver = { |
1061 | .probe = ci_hdrc_probe, | |
7690417d | 1062 | .remove = ci_hdrc_remove, |
e443b333 | 1063 | .driver = { |
5f36e231 | 1064 | .name = "ci_hdrc", |
8076932f | 1065 | .pm = &ci_pm_ops, |
e443b333 AS |
1066 | }, |
1067 | }; | |
1068 | ||
2f01a33b PC |
1069 | static int __init ci_hdrc_platform_register(void) |
1070 | { | |
1071 | ci_hdrc_host_driver_init(); | |
1072 | return platform_driver_register(&ci_hdrc_driver); | |
1073 | } | |
1074 | module_init(ci_hdrc_platform_register); | |
1075 | ||
1076 | static void __exit ci_hdrc_platform_unregister(void) | |
1077 | { | |
1078 | platform_driver_unregister(&ci_hdrc_driver); | |
1079 | } | |
1080 | module_exit(ci_hdrc_platform_unregister); | |
e443b333 | 1081 | |
5f36e231 | 1082 | MODULE_ALIAS("platform:ci_hdrc"); |
e443b333 AS |
1083 | MODULE_LICENSE("GPL v2"); |
1084 | MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); | |
5f36e231 | 1085 | MODULE_DESCRIPTION("ChipIdea HDRC Driver"); |