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Merge branch 'for-4.6-ns' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup
[deliverable/linux.git] / drivers / usb / dwc2 / core.c
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.c - DesignWare HS OTG Controller common routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * The Core code provides basic services for accessing and managing the
39 * DWC_otg hardware. These services are used by both the Host Controller
40 * Driver and the Peripheral Controller Driver.
41 */
42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/moduleparam.h>
45#include <linux/spinlock.h>
46#include <linux/interrupt.h>
47#include <linux/dma-mapping.h>
48#include <linux/delay.h>
49#include <linux/io.h>
50#include <linux/slab.h>
51#include <linux/usb.h>
52
53#include <linux/usb/hcd.h>
54#include <linux/usb/ch11.h>
55
56#include "core.h"
57#include "hcd.h"
58
d17ee77b
GH		 59/**
60 * dwc2_backup_global_registers() - Backup global controller registers.
61 * When suspending usb bus, registers needs to be backuped
62 * if controller power is disabled once suspended.
63 *
64 * @hsotg: Programming view of the DWC_otg controller
65 */
66static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
67{
68 struct dwc2_gregs_backup *gr;
69 int i;
70
71 /* Backup global regs */
cc1e204c 72 gr = &hsotg->gr_backup;
d17ee77b 73
95c8bc36
AS		 74 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
75 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
76 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
77 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
78 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
79 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
80 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
81 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
d17ee77b 82 for (i = 0; i < MAX_EPS_CHANNELS; i++)
95c8bc36 83 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
d17ee77b 84
cc1e204c 85 gr->valid = true;
d17ee77b
GH		 86 return 0;
87}
88
89/**
90 * dwc2_restore_global_registers() - Restore controller global registers.
91 * When resuming usb bus, device registers needs to be restored
92 * if controller power were disabled.
93 *
94 * @hsotg: Programming view of the DWC_otg controller
95 */
96static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
97{
98 struct dwc2_gregs_backup *gr;
99 int i;
100
101 dev_dbg(hsotg->dev, "%s\n", __func__);
102
103 /* Restore global regs */
cc1e204c
MYK		 104 gr = &hsotg->gr_backup;
105 if (!gr->valid) {
d17ee77b
GH		 106 dev_err(hsotg->dev, "%s: no global registers to restore\n",
107 __func__);
108 return -EINVAL;
109 }
cc1e204c 110 gr->valid = false;
d17ee77b 111
95c8bc36
AS		 112 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
113 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
114 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
115 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
116 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
117 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
118 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
119 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
120 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
d17ee77b 121 for (i = 0; i < MAX_EPS_CHANNELS; i++)
95c8bc36 122 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
d17ee77b
GH		 123
124 return 0;
125}
126
127/**
128 * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
129 *
130 * @hsotg: Programming view of the DWC_otg controller
131 * @restore: Controller registers need to be restored
132 */
133int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
134{
135 u32 pcgcctl;
136 int ret = 0;
137
285046aa
GH		 138 if (!hsotg->core_params->hibernation)
139 return -ENOTSUPP;
140
95c8bc36 141 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
d17ee77b 142 pcgcctl &= ~PCGCTL_STOPPCLK;
95c8bc36 143 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
d17ee77b 144
95c8bc36 145 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
d17ee77b 146 pcgcctl &= ~PCGCTL_PWRCLMP;
95c8bc36 147 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
d17ee77b 148
95c8bc36 149 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
d17ee77b 150 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
95c8bc36 151 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
d17ee77b
GH		 152
153 udelay(100);
154 if (restore) {
155 ret = dwc2_restore_global_registers(hsotg);
156 if (ret) {
157 dev_err(hsotg->dev, "%s: failed to restore registers\n",
158 __func__);
159 return ret;
160 }
161 if (dwc2_is_host_mode(hsotg)) {
162 ret = dwc2_restore_host_registers(hsotg);
163 if (ret) {
164 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
165 __func__);
166 return ret;
167 }
168 } else {
169 ret = dwc2_restore_device_registers(hsotg);
170 if (ret) {
171 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
172 __func__);
173 return ret;
174 }
175 }
176 }
177
178 return ret;
179}
180
181/**
182 * dwc2_enter_hibernation() - Put controller in Partial Power Down.
183 *
184 * @hsotg: Programming view of the DWC_otg controller
185 */
186int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
187{
188 u32 pcgcctl;
189 int ret = 0;
190
285046aa
GH		 191 if (!hsotg->core_params->hibernation)
192 return -ENOTSUPP;
193
d17ee77b
GH		 194 /* Backup all registers */
195 ret = dwc2_backup_global_registers(hsotg);
196 if (ret) {
197 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
198 __func__);
199 return ret;
200 }
201
202 if (dwc2_is_host_mode(hsotg)) {
203 ret = dwc2_backup_host_registers(hsotg);
204 if (ret) {
205 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
206 __func__);
207 return ret;
208 }
209 } else {
210 ret = dwc2_backup_device_registers(hsotg);
211 if (ret) {
212 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
213 __func__);
214 return ret;
215 }
216 }
217
cad73da2
GH		 218 /*
219 * Clear any pending interrupts since dwc2 will not be able to
220 * clear them after entering hibernation.
221 */
222 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
223
d17ee77b 224 /* Put the controller in low power state */
95c8bc36 225 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
d17ee77b
GH		 226
227 pcgcctl |= PCGCTL_PWRCLMP;
95c8bc36 228 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
d17ee77b
GH		 229 ndelay(20);
230
231 pcgcctl |= PCGCTL_RSTPDWNMODULE;
95c8bc36 232 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
d17ee77b
GH		 233 ndelay(20);
234
235 pcgcctl |= PCGCTL_STOPPCLK;
95c8bc36 236 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
d17ee77b
GH		 237
238 return ret;
239}
240
56f5b1cf
PZ		 241/*
242 * Do core a soft reset of the core. Be careful with this because it
243 * resets all the internal state machines of the core.
244 */
b5d308ab 245int dwc2_core_reset(struct dwc2_hsotg *hsotg)
56f5b1cf
PZ		 246{
247 u32 greset;
248 int count = 0;
249
250 dev_vdbg(hsotg->dev, "%s()\n", __func__);
251
b8ccc593
JY		 252 /* Core Soft Reset */
253 greset = dwc2_readl(hsotg->regs + GRSTCTL);
254 greset |= GRSTCTL_CSFTRST;
255 dwc2_writel(greset, hsotg->regs + GRSTCTL);
56f5b1cf 256 do {
20bde643 257 udelay(1);
95c8bc36 258 greset = dwc2_readl(hsotg->regs + GRSTCTL);
56f5b1cf
PZ		 259 if (++count > 50) {
260 dev_warn(hsotg->dev,
b8ccc593 261 "%s() HANG! Soft Reset GRSTCTL=%0x\n",
56f5b1cf 262 __func__, greset);
beb7e592 263 return -EBUSY;
56f5b1cf 264 }
b8ccc593 265 } while (greset & GRSTCTL_CSFTRST);
56f5b1cf 266
b8ccc593 267 /* Wait for AHB master IDLE state */
56f5b1cf 268 count = 0;
56f5b1cf 269 do {
20bde643 270 udelay(1);
95c8bc36 271 greset = dwc2_readl(hsotg->regs + GRSTCTL);
56f5b1cf
PZ		 272 if (++count > 50) {
273 dev_warn(hsotg->dev,
b8ccc593 274 "%s() HANG! AHB Idle GRSTCTL=%0x\n",
56f5b1cf 275 __func__, greset);
beb7e592 276 return -EBUSY;
56f5b1cf 277 }
b8ccc593 278 } while (!(greset & GRSTCTL_AHBIDLE));
56f5b1cf 279
b5d308ab
JY		 280 return 0;
281}
282
09c96980
JY		 283/*
284 * Force the mode of the controller.
285 *
286 * Forcing the mode is needed for two cases:
287 *
288 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
289 * controller to stay in a particular mode regardless of ID pin
290 * changes. We do this usually after a core reset.
291 *
292 * 2) During probe we want to read reset values of the hw
293 * configuration registers that are only available in either host or
294 * device mode. We may need to force the mode if the current mode does
295 * not allow us to access the register in the mode that we want.
296 *
297 * In either case it only makes sense to force the mode if the
298 * controller hardware is OTG capable.
299 *
300 * Checks are done in this function to determine whether doing a force
301 * would be valid or not.
302 *
303 * If a force is done, it requires a 25ms delay to take effect.
304 *
305 * Returns true if the mode was forced.
306 */
307static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
308{
309 u32 gusbcfg;
310 u32 set;
311 u32 clear;
312
313 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
314
315 /*
316 * Force mode has no effect if the hardware is not OTG.
317 */
318 if (!dwc2_hw_is_otg(hsotg))
319 return false;
320
321 /*
322 * If dr_mode is either peripheral or host only, there is no
323 * need to ever force the mode to the opposite mode.
324 */
325 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
326 return false;
327
328 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
329 return false;
330
331 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
332
333 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
334 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
335
09c96980
JY		 336 gusbcfg &= ~clear;
337 gusbcfg |= set;
338 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
339
340 msleep(25);
341 return true;
342}
343
344/*
345 * Clears the force mode bits.
346 */
347static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
348{
349 u32 gusbcfg;
350
351 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
352 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
353 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
354 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
355
356 /*
357 * NOTE: This long sleep is _very_ important, otherwise the core will
358 * not stay in host mode after a connector ID change!
359 */
97e46388 360 msleep(25);
09c96980
JY		 361}
362
363/*
364 * Sets or clears force mode based on the dr_mode parameter.
365 */
366void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
367{
368 switch (hsotg->dr_mode) {
369 case USB_DR_MODE_HOST:
370 dwc2_force_mode(hsotg, true);
371 break;
372 case USB_DR_MODE_PERIPHERAL:
373 dwc2_force_mode(hsotg, false);
374 break;
375 case USB_DR_MODE_OTG:
376 dwc2_clear_force_mode(hsotg);
377 break;
378 default:
379 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
380 __func__, hsotg->dr_mode);
381 break;
382 }
bd84f4ae
JY		 383
384 /*
385 * NOTE: This is required for some rockchip soc based
386 * platforms.
387 */
388 msleep(50);
09c96980
JY		 389}
390
b5d308ab
JY		 391/*
392 * Do core a soft reset of the core. Be careful with this because it
393 * resets all the internal state machines of the core.
394 *
395 * Additionally this will apply force mode as per the hsotg->dr_mode
396 * parameter.
397 */
398int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
399{
400 int retval;
b5d308ab
JY		 401
402 retval = dwc2_core_reset(hsotg);
403 if (retval)
404 return retval;
405
09c96980 406 dwc2_force_dr_mode(hsotg);
beb7e592 407 return 0;
56f5b1cf
PZ		 408}
409
56f5b1cf
PZ		 410/**
411 * dwc2_dump_host_registers() - Prints the host registers
412 *
413 * @hsotg: Programming view of DWC_otg controller
414 *
415 * NOTE: This function will be removed once the peripheral controller code
416 * is integrated and the driver is stable
417 */
418void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
419{
420#ifdef DEBUG
421 u32 __iomem *addr;
422 int i;
423
424 dev_dbg(hsotg->dev, "Host Global Registers\n");
425 addr = hsotg->regs + HCFG;
426 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
95c8bc36 427 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 428 addr = hsotg->regs + HFIR;
429 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
95c8bc36 430 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 431 addr = hsotg->regs + HFNUM;
432 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
95c8bc36 433 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 434 addr = hsotg->regs + HPTXSTS;
435 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
95c8bc36 436 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 437 addr = hsotg->regs + HAINT;
438 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
95c8bc36 439 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 440 addr = hsotg->regs + HAINTMSK;
441 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
95c8bc36 442 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 443 if (hsotg->core_params->dma_desc_enable > 0) {
444 addr = hsotg->regs + HFLBADDR;
445 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
95c8bc36 446 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 447 }
448
449 addr = hsotg->regs + HPRT0;
450 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
95c8bc36 451 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 452
453 for (i = 0; i < hsotg->core_params->host_channels; i++) {
454 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
455 addr = hsotg->regs + HCCHAR(i);
456 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
95c8bc36 457 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 458 addr = hsotg->regs + HCSPLT(i);
459 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
95c8bc36 460 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 461 addr = hsotg->regs + HCINT(i);
462 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
95c8bc36 463 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 464 addr = hsotg->regs + HCINTMSK(i);
465 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
95c8bc36 466 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 467 addr = hsotg->regs + HCTSIZ(i);
468 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
95c8bc36 469 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 470 addr = hsotg->regs + HCDMA(i);
471 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
95c8bc36 472 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 473 if (hsotg->core_params->dma_desc_enable > 0) {
474 addr = hsotg->regs + HCDMAB(i);
475 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
95c8bc36 476 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 477 }
478 }
479#endif
480}
481
482/**
483 * dwc2_dump_global_registers() - Prints the core global registers
484 *
485 * @hsotg: Programming view of DWC_otg controller
486 *
487 * NOTE: This function will be removed once the peripheral controller code
488 * is integrated and the driver is stable
489 */
490void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
491{
492#ifdef DEBUG
493 u32 __iomem *addr;
56f5b1cf
PZ		 494
495 dev_dbg(hsotg->dev, "Core Global Registers\n");
496 addr = hsotg->regs + GOTGCTL;
497 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
95c8bc36 498 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 499 addr = hsotg->regs + GOTGINT;
500 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
95c8bc36 501 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 502 addr = hsotg->regs + GAHBCFG;
503 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
95c8bc36 504 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 505 addr = hsotg->regs + GUSBCFG;
506 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
95c8bc36 507 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 508 addr = hsotg->regs + GRSTCTL;
509 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
95c8bc36 510 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 511 addr = hsotg->regs + GINTSTS;
512 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
95c8bc36 513 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 514 addr = hsotg->regs + GINTMSK;
515 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
95c8bc36 516 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 517 addr = hsotg->regs + GRXSTSR;
518 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
95c8bc36 519 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 520 addr = hsotg->regs + GRXFSIZ;
521 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
95c8bc36 522 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 523 addr = hsotg->regs + GNPTXFSIZ;
524 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
95c8bc36 525 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 526 addr = hsotg->regs + GNPTXSTS;
527 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
95c8bc36 528 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 529 addr = hsotg->regs + GI2CCTL;
530 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
95c8bc36 531 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 532 addr = hsotg->regs + GPVNDCTL;
533 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
95c8bc36 534 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 535 addr = hsotg->regs + GGPIO;
536 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
95c8bc36 537 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 538 addr = hsotg->regs + GUID;
539 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
95c8bc36 540 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 541 addr = hsotg->regs + GSNPSID;
542 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
95c8bc36 543 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 544 addr = hsotg->regs + GHWCFG1;
545 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
95c8bc36 546 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 547 addr = hsotg->regs + GHWCFG2;
548 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
95c8bc36 549 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 550 addr = hsotg->regs + GHWCFG3;
551 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
95c8bc36 552 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 553 addr = hsotg->regs + GHWCFG4;
554 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
95c8bc36 555 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 556 addr = hsotg->regs + GLPMCFG;
557 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
95c8bc36 558 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 559 addr = hsotg->regs + GPWRDN;
560 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
95c8bc36 561 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 562 addr = hsotg->regs + GDFIFOCFG;
563 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
95c8bc36 564 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 565 addr = hsotg->regs + HPTXFSIZ;
566 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
95c8bc36 567 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf 568
56f5b1cf
PZ		 569 addr = hsotg->regs + PCGCTL;
570 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
95c8bc36 571 (unsigned long)addr, dwc2_readl(addr));
56f5b1cf
PZ		 572#endif
573}
574
575/**
576 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
577 *
578 * @hsotg: Programming view of DWC_otg controller
579 * @num: Tx FIFO to flush
580 */
581void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
582{
583 u32 greset;
584 int count = 0;
585
586 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
587
588 greset = GRSTCTL_TXFFLSH;
589 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
95c8bc36 590 dwc2_writel(greset, hsotg->regs + GRSTCTL);
56f5b1cf
PZ		 591
592 do {
95c8bc36 593 greset = dwc2_readl(hsotg->regs + GRSTCTL);
56f5b1cf
PZ		 594 if (++count > 10000) {
595 dev_warn(hsotg->dev,
596 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
597 __func__, greset,
95c8bc36 598 dwc2_readl(hsotg->regs + GNPTXSTS));
56f5b1cf
PZ		 599 break;
600 }
601 udelay(1);
602 } while (greset & GRSTCTL_TXFFLSH);
603
604 /* Wait for at least 3 PHY Clocks */
605 udelay(1);
606}
607
608/**
609 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
610 *
611 * @hsotg: Programming view of DWC_otg controller
612 */
613void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
614{
615 u32 greset;
616 int count = 0;
617
618 dev_vdbg(hsotg->dev, "%s()\n", __func__);
619
620 greset = GRSTCTL_RXFFLSH;
95c8bc36 621 dwc2_writel(greset, hsotg->regs + GRSTCTL);
56f5b1cf
PZ		 622
623 do {
95c8bc36 624 greset = dwc2_readl(hsotg->regs + GRSTCTL);
56f5b1cf
PZ		 625 if (++count > 10000) {
626 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
627 __func__, greset);
628 break;
629 }
630 udelay(1);
631 } while (greset & GRSTCTL_RXFFLSH);
632
633 /* Wait for at least 3 PHY Clocks */
634 udelay(1);
635}
636
498f0669 637#define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c))
56f5b1cf
PZ		 638
639/* Parameter access functions */
7218dae7 640void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 641{
642 int valid = 1;
56f5b1cf
PZ		 643
644 switch (val) {
645 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
9badec2f 646 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
56f5b1cf
PZ		 647 valid = 0;
648 break;
649 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
9badec2f 650 switch (hsotg->hw_params.op_mode) {
56f5b1cf
PZ		 651 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
652 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
653 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
654 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
655 break;
656 default:
657 valid = 0;
658 break;
659 }
660 break;
661 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
662 /* always valid */
663 break;
664 default:
665 valid = 0;
666 break;
667 }
668
669 if (!valid) {
670 if (val >= 0)
671 dev_err(hsotg->dev,
672 "%d invalid for otg_cap parameter. Check HW configuration.\n",
673 val);
9badec2f 674 switch (hsotg->hw_params.op_mode) {
56f5b1cf
PZ		 675 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
676 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
677 break;
678 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
679 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
680 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
681 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
682 break;
683 default:
684 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
685 break;
686 }
687 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
56f5b1cf
PZ		 688 }
689
690 hsotg->core_params->otg_cap = val;
56f5b1cf
PZ		 691}
692
7218dae7 693void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 694{
695 int valid = 1;
56f5b1cf 696
9badec2f 697 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
56f5b1cf
PZ		 698 valid = 0;
699 if (val < 0)
700 valid = 0;
701
702 if (!valid) {
703 if (val >= 0)
704 dev_err(hsotg->dev,
705 "%d invalid for dma_enable parameter. Check HW configuration.\n",
706 val);
9badec2f 707 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
56f5b1cf 708 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
56f5b1cf
PZ		 709 }
710
711 hsotg->core_params->dma_enable = val;
56f5b1cf
PZ		 712}
713
7218dae7 714void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 715{
716 int valid = 1;
56f5b1cf
PZ		 717
718 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
9badec2f 719 !hsotg->hw_params.dma_desc_enable))
56f5b1cf
PZ		 720 valid = 0;
721 if (val < 0)
722 valid = 0;
723
724 if (!valid) {
725 if (val >= 0)
726 dev_err(hsotg->dev,
727 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
728 val);
729 val = (hsotg->core_params->dma_enable > 0 &&
9badec2f 730 hsotg->hw_params.dma_desc_enable);
56f5b1cf 731 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
56f5b1cf
PZ		 732 }
733
734 hsotg->core_params->dma_desc_enable = val;
56f5b1cf
PZ		 735}
736
fbb9e22b
MYK		 737void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
738{
739 int valid = 1;
740
741 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
742 !hsotg->hw_params.dma_desc_enable))
743 valid = 0;
744 if (val < 0)
745 valid = 0;
746
747 if (!valid) {
748 if (val >= 0)
749 dev_err(hsotg->dev,
750 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
751 val);
752 val = (hsotg->core_params->dma_enable > 0 &&
753 hsotg->hw_params.dma_desc_enable);
754 }
755
756 hsotg->core_params->dma_desc_fs_enable = val;
757 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
758}
759
7218dae7
PZ		 760void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
761 int val)
56f5b1cf 762{
498f0669 763 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 764 if (val >= 0) {
765 dev_err(hsotg->dev,
766 "Wrong value for host_support_fs_low_power\n");
767 dev_err(hsotg->dev,
768 "host_support_fs_low_power must be 0 or 1\n");
769 }
770 val = 0;
771 dev_dbg(hsotg->dev,
772 "Setting host_support_fs_low_power to %d\n", val);
56f5b1cf
PZ		 773 }
774
775 hsotg->core_params->host_support_fs_ls_low_power = val;
56f5b1cf
PZ		 776}
777
7218dae7 778void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 779{
780 int valid = 1;
56f5b1cf 781
9badec2f 782 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
56f5b1cf
PZ		 783 valid = 0;
784 if (val < 0)
785 valid = 0;
786
787 if (!valid) {
788 if (val >= 0)
789 dev_err(hsotg->dev,
790 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
791 val);
9badec2f 792 val = hsotg->hw_params.enable_dynamic_fifo;
56f5b1cf 793 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
56f5b1cf
PZ		 794 }
795
796 hsotg->core_params->enable_dynamic_fifo = val;
56f5b1cf
PZ		 797}
798
7218dae7 799void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 800{
801 int valid = 1;
56f5b1cf 802
9badec2f 803 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
56f5b1cf
PZ		 804 valid = 0;
805
806 if (!valid) {
807 if (val >= 0)
808 dev_err(hsotg->dev,
809 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
810 val);
9badec2f 811 val = hsotg->hw_params.host_rx_fifo_size;
56f5b1cf 812 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
56f5b1cf
PZ		 813 }
814
815 hsotg->core_params->host_rx_fifo_size = val;
56f5b1cf
PZ		 816}
817
7218dae7 818void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 819{
820 int valid = 1;
56f5b1cf 821
9badec2f 822 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
56f5b1cf
PZ		 823 valid = 0;
824
825 if (!valid) {
826 if (val >= 0)
827 dev_err(hsotg->dev,
828 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
829 val);
9badec2f 830 val = hsotg->hw_params.host_nperio_tx_fifo_size;
56f5b1cf
PZ		 831 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
832 val);
56f5b1cf
PZ		 833 }
834
835 hsotg->core_params->host_nperio_tx_fifo_size = val;
56f5b1cf
PZ		 836}
837
7218dae7 838void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 839{
840 int valid = 1;
56f5b1cf 841
9badec2f 842 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
56f5b1cf
PZ		 843 valid = 0;
844
845 if (!valid) {
846 if (val >= 0)
847 dev_err(hsotg->dev,
848 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
849 val);
9badec2f 850 val = hsotg->hw_params.host_perio_tx_fifo_size;
56f5b1cf
PZ		 851 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
852 val);
56f5b1cf
PZ		 853 }
854
855 hsotg->core_params->host_perio_tx_fifo_size = val;
56f5b1cf
PZ		 856}
857
7218dae7 858void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 859{
860 int valid = 1;
56f5b1cf 861
9badec2f 862 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
56f5b1cf
PZ		 863 valid = 0;
864
865 if (!valid) {
866 if (val >= 0)
867 dev_err(hsotg->dev,
868 "%d invalid for max_transfer_size. Check HW configuration.\n",
869 val);
9badec2f 870 val = hsotg->hw_params.max_transfer_size;
56f5b1cf 871 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
56f5b1cf
PZ		 872 }
873
874 hsotg->core_params->max_transfer_size = val;
56f5b1cf
PZ		 875}
876
7218dae7 877void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 878{
879 int valid = 1;
56f5b1cf 880
9badec2f 881 if (val < 15 || val > hsotg->hw_params.max_packet_count)
56f5b1cf
PZ		 882 valid = 0;
883
884 if (!valid) {
885 if (val >= 0)
886 dev_err(hsotg->dev,
887 "%d invalid for max_packet_count. Check HW configuration.\n",
888 val);
9badec2f 889 val = hsotg->hw_params.max_packet_count;
56f5b1cf 890 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
56f5b1cf
PZ		 891 }
892
893 hsotg->core_params->max_packet_count = val;
56f5b1cf
PZ		 894}
895
7218dae7 896void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 897{
898 int valid = 1;
56f5b1cf 899
9badec2f 900 if (val < 1 || val > hsotg->hw_params.host_channels)
56f5b1cf
PZ		 901 valid = 0;
902
903 if (!valid) {
904 if (val >= 0)
905 dev_err(hsotg->dev,
906 "%d invalid for host_channels. Check HW configuration.\n",
907 val);
9badec2f 908 val = hsotg->hw_params.host_channels;
56f5b1cf 909 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
56f5b1cf
PZ		 910 }
911
912 hsotg->core_params->host_channels = val;
56f5b1cf
PZ		 913}
914
7218dae7 915void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
56f5b1cf 916{
56f5b1cf 917 int valid = 0;
0464a3d2 918 u32 hs_phy_type, fs_phy_type;
56f5b1cf 919
498f0669
PZ		 920 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
921 DWC2_PHY_TYPE_PARAM_ULPI)) {
56f5b1cf
PZ		 922 if (val >= 0) {
923 dev_err(hsotg->dev, "Wrong value for phy_type\n");
924 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
925 }
926
56f5b1cf 927 valid = 0;
56f5b1cf
PZ		 928 }
929
9badec2f
MK		 930 hs_phy_type = hsotg->hw_params.hs_phy_type;
931 fs_phy_type = hsotg->hw_params.fs_phy_type;
56f5b1cf
PZ		 932 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
933 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
934 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
935 valid = 1;
936 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
937 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
938 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
939 valid = 1;
940 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
941 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
942 valid = 1;
943
944 if (!valid) {
945 if (val >= 0)
946 dev_err(hsotg->dev,
947 "%d invalid for phy_type. Check HW configuration.\n",
948 val);
929aea09 949 val = DWC2_PHY_TYPE_PARAM_FS;
56f5b1cf
PZ		 950 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
951 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
952 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
953 val = DWC2_PHY_TYPE_PARAM_UTMI;
954 else
955 val = DWC2_PHY_TYPE_PARAM_ULPI;
956 }
957 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
56f5b1cf 958 }
56f5b1cf
PZ		 959
960 hsotg->core_params->phy_type = val;
56f5b1cf
PZ		 961}
962
963static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
964{
965 return hsotg->core_params->phy_type;
966}
967
7218dae7 968void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 969{
970 int valid = 1;
56f5b1cf 971
498f0669 972 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 973 if (val >= 0) {
974 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
975 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
976 }
977 valid = 0;
978 }
979
929aea09
MK		 980 if (val == DWC2_SPEED_PARAM_HIGH &&
981 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
56f5b1cf
PZ		 982 valid = 0;
983
984 if (!valid) {
985 if (val >= 0)
986 dev_err(hsotg->dev,
987 "%d invalid for speed parameter. Check HW configuration.\n",
988 val);
989 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
929aea09 990 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
56f5b1cf 991 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
56f5b1cf
PZ		 992 }
993
994 hsotg->core_params->speed = val;
56f5b1cf
PZ		 995}
996
7218dae7 997void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 998{
999 int valid = 1;
56f5b1cf 1000
498f0669
PZ		 1001 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
1002 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
56f5b1cf
PZ		 1003 if (val >= 0) {
1004 dev_err(hsotg->dev,
1005 "Wrong value for host_ls_low_power_phy_clk parameter\n");
1006 dev_err(hsotg->dev,
1007 "host_ls_low_power_phy_clk must be 0 or 1\n");
1008 }
1009 valid = 0;
1010 }
1011
1012 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
1013 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
1014 valid = 0;
1015
1016 if (!valid) {
1017 if (val >= 0)
1018 dev_err(hsotg->dev,
1019 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
1020 val);
1021 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
1022 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
1023 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
1024 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
1025 val);
56f5b1cf
PZ		 1026 }
1027
1028 hsotg->core_params->host_ls_low_power_phy_clk = val;
56f5b1cf
PZ		 1029}
1030
7218dae7 1031void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
56f5b1cf 1032{
498f0669 1033 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 1034 if (val >= 0) {
1035 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
1036 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
1037 }
1038 val = 0;
1039 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
56f5b1cf
PZ		 1040 }
1041
1042 hsotg->core_params->phy_ulpi_ddr = val;
56f5b1cf
PZ		 1043}
1044
7218dae7 1045void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
56f5b1cf 1046{
498f0669 1047 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 1048 if (val >= 0) {
1049 dev_err(hsotg->dev,
1050 "Wrong value for phy_ulpi_ext_vbus\n");
1051 dev_err(hsotg->dev,
1052 "phy_ulpi_ext_vbus must be 0 or 1\n");
1053 }
1054 val = 0;
1055 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
56f5b1cf
PZ		 1056 }
1057
1058 hsotg->core_params->phy_ulpi_ext_vbus = val;
56f5b1cf
PZ		 1059}
1060
7218dae7 1061void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
56f5b1cf 1062{
de4a1931 1063 int valid = 0;
56f5b1cf 1064
de4a1931
MK		 1065 switch (hsotg->hw_params.utmi_phy_data_width) {
1066 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
1067 valid = (val == 8);
1068 break;
1069 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
1070 valid = (val == 16);
1071 break;
1072 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
1073 valid = (val == 8 || val == 16);
1074 break;
1075 }
1076
1077 if (!valid) {
56f5b1cf 1078 if (val >= 0) {
de4a1931
MK		 1079 dev_err(hsotg->dev,
1080 "%d invalid for phy_utmi_width. Check HW configuration.\n",
1081 val);
56f5b1cf 1082 }
de4a1931
MK		 1083 val = (hsotg->hw_params.utmi_phy_data_width ==
1084 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
56f5b1cf 1085 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
56f5b1cf
PZ		 1086 }
1087
1088 hsotg->core_params->phy_utmi_width = val;
56f5b1cf
PZ		 1089}
1090
7218dae7 1091void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
56f5b1cf 1092{
498f0669 1093 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 1094 if (val >= 0) {
1095 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
1096 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
1097 }
1098 val = 0;
1099 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
56f5b1cf
PZ		 1100 }
1101
1102 hsotg->core_params->ulpi_fs_ls = val;
56f5b1cf
PZ		 1103}
1104
7218dae7 1105void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
56f5b1cf 1106{
498f0669 1107 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 1108 if (val >= 0) {
1109 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
1110 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
1111 }
1112 val = 0;
1113 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
56f5b1cf
PZ		 1114 }
1115
1116 hsotg->core_params->ts_dline = val;
56f5b1cf
PZ		 1117}
1118
7218dae7 1119void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
56f5b1cf 1120{
56f5b1cf 1121 int valid = 1;
56f5b1cf 1122
498f0669 1123 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 1124 if (val >= 0) {
1125 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
1126 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
1127 }
1128
56f5b1cf 1129 valid = 0;
56f5b1cf
PZ		 1130 }
1131
9badec2f 1132 if (val == 1 && !(hsotg->hw_params.i2c_enable))
56f5b1cf
PZ		 1133 valid = 0;
1134
1135 if (!valid) {
1136 if (val >= 0)
1137 dev_err(hsotg->dev,
1138 "%d invalid for i2c_enable. Check HW configuration.\n",
1139 val);
9badec2f 1140 val = hsotg->hw_params.i2c_enable;
56f5b1cf 1141 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
56f5b1cf 1142 }
56f5b1cf
PZ		 1143
1144 hsotg->core_params->i2c_enable = val;
56f5b1cf
PZ		 1145}
1146
7218dae7 1147void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 1148{
1149 int valid = 1;
56f5b1cf 1150
498f0669 1151 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 1152 if (val >= 0) {
1153 dev_err(hsotg->dev,
1154 "Wrong value for en_multiple_tx_fifo,\n");
1155 dev_err(hsotg->dev,
1156 "en_multiple_tx_fifo must be 0 or 1\n");
1157 }
1158 valid = 0;
1159 }
1160
9badec2f 1161 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
56f5b1cf
PZ		 1162 valid = 0;
1163
1164 if (!valid) {
1165 if (val >= 0)
1166 dev_err(hsotg->dev,
1167 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
1168 val);
9badec2f 1169 val = hsotg->hw_params.en_multiple_tx_fifo;
56f5b1cf 1170 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
56f5b1cf
PZ		 1171 }
1172
1173 hsotg->core_params->en_multiple_tx_fifo = val;
56f5b1cf
PZ		 1174}
1175
7218dae7 1176void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
56f5b1cf
PZ		 1177{
1178 int valid = 1;
56f5b1cf 1179
498f0669 1180 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 1181 if (val >= 0) {
1182 dev_err(hsotg->dev,
1183 "'%d' invalid for parameter reload_ctl\n", val);
1184 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
1185 }
1186 valid = 0;
1187 }
1188
9badec2f 1189 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
56f5b1cf
PZ		 1190 valid = 0;
1191
1192 if (!valid) {
1193 if (val >= 0)
1194 dev_err(hsotg->dev,
1195 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
1196 val);
9badec2f 1197 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
56f5b1cf 1198 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
56f5b1cf
PZ		 1199 }
1200
1201 hsotg->core_params->reload_ctl = val;
56f5b1cf
PZ		 1202}
1203
7218dae7 1204void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
56f5b1cf 1205{
4d3190e1
PZ		 1206 if (val != -1)
1207 hsotg->core_params->ahbcfg = val;
1208 else
f9234633 1209 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
0464a3d2 1210 GAHBCFG_HBSTLEN_SHIFT;
56f5b1cf
PZ		 1211}
1212
7218dae7 1213void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
56f5b1cf 1214{
498f0669 1215 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
56f5b1cf
PZ		 1216 if (val >= 0) {
1217 dev_err(hsotg->dev,
1218 "'%d' invalid for parameter otg_ver\n", val);
1219 dev_err(hsotg->dev,
1220 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
1221 }
1222 val = 0;
1223 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
56f5b1cf
PZ		 1224 }
1225
1226 hsotg->core_params->otg_ver = val;
56f5b1cf
PZ		 1227}
1228
49cf10c6 1229static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
e8576e68
PZ		 1230{
1231 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1232 if (val >= 0) {
1233 dev_err(hsotg->dev,
1234 "'%d' invalid for parameter uframe_sched\n",
1235 val);
1236 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
1237 }
1238 val = 1;
1239 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
1240 }
1241
1242 hsotg->core_params->uframe_sched = val;
1243}
1244
a6d249d8
GH		 1245static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
1246 int val)
1247{
1248 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1249 if (val >= 0) {
1250 dev_err(hsotg->dev,
1251 "'%d' invalid for parameter external_id_pin_ctl\n",
1252 val);
1253 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
1254 }
1255 val = 0;
1256 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
1257 }
1258
1259 hsotg->core_params->external_id_pin_ctl = val;
1260}
1261
285046aa
GH		 1262static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
1263 int val)
1264{
1265 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1266 if (val >= 0) {
1267 dev_err(hsotg->dev,
1268 "'%d' invalid for parameter hibernation\n",
1269 val);
1270 dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
1271 }
1272 val = 0;
1273 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
1274 }
1275
1276 hsotg->core_params->hibernation = val;
1277}
1278
e8576e68
PZ		 1279/*
1280 * This function is called during module intialization to pass module parameters
1281 * for the DWC_otg core.
1282 */
1283void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1284 const struct dwc2_core_params *params)
1285{
1286 dev_dbg(hsotg->dev, "%s()\n", __func__);
1287
1288 dwc2_set_param_otg_cap(hsotg, params->otg_cap);
1289 dwc2_set_param_dma_enable(hsotg, params->dma_enable);
1290 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
fbb9e22b 1291 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
e8576e68
PZ		 1292 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
1293 params->host_support_fs_ls_low_power);
1294 dwc2_set_param_enable_dynamic_fifo(hsotg,
1295 params->enable_dynamic_fifo);
1296 dwc2_set_param_host_rx_fifo_size(hsotg,
1297 params->host_rx_fifo_size);
1298 dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
1299 params->host_nperio_tx_fifo_size);
1300 dwc2_set_param_host_perio_tx_fifo_size(hsotg,
1301 params->host_perio_tx_fifo_size);
1302 dwc2_set_param_max_transfer_size(hsotg,
1303 params->max_transfer_size);
1304 dwc2_set_param_max_packet_count(hsotg,
1305 params->max_packet_count);
1306 dwc2_set_param_host_channels(hsotg, params->host_channels);
1307 dwc2_set_param_phy_type(hsotg, params->phy_type);
1308 dwc2_set_param_speed(hsotg, params->speed);
1309 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
1310 params->host_ls_low_power_phy_clk);
1311 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
1312 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
1313 params->phy_ulpi_ext_vbus);
1314 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
1315 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
1316 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
1317 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
1318 dwc2_set_param_en_multiple_tx_fifo(hsotg,
1319 params->en_multiple_tx_fifo);
1320 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
1321 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
1322 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
1323 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
a6d249d8 1324 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
285046aa 1325 dwc2_set_param_hibernation(hsotg, params->hibernation);
e8576e68
PZ		 1326}
1327
09c96980
JY		 1328/*
1329 * Forces either host or device mode if the controller is not
1330 * currently in that mode.
1331 *
1332 * Returns true if the mode was forced.
1333 */
1334static bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
1335{
1336 if (host && dwc2_is_host_mode(hsotg))
1337 return false;
1338 else if (!host && dwc2_is_device_mode(hsotg))
1339 return false;
1340
1341 return dwc2_force_mode(hsotg, host);
1342}
1343
55e1040e
JY		 1344/*
1345 * Gets host hardware parameters. Forces host mode if not currently in
1346 * host mode. Should be called immediately after a core soft reset in
1347 * order to get the reset values.
1348 */
1349static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
1350{
1351 struct dwc2_hw_params *hw = &hsotg->hw_params;
1352 u32 gnptxfsiz;
1353 u32 hptxfsiz;
1354 bool forced;
1355
1356 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
1357 return;
1358
1359 forced = dwc2_force_mode_if_needed(hsotg, true);
1360
1361 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1362 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
1363 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1364 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
1365
1366 if (forced)
1367 dwc2_clear_force_mode(hsotg);
1368
1369 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1370 FIFOSIZE_DEPTH_SHIFT;
1371 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1372 FIFOSIZE_DEPTH_SHIFT;
1373}
1374
1375/*
1376 * Gets device hardware parameters. Forces device mode if not
1377 * currently in device mode. Should be called immediately after a core
1378 * soft reset in order to get the reset values.
1379 */
1380static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
1381{
1382 struct dwc2_hw_params *hw = &hsotg->hw_params;
1383 bool forced;
1384 u32 gnptxfsiz;
1385
1386 if (hsotg->dr_mode == USB_DR_MODE_HOST)
1387 return;
1388
1389 forced = dwc2_force_mode_if_needed(hsotg, false);
1390
1391 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1392 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1393
1394 if (forced)
1395 dwc2_clear_force_mode(hsotg);
1396
1397 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1398 FIFOSIZE_DEPTH_SHIFT;
1399}
1400
9badec2f
MK		 1401/**
1402 * During device initialization, read various hardware configuration
1403 * registers and interpret the contents.
1404 */
1405int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
1406{
1407 struct dwc2_hw_params *hw = &hsotg->hw_params;
1408 unsigned width;
1409 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
55e1040e 1410 u32 grxfsiz;
9badec2f
MK		 1411
1412 /*
1413 * Attempt to ensure this device is really a DWC_otg Controller.
1414 * Read and verify the GSNPSID register contents. The value should be
1415 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
1416 * as in "OTG version 2.xx" or "OTG version 3.xx".
1417 */
95c8bc36 1418 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
9badec2f
MK		 1419 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
1420 (hw->snpsid & 0xfffff000) != 0x4f543000) {
1421 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
1422 hw->snpsid);
1423 return -ENODEV;
1424 }
1425
1426 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
1427 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
1428 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
1429
95c8bc36
AS		 1430 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
1431 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
1432 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
1433 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
1434 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
9badec2f
MK		 1435
1436 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
1437 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
1438 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
1439 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
9badec2f
MK		 1440 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
1441
55e1040e
JY		 1442 /*
1443 * Host specific hardware parameters. Reading these parameters
1444 * requires the controller to be in host mode. The mode will
1445 * be forced, if necessary, to read these values.
1446 */
1447 dwc2_get_host_hwparams(hsotg);
1448 dwc2_get_dev_hwparams(hsotg);
9badec2f 1449
55e1040e
JY		 1450 /* hwcfg1 */
1451 hw->dev_ep_dirs = hwcfg1;
9badec2f
MK		 1452
1453 /* hwcfg2 */
1454 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
1455 GHWCFG2_OP_MODE_SHIFT;
1456 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
1457 GHWCFG2_ARCHITECTURE_SHIFT;
1458 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
1459 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
1460 GHWCFG2_NUM_HOST_CHAN_SHIFT);
1461 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
1462 GHWCFG2_HS_PHY_TYPE_SHIFT;
1463 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
1464 GHWCFG2_FS_PHY_TYPE_SHIFT;
1465 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
1466 GHWCFG2_NUM_DEV_EP_SHIFT;
1467 hw->nperio_tx_q_depth =
1468 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
1469 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
1470 hw->host_perio_tx_q_depth =
1471 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
1472 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
1473 hw->dev_token_q_depth =
1474 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
1475 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
1476
1477 /* hwcfg3 */
1478 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
1479 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
1480 hw->max_transfer_size = (1 << (width + 11)) - 1;
1481 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
1482 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
1483 hw->max_packet_count = (1 << (width + 4)) - 1;
1484 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
1485 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
1486 GHWCFG3_DFIFO_DEPTH_SHIFT;
1487
1488 /* hwcfg4 */
1489 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
1490 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
1491 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
1492 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
1493 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
de4a1931
MK		 1494 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
1495 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
9badec2f
MK		 1496
1497 /* fifo sizes */
1498 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
1499 GRXFSIZ_DEPTH_SHIFT;
9badec2f
MK		 1500
1501 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
1502 dev_dbg(hsotg->dev, " op_mode=%d\n",
1503 hw->op_mode);
1504 dev_dbg(hsotg->dev, " arch=%d\n",
1505 hw->arch);
1506 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
1507 hw->dma_desc_enable);
1508 dev_dbg(hsotg->dev, " power_optimized=%d\n",
1509 hw->power_optimized);
1510 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
1511 hw->i2c_enable);
1512 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
1513 hw->hs_phy_type);
1514 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
1515 hw->fs_phy_type);
971bd8fa 1516 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
de4a1931 1517 hw->utmi_phy_data_width);
9badec2f
MK		 1518 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
1519 hw->num_dev_ep);
1520 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
1521 hw->num_dev_perio_in_ep);
1522 dev_dbg(hsotg->dev, " host_channels=%d\n",
1523 hw->host_channels);
1524 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
1525 hw->max_transfer_size);
1526 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
1527 hw->max_packet_count);
1528 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
1529 hw->nperio_tx_q_depth);
1530 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
1531 hw->host_perio_tx_q_depth);
1532 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
1533 hw->dev_token_q_depth);
1534 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
1535 hw->enable_dynamic_fifo);
1536 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
1537 hw->en_multiple_tx_fifo);
1538 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
1539 hw->total_fifo_size);
1540 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n",
1541 hw->host_rx_fifo_size);
1542 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
1543 hw->host_nperio_tx_fifo_size);
1544 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
1545 hw->host_perio_tx_fifo_size);
1546 dev_dbg(hsotg->dev, "\n");
1547
1548 return 0;
1549}
ecb176c6
MYK		 1550
1551/*
1552 * Sets all parameters to the given value.
1553 *
1554 * Assumes that the dwc2_core_params struct contains only integers.
1555 */
1556void dwc2_set_all_params(struct dwc2_core_params *params, int value)
1557{
1558 int *p = (int *)params;
1559 size_t size = sizeof(*params) / sizeof(*p);
1560 int i;
1561
1562 for (i = 0; i < size; i++)
1563 p[i] = value;
1564}
ecb176c6 1565
9badec2f 1566
56f5b1cf
PZ		 1567u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
1568{
b66a3f05 1569 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;
56f5b1cf
PZ		 1570}
1571
057715f2 1572bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
56f5b1cf 1573{
95c8bc36 1574 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
057715f2 1575 return false;
56f5b1cf 1576 else
057715f2 1577 return true;
56f5b1cf
PZ		 1578}
1579
1580/**
1581 * dwc2_enable_global_interrupts() - Enables the controller's Global
1582 * Interrupt in the AHB Config register
1583 *
1584 * @hsotg: Programming view of DWC_otg controller
1585 */
1586void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
1587{
95c8bc36 1588 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
56f5b1cf
PZ		 1589
1590 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
95c8bc36 1591 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
56f5b1cf
PZ		 1592}
1593
1594/**
1595 * dwc2_disable_global_interrupts() - Disables the controller's Global
1596 * Interrupt in the AHB Config register
1597 *
1598 * @hsotg: Programming view of DWC_otg controller
1599 */
1600void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
1601{
95c8bc36 1602 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
56f5b1cf
PZ		 1603
1604 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
95c8bc36 1605 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
56f5b1cf
PZ		 1606}
1607
6bea9620
JY		 1608/* Returns the controller's GHWCFG2.OTG_MODE. */
1609unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg)
1610{
1611 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
1612
1613 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
1614 GHWCFG2_OP_MODE_SHIFT;
1615}
1616
1617/* Returns true if the controller is capable of DRD. */
1618bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
1619{
1620 unsigned op_mode = dwc2_op_mode(hsotg);
1621
1622 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
1623 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
1624 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
1625}
1626
1627/* Returns true if the controller is host-only. */
1628bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
1629{
1630 unsigned op_mode = dwc2_op_mode(hsotg);
1631
1632 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
1633 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
1634}
1635
1636/* Returns true if the controller is device-only. */
1637bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
1638{
1639 unsigned op_mode = dwc2_op_mode(hsotg);
1640
1641 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
1642 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
1643}
1644
56f5b1cf
PZ		 1645MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1646MODULE_AUTHOR("Synopsys, Inc.");
1647MODULE_LICENSE("Dual BSD/GPL");
Linux kernel - Deliverables
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