[deliverable/linux.git] / drivers / usb / dwc3 / core.c

/**
 * core.c - DesignWare USB3 DRD Controller Core file
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>

#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/module.h>

#include "core.h"
#include "gadget.h"
#include "io.h"

#include "debug.h"

static char *maximum_speed = "super";
module_param(maximum_speed, charp, 0);
MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");

/**
 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 * @dwc: pointer to our context structure
 */
static void dwc3_core_soft_reset(struct dwc3 *dwc)
{
	u32		reg;

	/* Before Resetting PHY, put Core in Reset */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg |= DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	/* Assert USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Assert USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	mdelay(100);

	/* Clear USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Clear USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	/* After PHYs are stable we can take Core out of reset state */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_free_one_event_buffer - Frees one event buffer
 * @dwc: Pointer to our controller context structure
 * @evt: Pointer to event buffer to be freed
 */
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
		struct dwc3_event_buffer *evt)
{
	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
	kfree(evt);
}

/**
 * dwc3_alloc_one_event_buffer - Allocated one event buffer structure
 * @dwc: Pointer to our controller context structure
 * @length: size of the event buffer
 *
 * Returns a pointer to the allocated event buffer structure on succes
 * otherwise ERR_PTR(errno).
 */
static struct dwc3_event_buffer *__devinit
dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
{
	struct dwc3_event_buffer	*evt;

	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
	if (!evt)
		return ERR_PTR(-ENOMEM);

	evt->dwc	= dwc;
	evt->length	= length;
	evt->buf	= dma_alloc_coherent(dwc->dev, length,
			&evt->dma, GFP_KERNEL);
	if (!evt->buf) {
		kfree(evt);
		return ERR_PTR(-ENOMEM);
	}

	return evt;
}

/**
 * dwc3_free_event_buffers - frees all allocated event buffers
 * @dwc: Pointer to our controller context structure
 */
static void dwc3_free_event_buffers(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int i;

	for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
		evt = dwc->ev_buffs[i];
		if (evt) {
			dwc3_free_one_event_buffer(dwc, evt);
			dwc->ev_buffs[i] = NULL;
		}
	}
}

/**
 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 * @dwc: Pointer to out controller context structure
 * @num: number of event buffers to allocate
 * @length: size of event buffer
 *
 * Returns 0 on success otherwise negative errno. In error the case, dwc
 * may contain some buffers allocated but not all which were requested.
 */
static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned num,
		unsigned length)
{
	int			i;

	for (i = 0; i < num; i++) {
		struct dwc3_event_buffer	*evt;

		evt = dwc3_alloc_one_event_buffer(dwc, length);
		if (IS_ERR(evt)) {
			dev_err(dwc->dev, "can't allocate event buffer\n");
			return PTR_ERR(evt);
		}
		dwc->ev_buffs[i] = evt;
	}

	return 0;
}

/**
 * dwc3_event_buffers_setup - setup our allocated event buffers
 * @dwc: Pointer to out controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
		evt = dwc->ev_buffs[n];
		dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
				evt->buf, (unsigned long long) evt->dma,
				evt->length);

		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
				lower_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
				upper_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
				evt->length & 0xffff);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}

	return 0;
}

static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
		evt = dwc->ev_buffs[n];
		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}
}

static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
{
	struct dwc3_hwparams	*parms = &dwc->hwparams;

	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
}

/**
 * dwc3_core_init - Low-level initialization of DWC3 Core
 * @dwc: Pointer to our controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int __devinit dwc3_core_init(struct dwc3 *dwc)
{
	unsigned long		timeout;
	u32			reg;
	int			ret;

	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	/* This should read as U3 followed by revision number */
	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
		ret = -ENODEV;
		goto err0;
	}
	dwc->revision = reg & DWC3_GSNPSREV_MASK;

	dwc3_core_soft_reset(dwc);

	/* issue device SoftReset too */
	timeout = jiffies + msecs_to_jiffies(500);
	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	do {
		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
		if (!(reg & DWC3_DCTL_CSFTRST))
			break;

		if (time_after(jiffies, timeout)) {
			dev_err(dwc->dev, "Reset Timed Out\n");
			ret = -ETIMEDOUT;
			goto err0;
		}

		cpu_relax();
	} while (true);

	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_NUM,
			DWC3_EVENT_BUFFERS_SIZE);
	if (ret) {
		dev_err(dwc->dev, "failed to allocate event buffers\n");
		ret = -ENOMEM;
		goto err1;
	}

	ret = dwc3_event_buffers_setup(dwc);
	if (ret) {
		dev_err(dwc->dev, "failed to setup event buffers\n");
		goto err1;
	}

	dwc3_cache_hwparams(dwc);

	return 0;

err1:
	dwc3_free_event_buffers(dwc);

err0:
	return ret;
}

static void dwc3_core_exit(struct dwc3 *dwc)
{
	dwc3_event_buffers_cleanup(dwc);
	dwc3_free_event_buffers(dwc);
}

#define DWC3_ALIGN_MASK		(16 - 1)

static int __devinit dwc3_probe(struct platform_device *pdev)
{
	const struct platform_device_id *id = platform_get_device_id(pdev);
	struct resource		*res;
	struct dwc3		*dwc;
	void __iomem		*regs;
	unsigned int		features = id->driver_data;
	int			ret = -ENOMEM;
	int			irq;
	void			*mem;

	mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
	if (!mem) {
		dev_err(&pdev->dev, "not enough memory\n");
		goto err0;
	}
	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	dwc->mem = mem;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "missing resource\n");
		goto err1;
	}

	res = request_mem_region(res->start, resource_size(res),
			dev_name(&pdev->dev));
	if (!res) {
		dev_err(&pdev->dev, "can't request mem region\n");
		goto err1;
	}

	regs = ioremap(res->start, resource_size(res));
	if (!regs) {
		dev_err(&pdev->dev, "ioremap failed\n");
		goto err2;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "missing IRQ\n");
		goto err3;
	}

	spin_lock_init(&dwc->lock);
	platform_set_drvdata(pdev, dwc);

	dwc->regs	= regs;
	dwc->regs_size	= resource_size(res);
	dwc->dev	= &pdev->dev;
	dwc->irq	= irq;

	if (!strncmp("super", maximum_speed, 5))
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	else if (!strncmp("high", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	else if (!strncmp("full", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	else if (!strncmp("low", maximum_speed, 3))
		dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	else
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_forbid(&pdev->dev);

	ret = dwc3_core_init(dwc);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize core\n");
		goto err3;
	}

	if (features & DWC3_HAS_PERIPHERAL) {
		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(&pdev->dev, "failed to initialized gadget\n");
			goto err4;
		}
	}

	ret = dwc3_debugfs_init(dwc);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize debugfs\n");
		goto err5;
	}

	pm_runtime_allow(&pdev->dev);

	return 0;

err5:
	if (features & DWC3_HAS_PERIPHERAL)
		dwc3_gadget_exit(dwc);

err4:
	dwc3_core_exit(dwc);

err3:
	iounmap(regs);

err2:
	release_mem_region(res->start, resource_size(res));

err1:
	kfree(dwc->mem);

err0:
	return ret;
}

static int __devexit dwc3_remove(struct platform_device *pdev)
{
	const struct platform_device_id *id = platform_get_device_id(pdev);
	struct dwc3	*dwc = platform_get_drvdata(pdev);
	struct resource	*res;
	unsigned int	features = id->driver_data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	dwc3_debugfs_exit(dwc);

	if (features & DWC3_HAS_PERIPHERAL)
		dwc3_gadget_exit(dwc);

	dwc3_core_exit(dwc);
	release_mem_region(res->start, resource_size(res));
	iounmap(dwc->regs);
	kfree(dwc->mem);

	return 0;
}

static const struct platform_device_id dwc3_id_table[] __devinitconst = {
	{
		.name	= "dwc3-omap",
		.driver_data = (DWC3_HAS_PERIPHERAL
			| DWC3_HAS_XHCI
			| DWC3_HAS_OTG),
	},
	{
		.name	= "dwc3-pci",
		.driver_data = DWC3_HAS_PERIPHERAL,
	},
	{  },	/* Terminating Entry */
};
MODULE_DEVICE_TABLE(platform, dwc3_id_table);

static struct platform_driver dwc3_driver = {
	.probe		= dwc3_probe,
	.remove		= __devexit_p(dwc3_remove),
	.driver		= {
		.name	= "dwc3",
	},
	.id_table	= dwc3_id_table,
};

MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");

static int __devinit dwc3_init(void)
{
	return platform_driver_register(&dwc3_driver);
}
module_init(dwc3_init);

static void __exit dwc3_exit(void)
{
	platform_driver_unregister(&dwc3_driver);
}
module_exit(dwc3_exit);
Commit	Line	Data
72246da4 FB	1	/**
	2	* core.c - DesignWare USB3 DRD Controller Core file
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
	9	* Redistribution and use in source and binary forms, with or without
	10	* modification, are permitted provided that the following conditions
	11	* are met:
	12	* 1. Redistributions of source code must retain the above copyright
	13	* notice, this list of conditions, and the following disclaimer,
	14	* without modification.
	15	* 2. Redistributions in binary form must reproduce the above copyright
	16	* notice, this list of conditions and the following disclaimer in the
	17	* documentation and/or other materials provided with the distribution.
	18	* 3. The names of the above-listed copyright holders may not be used
	19	* to endorse or promote products derived from this software without
	20	* specific prior written permission.
	21	*
	22	* ALTERNATIVELY, this software may be distributed under the terms of the
	23	* GNU General Public License ("GPL") version 2, as published by the Free
	24	* Software Foundation.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	27	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	28	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	29	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	30	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	31	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	32	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	33	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	34	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	35	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	36	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	*/
	38
a72e658b	39	#include <linux/module.h>
72246da4 FB	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/platform_device.h>
	44	#include <linux/pm_runtime.h>
	45	#include <linux/interrupt.h>
	46	#include <linux/ioport.h>
	47	#include <linux/io.h>
	48	#include <linux/list.h>
	49	#include <linux/delay.h>
	50	#include <linux/dma-mapping.h>
	51
	52	#include <linux/usb/ch9.h>
	53	#include <linux/usb/gadget.h>
2204fdee	54	#include <linux/module.h>
72246da4 FB	55
	56	#include "core.h"
	57	#include "gadget.h"
	58	#include "io.h"
	59
	60	#include "debug.h"
	61
6c167fc9 FB	62	static char *maximum_speed = "super";
	63	module_param(maximum_speed, charp, 0);
	64	MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
	65
72246da4 FB	66	/**
	67	* dwc3_core_soft_reset - Issues core soft reset and PHY reset
	68	* @dwc: pointer to our context structure
	69	*/
	70	static void dwc3_core_soft_reset(struct dwc3 *dwc)
	71	{
	72	u32 reg;
	73
	74	/* Before Resetting PHY, put Core in Reset */
	75	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	76	reg \|= DWC3_GCTL_CORESOFTRESET;
	77	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	78
	79	/* Assert USB3 PHY reset */
	80	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	81	reg \|= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	82	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	83
	84	/* Assert USB2 PHY reset */
	85	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	86	reg \|= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	87	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	88
	89	mdelay(100);
	90
	91	/* Clear USB3 PHY reset */
	92	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	93	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	94	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	95
	96	/* Clear USB2 PHY reset */
	97	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	98	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	99	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	100
	101	/* After PHYs are stable we can take Core out of reset state */
	102	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	103	reg &= ~DWC3_GCTL_CORESOFTRESET;
	104	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	105	}
	106
	107	/**
	108	* dwc3_free_one_event_buffer - Frees one event buffer
	109	* @dwc: Pointer to our controller context structure
	110	* @evt: Pointer to event buffer to be freed
	111	*/
	112	static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
	113	struct dwc3_event_buffer *evt)
	114	{
	115	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
	116	kfree(evt);
	117	}
	118
	119	/**
	120	* dwc3_alloc_one_event_buffer - Allocated one event buffer structure
	121	* @dwc: Pointer to our controller context structure
	122	* @length: size of the event buffer
	123	*
	124	* Returns a pointer to the allocated event buffer structure on succes
	125	* otherwise ERR_PTR(errno).
	126	*/
	127	static struct dwc3_event_buffer *__devinit
	128	dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
	129	{
130	struct dwc3_event_buffer *evt;
131
132	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
133	if (!evt)
134	return ERR_PTR(-ENOMEM);
135
136	evt->dwc = dwc;
137	evt->length = length;
138	evt->buf = dma_alloc_coherent(dwc->dev, length,
139	&evt->dma, GFP_KERNEL);
140	if (!evt->buf) {
141	kfree(evt);
142	return ERR_PTR(-ENOMEM);
143	}
144
145	return evt;
146	}
147
148	/**
149	* dwc3_free_event_buffers - frees all allocated event buffers
150	* @dwc: Pointer to our controller context structure
151	*/
152	static void dwc3_free_event_buffers(struct dwc3 *dwc)
153	{
154	struct dwc3_event_buffer *evt;
155	int i;
156
157	for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
158	evt = dwc->ev_buffs[i];
159	if (evt) {
160	dwc3_free_one_event_buffer(dwc, evt);
161	dwc->ev_buffs[i] = NULL;
162	}
163	}
164	}
165
166	/**
167	* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
168	* @dwc: Pointer to out controller context structure
169	* @num: number of event buffers to allocate
170	* @length: size of event buffer
171	*
172	* Returns 0 on success otherwise negative errno. In error the case, dwc
173	* may contain some buffers allocated but not all which were requested.
174	*/
175	static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned num,
176	unsigned length)
177	{
178	int i;
179
180	for (i = 0; i < num; i++) {
181	struct dwc3_event_buffer *evt;
182
183	evt = dwc3_alloc_one_event_buffer(dwc, length);
184	if (IS_ERR(evt)) {
185	dev_err(dwc->dev, "can't allocate event buffer\n");
186	return PTR_ERR(evt);
187	}
188	dwc->ev_buffs[i] = evt;
189	}
190
191	return 0;
192	}
193
194	/**
195	* dwc3_event_buffers_setup - setup our allocated event buffers
196	* @dwc: Pointer to out controller context structure
197	*
198	* Returns 0 on success otherwise negative errno.
199	*/
200	static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
201	{
202	struct dwc3_event_buffer *evt;
203	int n;
204
205	for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
206	evt = dwc->ev_buffs[n];
207	dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
208	evt->buf, (unsigned long long) evt->dma,
209	evt->length);
210
211	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
212	lower_32_bits(evt->dma));
213	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
214	upper_32_bits(evt->dma));
215	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
216	evt->length & 0xffff);
217	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
218	}
219
220	return 0;
221	}
222
223	static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
224	{
225	struct dwc3_event_buffer *evt;
226	int n;
227
228	for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
229	evt = dwc->ev_buffs[n];
230	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
231	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
232	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
233	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
234	}
235	}
236
26ceca97 FB	237	static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
	238	{
	239	struct dwc3_hwparams *parms = &dwc->hwparams;
	240
	241	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	242	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	243	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	244	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	245	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	246	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	247	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	248	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	249	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
	250	}
	251
72246da4 FB	252	/**
	253	* dwc3_core_init - Low-level initialization of DWC3 Core
	254	* @dwc: Pointer to our controller context structure
	255	*
	256	* Returns 0 on success otherwise negative errno.
	257	*/
	258	static int __devinit dwc3_core_init(struct dwc3 *dwc)
	259	{
	260	unsigned long timeout;
	261	u32 reg;
	262	int ret;
	263
7650bd74 SAS	264	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	265	/* This should read as U3 followed by revision number */
	266	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
	267	dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
	268	ret = -ENODEV;
	269	goto err0;
	270	}
	271	dwc->revision = reg & DWC3_GSNPSREV_MASK;
	272
72246da4 FB	273	dwc3_core_soft_reset(dwc);
	274
	275	/* issue device SoftReset too */
	276	timeout = jiffies + msecs_to_jiffies(500);
	277	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	278	do {
	279	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	280	if (!(reg & DWC3_DCTL_CSFTRST))
	281	break;
	282
	283	if (time_after(jiffies, timeout)) {
	284	dev_err(dwc->dev, "Reset Timed Out\n");
	285	ret = -ETIMEDOUT;
	286	goto err0;
	287	}
	288
	289	cpu_relax();
	290	} while (true);
	291
72246da4 FB	292	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_NUM,
	293	DWC3_EVENT_BUFFERS_SIZE);
	294	if (ret) {
	295	dev_err(dwc->dev, "failed to allocate event buffers\n");
	296	ret = -ENOMEM;
	297	goto err1;
	298	}
	299
	300	ret = dwc3_event_buffers_setup(dwc);
	301	if (ret) {
	302	dev_err(dwc->dev, "failed to setup event buffers\n");
	303	goto err1;
	304	}
	305
26ceca97 FB	306	dwc3_cache_hwparams(dwc);
26ceca97 FB	307
72246da4 FB	308	return 0;
	309
	310	err1:
	311	dwc3_free_event_buffers(dwc);
	312
	313	err0:
	314	return ret;
	315	}
	316
	317	static void dwc3_core_exit(struct dwc3 *dwc)
	318	{
	319	dwc3_event_buffers_cleanup(dwc);
	320	dwc3_free_event_buffers(dwc);
	321	}
	322
	323	#define DWC3_ALIGN_MASK (16 - 1)
	324
	325	static int __devinit dwc3_probe(struct platform_device *pdev)
	326	{
	327	const struct platform_device_id *id = platform_get_device_id(pdev);
	328	struct resource *res;
	329	struct dwc3 *dwc;
	330	void __iomem *regs;
	331	unsigned int features = id->driver_data;
	332	int ret = -ENOMEM;
	333	int irq;
	334	void *mem;
	335
	336	mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
	337	if (!mem) {
	338	dev_err(&pdev->dev, "not enough memory\n");
	339	goto err0;
	340	}
	341	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	342	dwc->mem = mem;
	343
	344	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	345	if (!res) {
	346	dev_err(&pdev->dev, "missing resource\n");
	347	goto err1;
	348	}
	349
	350	res = request_mem_region(res->start, resource_size(res),
	351	dev_name(&pdev->dev));
	352	if (!res) {
	353	dev_err(&pdev->dev, "can't request mem region\n");
	354	goto err1;
	355	}
	356
	357	regs = ioremap(res->start, resource_size(res));
	358	if (!regs) {
	359	dev_err(&pdev->dev, "ioremap failed\n");
	360	goto err2;
	361	}
	362
	363	irq = platform_get_irq(pdev, 0);
	364	if (irq < 0) {
	365	dev_err(&pdev->dev, "missing IRQ\n");
	366	goto err3;
	367	}
	368
	369	spin_lock_init(&dwc->lock);
	370	platform_set_drvdata(pdev, dwc);
	371
372	dwc->regs = regs;
373	dwc->regs_size = resource_size(res);
374	dwc->dev = &pdev->dev;
375	dwc->irq = irq;
376
6c167fc9 FB	377	if (!strncmp("super", maximum_speed, 5))
	378	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	379	else if (!strncmp("high", maximum_speed, 4))
	380	dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	381	else if (!strncmp("full", maximum_speed, 4))
	382	dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	383	else if (!strncmp("low", maximum_speed, 3))
	384	dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	385	else
	386	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	387
72246da4 FB	388	pm_runtime_enable(&pdev->dev);
	389	pm_runtime_get_sync(&pdev->dev);
	390	pm_runtime_forbid(&pdev->dev);
	391
	392	ret = dwc3_core_init(dwc);
	393	if (ret) {
	394	dev_err(&pdev->dev, "failed to initialize core\n");
	395	goto err3;
	396	}
	397
	398	if (features & DWC3_HAS_PERIPHERAL) {
	399	ret = dwc3_gadget_init(dwc);
	400	if (ret) {
	401	dev_err(&pdev->dev, "failed to initialized gadget\n");
	402	goto err4;
	403	}
	404	}
	405
	406	ret = dwc3_debugfs_init(dwc);
	407	if (ret) {
	408	dev_err(&pdev->dev, "failed to initialize debugfs\n");
	409	goto err5;
	410	}
	411
	412	pm_runtime_allow(&pdev->dev);
	413
	414	return 0;
	415
	416	err5:
	417	if (features & DWC3_HAS_PERIPHERAL)
	418	dwc3_gadget_exit(dwc);
	419
	420	err4:
	421	dwc3_core_exit(dwc);
	422
	423	err3:
	424	iounmap(regs);
	425
	426	err2:
	427	release_mem_region(res->start, resource_size(res));
	428
	429	err1:
	430	kfree(dwc->mem);
	431
	432	err0:
	433	return ret;
	434	}
	435
	436	static int __devexit dwc3_remove(struct platform_device *pdev)
	437	{
	438	const struct platform_device_id *id = platform_get_device_id(pdev);
	439	struct dwc3 *dwc = platform_get_drvdata(pdev);
	440	struct resource *res;
	441	unsigned int features = id->driver_data;
	442
	443	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	444
	445	pm_runtime_put(&pdev->dev);
	446	pm_runtime_disable(&pdev->dev);
	447
	448	dwc3_debugfs_exit(dwc);
	449
	450	if (features & DWC3_HAS_PERIPHERAL)
	451	dwc3_gadget_exit(dwc);
452
453	dwc3_core_exit(dwc);
454	release_mem_region(res->start, resource_size(res));
455	iounmap(dwc->regs);
456	kfree(dwc->mem);
457
458	return 0;
459	}
460
461	static const struct platform_device_id dwc3_id_table[] __devinitconst = {
462	{
463	.name = "dwc3-omap",
464	.driver_data = (DWC3_HAS_PERIPHERAL
465	\| DWC3_HAS_XHCI
466	\| DWC3_HAS_OTG),
467	},
468	{
469	.name = "dwc3-pci",
470	.driver_data = DWC3_HAS_PERIPHERAL,
471	},
472	{ }, /* Terminating Entry */
473	};
474	MODULE_DEVICE_TABLE(platform, dwc3_id_table);
475
476	static struct platform_driver dwc3_driver = {
477	.probe = dwc3_probe,
478	.remove = __devexit_p(dwc3_remove),
479	.driver = {
480	.name = "dwc3",
481	},
482	.id_table = dwc3_id_table,
483	};
484
485	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
486	MODULE_LICENSE("Dual BSD/GPL");
487	MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
488
489	static int __devinit dwc3_init(void)
490	{
491	return platform_driver_register(&dwc3_driver);
492	}
493	module_init(dwc3_init);
494
495	static void __exit dwc3_exit(void)
496	{
497	platform_driver_unregister(&dwc3_driver);
498	}
499	module_exit(dwc3_exit);