Commit | Line | Data |
---|---|---|
f83fca07 PG |
1 | /** |
2 | * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms | |
3 | * | |
4 | * This is a small driver for the dwc3 to provide the glue logic | |
5 | * to configure the controller. Tested on STi platforms. | |
6 | * | |
7 | * Copyright (C) 2014 Stmicroelectronics | |
8 | * | |
9 | * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
10 | * Contributors: Aymen Bouattay <aymen.bouattay@st.com> | |
11 | * Peter Griffin <peter.griffin@linaro.org> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * Inspired by dwc3-omap.c and dwc3-exynos.c. | |
19 | */ | |
20 | ||
21 | #include <linux/delay.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/mfd/syscon.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/of.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/regmap.h> | |
33 | #include <linux/reset.h> | |
34 | #include <linux/usb/of.h> | |
35 | ||
36 | #include "core.h" | |
37 | #include "io.h" | |
38 | ||
39 | /* glue registers */ | |
40 | #define CLKRST_CTRL 0x00 | |
41 | #define AUX_CLK_EN BIT(0) | |
42 | #define SW_PIPEW_RESET_N BIT(4) | |
43 | #define EXT_CFG_RESET_N BIT(8) | |
44 | /* | |
45 | * 1'b0 : The host controller complies with the xHCI revision 0.96 | |
46 | * 1'b1 : The host controller complies with the xHCI revision 1.0 | |
47 | */ | |
48 | #define XHCI_REVISION BIT(12) | |
49 | ||
50 | #define USB2_VBUS_MNGMNT_SEL1 0x2C | |
51 | /* | |
52 | * For all fields in USB2_VBUS_MNGMNT_SEL1 | |
53 | * 2’b00 : Override value from Reg 0x30 is selected | |
54 | * 2’b01 : utmiotg_<signal_name> from usb3_top is selected | |
55 | * 2’b10 : pipew_<signal_name> from PIPEW instance is selected | |
56 | * 2’b11 : value is 1'b0 | |
57 | */ | |
58 | #define USB2_VBUS_REG30 0x0 | |
59 | #define USB2_VBUS_UTMIOTG 0x1 | |
60 | #define USB2_VBUS_PIPEW 0x2 | |
61 | #define USB2_VBUS_ZERO 0x3 | |
62 | ||
63 | #define SEL_OVERRIDE_VBUSVALID(n) (n << 0) | |
64 | #define SEL_OVERRIDE_POWERPRESENT(n) (n << 4) | |
65 | #define SEL_OVERRIDE_BVALID(n) (n << 8) | |
66 | ||
67 | /* Static DRD configuration */ | |
68 | #define USB3_CONTROL_MASK 0xf77 | |
69 | ||
70 | #define USB3_DEVICE_NOT_HOST BIT(0) | |
71 | #define USB3_FORCE_VBUSVALID BIT(1) | |
72 | #define USB3_DELAY_VBUSVALID BIT(2) | |
73 | #define USB3_SEL_FORCE_OPMODE BIT(4) | |
74 | #define USB3_FORCE_OPMODE(n) (n << 5) | |
75 | #define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) | |
76 | #define USB3_FORCE_DPPULLDOWN2 BIT(9) | |
77 | #define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) | |
78 | #define USB3_FORCE_DMPULLDOWN2 BIT(11) | |
79 | ||
80 | /** | |
81 | * struct st_dwc3 - dwc3-st driver private structure | |
82 | * @dev: device pointer | |
83 | * @glue_base: ioaddr for the glue registers | |
84 | * @regmap: regmap pointer for getting syscfg | |
85 | * @syscfg_reg_off: usb syscfg control offset | |
86 | * @dr_mode: drd static host/device config | |
87 | * @rstc_pwrdn: rest controller for powerdown signal | |
88 | * @rstc_rst: reset controller for softreset signal | |
89 | */ | |
90 | ||
91 | struct st_dwc3 { | |
92 | struct device *dev; | |
93 | void __iomem *glue_base; | |
94 | struct regmap *regmap; | |
95 | int syscfg_reg_off; | |
96 | enum usb_dr_mode dr_mode; | |
97 | struct reset_control *rstc_pwrdn; | |
98 | struct reset_control *rstc_rst; | |
99 | }; | |
100 | ||
101 | static inline u32 st_dwc3_readl(void __iomem *base, u32 offset) | |
102 | { | |
103 | return readl_relaxed(base + offset); | |
104 | } | |
105 | ||
106 | static inline void st_dwc3_writel(void __iomem *base, u32 offset, u32 value) | |
107 | { | |
108 | writel_relaxed(value, base + offset); | |
109 | } | |
110 | ||
111 | /** | |
112 | * st_dwc3_drd_init: program the port | |
113 | * @dwc3_data: driver private structure | |
114 | * Description: this function is to program the port as either host or device | |
115 | * according to the static configuration passed from devicetree. | |
116 | * OTG and dual role are not yet supported! | |
117 | */ | |
118 | static int st_dwc3_drd_init(struct st_dwc3 *dwc3_data) | |
119 | { | |
120 | u32 val; | |
121 | int err; | |
122 | ||
123 | err = regmap_read(dwc3_data->regmap, dwc3_data->syscfg_reg_off, &val); | |
124 | if (err) | |
125 | return err; | |
126 | ||
127 | val &= USB3_CONTROL_MASK; | |
128 | ||
129 | switch (dwc3_data->dr_mode) { | |
130 | case USB_DR_MODE_PERIPHERAL: | |
131 | ||
132 | val &= ~(USB3_FORCE_VBUSVALID | USB3_DELAY_VBUSVALID | |
133 | | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) | |
134 | | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 | |
135 | | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); | |
136 | ||
137 | val |= USB3_DEVICE_NOT_HOST; | |
f83fca07 PG |
138 | break; |
139 | ||
140 | case USB_DR_MODE_HOST: | |
141 | ||
142 | val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID | |
143 | | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) | |
144 | | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 | |
145 | | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); | |
146 | ||
147 | /* | |
148 | * USB3_DELAY_VBUSVALID is ANDed with USB_C_VBUSVALID. Thus, | |
149 | * when set to ‘0‘, it can delay the arrival of VBUSVALID | |
150 | * information to VBUSVLDEXT2 input of the pico PHY. | |
151 | * We don't want to do that so we set the bit to '1'. | |
152 | */ | |
153 | ||
154 | val |= USB3_DELAY_VBUSVALID; | |
f83fca07 PG |
155 | break; |
156 | ||
157 | default: | |
158 | dev_err(dwc3_data->dev, "Unsupported mode of operation %d\n", | |
159 | dwc3_data->dr_mode); | |
160 | return -EINVAL; | |
161 | } | |
162 | ||
163 | return regmap_write(dwc3_data->regmap, dwc3_data->syscfg_reg_off, val); | |
164 | } | |
165 | ||
166 | /** | |
167 | * st_dwc3_init: init the controller via glue logic | |
168 | * @dwc3_data: driver private structure | |
169 | */ | |
170 | static void st_dwc3_init(struct st_dwc3 *dwc3_data) | |
171 | { | |
172 | u32 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); | |
173 | ||
174 | reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION; | |
175 | reg &= ~SW_PIPEW_RESET_N; | |
176 | st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); | |
177 | ||
178 | /* configure mux for vbus, powerpresent and bvalid signals */ | |
179 | reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1); | |
180 | ||
181 | reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | | |
182 | SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | | |
183 | SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG); | |
184 | ||
185 | st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg); | |
186 | ||
187 | reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); | |
188 | reg |= SW_PIPEW_RESET_N; | |
189 | st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); | |
190 | } | |
191 | ||
192 | static int st_dwc3_probe(struct platform_device *pdev) | |
193 | { | |
194 | struct st_dwc3 *dwc3_data; | |
195 | struct resource *res; | |
196 | struct device *dev = &pdev->dev; | |
197 | struct device_node *node = dev->of_node, *child; | |
66647273 | 198 | struct platform_device *child_pdev; |
f83fca07 PG |
199 | struct regmap *regmap; |
200 | int ret; | |
201 | ||
202 | dwc3_data = devm_kzalloc(dev, sizeof(*dwc3_data), GFP_KERNEL); | |
203 | if (!dwc3_data) | |
204 | return -ENOMEM; | |
205 | ||
206 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg-glue"); | |
207 | dwc3_data->glue_base = devm_ioremap_resource(dev, res); | |
208 | if (IS_ERR(dwc3_data->glue_base)) | |
209 | return PTR_ERR(dwc3_data->glue_base); | |
210 | ||
211 | regmap = syscon_regmap_lookup_by_phandle(node, "st,syscfg"); | |
212 | if (IS_ERR(regmap)) | |
213 | return PTR_ERR(regmap); | |
214 | ||
215 | dma_set_coherent_mask(dev, dev->coherent_dma_mask); | |
216 | dwc3_data->dev = dev; | |
217 | dwc3_data->regmap = regmap; | |
218 | ||
219 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "syscfg-reg"); | |
220 | if (!res) { | |
221 | ret = -ENXIO; | |
222 | goto undo_platform_dev_alloc; | |
223 | } | |
224 | ||
225 | dwc3_data->syscfg_reg_off = res->start; | |
226 | ||
227 | dev_vdbg(&pdev->dev, "glue-logic addr 0x%p, syscfg-reg offset 0x%x\n", | |
228 | dwc3_data->glue_base, dwc3_data->syscfg_reg_off); | |
229 | ||
230 | dwc3_data->rstc_pwrdn = devm_reset_control_get(dev, "powerdown"); | |
231 | if (IS_ERR(dwc3_data->rstc_pwrdn)) { | |
232 | dev_err(&pdev->dev, "could not get power controller\n"); | |
233 | ret = PTR_ERR(dwc3_data->rstc_pwrdn); | |
234 | goto undo_platform_dev_alloc; | |
235 | } | |
236 | ||
237 | /* Manage PowerDown */ | |
238 | reset_control_deassert(dwc3_data->rstc_pwrdn); | |
239 | ||
240 | dwc3_data->rstc_rst = devm_reset_control_get(dev, "softreset"); | |
241 | if (IS_ERR(dwc3_data->rstc_rst)) { | |
242 | dev_err(&pdev->dev, "could not get reset controller\n"); | |
6cd6159d | 243 | ret = PTR_ERR(dwc3_data->rstc_rst); |
f83fca07 PG |
244 | goto undo_powerdown; |
245 | } | |
246 | ||
247 | /* Manage SoftReset */ | |
248 | reset_control_deassert(dwc3_data->rstc_rst); | |
249 | ||
250 | child = of_get_child_by_name(node, "dwc3"); | |
251 | if (!child) { | |
252 | dev_err(&pdev->dev, "failed to find dwc3 core node\n"); | |
253 | ret = -ENODEV; | |
254 | goto undo_softreset; | |
255 | } | |
256 | ||
f83fca07 PG |
257 | /* Allocate and initialize the core */ |
258 | ret = of_platform_populate(node, NULL, NULL, dev); | |
259 | if (ret) { | |
260 | dev_err(dev, "failed to add dwc3 core\n"); | |
261 | goto undo_softreset; | |
262 | } | |
263 | ||
66647273 HK |
264 | child_pdev = of_find_device_by_node(child); |
265 | if (!child_pdev) { | |
266 | dev_err(dev, "failed to find dwc3 core device\n"); | |
267 | ret = -ENODEV; | |
268 | goto undo_softreset; | |
269 | } | |
270 | ||
06e7114f | 271 | dwc3_data->dr_mode = usb_get_dr_mode(&child_pdev->dev); |
66647273 | 272 | |
f83fca07 PG |
273 | /* |
274 | * Configure the USB port as device or host according to the static | |
275 | * configuration passed from DT. | |
276 | * DRD is the only mode currently supported so this will be enhanced | |
277 | * as soon as OTG is available. | |
278 | */ | |
279 | ret = st_dwc3_drd_init(dwc3_data); | |
280 | if (ret) { | |
281 | dev_err(dev, "drd initialisation failed\n"); | |
282 | goto undo_softreset; | |
283 | } | |
284 | ||
285 | /* ST glue logic init */ | |
286 | st_dwc3_init(dwc3_data); | |
287 | ||
288 | platform_set_drvdata(pdev, dwc3_data); | |
289 | return 0; | |
290 | ||
291 | undo_softreset: | |
292 | reset_control_assert(dwc3_data->rstc_rst); | |
293 | undo_powerdown: | |
294 | reset_control_assert(dwc3_data->rstc_pwrdn); | |
295 | undo_platform_dev_alloc: | |
296 | platform_device_put(pdev); | |
297 | return ret; | |
298 | } | |
299 | ||
300 | static int st_dwc3_remove(struct platform_device *pdev) | |
301 | { | |
302 | struct st_dwc3 *dwc3_data = platform_get_drvdata(pdev); | |
303 | ||
304 | of_platform_depopulate(&pdev->dev); | |
305 | ||
306 | reset_control_assert(dwc3_data->rstc_pwrdn); | |
307 | reset_control_assert(dwc3_data->rstc_rst); | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | #ifdef CONFIG_PM_SLEEP | |
313 | static int st_dwc3_suspend(struct device *dev) | |
314 | { | |
315 | struct st_dwc3 *dwc3_data = dev_get_drvdata(dev); | |
316 | ||
317 | reset_control_assert(dwc3_data->rstc_pwrdn); | |
318 | reset_control_assert(dwc3_data->rstc_rst); | |
319 | ||
320 | pinctrl_pm_select_sleep_state(dev); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | static int st_dwc3_resume(struct device *dev) | |
326 | { | |
327 | struct st_dwc3 *dwc3_data = dev_get_drvdata(dev); | |
328 | int ret; | |
329 | ||
330 | pinctrl_pm_select_default_state(dev); | |
331 | ||
332 | reset_control_deassert(dwc3_data->rstc_pwrdn); | |
333 | reset_control_deassert(dwc3_data->rstc_rst); | |
334 | ||
335 | ret = st_dwc3_drd_init(dwc3_data); | |
336 | if (ret) { | |
337 | dev_err(dev, "drd initialisation failed\n"); | |
338 | return ret; | |
339 | } | |
340 | ||
341 | /* ST glue logic init */ | |
342 | st_dwc3_init(dwc3_data); | |
343 | ||
344 | return 0; | |
345 | } | |
346 | #endif /* CONFIG_PM_SLEEP */ | |
347 | ||
348 | static SIMPLE_DEV_PM_OPS(st_dwc3_dev_pm_ops, st_dwc3_suspend, st_dwc3_resume); | |
349 | ||
350 | static const struct of_device_id st_dwc3_match[] = { | |
351 | { .compatible = "st,stih407-dwc3" }, | |
352 | { /* sentinel */ }, | |
353 | }; | |
354 | ||
355 | MODULE_DEVICE_TABLE(of, st_dwc3_match); | |
356 | ||
357 | static struct platform_driver st_dwc3_driver = { | |
358 | .probe = st_dwc3_probe, | |
359 | .remove = st_dwc3_remove, | |
360 | .driver = { | |
361 | .name = "usb-st-dwc3", | |
362 | .of_match_table = st_dwc3_match, | |
363 | .pm = &st_dwc3_dev_pm_ops, | |
364 | }, | |
365 | }; | |
366 | ||
367 | module_platform_driver(st_dwc3_driver); | |
368 | ||
369 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
370 | MODULE_DESCRIPTION("DesignWare USB3 STi Glue Layer"); | |
371 | MODULE_LICENSE("GPL v2"); |