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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
33 | #include "core.h" | |
34 | #include "gadget.h" | |
35 | #include "io.h" | |
36 | ||
04a9bfcd FB |
37 | /** |
38 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
39 | * @dwc: pointer to our context structure | |
40 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
41 | * | |
42 | * Caller should take care of locking. This function will | |
43 | * return 0 on success or -EINVAL if wrong Test Selector | |
44 | * is passed | |
45 | */ | |
46 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
47 | { | |
48 | u32 reg; | |
49 | ||
50 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
51 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
52 | ||
53 | switch (mode) { | |
54 | case TEST_J: | |
55 | case TEST_K: | |
56 | case TEST_SE0_NAK: | |
57 | case TEST_PACKET: | |
58 | case TEST_FORCE_EN: | |
59 | reg |= mode << 1; | |
60 | break; | |
61 | default: | |
62 | return -EINVAL; | |
63 | } | |
64 | ||
65 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
911f1f88 PZ |
70 | /** |
71 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
72 | * @dwc: pointer to our context structure | |
73 | * | |
74 | * Caller should take care of locking. This function will | |
75 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
76 | */ | |
77 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
78 | { | |
79 | u32 reg; | |
80 | ||
81 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
82 | ||
83 | return DWC3_DSTS_USBLNKST(reg); | |
84 | } | |
85 | ||
8598bde7 FB |
86 | /** |
87 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
88 | * @dwc: pointer to our context structure | |
89 | * @state: the state to put link into | |
90 | * | |
91 | * Caller should take care of locking. This function will | |
aee63e3c | 92 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
93 | */ |
94 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
95 | { | |
aee63e3c | 96 | int retries = 10000; |
8598bde7 FB |
97 | u32 reg; |
98 | ||
802fde98 PZ |
99 | /* |
100 | * Wait until device controller is ready. Only applies to 1.94a and | |
101 | * later RTL. | |
102 | */ | |
103 | if (dwc->revision >= DWC3_REVISION_194A) { | |
104 | while (--retries) { | |
105 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
106 | if (reg & DWC3_DSTS_DCNRD) | |
107 | udelay(5); | |
108 | else | |
109 | break; | |
110 | } | |
111 | ||
112 | if (retries <= 0) | |
113 | return -ETIMEDOUT; | |
114 | } | |
115 | ||
8598bde7 FB |
116 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
117 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
118 | ||
119 | /* set requested state */ | |
120 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
121 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
122 | ||
802fde98 PZ |
123 | /* |
124 | * The following code is racy when called from dwc3_gadget_wakeup, | |
125 | * and is not needed, at least on newer versions | |
126 | */ | |
127 | if (dwc->revision >= DWC3_REVISION_194A) | |
128 | return 0; | |
129 | ||
8598bde7 | 130 | /* wait for a change in DSTS */ |
aed430e5 | 131 | retries = 10000; |
8598bde7 FB |
132 | while (--retries) { |
133 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
134 | ||
8598bde7 FB |
135 | if (DWC3_DSTS_USBLNKST(reg) == state) |
136 | return 0; | |
137 | ||
aee63e3c | 138 | udelay(5); |
8598bde7 FB |
139 | } |
140 | ||
141 | dev_vdbg(dwc->dev, "link state change request timed out\n"); | |
142 | ||
143 | return -ETIMEDOUT; | |
144 | } | |
145 | ||
457e84b6 FB |
146 | /** |
147 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
148 | * @dwc: pointer to our context structure | |
149 | * | |
150 | * This function will a best effort FIFO allocation in order | |
151 | * to improve FIFO usage and throughput, while still allowing | |
152 | * us to enable as many endpoints as possible. | |
153 | * | |
154 | * Keep in mind that this operation will be highly dependent | |
155 | * on the configured size for RAM1 - which contains TxFifo -, | |
156 | * the amount of endpoints enabled on coreConsultant tool, and | |
157 | * the width of the Master Bus. | |
158 | * | |
159 | * In the ideal world, we would always be able to satisfy the | |
160 | * following equation: | |
161 | * | |
162 | * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ | |
163 | * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes | |
164 | * | |
165 | * Unfortunately, due to many variables that's not always the case. | |
166 | */ | |
167 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) | |
168 | { | |
169 | int last_fifo_depth = 0; | |
170 | int ram1_depth; | |
171 | int fifo_size; | |
172 | int mdwidth; | |
173 | int num; | |
174 | ||
175 | if (!dwc->needs_fifo_resize) | |
176 | return 0; | |
177 | ||
178 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
179 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
180 | ||
181 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
182 | mdwidth >>= 3; | |
183 | ||
184 | /* | |
185 | * FIXME For now we will only allocate 1 wMaxPacketSize space | |
186 | * for each enabled endpoint, later patches will come to | |
187 | * improve this algorithm so that we better use the internal | |
188 | * FIFO space | |
189 | */ | |
190 | for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { | |
191 | struct dwc3_ep *dep = dwc->eps[num]; | |
192 | int fifo_number = dep->number >> 1; | |
2e81c36a | 193 | int mult = 1; |
457e84b6 FB |
194 | int tmp; |
195 | ||
196 | if (!(dep->number & 1)) | |
197 | continue; | |
198 | ||
199 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
200 | continue; | |
201 | ||
16e78db7 IS |
202 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) |
203 | || usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2e81c36a FB |
204 | mult = 3; |
205 | ||
206 | /* | |
207 | * REVISIT: the following assumes we will always have enough | |
208 | * space available on the FIFO RAM for all possible use cases. | |
209 | * Make sure that's true somehow and change FIFO allocation | |
210 | * accordingly. | |
211 | * | |
212 | * If we have Bulk or Isochronous endpoints, we want | |
213 | * them to be able to be very, very fast. So we're giving | |
214 | * those endpoints a fifo_size which is enough for 3 full | |
215 | * packets | |
216 | */ | |
217 | tmp = mult * (dep->endpoint.maxpacket + mdwidth); | |
457e84b6 FB |
218 | tmp += mdwidth; |
219 | ||
220 | fifo_size = DIV_ROUND_UP(tmp, mdwidth); | |
2e81c36a | 221 | |
457e84b6 FB |
222 | fifo_size |= (last_fifo_depth << 16); |
223 | ||
224 | dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", | |
225 | dep->name, last_fifo_depth, fifo_size & 0xffff); | |
226 | ||
227 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), | |
228 | fifo_size); | |
229 | ||
230 | last_fifo_depth += (fifo_size & 0xffff); | |
231 | } | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
72246da4 FB |
236 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
237 | int status) | |
238 | { | |
239 | struct dwc3 *dwc = dep->dwc; | |
e5ba5ec8 | 240 | int i; |
72246da4 FB |
241 | |
242 | if (req->queued) { | |
e5ba5ec8 PA |
243 | i = 0; |
244 | do { | |
eeb720fb | 245 | dep->busy_slot++; |
e5ba5ec8 PA |
246 | /* |
247 | * Skip LINK TRB. We can't use req->trb and check for | |
248 | * DWC3_TRBCTL_LINK_TRB because it points the TRB we | |
249 | * just completed (not the LINK TRB). | |
250 | */ | |
251 | if (((dep->busy_slot & DWC3_TRB_MASK) == | |
252 | DWC3_TRB_NUM- 1) && | |
16e78db7 | 253 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
e5ba5ec8 PA |
254 | dep->busy_slot++; |
255 | } while(++i < req->request.num_mapped_sgs); | |
c9fda7d6 | 256 | req->queued = false; |
72246da4 FB |
257 | } |
258 | list_del(&req->list); | |
eeb720fb | 259 | req->trb = NULL; |
72246da4 FB |
260 | |
261 | if (req->request.status == -EINPROGRESS) | |
262 | req->request.status = status; | |
263 | ||
0416e494 PA |
264 | if (dwc->ep0_bounced && dep->number == 0) |
265 | dwc->ep0_bounced = false; | |
266 | else | |
267 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
268 | req->direction); | |
72246da4 FB |
269 | |
270 | dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", | |
271 | req, dep->name, req->request.actual, | |
272 | req->request.length, status); | |
273 | ||
274 | spin_unlock(&dwc->lock); | |
0fc9a1be | 275 | req->request.complete(&dep->endpoint, &req->request); |
72246da4 FB |
276 | spin_lock(&dwc->lock); |
277 | } | |
278 | ||
279 | static const char *dwc3_gadget_ep_cmd_string(u8 cmd) | |
280 | { | |
281 | switch (cmd) { | |
282 | case DWC3_DEPCMD_DEPSTARTCFG: | |
283 | return "Start New Configuration"; | |
284 | case DWC3_DEPCMD_ENDTRANSFER: | |
285 | return "End Transfer"; | |
286 | case DWC3_DEPCMD_UPDATETRANSFER: | |
287 | return "Update Transfer"; | |
288 | case DWC3_DEPCMD_STARTTRANSFER: | |
289 | return "Start Transfer"; | |
290 | case DWC3_DEPCMD_CLEARSTALL: | |
291 | return "Clear Stall"; | |
292 | case DWC3_DEPCMD_SETSTALL: | |
293 | return "Set Stall"; | |
802fde98 PZ |
294 | case DWC3_DEPCMD_GETEPSTATE: |
295 | return "Get Endpoint State"; | |
72246da4 FB |
296 | case DWC3_DEPCMD_SETTRANSFRESOURCE: |
297 | return "Set Endpoint Transfer Resource"; | |
298 | case DWC3_DEPCMD_SETEPCONFIG: | |
299 | return "Set Endpoint Configuration"; | |
300 | default: | |
301 | return "UNKNOWN command"; | |
302 | } | |
303 | } | |
304 | ||
427c3df6 FB |
305 | static const char *dwc3_gadget_generic_cmd_string(u8 cmd) |
306 | { | |
307 | switch (cmd) { | |
308 | case DWC3_DGCMD_SET_LMP: | |
309 | return "Set LMP"; | |
310 | case DWC3_DGCMD_SET_PERIODIC_PAR: | |
311 | return "Set Periodic Parameters"; | |
312 | case DWC3_DGCMD_XMIT_FUNCTION: | |
313 | return "Transmit Function Wake Device Notification"; | |
314 | case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO: | |
315 | return "Set Scratchpad Buffer Array Address Lo"; | |
316 | case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI: | |
317 | return "Set Scratchpad Buffer Array Address Hi"; | |
318 | case DWC3_DGCMD_SELECTED_FIFO_FLUSH: | |
319 | return "Selected FIFO Flush"; | |
320 | case DWC3_DGCMD_ALL_FIFO_FLUSH: | |
321 | return "All FIFO Flush"; | |
322 | case DWC3_DGCMD_SET_ENDPOINT_NRDY: | |
323 | return "Set Endpoint NRDY"; | |
324 | case DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK: | |
325 | return "Run SoC Bus Loopback Test"; | |
326 | default: | |
327 | return "UNKNOWN"; | |
328 | } | |
329 | } | |
330 | ||
e57ebc1d FB |
331 | static const char *dwc3_gadget_link_string(enum dwc3_link_state link_state) |
332 | { | |
333 | switch (link_state) { | |
334 | case DWC3_LINK_STATE_U0: | |
335 | return "U0"; | |
336 | case DWC3_LINK_STATE_U1: | |
337 | return "U1"; | |
338 | case DWC3_LINK_STATE_U2: | |
339 | return "U2"; | |
340 | case DWC3_LINK_STATE_U3: | |
341 | return "U3"; | |
342 | case DWC3_LINK_STATE_SS_DIS: | |
343 | return "SS.Disabled"; | |
344 | case DWC3_LINK_STATE_RX_DET: | |
345 | return "RX.Detect"; | |
346 | case DWC3_LINK_STATE_SS_INACT: | |
347 | return "SS.Inactive"; | |
348 | case DWC3_LINK_STATE_POLL: | |
349 | return "Polling"; | |
350 | case DWC3_LINK_STATE_RECOV: | |
351 | return "Recovery"; | |
352 | case DWC3_LINK_STATE_HRESET: | |
353 | return "Hot Reset"; | |
354 | case DWC3_LINK_STATE_CMPLY: | |
355 | return "Compliance"; | |
356 | case DWC3_LINK_STATE_LPBK: | |
357 | return "Loopback"; | |
358 | case DWC3_LINK_STATE_RESET: | |
359 | return "Reset"; | |
360 | case DWC3_LINK_STATE_RESUME: | |
361 | return "Resume"; | |
362 | default: | |
363 | return "UNKNOWN link state\n"; | |
364 | } | |
365 | } | |
366 | ||
b09bb642 FB |
367 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) |
368 | { | |
369 | u32 timeout = 500; | |
370 | u32 reg; | |
371 | ||
427c3df6 FB |
372 | dev_vdbg(dwc->dev, "generic cmd '%s' [%d] param %08x\n", |
373 | dwc3_gadget_generic_cmd_string(cmd), cmd, param); | |
374 | ||
b09bb642 FB |
375 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); |
376 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
377 | ||
378 | do { | |
379 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
380 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
381 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", | |
382 | DWC3_DGCMD_STATUS(reg)); | |
383 | return 0; | |
384 | } | |
385 | ||
386 | /* | |
387 | * We can't sleep here, because it's also called from | |
388 | * interrupt context. | |
389 | */ | |
390 | timeout--; | |
391 | if (!timeout) | |
392 | return -ETIMEDOUT; | |
393 | udelay(1); | |
394 | } while (1); | |
395 | } | |
396 | ||
72246da4 FB |
397 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
398 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
399 | { | |
400 | struct dwc3_ep *dep = dwc->eps[ep]; | |
61d58242 | 401 | u32 timeout = 500; |
72246da4 FB |
402 | u32 reg; |
403 | ||
40cc57c7 | 404 | dev_vdbg(dwc->dev, "%s: cmd '%s' [%d] params %08x %08x %08x\n", |
72246da4 | 405 | dep->name, |
40cc57c7 | 406 | dwc3_gadget_ep_cmd_string(cmd), cmd, params->param0, |
dc1c70a7 | 407 | params->param1, params->param2); |
72246da4 | 408 | |
dc1c70a7 FB |
409 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
410 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); | |
411 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); | |
72246da4 FB |
412 | |
413 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | |
414 | do { | |
415 | reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); | |
416 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
164f6e14 FB |
417 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", |
418 | DWC3_DEPCMD_STATUS(reg)); | |
72246da4 FB |
419 | return 0; |
420 | } | |
421 | ||
422 | /* | |
72246da4 FB |
423 | * We can't sleep here, because it is also called from |
424 | * interrupt context. | |
425 | */ | |
426 | timeout--; | |
427 | if (!timeout) | |
428 | return -ETIMEDOUT; | |
429 | ||
61d58242 | 430 | udelay(1); |
72246da4 FB |
431 | } while (1); |
432 | } | |
433 | ||
434 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
f6bafc6a | 435 | struct dwc3_trb *trb) |
72246da4 | 436 | { |
c439ef87 | 437 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
438 | |
439 | return dep->trb_pool_dma + offset; | |
440 | } | |
441 | ||
442 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
443 | { | |
444 | struct dwc3 *dwc = dep->dwc; | |
445 | ||
446 | if (dep->trb_pool) | |
447 | return 0; | |
448 | ||
449 | if (dep->number == 0 || dep->number == 1) | |
450 | return 0; | |
451 | ||
452 | dep->trb_pool = dma_alloc_coherent(dwc->dev, | |
453 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
454 | &dep->trb_pool_dma, GFP_KERNEL); | |
455 | if (!dep->trb_pool) { | |
456 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
457 | dep->name); | |
458 | return -ENOMEM; | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
465 | { | |
466 | struct dwc3 *dwc = dep->dwc; | |
467 | ||
468 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
469 | dep->trb_pool, dep->trb_pool_dma); | |
470 | ||
471 | dep->trb_pool = NULL; | |
472 | dep->trb_pool_dma = 0; | |
473 | } | |
474 | ||
475 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) | |
476 | { | |
477 | struct dwc3_gadget_ep_cmd_params params; | |
478 | u32 cmd; | |
479 | ||
480 | memset(¶ms, 0x00, sizeof(params)); | |
481 | ||
482 | if (dep->number != 1) { | |
483 | cmd = DWC3_DEPCMD_DEPSTARTCFG; | |
484 | /* XferRscIdx == 0 for ep0 and 2 for the remaining */ | |
b23c8439 PZ |
485 | if (dep->number > 1) { |
486 | if (dwc->start_config_issued) | |
487 | return 0; | |
488 | dwc->start_config_issued = true; | |
72246da4 | 489 | cmd |= DWC3_DEPCMD_PARAM(2); |
b23c8439 | 490 | } |
72246da4 FB |
491 | |
492 | return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); | |
493 | } | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
498 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 499 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 500 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 501 | bool ignore, bool restore) |
72246da4 FB |
502 | { |
503 | struct dwc3_gadget_ep_cmd_params params; | |
504 | ||
505 | memset(¶ms, 0x00, sizeof(params)); | |
506 | ||
dc1c70a7 | 507 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
508 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
509 | ||
510 | /* Burst size is only needed in SuperSpeed mode */ | |
511 | if (dwc->gadget.speed == USB_SPEED_SUPER) { | |
512 | u32 burst = dep->endpoint.maxburst - 1; | |
513 | ||
514 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); | |
515 | } | |
72246da4 | 516 | |
4b345c9a FB |
517 | if (ignore) |
518 | params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; | |
519 | ||
265b70a7 PZ |
520 | if (restore) { |
521 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; | |
522 | params.param2 |= dep->saved_state; | |
523 | } | |
524 | ||
dc1c70a7 FB |
525 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
526 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 527 | |
18b7ede5 | 528 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
529 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
530 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
531 | dep->stream_capable = true; |
532 | } | |
533 | ||
72246da4 | 534 | if (usb_endpoint_xfer_isoc(desc)) |
dc1c70a7 | 535 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
536 | |
537 | /* | |
538 | * We are doing 1:1 mapping for endpoints, meaning | |
539 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
540 | * so on. We consider the direction bit as part of the physical | |
541 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
542 | */ | |
dc1c70a7 | 543 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
544 | |
545 | /* | |
546 | * We must use the lower 16 TX FIFOs even though | |
547 | * HW might have more | |
548 | */ | |
549 | if (dep->direction) | |
dc1c70a7 | 550 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
551 | |
552 | if (desc->bInterval) { | |
dc1c70a7 | 553 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
554 | dep->interval = 1 << (desc->bInterval - 1); |
555 | } | |
556 | ||
557 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
558 | DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
559 | } | |
560 | ||
561 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
562 | { | |
563 | struct dwc3_gadget_ep_cmd_params params; | |
564 | ||
565 | memset(¶ms, 0x00, sizeof(params)); | |
566 | ||
dc1c70a7 | 567 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 FB |
568 | |
569 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
570 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | |
571 | } | |
572 | ||
573 | /** | |
574 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
575 | * @dep: endpoint to be initialized | |
576 | * @desc: USB Endpoint Descriptor | |
577 | * | |
578 | * Caller should take care of locking | |
579 | */ | |
580 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 581 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 582 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 583 | bool ignore, bool restore) |
72246da4 FB |
584 | { |
585 | struct dwc3 *dwc = dep->dwc; | |
586 | u32 reg; | |
b09e99ee | 587 | int ret; |
72246da4 | 588 | |
ff62d6b6 FB |
589 | dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); |
590 | ||
72246da4 FB |
591 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
592 | ret = dwc3_gadget_start_config(dwc, dep); | |
593 | if (ret) | |
594 | return ret; | |
595 | } | |
596 | ||
265b70a7 PZ |
597 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, |
598 | restore); | |
72246da4 FB |
599 | if (ret) |
600 | return ret; | |
601 | ||
602 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
603 | struct dwc3_trb *trb_st_hw; |
604 | struct dwc3_trb *trb_link; | |
72246da4 FB |
605 | |
606 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
607 | if (ret) | |
608 | return ret; | |
609 | ||
16e78db7 | 610 | dep->endpoint.desc = desc; |
c90bfaec | 611 | dep->comp_desc = comp_desc; |
72246da4 FB |
612 | dep->type = usb_endpoint_type(desc); |
613 | dep->flags |= DWC3_EP_ENABLED; | |
614 | ||
615 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
616 | reg |= DWC3_DALEPENA_EP(dep->number); | |
617 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
618 | ||
619 | if (!usb_endpoint_xfer_isoc(desc)) | |
620 | return 0; | |
621 | ||
622 | memset(&trb_link, 0, sizeof(trb_link)); | |
623 | ||
1d046793 | 624 | /* Link TRB for ISOC. The HWO bit is never reset */ |
72246da4 FB |
625 | trb_st_hw = &dep->trb_pool[0]; |
626 | ||
f6bafc6a | 627 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
72246da4 | 628 | |
f6bafc6a FB |
629 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
630 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
631 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
632 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
633 | } |
634 | ||
635 | return 0; | |
636 | } | |
637 | ||
b992e681 | 638 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 639 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
640 | { |
641 | struct dwc3_request *req; | |
642 | ||
ea53b882 | 643 | if (!list_empty(&dep->req_queued)) { |
b992e681 | 644 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 645 | |
57911504 | 646 | /* - giveback all requests to gadget driver */ |
1591633e PA |
647 | while (!list_empty(&dep->req_queued)) { |
648 | req = next_request(&dep->req_queued); | |
649 | ||
650 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
651 | } | |
ea53b882 FB |
652 | } |
653 | ||
72246da4 FB |
654 | while (!list_empty(&dep->request_list)) { |
655 | req = next_request(&dep->request_list); | |
656 | ||
624407f9 | 657 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 658 | } |
72246da4 FB |
659 | } |
660 | ||
661 | /** | |
662 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
663 | * @dep: the endpoint to disable | |
664 | * | |
624407f9 SAS |
665 | * This function also removes requests which are currently processed ny the |
666 | * hardware and those which are not yet scheduled. | |
667 | * Caller should take care of locking. | |
72246da4 | 668 | */ |
72246da4 FB |
669 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
670 | { | |
671 | struct dwc3 *dwc = dep->dwc; | |
672 | u32 reg; | |
673 | ||
624407f9 | 674 | dwc3_remove_requests(dwc, dep); |
72246da4 | 675 | |
687ef981 FB |
676 | /* make sure HW endpoint isn't stalled */ |
677 | if (dep->flags & DWC3_EP_STALL) | |
678 | __dwc3_gadget_ep_set_halt(dep, 0); | |
679 | ||
72246da4 FB |
680 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
681 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
682 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
683 | ||
879631aa | 684 | dep->stream_capable = false; |
f9c56cdd | 685 | dep->endpoint.desc = NULL; |
c90bfaec | 686 | dep->comp_desc = NULL; |
72246da4 | 687 | dep->type = 0; |
879631aa | 688 | dep->flags = 0; |
72246da4 FB |
689 | |
690 | return 0; | |
691 | } | |
692 | ||
693 | /* -------------------------------------------------------------------------- */ | |
694 | ||
695 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
696 | const struct usb_endpoint_descriptor *desc) | |
697 | { | |
698 | return -EINVAL; | |
699 | } | |
700 | ||
701 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
702 | { | |
703 | return -EINVAL; | |
704 | } | |
705 | ||
706 | /* -------------------------------------------------------------------------- */ | |
707 | ||
708 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
709 | const struct usb_endpoint_descriptor *desc) | |
710 | { | |
711 | struct dwc3_ep *dep; | |
712 | struct dwc3 *dwc; | |
713 | unsigned long flags; | |
714 | int ret; | |
715 | ||
716 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
717 | pr_debug("dwc3: invalid parameters\n"); | |
718 | return -EINVAL; | |
719 | } | |
720 | ||
721 | if (!desc->wMaxPacketSize) { | |
722 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
723 | return -EINVAL; | |
724 | } | |
725 | ||
726 | dep = to_dwc3_ep(ep); | |
727 | dwc = dep->dwc; | |
728 | ||
c6f83f38 FB |
729 | if (dep->flags & DWC3_EP_ENABLED) { |
730 | dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", | |
731 | dep->name); | |
732 | return 0; | |
733 | } | |
734 | ||
72246da4 FB |
735 | switch (usb_endpoint_type(desc)) { |
736 | case USB_ENDPOINT_XFER_CONTROL: | |
27a78d6a | 737 | strlcat(dep->name, "-control", sizeof(dep->name)); |
72246da4 FB |
738 | break; |
739 | case USB_ENDPOINT_XFER_ISOC: | |
27a78d6a | 740 | strlcat(dep->name, "-isoc", sizeof(dep->name)); |
72246da4 FB |
741 | break; |
742 | case USB_ENDPOINT_XFER_BULK: | |
27a78d6a | 743 | strlcat(dep->name, "-bulk", sizeof(dep->name)); |
72246da4 FB |
744 | break; |
745 | case USB_ENDPOINT_XFER_INT: | |
27a78d6a | 746 | strlcat(dep->name, "-int", sizeof(dep->name)); |
72246da4 FB |
747 | break; |
748 | default: | |
749 | dev_err(dwc->dev, "invalid endpoint transfer type\n"); | |
750 | } | |
751 | ||
72246da4 | 752 | spin_lock_irqsave(&dwc->lock, flags); |
265b70a7 | 753 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); |
72246da4 FB |
754 | spin_unlock_irqrestore(&dwc->lock, flags); |
755 | ||
756 | return ret; | |
757 | } | |
758 | ||
759 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
760 | { | |
761 | struct dwc3_ep *dep; | |
762 | struct dwc3 *dwc; | |
763 | unsigned long flags; | |
764 | int ret; | |
765 | ||
766 | if (!ep) { | |
767 | pr_debug("dwc3: invalid parameters\n"); | |
768 | return -EINVAL; | |
769 | } | |
770 | ||
771 | dep = to_dwc3_ep(ep); | |
772 | dwc = dep->dwc; | |
773 | ||
774 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
775 | dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", | |
776 | dep->name); | |
777 | return 0; | |
778 | } | |
779 | ||
780 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", | |
781 | dep->number >> 1, | |
782 | (dep->number & 1) ? "in" : "out"); | |
783 | ||
784 | spin_lock_irqsave(&dwc->lock, flags); | |
785 | ret = __dwc3_gadget_ep_disable(dep); | |
786 | spin_unlock_irqrestore(&dwc->lock, flags); | |
787 | ||
788 | return ret; | |
789 | } | |
790 | ||
791 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
792 | gfp_t gfp_flags) | |
793 | { | |
794 | struct dwc3_request *req; | |
795 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
796 | struct dwc3 *dwc = dep->dwc; | |
797 | ||
798 | req = kzalloc(sizeof(*req), gfp_flags); | |
799 | if (!req) { | |
800 | dev_err(dwc->dev, "not enough memory\n"); | |
801 | return NULL; | |
802 | } | |
803 | ||
804 | req->epnum = dep->number; | |
805 | req->dep = dep; | |
72246da4 FB |
806 | |
807 | return &req->request; | |
808 | } | |
809 | ||
810 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
811 | struct usb_request *request) | |
812 | { | |
813 | struct dwc3_request *req = to_dwc3_request(request); | |
814 | ||
815 | kfree(req); | |
816 | } | |
817 | ||
c71fc37c FB |
818 | /** |
819 | * dwc3_prepare_one_trb - setup one TRB from one request | |
820 | * @dep: endpoint for which this request is prepared | |
821 | * @req: dwc3_request pointer | |
822 | */ | |
68e823e2 | 823 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 824 | struct dwc3_request *req, dma_addr_t dma, |
e5ba5ec8 | 825 | unsigned length, unsigned last, unsigned chain, unsigned node) |
c71fc37c | 826 | { |
eeb720fb | 827 | struct dwc3 *dwc = dep->dwc; |
f6bafc6a | 828 | struct dwc3_trb *trb; |
c71fc37c | 829 | |
eeb720fb FB |
830 | dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", |
831 | dep->name, req, (unsigned long long) dma, | |
832 | length, last ? " last" : "", | |
833 | chain ? " chain" : ""); | |
834 | ||
c71fc37c | 835 | /* Skip the LINK-TRB on ISOC */ |
915e202a | 836 | if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && |
16e78db7 | 837 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
915e202a PA |
838 | dep->free_slot++; |
839 | ||
840 | trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; | |
c71fc37c | 841 | |
eeb720fb FB |
842 | if (!req->trb) { |
843 | dwc3_gadget_move_request_queued(req); | |
f6bafc6a FB |
844 | req->trb = trb; |
845 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e5ba5ec8 | 846 | req->start_slot = dep->free_slot & DWC3_TRB_MASK; |
eeb720fb | 847 | } |
c71fc37c | 848 | |
e5ba5ec8 PA |
849 | dep->free_slot++; |
850 | ||
f6bafc6a FB |
851 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
852 | trb->bpl = lower_32_bits(dma); | |
853 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 854 | |
16e78db7 | 855 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 856 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 857 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
858 | break; |
859 | ||
860 | case USB_ENDPOINT_XFER_ISOC: | |
e5ba5ec8 PA |
861 | if (!node) |
862 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
863 | else | |
864 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
c71fc37c FB |
865 | break; |
866 | ||
867 | case USB_ENDPOINT_XFER_BULK: | |
868 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 869 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
870 | break; |
871 | default: | |
872 | /* | |
873 | * This is only possible with faulty memory because we | |
874 | * checked it already :) | |
875 | */ | |
876 | BUG(); | |
877 | } | |
878 | ||
f3af3651 FB |
879 | if (!req->request.no_interrupt && !chain) |
880 | trb->ctrl |= DWC3_TRB_CTRL_IOC; | |
881 | ||
16e78db7 | 882 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
f6bafc6a FB |
883 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
884 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
e5ba5ec8 PA |
885 | } else if (last) { |
886 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
f6bafc6a | 887 | } |
c71fc37c | 888 | |
e5ba5ec8 PA |
889 | if (chain) |
890 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
891 | ||
16e78db7 | 892 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 893 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 894 | |
f6bafc6a | 895 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
c71fc37c FB |
896 | } |
897 | ||
72246da4 FB |
898 | /* |
899 | * dwc3_prepare_trbs - setup TRBs from requests | |
900 | * @dep: endpoint for which requests are being prepared | |
901 | * @starting: true if the endpoint is idle and no requests are queued. | |
902 | * | |
1d046793 PZ |
903 | * The function goes through the requests list and sets up TRBs for the |
904 | * transfers. The function returns once there are no more TRBs available or | |
905 | * it runs out of requests. | |
72246da4 | 906 | */ |
68e823e2 | 907 | static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) |
72246da4 | 908 | { |
68e823e2 | 909 | struct dwc3_request *req, *n; |
72246da4 | 910 | u32 trbs_left; |
8d62cd65 | 911 | u32 max; |
c71fc37c | 912 | unsigned int last_one = 0; |
72246da4 FB |
913 | |
914 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
915 | ||
916 | /* the first request must not be queued */ | |
917 | trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; | |
c71fc37c | 918 | |
8d62cd65 | 919 | /* Can't wrap around on a non-isoc EP since there's no link TRB */ |
16e78db7 | 920 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8d62cd65 PZ |
921 | max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); |
922 | if (trbs_left > max) | |
923 | trbs_left = max; | |
924 | } | |
925 | ||
72246da4 | 926 | /* |
1d046793 PZ |
927 | * If busy & slot are equal than it is either full or empty. If we are |
928 | * starting to process requests then we are empty. Otherwise we are | |
72246da4 FB |
929 | * full and don't do anything |
930 | */ | |
931 | if (!trbs_left) { | |
932 | if (!starting) | |
68e823e2 | 933 | return; |
72246da4 FB |
934 | trbs_left = DWC3_TRB_NUM; |
935 | /* | |
936 | * In case we start from scratch, we queue the ISOC requests | |
937 | * starting from slot 1. This is done because we use ring | |
938 | * buffer and have no LST bit to stop us. Instead, we place | |
1d046793 | 939 | * IOC bit every TRB_NUM/4. We try to avoid having an interrupt |
72246da4 FB |
940 | * after the first request so we start at slot 1 and have |
941 | * 7 requests proceed before we hit the first IOC. | |
942 | * Other transfer types don't use the ring buffer and are | |
943 | * processed from the first TRB until the last one. Since we | |
944 | * don't wrap around we have to start at the beginning. | |
945 | */ | |
16e78db7 | 946 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
947 | dep->busy_slot = 1; |
948 | dep->free_slot = 1; | |
949 | } else { | |
950 | dep->busy_slot = 0; | |
951 | dep->free_slot = 0; | |
952 | } | |
953 | } | |
954 | ||
955 | /* The last TRB is a link TRB, not used for xfer */ | |
16e78db7 | 956 | if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 957 | return; |
72246da4 FB |
958 | |
959 | list_for_each_entry_safe(req, n, &dep->request_list, list) { | |
eeb720fb FB |
960 | unsigned length; |
961 | dma_addr_t dma; | |
e5ba5ec8 | 962 | last_one = false; |
72246da4 | 963 | |
eeb720fb FB |
964 | if (req->request.num_mapped_sgs > 0) { |
965 | struct usb_request *request = &req->request; | |
966 | struct scatterlist *sg = request->sg; | |
967 | struct scatterlist *s; | |
968 | int i; | |
72246da4 | 969 | |
eeb720fb FB |
970 | for_each_sg(sg, s, request->num_mapped_sgs, i) { |
971 | unsigned chain = true; | |
72246da4 | 972 | |
eeb720fb FB |
973 | length = sg_dma_len(s); |
974 | dma = sg_dma_address(s); | |
72246da4 | 975 | |
1d046793 PZ |
976 | if (i == (request->num_mapped_sgs - 1) || |
977 | sg_is_last(s)) { | |
e5ba5ec8 PA |
978 | if (list_is_last(&req->list, |
979 | &dep->request_list)) | |
980 | last_one = true; | |
eeb720fb FB |
981 | chain = false; |
982 | } | |
72246da4 | 983 | |
eeb720fb FB |
984 | trbs_left--; |
985 | if (!trbs_left) | |
986 | last_one = true; | |
72246da4 | 987 | |
eeb720fb FB |
988 | if (last_one) |
989 | chain = false; | |
72246da4 | 990 | |
eeb720fb | 991 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 992 | last_one, chain, i); |
72246da4 | 993 | |
eeb720fb FB |
994 | if (last_one) |
995 | break; | |
996 | } | |
72246da4 | 997 | } else { |
eeb720fb FB |
998 | dma = req->request.dma; |
999 | length = req->request.length; | |
1000 | trbs_left--; | |
72246da4 | 1001 | |
eeb720fb FB |
1002 | if (!trbs_left) |
1003 | last_one = 1; | |
879631aa | 1004 | |
eeb720fb FB |
1005 | /* Is this the last request? */ |
1006 | if (list_is_last(&req->list, &dep->request_list)) | |
1007 | last_one = 1; | |
72246da4 | 1008 | |
eeb720fb | 1009 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 1010 | last_one, false, 0); |
72246da4 | 1011 | |
eeb720fb FB |
1012 | if (last_one) |
1013 | break; | |
72246da4 | 1014 | } |
72246da4 | 1015 | } |
72246da4 FB |
1016 | } |
1017 | ||
1018 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |
1019 | int start_new) | |
1020 | { | |
1021 | struct dwc3_gadget_ep_cmd_params params; | |
1022 | struct dwc3_request *req; | |
1023 | struct dwc3 *dwc = dep->dwc; | |
1024 | int ret; | |
1025 | u32 cmd; | |
1026 | ||
1027 | if (start_new && (dep->flags & DWC3_EP_BUSY)) { | |
1028 | dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); | |
1029 | return -EBUSY; | |
1030 | } | |
1031 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
1032 | ||
1033 | /* | |
1034 | * If we are getting here after a short-out-packet we don't enqueue any | |
1035 | * new requests as we try to set the IOC bit only on the last request. | |
1036 | */ | |
1037 | if (start_new) { | |
1038 | if (list_empty(&dep->req_queued)) | |
1039 | dwc3_prepare_trbs(dep, start_new); | |
1040 | ||
1041 | /* req points to the first request which will be sent */ | |
1042 | req = next_request(&dep->req_queued); | |
1043 | } else { | |
68e823e2 FB |
1044 | dwc3_prepare_trbs(dep, start_new); |
1045 | ||
72246da4 | 1046 | /* |
1d046793 | 1047 | * req points to the first request where HWO changed from 0 to 1 |
72246da4 | 1048 | */ |
68e823e2 | 1049 | req = next_request(&dep->req_queued); |
72246da4 FB |
1050 | } |
1051 | if (!req) { | |
1052 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1053 | return 0; | |
1054 | } | |
1055 | ||
1056 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1057 | |
1877d6c9 PA |
1058 | if (start_new) { |
1059 | params.param0 = upper_32_bits(req->trb_dma); | |
1060 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 | 1061 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1877d6c9 | 1062 | } else { |
72246da4 | 1063 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
1877d6c9 | 1064 | } |
72246da4 FB |
1065 | |
1066 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
1067 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
1068 | if (ret < 0) { | |
1069 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
1070 | ||
1071 | /* | |
1072 | * FIXME we need to iterate over the list of requests | |
1073 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 1074 | * requests instead of what we do now. |
72246da4 | 1075 | */ |
0fc9a1be FB |
1076 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
1077 | req->direction); | |
72246da4 FB |
1078 | list_del(&req->list); |
1079 | return ret; | |
1080 | } | |
1081 | ||
1082 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1083 | |
f898ae09 | 1084 | if (start_new) { |
b4996a86 | 1085 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
f898ae09 | 1086 | dep->number); |
b4996a86 | 1087 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1088 | } |
25b8ff68 | 1089 | |
72246da4 FB |
1090 | return 0; |
1091 | } | |
1092 | ||
d6d6ec7b PA |
1093 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1094 | struct dwc3_ep *dep, u32 cur_uf) | |
1095 | { | |
1096 | u32 uf; | |
1097 | ||
1098 | if (list_empty(&dep->request_list)) { | |
1099 | dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", | |
1100 | dep->name); | |
f4a53c55 | 1101 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1102 | return; |
1103 | } | |
1104 | ||
1105 | /* 4 micro frames in the future */ | |
1106 | uf = cur_uf + dep->interval * 4; | |
1107 | ||
1108 | __dwc3_gadget_kick_transfer(dep, uf, 1); | |
1109 | } | |
1110 | ||
1111 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1112 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1113 | { | |
1114 | u32 cur_uf, mask; | |
1115 | ||
1116 | mask = ~(dep->interval - 1); | |
1117 | cur_uf = event->parameters & mask; | |
1118 | ||
1119 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1120 | } | |
1121 | ||
72246da4 FB |
1122 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1123 | { | |
0fc9a1be FB |
1124 | struct dwc3 *dwc = dep->dwc; |
1125 | int ret; | |
1126 | ||
72246da4 FB |
1127 | req->request.actual = 0; |
1128 | req->request.status = -EINPROGRESS; | |
1129 | req->direction = dep->direction; | |
1130 | req->epnum = dep->number; | |
1131 | ||
1132 | /* | |
1133 | * We only add to our list of requests now and | |
1134 | * start consuming the list once we get XferNotReady | |
1135 | * IRQ. | |
1136 | * | |
1137 | * That way, we avoid doing anything that we don't need | |
1138 | * to do now and defer it until the point we receive a | |
1139 | * particular token from the Host side. | |
1140 | * | |
1141 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1142 | * many NAKs. |
72246da4 | 1143 | */ |
0fc9a1be FB |
1144 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1145 | dep->direction); | |
1146 | if (ret) | |
1147 | return ret; | |
1148 | ||
72246da4 FB |
1149 | list_add_tail(&req->list, &dep->request_list); |
1150 | ||
1151 | /* | |
b511e5e7 | 1152 | * There are a few special cases: |
72246da4 | 1153 | * |
f898ae09 PZ |
1154 | * 1. XferNotReady with empty list of requests. We need to kick the |
1155 | * transfer here in that situation, otherwise we will be NAKing | |
1156 | * forever. If we get XferNotReady before gadget driver has a | |
1157 | * chance to queue a request, we will ACK the IRQ but won't be | |
1158 | * able to receive the data until the next request is queued. | |
1159 | * The following code is handling exactly that. | |
72246da4 | 1160 | * |
72246da4 FB |
1161 | */ |
1162 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f4a53c55 PA |
1163 | /* |
1164 | * If xfernotready is already elapsed and it is a case | |
1165 | * of isoc transfer, then issue END TRANSFER, so that | |
1166 | * you can receive xfernotready again and can have | |
1167 | * notion of current microframe. | |
1168 | */ | |
1169 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
cdc359dd | 1170 | if (list_empty(&dep->req_queued)) { |
b992e681 | 1171 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1172 | dep->flags = DWC3_EP_ENABLED; |
1173 | } | |
f4a53c55 PA |
1174 | return 0; |
1175 | } | |
1176 | ||
b511e5e7 | 1177 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
348e026f | 1178 | if (ret && ret != -EBUSY) |
b511e5e7 FB |
1179 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1180 | dep->name); | |
15f86bde | 1181 | return ret; |
b511e5e7 | 1182 | } |
72246da4 | 1183 | |
b511e5e7 FB |
1184 | /* |
1185 | * 2. XferInProgress on Isoc EP with an active transfer. We need to | |
1186 | * kick the transfer here after queuing a request, otherwise the | |
1187 | * core may not see the modified TRB(s). | |
1188 | */ | |
1189 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
79c9046e PA |
1190 | (dep->flags & DWC3_EP_BUSY) && |
1191 | !(dep->flags & DWC3_EP_MISSED_ISOC)) { | |
b4996a86 FB |
1192 | WARN_ON_ONCE(!dep->resource_index); |
1193 | ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, | |
b511e5e7 | 1194 | false); |
348e026f | 1195 | if (ret && ret != -EBUSY) |
72246da4 FB |
1196 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1197 | dep->name); | |
15f86bde | 1198 | return ret; |
a0925324 | 1199 | } |
72246da4 | 1200 | |
b997ada5 FB |
1201 | /* |
1202 | * 4. Stream Capable Bulk Endpoints. We need to start the transfer | |
1203 | * right away, otherwise host will not know we have streams to be | |
1204 | * handled. | |
1205 | */ | |
1206 | if (dep->stream_capable) { | |
1207 | int ret; | |
1208 | ||
1209 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); | |
1210 | if (ret && ret != -EBUSY) { | |
1211 | struct dwc3 *dwc = dep->dwc; | |
1212 | ||
1213 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
1214 | dep->name); | |
1215 | } | |
1216 | } | |
1217 | ||
72246da4 FB |
1218 | return 0; |
1219 | } | |
1220 | ||
1221 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1222 | gfp_t gfp_flags) | |
1223 | { | |
1224 | struct dwc3_request *req = to_dwc3_request(request); | |
1225 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1226 | struct dwc3 *dwc = dep->dwc; | |
1227 | ||
1228 | unsigned long flags; | |
1229 | ||
1230 | int ret; | |
1231 | ||
16e78db7 | 1232 | if (!dep->endpoint.desc) { |
72246da4 FB |
1233 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
1234 | request, ep->name); | |
1235 | return -ESHUTDOWN; | |
1236 | } | |
1237 | ||
1238 | dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", | |
1239 | request, ep->name, request->length); | |
1240 | ||
1241 | spin_lock_irqsave(&dwc->lock, flags); | |
1242 | ret = __dwc3_gadget_ep_queue(dep, req); | |
1243 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1244 | ||
1245 | return ret; | |
1246 | } | |
1247 | ||
1248 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1249 | struct usb_request *request) | |
1250 | { | |
1251 | struct dwc3_request *req = to_dwc3_request(request); | |
1252 | struct dwc3_request *r = NULL; | |
1253 | ||
1254 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1255 | struct dwc3 *dwc = dep->dwc; | |
1256 | ||
1257 | unsigned long flags; | |
1258 | int ret = 0; | |
1259 | ||
1260 | spin_lock_irqsave(&dwc->lock, flags); | |
1261 | ||
1262 | list_for_each_entry(r, &dep->request_list, list) { | |
1263 | if (r == req) | |
1264 | break; | |
1265 | } | |
1266 | ||
1267 | if (r != req) { | |
1268 | list_for_each_entry(r, &dep->req_queued, list) { | |
1269 | if (r == req) | |
1270 | break; | |
1271 | } | |
1272 | if (r == req) { | |
1273 | /* wait until it is processed */ | |
b992e681 | 1274 | dwc3_stop_active_transfer(dwc, dep->number, true); |
e8d4e8be | 1275 | goto out1; |
72246da4 FB |
1276 | } |
1277 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1278 | request, ep->name); | |
1279 | ret = -EINVAL; | |
1280 | goto out0; | |
1281 | } | |
1282 | ||
e8d4e8be | 1283 | out1: |
72246da4 FB |
1284 | /* giveback the request */ |
1285 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1286 | ||
1287 | out0: | |
1288 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1289 | ||
1290 | return ret; | |
1291 | } | |
1292 | ||
1293 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) | |
1294 | { | |
1295 | struct dwc3_gadget_ep_cmd_params params; | |
1296 | struct dwc3 *dwc = dep->dwc; | |
1297 | int ret; | |
1298 | ||
1299 | memset(¶ms, 0x00, sizeof(params)); | |
1300 | ||
1301 | if (value) { | |
72246da4 FB |
1302 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
1303 | DWC3_DEPCMD_SETSTALL, ¶ms); | |
1304 | if (ret) | |
3f89204b | 1305 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1306 | dep->name); |
1307 | else | |
1308 | dep->flags |= DWC3_EP_STALL; | |
1309 | } else { | |
1310 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1311 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1312 | if (ret) | |
3f89204b | 1313 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1314 | dep->name); |
1315 | else | |
a535d81c | 1316 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1317 | } |
5275455a | 1318 | |
72246da4 FB |
1319 | return ret; |
1320 | } | |
1321 | ||
1322 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1323 | { | |
1324 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1325 | struct dwc3 *dwc = dep->dwc; | |
1326 | ||
1327 | unsigned long flags; | |
1328 | ||
1329 | int ret; | |
1330 | ||
1331 | spin_lock_irqsave(&dwc->lock, flags); | |
1332 | ||
16e78db7 | 1333 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1334 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); |
1335 | ret = -EINVAL; | |
1336 | goto out; | |
1337 | } | |
1338 | ||
1339 | ret = __dwc3_gadget_ep_set_halt(dep, value); | |
1340 | out: | |
1341 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1342 | ||
1343 | return ret; | |
1344 | } | |
1345 | ||
1346 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1347 | { | |
1348 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1349 | struct dwc3 *dwc = dep->dwc; |
1350 | unsigned long flags; | |
72246da4 | 1351 | |
249a4569 | 1352 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1353 | dep->flags |= DWC3_EP_WEDGE; |
249a4569 | 1354 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 | 1355 | |
08f0d966 PA |
1356 | if (dep->number == 0 || dep->number == 1) |
1357 | return dwc3_gadget_ep0_set_halt(ep, 1); | |
1358 | else | |
1359 | return dwc3_gadget_ep_set_halt(ep, 1); | |
72246da4 FB |
1360 | } |
1361 | ||
1362 | /* -------------------------------------------------------------------------- */ | |
1363 | ||
1364 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1365 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1366 | .bDescriptorType = USB_DT_ENDPOINT, | |
1367 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1368 | }; | |
1369 | ||
1370 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1371 | .enable = dwc3_gadget_ep0_enable, | |
1372 | .disable = dwc3_gadget_ep0_disable, | |
1373 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1374 | .free_request = dwc3_gadget_ep_free_request, | |
1375 | .queue = dwc3_gadget_ep0_queue, | |
1376 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1377 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1378 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1379 | }; | |
1380 | ||
1381 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1382 | .enable = dwc3_gadget_ep_enable, | |
1383 | .disable = dwc3_gadget_ep_disable, | |
1384 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1385 | .free_request = dwc3_gadget_ep_free_request, | |
1386 | .queue = dwc3_gadget_ep_queue, | |
1387 | .dequeue = dwc3_gadget_ep_dequeue, | |
1388 | .set_halt = dwc3_gadget_ep_set_halt, | |
1389 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1390 | }; | |
1391 | ||
1392 | /* -------------------------------------------------------------------------- */ | |
1393 | ||
1394 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1395 | { | |
1396 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1397 | u32 reg; | |
1398 | ||
1399 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1400 | return DWC3_DSTS_SOFFN(reg); | |
1401 | } | |
1402 | ||
1403 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1404 | { | |
1405 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1406 | ||
1407 | unsigned long timeout; | |
1408 | unsigned long flags; | |
1409 | ||
1410 | u32 reg; | |
1411 | ||
1412 | int ret = 0; | |
1413 | ||
1414 | u8 link_state; | |
1415 | u8 speed; | |
1416 | ||
1417 | spin_lock_irqsave(&dwc->lock, flags); | |
1418 | ||
1419 | /* | |
1420 | * According to the Databook Remote wakeup request should | |
1421 | * be issued only when the device is in early suspend state. | |
1422 | * | |
1423 | * We can check that via USB Link State bits in DSTS register. | |
1424 | */ | |
1425 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1426 | ||
1427 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
1428 | if (speed == DWC3_DSTS_SUPERSPEED) { | |
1429 | dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); | |
1430 | ret = -EINVAL; | |
1431 | goto out; | |
1432 | } | |
1433 | ||
1434 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1435 | ||
1436 | switch (link_state) { | |
1437 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1438 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1439 | break; | |
1440 | default: | |
1441 | dev_dbg(dwc->dev, "can't wakeup from link state %d\n", | |
1442 | link_state); | |
1443 | ret = -EINVAL; | |
1444 | goto out; | |
1445 | } | |
1446 | ||
8598bde7 FB |
1447 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1448 | if (ret < 0) { | |
1449 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
1450 | goto out; | |
1451 | } | |
72246da4 | 1452 | |
802fde98 PZ |
1453 | /* Recent versions do this automatically */ |
1454 | if (dwc->revision < DWC3_REVISION_194A) { | |
1455 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1456 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1457 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1458 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1459 | } | |
72246da4 | 1460 | |
1d046793 | 1461 | /* poll until Link State changes to ON */ |
72246da4 FB |
1462 | timeout = jiffies + msecs_to_jiffies(100); |
1463 | ||
1d046793 | 1464 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1465 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1466 | ||
1467 | /* in HS, means ON */ | |
1468 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1469 | break; | |
1470 | } | |
1471 | ||
1472 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1473 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
1474 | ret = -EINVAL; | |
1475 | } | |
1476 | ||
1477 | out: | |
1478 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1479 | ||
1480 | return ret; | |
1481 | } | |
1482 | ||
1483 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1484 | int is_selfpowered) | |
1485 | { | |
1486 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1487 | unsigned long flags; |
72246da4 | 1488 | |
249a4569 | 1489 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1490 | dwc->is_selfpowered = !!is_selfpowered; |
249a4569 | 1491 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1492 | |
1493 | return 0; | |
1494 | } | |
1495 | ||
7b2a0368 | 1496 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1497 | { |
1498 | u32 reg; | |
61d58242 | 1499 | u32 timeout = 500; |
72246da4 FB |
1500 | |
1501 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
8db7ed15 | 1502 | if (is_on) { |
802fde98 PZ |
1503 | if (dwc->revision <= DWC3_REVISION_187A) { |
1504 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1505 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1506 | } | |
1507 | ||
1508 | if (dwc->revision >= DWC3_REVISION_194A) | |
1509 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1510 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1511 | |
1512 | if (dwc->has_hibernation) | |
1513 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1514 | ||
9fcb3bd8 | 1515 | dwc->pullups_connected = true; |
8db7ed15 | 1516 | } else { |
72246da4 | 1517 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1518 | |
1519 | if (dwc->has_hibernation && !suspend) | |
1520 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1521 | ||
9fcb3bd8 | 1522 | dwc->pullups_connected = false; |
8db7ed15 | 1523 | } |
72246da4 FB |
1524 | |
1525 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1526 | ||
1527 | do { | |
1528 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1529 | if (is_on) { | |
1530 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1531 | break; | |
1532 | } else { | |
1533 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1534 | break; | |
1535 | } | |
72246da4 FB |
1536 | timeout--; |
1537 | if (!timeout) | |
6f17f74b | 1538 | return -ETIMEDOUT; |
61d58242 | 1539 | udelay(1); |
72246da4 FB |
1540 | } while (1); |
1541 | ||
1542 | dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", | |
1543 | dwc->gadget_driver | |
1544 | ? dwc->gadget_driver->function : "no-function", | |
1545 | is_on ? "connect" : "disconnect"); | |
6f17f74b PA |
1546 | |
1547 | return 0; | |
72246da4 FB |
1548 | } |
1549 | ||
1550 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1551 | { | |
1552 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1553 | unsigned long flags; | |
6f17f74b | 1554 | int ret; |
72246da4 FB |
1555 | |
1556 | is_on = !!is_on; | |
1557 | ||
1558 | spin_lock_irqsave(&dwc->lock, flags); | |
7b2a0368 | 1559 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1560 | spin_unlock_irqrestore(&dwc->lock, flags); |
1561 | ||
6f17f74b | 1562 | return ret; |
72246da4 FB |
1563 | } |
1564 | ||
8698e2ac FB |
1565 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1566 | { | |
1567 | u32 reg; | |
1568 | ||
1569 | /* Enable all but Start and End of Frame IRQs */ | |
1570 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1571 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1572 | DWC3_DEVTEN_CMDCMPLTEN | | |
1573 | DWC3_DEVTEN_ERRTICERREN | | |
1574 | DWC3_DEVTEN_WKUPEVTEN | | |
1575 | DWC3_DEVTEN_ULSTCNGEN | | |
1576 | DWC3_DEVTEN_CONNECTDONEEN | | |
1577 | DWC3_DEVTEN_USBRSTEN | | |
1578 | DWC3_DEVTEN_DISCONNEVTEN); | |
1579 | ||
1580 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1581 | } | |
1582 | ||
1583 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1584 | { | |
1585 | /* mask all interrupts */ | |
1586 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1587 | } | |
1588 | ||
1589 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1590 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1591 | |
72246da4 FB |
1592 | static int dwc3_gadget_start(struct usb_gadget *g, |
1593 | struct usb_gadget_driver *driver) | |
1594 | { | |
1595 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1596 | struct dwc3_ep *dep; | |
1597 | unsigned long flags; | |
1598 | int ret = 0; | |
8698e2ac | 1599 | int irq; |
72246da4 FB |
1600 | u32 reg; |
1601 | ||
b0d7ffd4 FB |
1602 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1603 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
e8adfc30 | 1604 | IRQF_SHARED, "dwc3", dwc); |
b0d7ffd4 FB |
1605 | if (ret) { |
1606 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1607 | irq, ret); | |
1608 | goto err0; | |
1609 | } | |
1610 | ||
72246da4 FB |
1611 | spin_lock_irqsave(&dwc->lock, flags); |
1612 | ||
1613 | if (dwc->gadget_driver) { | |
1614 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1615 | dwc->gadget.name, | |
1616 | dwc->gadget_driver->driver.name); | |
1617 | ret = -EBUSY; | |
b0d7ffd4 | 1618 | goto err1; |
72246da4 FB |
1619 | } |
1620 | ||
1621 | dwc->gadget_driver = driver; | |
72246da4 | 1622 | |
72246da4 FB |
1623 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1624 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1625 | |
1626 | /** | |
1627 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1628 | * which would cause metastability state on Run/Stop | |
1629 | * bit if we try to force the IP to USB2-only mode. | |
1630 | * | |
1631 | * Because of that, we cannot configure the IP to any | |
1632 | * speed other than the SuperSpeed | |
1633 | * | |
1634 | * Refers to: | |
1635 | * | |
1636 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1637 | * USB 2.0 Mode | |
1638 | */ | |
f7e846f0 | 1639 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1640 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1641 | } else { |
1642 | switch (dwc->maximum_speed) { | |
1643 | case USB_SPEED_LOW: | |
1644 | reg |= DWC3_DSTS_LOWSPEED; | |
1645 | break; | |
1646 | case USB_SPEED_FULL: | |
1647 | reg |= DWC3_DSTS_FULLSPEED1; | |
1648 | break; | |
1649 | case USB_SPEED_HIGH: | |
1650 | reg |= DWC3_DSTS_HIGHSPEED; | |
1651 | break; | |
1652 | case USB_SPEED_SUPER: /* FALLTHROUGH */ | |
1653 | case USB_SPEED_UNKNOWN: /* FALTHROUGH */ | |
1654 | default: | |
1655 | reg |= DWC3_DSTS_SUPERSPEED; | |
1656 | } | |
1657 | } | |
72246da4 FB |
1658 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1659 | ||
b23c8439 PZ |
1660 | dwc->start_config_issued = false; |
1661 | ||
72246da4 FB |
1662 | /* Start with SuperSpeed Default */ |
1663 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1664 | ||
1665 | dep = dwc->eps[0]; | |
265b70a7 PZ |
1666 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1667 | false); | |
72246da4 FB |
1668 | if (ret) { |
1669 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1670 | goto err2; |
72246da4 FB |
1671 | } |
1672 | ||
1673 | dep = dwc->eps[1]; | |
265b70a7 PZ |
1674 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1675 | false); | |
72246da4 FB |
1676 | if (ret) { |
1677 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1678 | goto err3; |
72246da4 FB |
1679 | } |
1680 | ||
1681 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1682 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1683 | dwc3_ep0_out_start(dwc); |
1684 | ||
8698e2ac FB |
1685 | dwc3_gadget_enable_irq(dwc); |
1686 | ||
72246da4 FB |
1687 | spin_unlock_irqrestore(&dwc->lock, flags); |
1688 | ||
1689 | return 0; | |
1690 | ||
b0d7ffd4 | 1691 | err3: |
72246da4 FB |
1692 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1693 | ||
b0d7ffd4 | 1694 | err2: |
cdcedd69 | 1695 | dwc->gadget_driver = NULL; |
b0d7ffd4 FB |
1696 | |
1697 | err1: | |
72246da4 FB |
1698 | spin_unlock_irqrestore(&dwc->lock, flags); |
1699 | ||
b0d7ffd4 FB |
1700 | free_irq(irq, dwc); |
1701 | ||
1702 | err0: | |
72246da4 FB |
1703 | return ret; |
1704 | } | |
1705 | ||
1706 | static int dwc3_gadget_stop(struct usb_gadget *g, | |
1707 | struct usb_gadget_driver *driver) | |
1708 | { | |
1709 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1710 | unsigned long flags; | |
8698e2ac | 1711 | int irq; |
72246da4 FB |
1712 | |
1713 | spin_lock_irqsave(&dwc->lock, flags); | |
1714 | ||
8698e2ac | 1715 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1716 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1717 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1718 | ||
1719 | dwc->gadget_driver = NULL; | |
72246da4 FB |
1720 | |
1721 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1722 | ||
b0d7ffd4 FB |
1723 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1724 | free_irq(irq, dwc); | |
1725 | ||
72246da4 FB |
1726 | return 0; |
1727 | } | |
802fde98 | 1728 | |
72246da4 FB |
1729 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1730 | .get_frame = dwc3_gadget_get_frame, | |
1731 | .wakeup = dwc3_gadget_wakeup, | |
1732 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1733 | .pullup = dwc3_gadget_pullup, | |
1734 | .udc_start = dwc3_gadget_start, | |
1735 | .udc_stop = dwc3_gadget_stop, | |
1736 | }; | |
1737 | ||
1738 | /* -------------------------------------------------------------------------- */ | |
1739 | ||
6a1e3ef4 FB |
1740 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1741 | u8 num, u32 direction) | |
72246da4 FB |
1742 | { |
1743 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1744 | u8 i; |
72246da4 | 1745 | |
6a1e3ef4 FB |
1746 | for (i = 0; i < num; i++) { |
1747 | u8 epnum = (i << 1) | (!!direction); | |
72246da4 | 1748 | |
72246da4 FB |
1749 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
1750 | if (!dep) { | |
1751 | dev_err(dwc->dev, "can't allocate endpoint %d\n", | |
1752 | epnum); | |
1753 | return -ENOMEM; | |
1754 | } | |
1755 | ||
1756 | dep->dwc = dwc; | |
1757 | dep->number = epnum; | |
9aa62ae4 | 1758 | dep->direction = !!direction; |
72246da4 FB |
1759 | dwc->eps[epnum] = dep; |
1760 | ||
1761 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1762 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1763 | |
72246da4 | 1764 | dep->endpoint.name = dep->name; |
72246da4 | 1765 | |
653df35e FB |
1766 | dev_vdbg(dwc->dev, "initializing %s\n", dep->name); |
1767 | ||
72246da4 | 1768 | if (epnum == 0 || epnum == 1) { |
e117e742 | 1769 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1770 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1771 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1772 | if (!epnum) | |
1773 | dwc->gadget.ep0 = &dep->endpoint; | |
1774 | } else { | |
1775 | int ret; | |
1776 | ||
e117e742 | 1777 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1778 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1779 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1780 | list_add_tail(&dep->endpoint.ep_list, | |
1781 | &dwc->gadget.ep_list); | |
1782 | ||
1783 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1784 | if (ret) |
72246da4 | 1785 | return ret; |
72246da4 | 1786 | } |
25b8ff68 | 1787 | |
72246da4 FB |
1788 | INIT_LIST_HEAD(&dep->request_list); |
1789 | INIT_LIST_HEAD(&dep->req_queued); | |
1790 | } | |
1791 | ||
1792 | return 0; | |
1793 | } | |
1794 | ||
6a1e3ef4 FB |
1795 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1796 | { | |
1797 | int ret; | |
1798 | ||
1799 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1800 | ||
1801 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1802 | if (ret < 0) { | |
1803 | dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n"); | |
1804 | return ret; | |
1805 | } | |
1806 | ||
1807 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1808 | if (ret < 0) { | |
1809 | dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n"); | |
1810 | return ret; | |
1811 | } | |
1812 | ||
1813 | return 0; | |
1814 | } | |
1815 | ||
72246da4 FB |
1816 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1817 | { | |
1818 | struct dwc3_ep *dep; | |
1819 | u8 epnum; | |
1820 | ||
1821 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1822 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1823 | if (!dep) |
1824 | continue; | |
5bf8fae3 GC |
1825 | /* |
1826 | * Physical endpoints 0 and 1 are special; they form the | |
1827 | * bi-directional USB endpoint 0. | |
1828 | * | |
1829 | * For those two physical endpoints, we don't allocate a TRB | |
1830 | * pool nor do we add them the endpoints list. Due to that, we | |
1831 | * shouldn't do these two operations otherwise we would end up | |
1832 | * with all sorts of bugs when removing dwc3.ko. | |
1833 | */ | |
1834 | if (epnum != 0 && epnum != 1) { | |
1835 | dwc3_free_trb_pool(dep); | |
72246da4 | 1836 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1837 | } |
72246da4 FB |
1838 | |
1839 | kfree(dep); | |
1840 | } | |
1841 | } | |
1842 | ||
72246da4 | 1843 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1844 | |
e5ba5ec8 PA |
1845 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1846 | struct dwc3_request *req, struct dwc3_trb *trb, | |
72246da4 FB |
1847 | const struct dwc3_event_depevt *event, int status) |
1848 | { | |
72246da4 FB |
1849 | unsigned int count; |
1850 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1851 | unsigned int trb_status; |
72246da4 | 1852 | |
e5ba5ec8 PA |
1853 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
1854 | /* | |
1855 | * We continue despite the error. There is not much we | |
1856 | * can do. If we don't clean it up we loop forever. If | |
1857 | * we skip the TRB then it gets overwritten after a | |
1858 | * while since we use them in a ring buffer. A BUG() | |
1859 | * would help. Lets hope that if this occurs, someone | |
1860 | * fixes the root cause instead of looking away :) | |
1861 | */ | |
1862 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", | |
1863 | dep->name, trb); | |
1864 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1865 | ||
1866 | if (dep->direction) { | |
1867 | if (count) { | |
1868 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1869 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
1870 | dev_dbg(dwc->dev, "incomplete IN transfer %s\n", | |
1871 | dep->name); | |
1872 | /* | |
1873 | * If missed isoc occurred and there is | |
1874 | * no request queued then issue END | |
1875 | * TRANSFER, so that core generates | |
1876 | * next xfernotready and we will issue | |
1877 | * a fresh START TRANSFER. | |
1878 | * If there are still queued request | |
1879 | * then wait, do not issue either END | |
1880 | * or UPDATE TRANSFER, just attach next | |
1881 | * request in request_list during | |
1882 | * giveback.If any future queued request | |
1883 | * is successfully transferred then we | |
1884 | * will issue UPDATE TRANSFER for all | |
1885 | * request in the request_list. | |
1886 | */ | |
1887 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1888 | } else { | |
1889 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1890 | dep->name); | |
1891 | status = -ECONNRESET; | |
1892 | } | |
1893 | } else { | |
1894 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1895 | } | |
1896 | } else { | |
1897 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1898 | s_pkt = 1; | |
1899 | } | |
1900 | ||
1901 | /* | |
1902 | * We assume here we will always receive the entire data block | |
1903 | * which we should receive. Meaning, if we program RX to | |
1904 | * receive 4K but we receive only 2K, we assume that's all we | |
1905 | * should receive and we simply bounce the request back to the | |
1906 | * gadget driver for further processing. | |
1907 | */ | |
1908 | req->request.actual += req->request.length - count; | |
1909 | if (s_pkt) | |
1910 | return 1; | |
1911 | if ((event->status & DEPEVT_STATUS_LST) && | |
1912 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1913 | DWC3_TRB_CTRL_HWO))) | |
1914 | return 1; | |
1915 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1916 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1917 | return 1; | |
1918 | return 0; | |
1919 | } | |
1920 | ||
1921 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1922 | const struct dwc3_event_depevt *event, int status) | |
1923 | { | |
1924 | struct dwc3_request *req; | |
1925 | struct dwc3_trb *trb; | |
1926 | unsigned int slot; | |
1927 | unsigned int i; | |
1928 | int ret; | |
1929 | ||
72246da4 FB |
1930 | do { |
1931 | req = next_request(&dep->req_queued); | |
d39ee7be SAS |
1932 | if (!req) { |
1933 | WARN_ON_ONCE(1); | |
1934 | return 1; | |
1935 | } | |
e5ba5ec8 PA |
1936 | i = 0; |
1937 | do { | |
1938 | slot = req->start_slot + i; | |
1939 | if ((slot == DWC3_TRB_NUM - 1) && | |
1940 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
1941 | slot++; | |
1942 | slot %= DWC3_TRB_NUM; | |
1943 | trb = &dep->trb_pool[slot]; | |
72246da4 | 1944 | |
e5ba5ec8 PA |
1945 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
1946 | event, status); | |
1947 | if (ret) | |
1948 | break; | |
1949 | }while (++i < req->request.num_mapped_sgs); | |
72246da4 | 1950 | |
72246da4 | 1951 | dwc3_gadget_giveback(dep, req, status); |
e5ba5ec8 PA |
1952 | |
1953 | if (ret) | |
72246da4 FB |
1954 | break; |
1955 | } while (1); | |
1956 | ||
cdc359dd PA |
1957 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
1958 | list_empty(&dep->req_queued)) { | |
1959 | if (list_empty(&dep->request_list)) { | |
1960 | /* | |
1961 | * If there is no entry in request list then do | |
1962 | * not issue END TRANSFER now. Just set PENDING | |
1963 | * flag, so that END TRANSFER is issued when an | |
1964 | * entry is added into request list. | |
1965 | */ | |
1966 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
1967 | } else { | |
b992e681 | 1968 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1969 | dep->flags = DWC3_EP_ENABLED; |
1970 | } | |
7efea86c PA |
1971 | return 1; |
1972 | } | |
1973 | ||
72246da4 FB |
1974 | return 1; |
1975 | } | |
1976 | ||
1977 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
1978 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event, | |
1979 | int start_new) | |
1980 | { | |
1981 | unsigned status = 0; | |
1982 | int clean_busy; | |
1983 | ||
1984 | if (event->status & DEPEVT_STATUS_BUSERR) | |
1985 | status = -ECONNRESET; | |
1986 | ||
1d046793 | 1987 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
c2df85ca | 1988 | if (clean_busy) |
72246da4 | 1989 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
1990 | |
1991 | /* | |
1992 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
1993 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
1994 | */ | |
1995 | if (dwc->revision < DWC3_REVISION_183A) { | |
1996 | u32 reg; | |
1997 | int i; | |
1998 | ||
1999 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2000 | dep = dwc->eps[i]; |
fae2b904 FB |
2001 | |
2002 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2003 | continue; | |
2004 | ||
2005 | if (!list_empty(&dep->req_queued)) | |
2006 | return; | |
2007 | } | |
2008 | ||
2009 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2010 | reg |= dwc->u1u2; | |
2011 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2012 | ||
2013 | dwc->u1u2 = 0; | |
2014 | } | |
72246da4 FB |
2015 | } |
2016 | ||
72246da4 FB |
2017 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2018 | const struct dwc3_event_depevt *event) | |
2019 | { | |
2020 | struct dwc3_ep *dep; | |
2021 | u8 epnum = event->endpoint_number; | |
2022 | ||
2023 | dep = dwc->eps[epnum]; | |
2024 | ||
3336abb5 FB |
2025 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2026 | return; | |
2027 | ||
72246da4 FB |
2028 | dev_vdbg(dwc->dev, "%s: %s\n", dep->name, |
2029 | dwc3_ep_event_string(event->endpoint_event)); | |
2030 | ||
2031 | if (epnum == 0 || epnum == 1) { | |
2032 | dwc3_ep0_interrupt(dwc, event); | |
2033 | return; | |
2034 | } | |
2035 | ||
2036 | switch (event->endpoint_event) { | |
2037 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 2038 | dep->resource_index = 0; |
c2df85ca | 2039 | |
16e78db7 | 2040 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2041 | dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", |
2042 | dep->name); | |
2043 | return; | |
2044 | } | |
2045 | ||
2046 | dwc3_endpoint_transfer_complete(dwc, dep, event, 1); | |
2047 | break; | |
2048 | case DWC3_DEPEVT_XFERINPROGRESS: | |
16e78db7 | 2049 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2050 | dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", |
2051 | dep->name); | |
2052 | return; | |
2053 | } | |
2054 | ||
2055 | dwc3_endpoint_transfer_complete(dwc, dep, event, 0); | |
2056 | break; | |
2057 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2058 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2059 | dwc3_gadget_start_isoc(dwc, dep, event); |
2060 | } else { | |
2061 | int ret; | |
2062 | ||
2063 | dev_vdbg(dwc->dev, "%s: reason %s\n", | |
40aa41fb FB |
2064 | dep->name, event->status & |
2065 | DEPEVT_STATUS_TRANSFER_ACTIVE | |
72246da4 FB |
2066 | ? "Transfer Active" |
2067 | : "Transfer Not Active"); | |
2068 | ||
2069 | ret = __dwc3_gadget_kick_transfer(dep, 0, 1); | |
2070 | if (!ret || ret == -EBUSY) | |
2071 | return; | |
2072 | ||
2073 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
2074 | dep->name); | |
2075 | } | |
2076 | ||
879631aa FB |
2077 | break; |
2078 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2079 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2080 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2081 | dep->name); | |
2082 | return; | |
2083 | } | |
2084 | ||
2085 | switch (event->status) { | |
2086 | case DEPEVT_STREAMEVT_FOUND: | |
2087 | dev_vdbg(dwc->dev, "Stream %d found and started\n", | |
2088 | event->parameters); | |
2089 | ||
2090 | break; | |
2091 | case DEPEVT_STREAMEVT_NOTFOUND: | |
2092 | /* FALLTHROUGH */ | |
2093 | default: | |
2094 | dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); | |
2095 | } | |
72246da4 FB |
2096 | break; |
2097 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
2098 | dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); | |
2099 | break; | |
72246da4 | 2100 | case DWC3_DEPEVT_EPCMDCMPLT: |
ea53b882 | 2101 | dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); |
72246da4 FB |
2102 | break; |
2103 | } | |
2104 | } | |
2105 | ||
2106 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2107 | { | |
2108 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2109 | spin_unlock(&dwc->lock); | |
2110 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2111 | spin_lock(&dwc->lock); | |
2112 | } | |
2113 | } | |
2114 | ||
bc5ba2e0 FB |
2115 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2116 | { | |
73a30bfc | 2117 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2118 | spin_unlock(&dwc->lock); |
2119 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2120 | spin_lock(&dwc->lock); | |
2121 | } | |
2122 | } | |
2123 | ||
2124 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2125 | { | |
73a30bfc | 2126 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2127 | spin_unlock(&dwc->lock); |
2128 | dwc->gadget_driver->resume(&dwc->gadget); | |
2129 | spin_lock(&dwc->lock); | |
2130 | } | |
2131 | } | |
2132 | ||
b992e681 | 2133 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2134 | { |
2135 | struct dwc3_ep *dep; | |
2136 | struct dwc3_gadget_ep_cmd_params params; | |
2137 | u32 cmd; | |
2138 | int ret; | |
2139 | ||
2140 | dep = dwc->eps[epnum]; | |
2141 | ||
b4996a86 | 2142 | if (!dep->resource_index) |
3daf74d7 PA |
2143 | return; |
2144 | ||
57911504 PA |
2145 | /* |
2146 | * NOTICE: We are violating what the Databook says about the | |
2147 | * EndTransfer command. Ideally we would _always_ wait for the | |
2148 | * EndTransfer Command Completion IRQ, but that's causing too | |
2149 | * much trouble synchronizing between us and gadget driver. | |
2150 | * | |
2151 | * We have discussed this with the IP Provider and it was | |
2152 | * suggested to giveback all requests here, but give HW some | |
2153 | * extra time to synchronize with the interconnect. We're using | |
2154 | * an arbitraty 100us delay for that. | |
2155 | * | |
2156 | * Note also that a similar handling was tested by Synopsys | |
2157 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2158 | * In short, what we're doing is: | |
2159 | * | |
2160 | * - Issue EndTransfer WITH CMDIOC bit set | |
2161 | * - Wait 100us | |
2162 | */ | |
2163 | ||
3daf74d7 | 2164 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2165 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2166 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2167 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 PA |
2168 | memset(¶ms, 0, sizeof(params)); |
2169 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
2170 | WARN_ON_ONCE(ret); | |
b4996a86 | 2171 | dep->resource_index = 0; |
041d81f4 | 2172 | dep->flags &= ~DWC3_EP_BUSY; |
57911504 | 2173 | udelay(100); |
72246da4 FB |
2174 | } |
2175 | ||
2176 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2177 | { | |
2178 | u32 epnum; | |
2179 | ||
2180 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2181 | struct dwc3_ep *dep; | |
2182 | ||
2183 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2184 | if (!dep) |
2185 | continue; | |
2186 | ||
72246da4 FB |
2187 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2188 | continue; | |
2189 | ||
624407f9 | 2190 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
2191 | } |
2192 | } | |
2193 | ||
2194 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2195 | { | |
2196 | u32 epnum; | |
2197 | ||
2198 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2199 | struct dwc3_ep *dep; | |
2200 | struct dwc3_gadget_ep_cmd_params params; | |
2201 | int ret; | |
2202 | ||
2203 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2204 | if (!dep) |
2205 | continue; | |
72246da4 FB |
2206 | |
2207 | if (!(dep->flags & DWC3_EP_STALL)) | |
2208 | continue; | |
2209 | ||
2210 | dep->flags &= ~DWC3_EP_STALL; | |
2211 | ||
2212 | memset(¶ms, 0, sizeof(params)); | |
2213 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
2214 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
2215 | WARN_ON_ONCE(ret); | |
2216 | } | |
2217 | } | |
2218 | ||
2219 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2220 | { | |
c4430a26 FB |
2221 | int reg; |
2222 | ||
72246da4 | 2223 | dev_vdbg(dwc->dev, "%s\n", __func__); |
72246da4 FB |
2224 | |
2225 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2226 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2227 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2228 | ||
2229 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2230 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2231 | |
72246da4 | 2232 | dwc3_disconnect_gadget(dwc); |
b23c8439 | 2233 | dwc->start_config_issued = false; |
72246da4 FB |
2234 | |
2235 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2236 | dwc->setup_packet_pending = false; |
72246da4 FB |
2237 | } |
2238 | ||
72246da4 FB |
2239 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2240 | { | |
2241 | u32 reg; | |
2242 | ||
2243 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2244 | ||
df62df56 FB |
2245 | /* |
2246 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2247 | * would cause a missing Disconnect Event if there's a | |
2248 | * pending Setup Packet in the FIFO. | |
2249 | * | |
2250 | * There's no suggested workaround on the official Bug | |
2251 | * report, which states that "unless the driver/application | |
2252 | * is doing any special handling of a disconnect event, | |
2253 | * there is no functional issue". | |
2254 | * | |
2255 | * Unfortunately, it turns out that we _do_ some special | |
2256 | * handling of a disconnect event, namely complete all | |
2257 | * pending transfers, notify gadget driver of the | |
2258 | * disconnection, and so on. | |
2259 | * | |
2260 | * Our suggested workaround is to follow the Disconnect | |
2261 | * Event steps here, instead, based on a setup_packet_pending | |
2262 | * flag. Such flag gets set whenever we have a XferNotReady | |
2263 | * event on EP0 and gets cleared on XferComplete for the | |
2264 | * same endpoint. | |
2265 | * | |
2266 | * Refers to: | |
2267 | * | |
2268 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2269 | * generated if setup packet pending in FIFO | |
2270 | */ | |
2271 | if (dwc->revision < DWC3_REVISION_188A) { | |
2272 | if (dwc->setup_packet_pending) | |
2273 | dwc3_gadget_disconnect_interrupt(dwc); | |
2274 | } | |
2275 | ||
961906ed | 2276 | /* after reset -> Default State */ |
14cd592f | 2277 | usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); |
961906ed | 2278 | |
72246da4 FB |
2279 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) |
2280 | dwc3_disconnect_gadget(dwc); | |
2281 | ||
2282 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2283 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2284 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2285 | dwc->test_mode = false; |
72246da4 FB |
2286 | |
2287 | dwc3_stop_active_transfers(dwc); | |
2288 | dwc3_clear_stall_all_ep(dwc); | |
b23c8439 | 2289 | dwc->start_config_issued = false; |
72246da4 FB |
2290 | |
2291 | /* Reset device address to zero */ | |
2292 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2293 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2294 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2295 | } |
2296 | ||
2297 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2298 | { | |
2299 | u32 reg; | |
2300 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2301 | ||
2302 | /* | |
2303 | * We change the clock only at SS but I dunno why I would want to do | |
2304 | * this. Maybe it becomes part of the power saving plan. | |
2305 | */ | |
2306 | ||
2307 | if (speed != DWC3_DSTS_SUPERSPEED) | |
2308 | return; | |
2309 | ||
2310 | /* | |
2311 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2312 | * each time on Connect Done. | |
2313 | */ | |
2314 | if (!usb30_clock) | |
2315 | return; | |
2316 | ||
2317 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2318 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2319 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2320 | } | |
2321 | ||
72246da4 FB |
2322 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2323 | { | |
72246da4 FB |
2324 | struct dwc3_ep *dep; |
2325 | int ret; | |
2326 | u32 reg; | |
2327 | u8 speed; | |
2328 | ||
2329 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2330 | ||
72246da4 FB |
2331 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2332 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2333 | dwc->speed = speed; | |
2334 | ||
2335 | dwc3_update_ram_clk_sel(dwc, speed); | |
2336 | ||
2337 | switch (speed) { | |
2338 | case DWC3_DCFG_SUPERSPEED: | |
05870c5b FB |
2339 | /* |
2340 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2341 | * would cause a missing USB3 Reset event. | |
2342 | * | |
2343 | * In such situations, we should force a USB3 Reset | |
2344 | * event by calling our dwc3_gadget_reset_interrupt() | |
2345 | * routine. | |
2346 | * | |
2347 | * Refers to: | |
2348 | * | |
2349 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2350 | * not be generated always when the link enters poll | |
2351 | */ | |
2352 | if (dwc->revision < DWC3_REVISION_190A) | |
2353 | dwc3_gadget_reset_interrupt(dwc); | |
2354 | ||
72246da4 FB |
2355 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2356 | dwc->gadget.ep0->maxpacket = 512; | |
2357 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2358 | break; | |
2359 | case DWC3_DCFG_HIGHSPEED: | |
2360 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2361 | dwc->gadget.ep0->maxpacket = 64; | |
2362 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2363 | break; | |
2364 | case DWC3_DCFG_FULLSPEED2: | |
2365 | case DWC3_DCFG_FULLSPEED1: | |
2366 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2367 | dwc->gadget.ep0->maxpacket = 64; | |
2368 | dwc->gadget.speed = USB_SPEED_FULL; | |
2369 | break; | |
2370 | case DWC3_DCFG_LOWSPEED: | |
2371 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2372 | dwc->gadget.ep0->maxpacket = 8; | |
2373 | dwc->gadget.speed = USB_SPEED_LOW; | |
2374 | break; | |
2375 | } | |
2376 | ||
2b758350 PA |
2377 | /* Enable USB2 LPM Capability */ |
2378 | ||
2379 | if ((dwc->revision > DWC3_REVISION_194A) | |
2380 | && (speed != DWC3_DCFG_SUPERSPEED)) { | |
2381 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2382 | reg |= DWC3_DCFG_LPM_CAP; | |
2383 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2384 | ||
2385 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2386 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2387 | ||
1a947746 FB |
2388 | /* |
2389 | * TODO: This should be configurable. For now using | |
2390 | * maximum allowed HIRD threshold value of 0b1100 | |
2391 | */ | |
2392 | reg |= DWC3_DCTL_HIRD_THRES(12); | |
2b758350 | 2393 | |
356363bf FB |
2394 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2395 | } else { | |
2396 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2397 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2398 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2399 | } | |
2400 | ||
72246da4 | 2401 | dep = dwc->eps[0]; |
265b70a7 PZ |
2402 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2403 | false); | |
72246da4 FB |
2404 | if (ret) { |
2405 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2406 | return; | |
2407 | } | |
2408 | ||
2409 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2410 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2411 | false); | |
72246da4 FB |
2412 | if (ret) { |
2413 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2414 | return; | |
2415 | } | |
2416 | ||
2417 | /* | |
2418 | * Configure PHY via GUSB3PIPECTLn if required. | |
2419 | * | |
2420 | * Update GTXFIFOSIZn | |
2421 | * | |
2422 | * In both cases reset values should be sufficient. | |
2423 | */ | |
2424 | } | |
2425 | ||
2426 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2427 | { | |
2428 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2429 | ||
2430 | /* | |
2431 | * TODO take core out of low power mode when that's | |
2432 | * implemented. | |
2433 | */ | |
2434 | ||
2435 | dwc->gadget_driver->resume(&dwc->gadget); | |
2436 | } | |
2437 | ||
2438 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2439 | unsigned int evtinfo) | |
2440 | { | |
fae2b904 | 2441 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2442 | unsigned int pwropt; |
2443 | ||
2444 | /* | |
2445 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2446 | * Hibernation mode enabled which would show up when device detects | |
2447 | * host-initiated U3 exit. | |
2448 | * | |
2449 | * In that case, device will generate a Link State Change Interrupt | |
2450 | * from U3 to RESUME which is only necessary if Hibernation is | |
2451 | * configured in. | |
2452 | * | |
2453 | * There are no functional changes due to such spurious event and we | |
2454 | * just need to ignore it. | |
2455 | * | |
2456 | * Refers to: | |
2457 | * | |
2458 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2459 | * operational mode | |
2460 | */ | |
2461 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2462 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2463 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2464 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2465 | (next == DWC3_LINK_STATE_RESUME)) { | |
2466 | dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n"); | |
2467 | return; | |
2468 | } | |
2469 | } | |
fae2b904 FB |
2470 | |
2471 | /* | |
2472 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2473 | * on the link partner, the USB session might do multiple entry/exit | |
2474 | * of low power states before a transfer takes place. | |
2475 | * | |
2476 | * Due to this problem, we might experience lower throughput. The | |
2477 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2478 | * transitioning from U1/U2 to U0 and enable those bits again | |
2479 | * after a transfer completes and there are no pending transfers | |
2480 | * on any of the enabled endpoints. | |
2481 | * | |
2482 | * This is the first half of that workaround. | |
2483 | * | |
2484 | * Refers to: | |
2485 | * | |
2486 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2487 | * core send LGO_Ux entering U0 | |
2488 | */ | |
2489 | if (dwc->revision < DWC3_REVISION_183A) { | |
2490 | if (next == DWC3_LINK_STATE_U0) { | |
2491 | u32 u1u2; | |
2492 | u32 reg; | |
2493 | ||
2494 | switch (dwc->link_state) { | |
2495 | case DWC3_LINK_STATE_U1: | |
2496 | case DWC3_LINK_STATE_U2: | |
2497 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2498 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2499 | | DWC3_DCTL_ACCEPTU2ENA | |
2500 | | DWC3_DCTL_INITU1ENA | |
2501 | | DWC3_DCTL_ACCEPTU1ENA); | |
2502 | ||
2503 | if (!dwc->u1u2) | |
2504 | dwc->u1u2 = reg & u1u2; | |
2505 | ||
2506 | reg &= ~u1u2; | |
2507 | ||
2508 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2509 | break; | |
2510 | default: | |
2511 | /* do nothing */ | |
2512 | break; | |
2513 | } | |
2514 | } | |
2515 | } | |
2516 | ||
bc5ba2e0 FB |
2517 | switch (next) { |
2518 | case DWC3_LINK_STATE_U1: | |
2519 | if (dwc->speed == USB_SPEED_SUPER) | |
2520 | dwc3_suspend_gadget(dwc); | |
2521 | break; | |
2522 | case DWC3_LINK_STATE_U2: | |
2523 | case DWC3_LINK_STATE_U3: | |
2524 | dwc3_suspend_gadget(dwc); | |
2525 | break; | |
2526 | case DWC3_LINK_STATE_RESUME: | |
2527 | dwc3_resume_gadget(dwc); | |
2528 | break; | |
2529 | default: | |
2530 | /* do nothing */ | |
2531 | break; | |
2532 | } | |
2533 | ||
e57ebc1d FB |
2534 | dev_vdbg(dwc->dev, "link change: %s [%d] -> %s [%d]\n", |
2535 | dwc3_gadget_link_string(dwc->link_state), | |
2536 | dwc->link_state, dwc3_gadget_link_string(next), next); | |
2537 | ||
2538 | dwc->link_state = next; | |
72246da4 FB |
2539 | } |
2540 | ||
e1dadd3b FB |
2541 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2542 | unsigned int evtinfo) | |
2543 | { | |
2544 | unsigned int is_ss = evtinfo & BIT(4); | |
2545 | ||
2546 | /** | |
2547 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2548 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2549 | * randomly. | |
2550 | * | |
2551 | * Because of this issue, core could generate bogus hibernation | |
2552 | * events which SW needs to ignore. | |
2553 | * | |
2554 | * Refers to: | |
2555 | * | |
2556 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2557 | * Device Fallback from SuperSpeed | |
2558 | */ | |
2559 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2560 | return; | |
2561 | ||
2562 | /* enter hibernation here */ | |
2563 | } | |
2564 | ||
72246da4 FB |
2565 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2566 | const struct dwc3_event_devt *event) | |
2567 | { | |
2568 | switch (event->type) { | |
2569 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2570 | dwc3_gadget_disconnect_interrupt(dwc); | |
2571 | break; | |
2572 | case DWC3_DEVICE_EVENT_RESET: | |
2573 | dwc3_gadget_reset_interrupt(dwc); | |
2574 | break; | |
2575 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2576 | dwc3_gadget_conndone_interrupt(dwc); | |
2577 | break; | |
2578 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2579 | dwc3_gadget_wakeup_interrupt(dwc); | |
2580 | break; | |
e1dadd3b FB |
2581 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2582 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2583 | "unexpected hibernation event\n")) | |
2584 | break; | |
2585 | ||
2586 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2587 | break; | |
72246da4 FB |
2588 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2589 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2590 | break; | |
2591 | case DWC3_DEVICE_EVENT_EOPF: | |
2592 | dev_vdbg(dwc->dev, "End of Periodic Frame\n"); | |
2593 | break; | |
2594 | case DWC3_DEVICE_EVENT_SOF: | |
2595 | dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); | |
2596 | break; | |
2597 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
2598 | dev_vdbg(dwc->dev, "Erratic Error\n"); | |
2599 | break; | |
2600 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
2601 | dev_vdbg(dwc->dev, "Command Complete\n"); | |
2602 | break; | |
2603 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
2604 | dev_vdbg(dwc->dev, "Overflow\n"); | |
2605 | break; | |
2606 | default: | |
2607 | dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); | |
2608 | } | |
2609 | } | |
2610 | ||
2611 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2612 | const union dwc3_event *event) | |
2613 | { | |
2614 | /* Endpoint IRQ, handle it and return early */ | |
2615 | if (event->type.is_devspec == 0) { | |
2616 | /* depevt */ | |
2617 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2618 | } | |
2619 | ||
2620 | switch (event->type.type) { | |
2621 | case DWC3_EVENT_TYPE_DEV: | |
2622 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2623 | break; | |
2624 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2625 | default: | |
2626 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2627 | } | |
2628 | } | |
2629 | ||
f42f2447 | 2630 | static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) |
b15a762f | 2631 | { |
f42f2447 | 2632 | struct dwc3_event_buffer *evt; |
b15a762f | 2633 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2634 | int left; |
e8adfc30 | 2635 | u32 reg; |
b15a762f | 2636 | |
f42f2447 FB |
2637 | evt = dwc->ev_buffs[buf]; |
2638 | left = evt->count; | |
b15a762f | 2639 | |
f42f2447 FB |
2640 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2641 | return IRQ_NONE; | |
b15a762f | 2642 | |
f42f2447 FB |
2643 | while (left > 0) { |
2644 | union dwc3_event event; | |
b15a762f | 2645 | |
f42f2447 | 2646 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2647 | |
f42f2447 | 2648 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2649 | |
f42f2447 FB |
2650 | /* |
2651 | * FIXME we wrap around correctly to the next entry as | |
2652 | * almost all entries are 4 bytes in size. There is one | |
2653 | * entry which has 12 bytes which is a regular entry | |
2654 | * followed by 8 bytes data. ATM I don't know how | |
2655 | * things are organized if we get next to the a | |
2656 | * boundary so I worry about that once we try to handle | |
2657 | * that. | |
2658 | */ | |
2659 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2660 | left -= 4; | |
b15a762f | 2661 | |
f42f2447 FB |
2662 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); |
2663 | } | |
b15a762f | 2664 | |
f42f2447 FB |
2665 | evt->count = 0; |
2666 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2667 | ret = IRQ_HANDLED; | |
b15a762f | 2668 | |
f42f2447 FB |
2669 | /* Unmask interrupt */ |
2670 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2671 | reg &= ~DWC3_GEVNTSIZ_INTMASK; | |
2672 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
b15a762f | 2673 | |
f42f2447 FB |
2674 | return ret; |
2675 | } | |
e8adfc30 | 2676 | |
f42f2447 FB |
2677 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) |
2678 | { | |
2679 | struct dwc3 *dwc = _dwc; | |
2680 | unsigned long flags; | |
2681 | irqreturn_t ret = IRQ_NONE; | |
2682 | int i; | |
2683 | ||
2684 | spin_lock_irqsave(&dwc->lock, flags); | |
2685 | ||
2686 | for (i = 0; i < dwc->num_event_buffers; i++) | |
2687 | ret |= dwc3_process_event_buf(dwc, i); | |
b15a762f FB |
2688 | |
2689 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2690 | ||
2691 | return ret; | |
2692 | } | |
2693 | ||
7f97aa98 | 2694 | static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) |
72246da4 FB |
2695 | { |
2696 | struct dwc3_event_buffer *evt; | |
72246da4 | 2697 | u32 count; |
e8adfc30 | 2698 | u32 reg; |
72246da4 | 2699 | |
b15a762f FB |
2700 | evt = dwc->ev_buffs[buf]; |
2701 | ||
72246da4 FB |
2702 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); |
2703 | count &= DWC3_GEVNTCOUNT_MASK; | |
2704 | if (!count) | |
2705 | return IRQ_NONE; | |
2706 | ||
b15a762f FB |
2707 | evt->count = count; |
2708 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2709 | |
e8adfc30 FB |
2710 | /* Mask interrupt */ |
2711 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2712 | reg |= DWC3_GEVNTSIZ_INTMASK; | |
2713 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
2714 | ||
b15a762f | 2715 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2716 | } |
2717 | ||
2718 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc) | |
2719 | { | |
2720 | struct dwc3 *dwc = _dwc; | |
2721 | int i; | |
2722 | irqreturn_t ret = IRQ_NONE; | |
2723 | ||
2724 | spin_lock(&dwc->lock); | |
2725 | ||
9f622b2a | 2726 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 FB |
2727 | irqreturn_t status; |
2728 | ||
7f97aa98 | 2729 | status = dwc3_check_event_buf(dwc, i); |
b15a762f | 2730 | if (status == IRQ_WAKE_THREAD) |
72246da4 FB |
2731 | ret = status; |
2732 | } | |
2733 | ||
2734 | spin_unlock(&dwc->lock); | |
2735 | ||
2736 | return ret; | |
2737 | } | |
2738 | ||
2739 | /** | |
2740 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2741 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2742 | * |
2743 | * Returns 0 on success otherwise negative errno. | |
2744 | */ | |
41ac7b3a | 2745 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2746 | { |
72246da4 | 2747 | int ret; |
72246da4 FB |
2748 | |
2749 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2750 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2751 | if (!dwc->ctrl_req) { | |
2752 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2753 | ret = -ENOMEM; | |
2754 | goto err0; | |
2755 | } | |
2756 | ||
2757 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2758 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
2759 | if (!dwc->ep0_trb) { | |
2760 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2761 | ret = -ENOMEM; | |
2762 | goto err1; | |
2763 | } | |
2764 | ||
3ef35faf | 2765 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 FB |
2766 | if (!dwc->setup_buf) { |
2767 | dev_err(dwc->dev, "failed to allocate setup buffer\n"); | |
2768 | ret = -ENOMEM; | |
2769 | goto err2; | |
2770 | } | |
2771 | ||
5812b1c2 | 2772 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2773 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2774 | GFP_KERNEL); | |
5812b1c2 FB |
2775 | if (!dwc->ep0_bounce) { |
2776 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2777 | ret = -ENOMEM; | |
2778 | goto err3; | |
2779 | } | |
2780 | ||
72246da4 | 2781 | dwc->gadget.ops = &dwc3_gadget_ops; |
d327ab5b | 2782 | dwc->gadget.max_speed = USB_SPEED_SUPER; |
72246da4 | 2783 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 2784 | dwc->gadget.sg_supported = true; |
72246da4 FB |
2785 | dwc->gadget.name = "dwc3-gadget"; |
2786 | ||
a4b9d94b DC |
2787 | /* |
2788 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2789 | * on ep out. | |
2790 | */ | |
2791 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2792 | ||
72246da4 FB |
2793 | /* |
2794 | * REVISIT: Here we should clear all pending IRQs to be | |
2795 | * sure we're starting from a well known location. | |
2796 | */ | |
2797 | ||
2798 | ret = dwc3_gadget_init_endpoints(dwc); | |
2799 | if (ret) | |
5812b1c2 | 2800 | goto err4; |
72246da4 | 2801 | |
72246da4 FB |
2802 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
2803 | if (ret) { | |
2804 | dev_err(dwc->dev, "failed to register udc\n"); | |
e1f80467 | 2805 | goto err4; |
72246da4 FB |
2806 | } |
2807 | ||
2808 | return 0; | |
2809 | ||
5812b1c2 | 2810 | err4: |
e1f80467 | 2811 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
2812 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2813 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2814 | |
72246da4 | 2815 | err3: |
0fc9a1be | 2816 | kfree(dwc->setup_buf); |
72246da4 FB |
2817 | |
2818 | err2: | |
2819 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2820 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2821 | ||
2822 | err1: | |
2823 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2824 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2825 | ||
2826 | err0: | |
2827 | return ret; | |
2828 | } | |
2829 | ||
7415f17c FB |
2830 | /* -------------------------------------------------------------------------- */ |
2831 | ||
72246da4 FB |
2832 | void dwc3_gadget_exit(struct dwc3 *dwc) |
2833 | { | |
72246da4 | 2834 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 2835 | |
72246da4 FB |
2836 | dwc3_gadget_free_endpoints(dwc); |
2837 | ||
3ef35faf FB |
2838 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2839 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2840 | |
0fc9a1be | 2841 | kfree(dwc->setup_buf); |
72246da4 FB |
2842 | |
2843 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2844 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2845 | ||
2846 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2847 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 2848 | } |
7415f17c FB |
2849 | |
2850 | int dwc3_gadget_prepare(struct dwc3 *dwc) | |
2851 | { | |
7b2a0368 | 2852 | if (dwc->pullups_connected) { |
7415f17c | 2853 | dwc3_gadget_disable_irq(dwc); |
7b2a0368 FB |
2854 | dwc3_gadget_run_stop(dwc, true, true); |
2855 | } | |
7415f17c FB |
2856 | |
2857 | return 0; | |
2858 | } | |
2859 | ||
2860 | void dwc3_gadget_complete(struct dwc3 *dwc) | |
2861 | { | |
2862 | if (dwc->pullups_connected) { | |
2863 | dwc3_gadget_enable_irq(dwc); | |
7b2a0368 | 2864 | dwc3_gadget_run_stop(dwc, true, false); |
7415f17c FB |
2865 | } |
2866 | } | |
2867 | ||
2868 | int dwc3_gadget_suspend(struct dwc3 *dwc) | |
2869 | { | |
2870 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2871 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
2872 | ||
2873 | dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2874 | ||
2875 | return 0; | |
2876 | } | |
2877 | ||
2878 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
2879 | { | |
2880 | struct dwc3_ep *dep; | |
2881 | int ret; | |
2882 | ||
2883 | /* Start with SuperSpeed Default */ | |
2884 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2885 | ||
2886 | dep = dwc->eps[0]; | |
265b70a7 PZ |
2887 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2888 | false); | |
7415f17c FB |
2889 | if (ret) |
2890 | goto err0; | |
2891 | ||
2892 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2893 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2894 | false); | |
7415f17c FB |
2895 | if (ret) |
2896 | goto err1; | |
2897 | ||
2898 | /* begin to receive SETUP packets */ | |
2899 | dwc->ep0state = EP0_SETUP_PHASE; | |
2900 | dwc3_ep0_out_start(dwc); | |
2901 | ||
2902 | dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); | |
2903 | ||
2904 | return 0; | |
2905 | ||
2906 | err1: | |
2907 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2908 | ||
2909 | err0: | |
2910 | return ret; | |
2911 | } |